Non-volatile storage device

Abstract

A non-volatile memory device includes: a die structure having a stack of word lines on a substrate and first and second string select lines on the word lines; a first cut structure passing through the die structure; a second cut structure passing through the die structure, the second cut structure being spaced apart from the first cut structure; a channel structure penetrating the die structure to connect to the substrate, the channel structure being between the first cut structure and the second cut structure; a first cut line cutting through the first string select line but not through the second string select line, the first cut line being between the first cut structure and the channel structure; and a second cut line cutting through the second string select line but not through the first string select line, the second cut line being between the second cut structure and the channel structure.

Description

Technical Field

[0001] The present disclosure relates to a non-volatile memory device and a method of manufacturing the same. More specifically, the present disclosure relates to a non-volatile memory device including a plurality of string selection lines and a method of manufacturing the same. Background Art

[0002] Semiconductor memory devices can be generally classified into volatile memory devices and non-volatile memory devices. The integration degree of non-volatile memory devices has been increased to meet excellent performance and low cost required by consumers. Incidentally, in the case of two-dimensional or planar memory devices, the integration degree is determined by the area occupied by a unit memory cell. Therefore, recently, three-dimensional memory devices in which unit memory cells are vertically arranged have been developed. Summary of the Invention

[0003] According to an aspect of the present disclosure, there is provided a non-volatile memory device including: a mold structure on a substrate, the mold structure including a stack of word lines and string selection lines, and the string selection lines including a first string selection line and a second string selection line on the word lines; a first cutting structure passing through the mold structure; a second cutting structure passing through the mold structure and spaced apart from the first cutting structure; a channel structure penetrating the mold structure to connect to the substrate, the channel structure being between the first cutting structure and the second cutting structure; a first cutting line passing through the first string selection line but not through the second string selection line, the first cutting line being between the first cutting structure and the channel structure; and a second cutting line passing through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

[0004] According to another aspect of the present disclosure, there is provided a non-volatile memory device including: a mold structure including a plurality of word lines stacked on a substrate and a first string selection line and a second string selection line sequentially stacked on the plurality of word lines; first to third channel structures penetrating the mold structure, connecting to the substrate, and being sequentially arranged; a first cutting line between the first channel structure and the second channel structure, the first cutting line cutting the first string selection line; and a second cutting line between the second channel structure and the third channel structure, the second cutting line cutting the second string selection line, wherein an upper surface of the first cutting line is lower than or equal to a bottom surface of the second string selection line, and a bottom surface of the second cutting line is higher than or equal to an upper surface of the first string selection line.

[0005] According to another aspect of the present disclosure, a non-volatile memory device is provided, which includes: a mold structure including a plurality of word lines stacked on a substrate and n string selection lines stacked on the plurality of word lines (here, n is a natural number of 2 or greater); a first word line cutting region for cutting the mold structure; a second word line cutting region spaced apart from the first word line cutting region to cut the mold structure; and n cutting lines between the first word line cutting region and the second word line cutting region, each of the n cutting lines cutting a corresponding one of the n string selection lines, wherein the n cutting lines are spaced apart from each other in a plan view.

[0006] According to another aspect of the present disclosure, a method of manufacturing a non-volatile memory device is provided, which includes: forming first sacrificial patterns and insulating patterns alternately stacked on a substrate; forming second sacrificial patterns on the first sacrificial patterns and the insulating patterns; forming a first cutting line for cutting the second sacrificial patterns; forming third sacrificial patterns on the second sacrificial patterns and the first cutting line; forming a second cutting line spaced apart from the first cutting line in a plan view and cutting the third sacrificial patterns; forming a first word line cutting region and a second word line cutting region that penetrate the first to third sacrificial patterns and the insulating patterns and are spaced apart from each other, with the second sacrificial patterns and the third sacrificial patterns interposed therebetween; and replacing the first to third sacrificial patterns with a plurality of conductive films using the first word line cutting region and the second word line cutting region.

[0007] According to another aspect of the present disclosure, a method of manufacturing a non-volatile memory device is provided, which includes: forming first sacrificial patterns and insulating patterns alternately stacked on a substrate; forming second sacrificial patterns on the first sacrificial patterns and the insulating patterns; forming a first cutting line for cutting the second sacrificial patterns; forming third sacrificial patterns on the second sacrificial patterns and the first cutting line; forming a second cutting line for cutting the third sacrificial patterns; forming a channel structure between the first cutting line and the second cutting line, the channel structure penetrating the first to third sacrificial patterns and the insulating patterns and connected to the substrate; forming a first word line cutting region and a second word line cutting region that penetrate the first to third sacrificial patterns and the insulating patterns and are spaced apart from each other, with the second sacrificial patterns and the third sacrificial patterns interposed therebetween; and replacing the first to third sacrificial patterns with a plurality of conductive patterns using the first word line cutting region and the second word line cutting region. Description of the Drawings

[0008] Features will become apparent to those skilled in the art by referring to the accompanying drawings in detail, in which:

[0009] Figure 1 A layout diagram of a non-volatile memory device according to some embodiments is shown.

[0010] Figure 2 Shows a cross-sectional view taken along line A-A of Figure 1 .

[0011] Figure 3 Shows an enlarged view of part R1 of Figure 2 .

[0012] Figures 4a to 4d Shows various enlarged views of part R2 of Figure 2 .

[0013] Figure 5 Shows a layout diagram of a non-volatile memory device according to some embodiments.

[0014] Figure 6 Shows a cross-sectional view taken along line B1-B1 of Figure 5 .

[0015] Figure 7 Shows a cross-sectional view taken along line B2-B2 of Figure 5 .

[0016] Figure 8 Shows a layout diagram of a non-volatile memory device according to some embodiments.

[0017] Figure 9 Shows a cross-sectional view taken along line C-C of Figure 8 .

[0018] Figure 10 Shows a layout diagram of a non-volatile memory device according to some embodiments.

[0019] Figure 11 Shows a cross-sectional view taken along line D-D of Figure 10 .

[0020] Figure 12 Shows a layout diagram of a non-volatile memory device according to some embodiments.

[0021] Figures 13 to 22 Shows a cross-sectional view of a stage in a method of manufacturing a non-volatile memory device according to some embodiments. Detailed Description

[0022] Hereinafter, a non-volatile memory device according to some embodiments of the present disclosure will be described with reference to Figures 1 to 12 .

[0023] Figure 1 is a layout diagram of a non-volatile memory device according to some embodiments. Figure 2 is a cross-sectional view taken along line A-A of Figure 1 , <� Figure 3 is Figure 2An enlarged view of part R1, and Figures 4a-4d is Figure 2 Various enlarged views of part R2.

[0024] Referring to Figure 1 and Figure 2 According to some embodiments, a non - volatile memory device may include a substrate 100, a mold structure MS, a plurality of channel structures CS1 to CS6, a plurality of scribe lines SS1 and SS2, and a plurality of bit lines BL1 and BL2.

[0025] For example, the substrate 100 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon - germanium substrate. In another example, the substrate 100 may include a silicon - on - insulator (SOI) substrate, a germanium - on - insulator (GOI) substrate, etc.

[0026] The mold structure MS may be formed on the substrate 100. The mold structure MS may include a plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U (e.g., a stack of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U) formed on the substrate 100 and a plurality of insulating patterns 125. For example, each of the gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U and each of the insulating patterns 125 may have a layered structure extending in a first direction Y and a second direction X.

[0027] The respective gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may be alternately stacked with the respective insulating patterns 125. For example, the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may be spaced apart from each other in a third direction Z and stacked in sequence. At this time, each insulating pattern 125 may be interposed between the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U. That is, the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may be electrically spaced apart from each other by the corresponding insulating patterns 125.

[0028] As Figure 1 shown, in some embodiments, the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may be stacked in a stepped manner. In Figure 2 although the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U are shown as having the same thickness as each other in, for example, the third direction Z, this is merely an example. For example, the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may have different thicknesses from each other.

[0029] In some embodiments, the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may include a ground selection line GSL, a plurality of word lines WL1 to WLn, and a plurality of string selection lines SSL_L and SSL_U. The ground selection line GSL, the plurality of word lines WL1 to WLn, and the plurality of string selection lines SSL_L and SSL_U may be sequentially stacked on the substrate 100.

[0030] Although only three word lines are schematically shown between the ground selection line GSL and the string selection lines SSL_L and SSL_U in Figure 2 , this is only for illustrative purposes. For example, eight, sixteen, thirty-two, sixty-four, or more word lines may be stacked between the ground selection line GSL and the string selection lines SSL_L and SSL_U.

[0031] The plurality of string selection lines SSL_L and SSL_U may include a first string selection line SSL_L and a second string selection line SSL_U, which are sequentially stacked on the plurality of word lines WL1 to WLn. For example, the first string selection line SSL_L may be formed on the topmost word line WLn and may be spaced apart from the topmost word line WLn by an insulating pattern 125. In addition, for example, the second string selection line SSL_U may be formed on the first string selection line SSL_L and may be spaced apart from the first string selection line SSL_L by the insulating pattern 125.

[0032] Each of the gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may include a conductive material. For example, each of the gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U may include, but is not limited to, a metal (such as tungsten (W), cobalt (Co), and nickel (Ni)) or a semiconductor material (such as silicon).

[0033] Each insulating pattern 125 may include an insulating material. For example, each insulating pattern 125 may include, but is not limited to, silicon oxide.

[0034] The mold structure MS may be divided into, for example, a plurality of sections by a first word line cutting region WLC1 and a second word line cutting region WLC2. For example, as Figure 1 shown, each of the first word line cutting region WLC1 and the second word line cutting region WLC2 may extend side by side in a first direction Y to cut the mold structure MS. For example, the first word line cutting region WLC1 and the second word line cutting region WLC2 may extend parallel to each other in the first direction Y and be spaced apart from each other in a second direction X to divide the mold structure MS into separate sections spaced apart from each other in the second direction X.

[0035] In some embodiments, the first cutting structure 150A may be formed in the first word line cutting region WLC1, and the second cutting structure 150B may be formed in the second word line cutting region WLC2. As Figure 2 shown, the first cutting structure 150A and the second cutting structure 150B may penetrate, for example, the entire mold structure MS and extend to the substrate 100. Accordingly, each of the first cutting structure 150A and the second cutting structure 150B may extend side by side in the first direction Y to cut the mold structure MS. In some embodiments, each of the first cutting structure 150A and the second cutting structure 150B may include a plug pattern 152 and a spacer 154.

[0036] The plug pattern 152 may penetrate the mold structure MS and may be connected to the substrate 100. In some embodiments, the plug pattern 152 may be provided as a common source line (CSL) of a non-volatile memory device according to some embodiments. For example, the plug pattern 152 may include a conductive material. In addition, the plug pattern 152 may be connected to the impurity region 105 in the substrate 100. The impurity region 105 may extend, for example, in the first direction Y. The same voltage may be electrically applied to the plug pattern 152 of the first cutting structure 150A and the plug pattern 152 of the second cutting structure 150B, or different voltages may be applied to the plug pattern 152 of the first cutting structure 150A and the plug pattern 152 of the second cutting structure 150B and they may be controlled separately.

[0037] The spacer 154 may be interposed between the plug pattern 152 and the mold structure MS. For example, the spacer 154 may extend along the sidewalls of the plug pattern 152. The spacer 154 may include an insulating material. Accordingly, the plug pattern 152 may be electrically insulated from, for example, spaced apart from the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U of the mold structure MS.

[0038] The plurality of channel structures CS1 to CS6 may penetrate the mold structure MS and may be connected to the substrate 100. For example, each of the channel structures CS1 to CS6 may be in the shape of a filler extending in the third direction Z. That is, each of the channel structures CS1 to CS6 may extend in a direction intersecting the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U. In addition, each of the channel structures CS1 to CS6 may include a semiconductor pattern 130 and an information storage film 132.

[0039] The semiconductor pattern 130 may penetrate the mold structure MS and may be connected to the substrate 100. In Figure 2In [the figure], the semiconductor pattern 130 is shown as cup-shaped, but this is merely an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a square cylindrical shape, and a solid filler shape. For example, the semiconductor pattern 130 may include a semiconductor material, such as single-crystalline silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nanostructure.

[0040] The information storage film 132 may be interposed between the semiconductor pattern 130 and the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U. For example, the information storage film 132 may extend along the sidewalls of the semiconductor pattern 130. In Figure 2 [the figure], although the information storage film 132 is shown as continuously extending along the sidewalls of the semiconductor pattern 130, this is merely an example. For example, the information storage film 132 may discontinuously extend on the sidewalls of the semiconductor pattern 130. In some embodiments, the information storage film 132 may extend along the upper surface and / or the lower surface of each of the gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U.

[0041] The information storage film 132 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant higher than that of silicon oxide. The high-k material may include at least one of, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0042] In some embodiments, the information storage film 132 may include a plurality of films. For example, as Figure 3 shown, the information storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a blocking insulating film 132c that are sequentially stacked on the semiconductor pattern 130. The tunnel insulating film 132a may include, for example, silicon oxide or a high-k material (such as aluminum oxide (Al2O3) and hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material (such as aluminum oxide (Al2O3) and hafnium oxide (HfO2)).

[0043] As Figure 2 further shown, in some embodiments, each of the channel structures CS1 to CS6 may further include a filled insulating pattern 134. The filled insulating pattern 134 may be formed to fill the interior of the cup-shaped semiconductor pattern 130. Accordingly, the semiconductor pattern 130 may conformally extend along the sidewalls and the bottom surface of the filled insulating pattern 134. The filled insulating pattern 134 may include, for example, silicon oxide.

[0044] In some embodiments, each of the channel structures CS1 to CS6 may further include a channel pad 136. The channel pad 136 may be formed to be connected to the upper portion of the semiconductor pattern 130. For example, the channel pad 136 may be formed in the first interlayer insulating film 140 formed on the mold structure MS.

[0045] In Figure 2 , although the channel pad 136 is shown as being formed on the upper surface of the semiconductor pattern 130, this is merely an example. For example, the upper portion of the semiconductor pattern 130 may be formed to extend along the sidewalls of the channel pad 136. The channel pad 136 may include, for example, polysilicon doped with impurities.

[0046] In some embodiments, the plurality of channel structures CS1 to CS6 may include first to sixth channel structures CS1 to CS6, which are sequentially arranged in the second direction X between the first word line cutting region WLC1 and the second word line cutting region WLC2. Hereinafter, although the first to sixth channel structures CS1 to CS6 will be described as being arranged in a zigzag form in the second direction X, this is merely an example, and the present disclosure is not limited thereto. For example, the first to sixth channel structures CS1 to CS6 may be arranged in a row in the second direction X.

[0047] Each of the plurality of cutting lines SS1 and SS2 may be disposed in the mold structure MS to cut the plurality of string selection lines SSL_L and SSL_U. In some embodiments, the plurality of cutting lines SS1 and SS2 may be formed in the same number as the number of the plurality of string selection lines SSL_L and SSL_U. For example, when the number of the plurality of string selection lines SSL_L and SSL_U stacked on the plurality of word lines WL1 to WLn is n (where n is a natural number of 2 or more), the plurality of cutting lines SS1 and SS2 may be formed in the number of n. For example, when two string selection lines (a first string selection line SSL_L and a second string selection line SSL_U) are formed on the mold structure MS, two cutting lines (a first cutting line SS1 and a second cutting line SS2) may be formed.

[0048] The first cutting line SS1 may be interposed between the first word line cutting region WLC1 and the second word line cutting region WLC2. In addition, the first cutting line SS1 may cut the first string selection line SSL_L. For example, the first cutting line SS1 may extend in the third direction Z through the entirety of the first string selection line SSL_L and the insulating pattern 125 below the first string selection line SSL_L ( Figure 4a ). That is, the first cutting line SS1 may further separate the first string selection line SSL_L that has already been divided into sections by the first word line cutting region WLC1 and the second word line cutting region WLC2.

[0049] For example, as Figure 1As shown, the first string select line SSL_L may include a first sub-string select line SSL_La and a second sub-string select line SSL_Lb separated by a first cut line SS1. The first sub-string select line SSL_La may be the region of the first string select line SSL_L between the first cut line SS1 and the first word line cut region WLC1 (e.g., separated by the first cut line SS1 and the first word line cut region WLC1), and the second sub-string select line SSL_Lb may be the region of the first string select line SSL_L between the first cut line SS1 and the second word line cut region WLC2 (e.g., separated by the first cut line SS1 and the second word line cut region WLC2).

[0050] However, the first cut line SS1 may not cut the second string select line SSL_U. For example, as Figure 2 shown, the upper surface of the first cut line SS1 may be formed to be lower than the bottom surface of the second string select line SSL_U.

[0051] A plurality of channel structures may be disposed between the first cut line SS1 and the first word line cut region WLC1 and between the first cut line SS1 and the second word line cut region WLC2. For example, as Figure 1 and Figure 2 shown, the first to fourth channel structures CS1 to CS4 may be disposed between the first cut line SS1 and the first word line cut region WLC1, and the fifth channel structure CS5 and the sixth channel structure CS6 may be disposed between the first cut line SS1 and the second word line cut region WLC2. Accordingly, the first to fourth channel structures CS1 to CS4 may intersect the first sub-string select line SSL_La, and the fifth channel structure CS5 and the sixth channel structure CS6 may intersect the second sub-string select line SSL_Lb.

[0052] In some embodiments, the first cut line SS1 may extend parallel to the first word line cut region WLC1 and the second word line cut region WLC2. For example, the first cut line SS1 may extend in the first direction Y. For example, referring to Figure 1 , the first cut line SS1 may extend in the first direction Y through the entire length of the first string select line SSL_L in the first direction Y. However, since the first string select line SSL_L has a shorter length than the gate electrode GSL in the first direction Y, for example, the length of the first cut line SS1 in the first direction Y may be shorter than the length of the first word line cut region WLC1. However, the present disclosure is not limited thereto, and the first cut line SS1 may extend in another direction intersecting the first direction Y. For example, different from the shown case, the first cut line SS1 may extend in the second direction X.

[0053] The second cutting line SS2 can be inserted between the first word line cutting region WLC1 and the second word line cutting region WLC2. In addition, the second cutting line SS2 can cut the second string selection line SSL_U. For example, the second cutting line SS2 can extend in the third direction Z through the entire second string selection line SSL_U and the insulating pattern 125 below the second string selection line SSL_U. That is, the second cutting line SS2 can further separate the second string selection line SSL_U that has been segmented by the first word line cutting region WLC1 and the second word line cutting region WLC2.

[0054] For example, as Figure 1 shown, the second string selection line SSL_U can include a third sub-string selection line SSL_Ua and a fourth sub-string selection line SSL_Ub separated by the second cutting line SS2. The third sub-string selection line SSL_Ua can be the region of the second string selection line SSL_U between the second cutting line SS2 and the first word line cutting region WLC1 (e.g., separated by the second cutting line SS2 and the first word line cutting region WLC1), and the fourth sub-string selection line SSL_Ub can be the region of the second string selection line SSL_U between the second cutting line SS2 and the second word line cutting region WLC2 (e.g., separated by the second cutting line SS2 and the second word line cutting region WLC2).

[0055] In some embodiments, the second cutting line SS2 can extend parallel to the first word line cutting region WLCl and the second word line cutting region WLC2. For example, the second cutting line SS2 can extend in the first direction Y. For example, referring to Figure 1 , the second cutting line SS2 can extend in the first direction Y through the entire length of the second string selection line SSL_U in the first direction Y. However, since the second string selection line SSL_U has a shorter length than the first string selection line SSL_L in the first direction Y, the length of the second cutting line SS2 in the first direction Y can be shorter than the length of the first cutting line SS1. However, the present disclosure is not limited thereto, and the second cutting line SS2 can extend in another direction intersecting the first direction Y. For example, different from the shown case, the second cutting line SS2 can extend in the second direction X.

[0056] In a plan view, the second cutting line SS2 can be spaced apart from the first cutting line SS1. For example, as Figure 1 shown, the second cutting line SS2 can be spaced apart from the first cutting line SS1 in the second direction X. In another example, if each of the first cutting line SS1 and the second cutting line SS2 extends in the second direction X, the second cutting line SS2 can be spaced apart from the first cutting line SS1 in the first direction Y.

[0057] In some embodiments, the first cutting line SS1 and the second cutting line SS2 may not overlap each other in a plan view. For example, the first cutting line SS1 and the second cutting line SS2 may extend side by side in parallel along a first direction Y.

[0058] However, the second cutting line SS2 may not cut the first string of select lines SSL_L. For example, as Figure 2 shown, the bottom surface of the second cutting line SS2 may be disposed in the same plane as the top surface of the first string of select lines SSL_L. That is, in a non-volatile memory device according to some embodiments, no string select line is cut by multiple cutting lines. For example, the first string of select lines SSL_L may be cut only by a single cutting line (the first cutting line SS1), and the second string of select lines SSL_U may also be cut only by a single cutting line (the second cutting line SS2).

[0059] The first cutting line SS1 and the second cutting line SS2 may include an insulating material. For example, each of the first cutting line SS1 and the second cutting line SS2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first cutting line SS1 and the second cutting line SS2 may include the same insulating material as each other.

[0060] A plurality of channel structures may be disposed between the second cutting line SS2 and the first word line cutting region WLCl and between the second cutting line SS2 and the second word line cutting region WLC2. For example, as Figure 1 and Figure 2 shown, the first channel structure CS1 and the second channel structure CS2 may be disposed between the second cutting line SS2 and the first word line cutting region WLC1, and the third to sixth channel structures CS3 to CS6 may be disposed between the second cutting line SS2 and the second word line cutting region WLC2. Accordingly, the first channel structure CS1 and the second channel structure CS2 may intersect the third sub-string select line SSL_Ua, and the third to sixth channel structures CS3 to CS6 may intersect the fourth sub-string select line SSL_Ub.

[0061] At least some of the plurality of channel structures CS1 to CS6 may be interposed between the first cutting line SS1 and the second cutting line SS2. For example, the third channel structure CS3 and the fourth channel structure CS4 may be interposed between the first cutting line SS1 and the second cutting line SS2. Accordingly, the first channel structure CS1 and the second channel structure CS2 may intersect with the first sub-string selection line SSL_La and the third sub-string selection line SSL_Ua. The third channel structure CS3 and the fourth channel structure CS4 may intersect with the first sub-string selection line SSL_La and the fourth sub-string selection line SSL_Ub. The fifth channel structure CS5 and the sixth channel structure CS6 may intersect with the second sub-string selection line SSL_Lb and the fourth sub-string selection line SSL_Ub.

[0062] In some embodiments, the second cutting line SS2 may extend parallel to the first word line cutting region WLC1 and the second word line cutting region WLC2. For example, the second cutting line SS2 may extend in the first direction Y. However, the present disclosure is not limited thereto, and the second cutting line SS2 may extend in another direction intersecting the first direction Y.

[0063] When the number of the plurality of cutting lines SS1 and SS2 is n (where n is a natural number of 2 or greater), (n + 1) or more channel structures spaced apart from each other by the plurality of cutting lines SS1 and SS2 may be arranged in a row along the second direction X. For example, when two cutting lines (the first cutting line SS1 and the second cutting line SS2) are formed, three channel structures (the first channel structure CS1, the third channel structure CS3, and the fifth channel structure CS5) spaced apart from each other by the first cutting line SS1 and the second cutting line SS2 may be arranged in a row along the second direction X. Alternatively, three other channel structures (the second channel structure CS2, the fourth channel structure CS4, and the sixth channel structure CS6) spaced apart from each other by the first cutting line SS1 and the second cutting line SS2 may be arranged in a row along the second direction X.

[0064] The plurality of bit lines BL1 and BL2 may be connected to the plurality of channel structures CS1 to CS6. For example, each of the bit lines BL1 and BL2 may be connected to each of the channel structures CS1 to CS6 through a bit line contact 170. The bit line contact 170 penetrates, for example, the second interlayer insulating film 160 on the mold structure MS, and may electrically connect the corresponding channel structures CS1 to CS6 to the corresponding bit lines BL1 and BL2.

[0065] In some embodiments, the plurality of bit lines BL1 and BL2 may intersect with the first cutting line SS1 and the second cutting line SS2. For example, the plurality of bit lines BL1 and BL2 may extend in the second direction X.

[0066] In some embodiments, each of bit lines BL1 and BL2 may be connected to a plurality of channel structures arranged in a row. For example, the first bit line BL1 may be connected to the first channel structure CS1, the third channel structure CS1, and the fifth channel structure CS5, and the second bit line BL2 may be connected to the second channel structure CS2, the fourth channel structure CS4, and the sixth channel structure CS6.

[0067] In some embodiments, a plurality of bit lines BL1 and BL2 may extend side by side in parallel at equal intervals. For example, the first bit line BL1 and the second bit line BL2 may be spaced apart from each other by a first pitch P1 and may extend side by side in the second direction X.

[0068] As the integration degree of the non-volatile memory device increases, the pitch between the bit lines gradually decreases. For example, as more channel structures are provided in the die structure cut by the word line cutting region, more bit lines may be required to separately control each channel structure. However, the narrowed pitch between the bit lines may increase the process difficulty and cause deterioration of the product reliability.

[0069] In contrast, the non-volatile memory device according to some embodiments may increase the integration degree of the non-volatile memory device without reducing the pitch between the bit lines. For example, Figure 1 the corresponding channel structures CS1 to CS6 may be separately selected and controlled from each other.

[0070] Specifically, the first channel structure CS1 may be selected by the first bit line BL1 and the first sub-string selection line SSL_La and the third sub-string selection line SSL_Ua. The second channel structure CS2 may be selected by the second bit line BL2 and the first sub-string selection line SSL_La and the third sub-string selection line SSL_Ua. The third channel structure CS3 may be selected by the first bit line BL1 and the first sub-string selection line SSL_La and the fourth sub-string selection line SSL_Ub. The fourth channel structure CS4 may be selected by the second bit line BL2 and the first sub-string selection line SSL_La and the fourth sub-string selection line SSL_Ub. The fifth channel structure CS5 may be selected by the first bit line BL1 and the second sub-string selection line SSL_Lb and the fourth sub-string selection line SSL_Ub. The sixth channel structure CS6 may be selected by the second bit line BL2 and the second sub-string selection line SSL_Lb and the fourth sub-string selection line SSL_Ub.

[0071] However, if the second cut line SS2 is not provided, additional bit lines for controlling the first channel structure CS1 and the third channel structure CS3, respectively, will be required. Furthermore, if the first cut line SS1 is not provided, additional bit lines for controlling the third channel structure CS3 and the fifth channel structure CS5, respectively, will be required. That is, according to some embodiments, a plurality of string selection lines (e.g., the first string selection line SSL_L and the second string selection line SSL_U) and a plurality of cut lines (e.g., the first cut line SS1 and the second cut line SS2) can be used to provide a nonvolatile memory device with improved integration.

[0072] The following will refer to Figures 4a to 4d Various shapes of the first cutting line SS1 and the second cutting line SS2 according to some embodiments of the present disclosure are described. Figures 4a to 4d Only the first cutting line SS1 is shown, but the second cutting line SS2 may have a similar shape.

[0073] In some embodiments, the bottom surface of the first cutting line SS1 may be formed to be lower than the bottom surface of the first string selection line SSL_L. For example, as previously described with reference to Figure 2 and Figure 4a As described, the first cutting line SS1 may penetrate the entire insulating pattern 125 disposed under the first string selection line SSL_L. Therefore, in some embodiments, the bottom surface of the first cutting line SS1 may contact the upper surface of the gate electrode (eg, word line WLn) disposed under the first string selection line SSL_L.

[0074] In some embodiments, the bottom surface of the first cutting line SS1 may be formed to be higher than the bottom surface of the insulating pattern 125 disposed under the first string selection line SSL_L. Figure 4b As shown, the lower portion of the first cut line SS1 may be buried in the insulating pattern 125 disposed under the first string selection line SSL_L. Therefore, in some embodiments, the bottom surface of the first cut line SS1 may not contact the upper surface of the gate electrode (e.g., word line WLn) disposed under the first string selection line SSL_L.

[0075] In some embodiments, the bottom surface of the first cutting line SS1 may be disposed on the same plane as the bottom surface of the first string selection line SSL_L. In this specification, the term "same" not only means completely identical, but also refers to slight differences that may occur due to process margins, etc. For example, Figure 4c As shown, a bottom surface of the first cutting line SS1 may make contact with an upper surface of the insulating pattern 125 disposed under the first string selection line SSL_L.

[0076] In some embodiments, the upper surface of the first cutting line SS1 may be formed to be higher than the upper surface of the first string selection line SSL_L. For example, as Figure 4d shown, the first cutting line SS1 may penetrate the insulating pattern 125 provided on the first string selection line SSL_L. Accordingly, in some embodiments, the upper surface of the first cutting line SS1 may be in contact with the bottom surface of a gate electrode (e.g., the second string selection line SSL_U) provided on the first string selection line SSL_L.

[0077] Figure 5 FIG. Figure 6 is a layout diagram of a non-volatile memory device according to some embodiments of the present disclosure. Figure 6 FIG. Figure 5 is a cross-sectional view taken along line B1-B1 of Figure 5 . Figure 7 FIG. Figure 5 is a cross-sectional view taken along line B2-B2 of Figure 5 . For ease of description, repeated portions of those parts described with Figures 1 to 4d will be briefly described or omitted only.

[0078] Referring to Figures 5 to 7 , a non-volatile memory device according to some embodiments may further include dummy channel structures DCS1 and DCS2.

[0079] The dummy channel structures DCS1 and DCS2 may penetrate the mold structure MS and may be connected to the substrate 100. In some embodiments, the dummy channel structures DCS1 and DCS2 may have the same shape as that of the plurality of channel structures CS1 to CS12. For example, the dummy channel structures DCS1 and DCS2 may have a filler shape extending in the third direction Z. In addition, the dummy channel structures DCS1 and DCS2 may include a semiconductor pattern 130 and an information storage film 132.

[0080] In some embodiments, the dummy channel structures DCS1 and DCS2 may cross the first cutting line SS1 and / or the second cutting line SS2. For example, as Figure 5 and Figure 7 shown, the dummy channel structures DCS1 and DCS2 may include a first dummy channel structure DCS1 crossing the second cutting line SS2 and a second dummy channel structure DCS2 crossing the first cutting line SS1.

[0081] Although each of the two dummy channel structures DCS1 and DCS2 is shown as crossing the first cutting line SS1 and the second cutting line SS2, this is merely an example, and the present disclosure is not limited thereto. For example, one of the first dummy channel structure DCS1 and the second dummy channel structure DCS2 may be omitted.

[0082] In some embodiments, twelve or more channel structures CSl to CS12 arranged along the second direction X may be disposed between the first word line cutting region WLCl and the second word line cutting region WLC2. For example, the first to fourth channel structures CS1 to CS4, the first dummy channel structure DCS1, the fifth to eighth channel structures CS5 to CS8, the second dummy channel structure DCS2, and the ninth to twelfth channel structures CS9 to CS12 may be sequentially arranged between the first word line cutting region WLC1 and the second word line cutting region WLC2. That is, a total of fourteen channel structures (CS1 to CS12 and the dummy channel structures DCS1 and DCS2) may be arranged along the second direction X between the first word line cutting region WLC1 and the second word line cutting region WLC2. Although the channel structures CS1 to CS12 and the dummy channel structures DCS1 and DCS2 are shown in Figure 5 as being arranged in a zigzag form along the second direction X, this is merely an example, and the present disclosure is not limited thereto.

[0083] As the number of channel structures CS1 to CS12 between the first word line cutting region WLC1 and the second word line cutting region WLC2 increases, the number of bit lines required on the channel structures CS1 to CS12 also increases. For example, Figure 5 the number of bit lines BL1 to BL4 is greater than Figure 1 the number of bit lines BL1 and BL2.

[0084] In some embodiments, each of the bit lines BLl to BL4 may be connected to a plurality of channel structures CSl to CS12 arranged in a row. For example, the first bit line BL1 may be connected to the first channel structure CS1, the sixth channel structure CS6, and the ninth channel structure CS9. The second bit line BL2 may be connected to the third channel structure CS3, the eighth channel structure CS8, and the eleventh channel structure CS11. The third bit line BL3 may be connected to the second channel structure CS2, the fifth channel structure CS5, and the tenth channel structure CS10. The fourth bit line BL4 may be connected to the fourth channel structure CS4, the seventh channel structure CS7, and the twelfth channel structure CS12.

[0085] In some embodiments, the dummy channel structures DCS1 and DCS2 may not be connected to the plurality of bit lines BL1 to BL4. For example, bit line contacts 170 may not be formed on the dummy channel structures DCS1 and DCS2.

[0086] In some embodiments, the plurality of bit lines BL1 to BL4 may extend side by side at equal intervals. For example, the first to fourth bit lines BL1 to BL4 may be spaced apart from each other by a second pitch P2 and may extend side by side along the second direction X. In some embodiments, Figure 5 the second pitch P2 may be less thanFigure 1 The first pitch P1.

[0087] Figure 8 is a layout diagram of a non-volatile memory device according to some embodiments of the present disclosure. Figure 9 is along Figure 8 is a cross-sectional view taken along line C-C. For ease of description, repeated portions of those parts described with Figures 1 to 7 will only be briefly described or omitted.

[0088] Referring to Figure 8 and Figure 9 , in a non-volatile memory device according to some embodiments, the first cutting line SS1 and / or the second cutting line SS2 cut a plurality of string selection lines.

[0089] For example, the first string selection line SSL_L may include a first lower string selection line SSL_L1 and a first upper string selection line SSL_L2. The first lower string selection line SSL_L1 may be formed on the topmost word line WLn and may be spaced apart from the topmost word line WLn by an insulating pattern 125. The first upper string selection line SSL_L2 may be formed on the first lower string selection line SSL_L1 and may be spaced apart from the first lower string selection line SSL_L1 by an insulating pattern 125. At this time, the first cutting line SS1 may cut both the first lower string selection line SSL_L1 and the first upper string selection line SSL_L2.

[0090] In addition, for example, the second string selection line SSL_U may include a second lower string selection line SSL_U1 and a second upper string selection line SSL_U2. The second lower string selection line SSL_U1 may be formed on the first upper string selection line SSL_L2 and may be spaced apart from the first upper string selection line SSL_L2 by an insulating pattern 125. The second upper string selection line SSL_U2 may be formed on the second lower string selection line SSL_U1 and may be spaced apart from the second lower string selection line SSL_U1 by an insulating pattern 125. At this time, the second cutting line SS2 may cut both the second lower string selection line SSL_U1 and the second upper string selection line SSL_U2.

[0091] Although each of the first cutting line SS1 and / or the second cutting line SS2 is shown as cutting only two string selection lines, this is only for ease of illustration. For example, the first cutting line SS1 and / or the second cutting line SS2 may also cut three or more string selection lines, respectively.

[0092] In addition, although both the first cutting line SS1 and the second cutting line SS2 are shown as cutting two string selection lines, respectively, this is only an example. For example, one of the first cutting line SS1 and the second cutting line SS2 may cut only one string selection line.

[0093] Figure 10 is a layout diagram of a non - volatile memory device according to some embodiments of the present disclosure. Figure 11 is a cross - sectional view taken along the Figure 10 line D - D. For ease of description, repeated portions of those parts described with Figures 1 to 7 will only be briefly described or omitted.

[0094] Referring to Figure 10 and Figure 11 , in a non - volatile memory device according to some embodiments, the first cutting line SS1 and / or the second cutting line SS2 may have a zig - zag shape in a plan view. For example, in a top view, the first cutting line SS1 and / or the second cutting line SS2 may include a shape of a plurality of connecting segments that turn from one side to the other along a first direction Y to define a zig - zag shape.

[0095] For example, as Figure 10 shown, the first cutting line SS1 may cross a portion between the eighth channel structure CS8 and the ninth channel structure CS9 in a zig - zag shape. In addition, for example, the second cutting line SS2 may cross a portion between the fourth channel structure CS4 and the fifth channel structure CS5 in a zig - zag shape. In some embodiments, the first cutting line SS1 and / or the second cutting line SS2 may extend in a zig - zag form along the first direction Y.

[0096] Although both the first cutting line SS1 and the second cutting line SS2 are shown in a zig - zag form in the plan view, this is only an example. For example, the first cutting line SS1 or the second cutting line SS2 may extend in a straight line form along the first direction Y.

[0097] In the present embodiment, since the dummy channel structure is not formed between the first word - line cutting region WLC1 and the second word - line cutting region WLC2, a non - volatile memory device with further improved integration can be provided.

[0098] Figure 12 is a layout diagram of a non - volatile memory device according to some embodiments of the present disclosure. For ease of description, repeated portions of those parts described with Figures 1 to 7 will only be briefly described or omitted.

[0099] Referring to Figure 12 , a non - volatile memory device according to some embodiments may further include a third string selection line SSL_M and a third cutting line SS3.

[0100] The third string selection line SSL_M can be interposed, for example, between the first string selection line SSL_L and the second string selection line SSL_U. In addition, the third string selection line SSL_M can be spaced apart from the first string selection line SSL_L and the second string selection line SSL_U by the insulating pattern 125.

[0101] The third cutting line SS3 can be interposed between the first word line cutting region WLC1 and the second word line cutting region WLC2. In addition, the third cutting line SS3 can cut the third string selection line SSL_M.

[0102] For example, the third string selection line SSL_M can include a fifth sub-string selection line SSL_Ma and a sixth sub-string selection line SSL_Mb separated by the third cutting line SS3. The fifth sub-string selection line SSL_Ma can be the region of the third string selection line SSL_M separated by the third cutting line SS3 and the first word line cutting region WLC1, and the sixth sub-string selection line SSL_Mb can be the region of the third string selection line SSL_M separated by the third cutting line SS3 and the second word line cutting region WLC2.

[0103] In some embodiments, the dummy channel structures DCS1 to DCS3 can cross the first to third cutting lines SS1 to SS3. For example, the first dummy channel structure DCS1 can cross the second cutting line SS2, the second dummy channel structure DCS2 can cross the third cutting line SS3, and the third dummy channel structure DCS3 can cross the first cutting line SS1.

[0104] In some embodiments, the plurality of channel structures CS1 to CS16 can be independently selected and controlled from each other. For example, the first channel structure CS1 can be selected by the first bit line BL1 and the first sub-string selection line SSL_La, the fifth sub-string selection line SSL_Ma, and the third sub-string selection line SSL_Ua. For example, the fifth channel structure CS5 can be selected by the third bit line BL3 and the first sub-string selection line SSL_La, the fifth sub-string selection line SSL_Ma, and the fourth sub-string selection line SSL_Ub. For example, the eleventh channel structure CS11 can be selected by the second bit line BL2 and the first sub-string selection line SSL_La, the sixth sub-string selection line SSL_Mb, and the fourth sub-string selection line SSL_Ub. For example, the fifteenth channel structure CS15 can be selected by the fourth bit line BL4 and the second sub-string selection line SSL_Lb, the sixth sub-string selection line SSL_Mb, and the fourth sub-string selection line SSL_Ub. In this embodiment, since the additional string selection lines and additional cutting lines are formed, a larger number of channel structures can be provided between the first word line cutting region WLC1 and the second word line cutting region WLC2.

[0105] Hereinafter, reference will be made to Figures 1 to 4d andFigures 13 to 22 A method of manufacturing a non-volatile memory device according to some embodiments of the present disclosure is described.

[0106] Figures 13 to 22 is a view of a stage in a method of manufacturing a non-volatile memory device according to some embodiments of the present disclosure. For ease of description, repeated portions of those parts described with reference to Figures 1 to 4d will only be briefly described or omitted. For reference, Figures 13 to 22 corresponds to Figure 1 a cross-sectional view taken along line A-A.

[0107] With reference to Figure 13 , a plurality of first sacrificial patterns 127, a plurality of insulating patterns 125, and a second sacrificial pattern 210 are formed on a substrate 100.

[0108] Each of the first sacrificial patterns 127 may be alternately stacked with each of the insulating patterns 125. For example, the plurality of first sacrificial patterns 127 may be spaced apart from each other in a third direction Z and stacked in sequence. At this time, each insulating pattern 125 may be interposed between the plurality of first sacrificial patterns 127.

[0109] The plurality of first sacrificial patterns 127 may include a material having an etching selectivity with respect to the plurality of insulating patterns 125. For example, when the plurality of insulating patterns 125 include silicon oxide, the plurality of first sacrificial patterns 127 may include polysilicon.

[0110] The second sacrificial pattern 210 may be stacked on the plurality of first sacrificial patterns 127. For example, the second sacrificial pattern 210 may be formed on the uppermost first sacrificial pattern 127. In addition, the second sacrificial pattern 210 may be spaced apart from the uppermost first sacrificial pattern 127 by the insulating pattern 125.

[0111] In some embodiments, the second sacrificial pattern 210 may include a material having an etching selectivity with respect to the plurality of insulating patterns 125. For example, if the plurality of insulating patterns 125 include silicon oxide, the second sacrificial pattern 210 may include polysilicon.

[0112] With reference to Figure 14 , the second sacrificial pattern 210 is cut. For example, a trench 210T for cutting the second sacrificial pattern 210 may be formed in the second sacrificial pattern 210. The trench 210T may be formed, for example, by etching a part of the second sacrificial pattern 210.

[0113] In some embodiments, the trench 210T may extend in the first direction Y. In some embodiments, the bottom surface of the trench 210T may be lower than the bottom surface of the second sacrificial pattern 210. For example, the trench 210T may further penetrate through the insulating pattern 125 disposed below the second sacrificial pattern 210 to expose the upper surface of the first sacrificial pattern 127.

[0114] Although the cutting of the second sacrificial pattern 210 is shown as being performed in a state where the upper surface of the second sacrificial pattern 210 is exposed, this is merely an example. For example, the cutting of the second sacrificial pattern 210 may be performed in a state where the upper surface of the insulating pattern 125 is exposed after the insulating pattern 125 is formed on the second sacrificial pattern 210.

[0115] Referring to Figure 15 , a first cutting line SS1 for cutting the second sacrificial pattern 210 is formed. For example, an insulating material filling the trench 210T is formed on the second sacrificial pattern 210, and then a planarization process may be performed. Accordingly, the first cutting line SS1 for filling the trench 210T may be formed. The insulating material may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0116] Referring to Figure 16 , a third sacrificial pattern 220 is formed on the second sacrificial pattern 210 and the first cutting line SS1. The third sacrificial pattern 220 may be stacked on the second sacrificial pattern 210 and the first cutting line SS1. In addition, the third sacrificial pattern 220 may be spaced apart from the second sacrificial pattern 210 by the insulating pattern 125.

[0117] In some embodiments, the third sacrificial pattern 220 may include a material having an etching selectivity with respect to the plurality of insulating patterns 125. For example, if the plurality of insulating patterns 125 include silicon oxide, the third sacrificial pattern 220 may include polysilicon.

[0118] Referring to Figure 17 , a second cutting line SS2 for cutting the third sacrificial pattern 220 is formed. Since the formation of the second cutting line SS2 is similar to the formation of the first cutting line SS1 described above in Figure 14 and Figure 15 , a detailed description will not be provided below.

[0119] In a plan view, the second cutting line SS2 may be spaced apart from the first cutting line SS1. For example, the second cutting line SS2 may be spaced apart from the first cutting line SS1 in the second direction X. In some embodiments, the first cutting line SS1 and the second cutting line SS2 may not overlap each other in the plan view.

[0120] However, the second cutting line SS2 may not cut the second sacrificial pattern 210. For example, the bottom surface of the second cutting line SS2 may be formed to be higher than or the same as the upper surface of the second sacrificial pattern 210.

[0121] As a result, no sacrificial pattern can be cut by multiple cutting lines. For example, the second sacrificial pattern 210 may be cut by only one cutting line (the first cutting line SS1), and the third sacrificial pattern 220 may also be cut by only one cutting line (the second cutting line SS2).

[0122] Referring to Figure 18 , a plurality of channel structures CS1 to CS6 (not shown) are formed to penetrate through the plurality of first sacrificial patterns 127, the plurality of insulating patterns 125, the second sacrificial pattern 210, and the third sacrificial pattern 220 and are connected to the substrate 100. For example, a via hole may be formed to penetrate through the plurality of first sacrificial patterns 127, the plurality of insulating patterns 125, the second sacrificial pattern 210, and the third sacrificial pattern 220 to expose the substrate 100. Subsequently, an information storage film 132 and a semiconductor pattern 130 may be formed to be sequentially stacked in the via hole.

[0123] In some embodiments, a filled insulating pattern 134 may be further formed on the semiconductor pattern 130. The filled insulating pattern 134 may be formed to fill, for example, the inside of the cup-shaped semiconductor pattern 130.

[0124] In some embodiments, a channel pad 136 may be further formed on the semiconductor pattern 130. The channel pad 136 may be formed to be connected to, for example, the upper portion of the semiconductor pattern 130.

[0125] Referring to Figure 19 , a first word line cutting region WLC1 and a second word line cutting region WLC2 are formed in the plurality of first sacrificial patterns 127, the plurality of insulating patterns 125, the second sacrificial pattern 210, and the third sacrificial pattern 220. The first word line cutting region WLC1 and the second word line cutting region WLC2 may be formed to penetrate through the plurality of first sacrificial patterns 127, the plurality of insulating patterns 125, the second sacrificial pattern 210, and the third sacrificial pattern 220 to expose the substrate 100. As a result, the first word line cutting region WLC1 and the second word line cutting region WLC2 may cut the plurality of first sacrificial patterns 127, the plurality of insulating patterns 125, the second sacrificial pattern 210, and the third sacrificial pattern 220.

[0126] In some embodiments, each of the first word line cutting region WLC1 and the second word line cutting region WLC2 may be formed to extend side by side along the first direction Y. In some embodiments, an impurity region 105 may be formed in the substrate 100 exposed by the first word line cutting region WLC1 and the second word line cutting region WLC2.

[0127] Referring to Figure 20 , a plurality of first sacrificial patterns 127, second sacrificial patterns 210, and third sacrificial patterns 220 exposed by the first word line cutting region WLC1 and the second word line cutting region WLC2 are removed. The removal of the plurality of first sacrificial patterns 127, second sacrificial patterns 210, and third sacrificial patterns 220 can be performed by, for example, an anisotropic etching process.

[0128] On the other hand, since no sacrificial pattern is cut by the two cutting lines, the plurality of first sacrificial patterns 127, second sacrificial patterns 210, and third sacrificial patterns 220 can be completely removed.

[0129] If the second sacrificial pattern 210 is cut by the first cutting line SS1 and the second cutting line SS2, since both the first cutting line SS1 and the second cutting line SS2 are interposed between the first word line cutting region WLC1 and the second word line cutting region WLC2, the second sacrificial pattern 210 between the first cutting line SS1 and the second cutting line SS2 will not be removed. However, in a method of manufacturing a non-volatile memory device according to some embodiments, since one side of the first cutting line SS1 is exposed through the first word line cutting region WLC1 and the other side of the first cutting line SS1 is exposed through the second word line cutting region WLC2, the second sacrificial pattern 210 between the first cutting line SS1 and the second cutting line SS2 can also be removed. In addition, in a method of manufacturing a non-volatile memory device according to some embodiments, since one side of the second cutting line SS2 is exposed through the first word line cutting region WLC1 and the other side of the second cutting line SS2 is exposed through the second word line cutting region WLC2, the third sacrificial pattern 220 between the first cutting line SS1 and the second cutting line SS2 can also be removed.

[0130] Referring to Figure 21 , a plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U are formed on the substrate 100. The plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U can be formed in a region where the plurality of first sacrificial patterns 127, second sacrificial patterns 210, and third sacrificial patterns 220 are removed. That is, the first sacrificial patterns 127, second sacrificial patterns 210, and third sacrificial patterns 220 can be replaced by the plurality of gate electrodes GSL, WL1 to WLn, SSL_L, and SSL_U.

[0131] Specifically, multiple first sacrificial patterns 127 can be replaced by a ground selection line GSL and multiple word lines WL1 to WLn. The second sacrificial pattern 210 can be replaced by a first string selection line SSL_L. The third sacrificial pattern 220 can be replaced by a second string selection line SSL_U. Accordingly, the first cutting line SS1 can cut the first string selection line SSL_L, and the second cutting line SS2 can cut the second string selection line SSL_U.

[0132] Referring Figure 22 , a first cutting structure 150A and a second cutting structure 150B are formed in a first word line cutting region WLC1 and a second word line cutting region WLC2. The first cutting structure 150A can be formed in the first word line cutting region WLC1, and the second cutting structure 150B can be formed in the second word line cutting region WLC2. In some embodiments, the first cutting structure 150A and the second cutting structure 150B can each include a plug pattern 152 and a spacer 154.

[0133] Subsequently, referring Figure 2 , multiple bit lines BL1 and BL2 are formed on a mold structure MS. The multiple bit lines BL1 and BL2 can be formed to be connected to multiple channel structures CS1 to CS6. For example, a second interlayer insulating film 160 can be formed on the mold structure MS. Subsequently, bit line contacts 170 can be formed to penetrate the second interlayer insulating film 160 to electrically connect the corresponding channel structures CS1 to CS6 to the corresponding bit lines BL1 and BL2.

[0134] By way of summary and review, aspects of the present disclosure provide a non-volatile memory device having improved integration. Aspects of the present disclosure also provide a method of manufacturing a non-volatile memory device having improved integration.

[0135] Example embodiments have been disclosed herein, and although specific terms have been employed, they have been used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art at the time of filing of this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Accordingly, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0136] Korean Patent Application No. 10-2019-0063805, filed with the Korean Intellectual Property Office on May 30, 2019, entitled "Nonvolatile Memory Device and Method for Fabricating the Same", is incorporated herein by reference in its entirety.

Claims

1. A non-volatile memory device, comprising: A mold structure on a substrate, the mold structure including a stack of word lines and string selection lines, and the string selection lines including a first string selection line and a second string selection line on the word lines; A first cutting structure passing through the mold structure; A second cutting structure passing through the mold structure, the second cutting structure being spaced apart from the first cutting structure; A channel structure penetrating the mold structure to connect to the substrate, the channel structure being between the first cutting structure and the second cutting structure; A first cutting line passing through the first string selection line but not through the second string selection line, the first cutting line being between the first cutting structure and the channel structure; And A second cutting line passing through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

2. The non-volatile memory device according to claim 1, wherein The mold structure further includes a third string selection line on the word line and adjacent to the first string selection line, and the first cutting line extends through the first string selection line and the third string selection line.

3. The non-volatile memory device according to claim 2, wherein The first cutting structure and the second cutting structure extend side by side in a first direction.

4. The non-volatile memory device according to claim 3, wherein, The first cutting line and the second cutting line extend side by side in the first direction.

5. The non-volatile memory device according to claim 3, wherein The first cutting line and the second cutting line extend side by side in a second direction intersecting the first direction, and the first cutting line and the second cutting line are spaced apart from each other in the first direction.

6. The non-volatile memory device according to claim 3, further comprising a bit line on the mold structure and electrically connected to the channel structure, the bit line extending in a second direction intersecting the first direction.

7. The non-volatile memory device according to claim 1, further comprising a dummy channel structure passing through the mold structure and spaced apart from the channel structure, the dummy channel structure being connected to the substrate and intersecting the first string selection line.

8. The non-volatile memory device according to claim 1, wherein, The first cutting line and the second cutting line do not overlap each other in a plan view.

9. The non-volatile memory device according to claim 1, wherein, The first cutting line has a zigzag shape in a plan view.

10. The non-volatile memory device according to claim 1, wherein The first cutting line and the second cutting line include an insulating material.

11. A non-volatile memory device, comprising: A mold structure including a plurality of word lines, a first string selection line, and a second string selection line, the plurality of word lines, the first string selection line, and the second string selection line being stacked on a substrate in the order; First to third channel structures penetrating the mold structure to connect to the substrate, the first to third channel structures being arranged in sequence; A first cutting line between the first channel structure and the second channel structure, the first cutting line passing through the first string selection line; And A second cutting line between the second channel structure and the third channel structure, the second cutting line passing through the second string selection line, Wherein, an upper surface of the first cutting line is lower than or equal to a bottom surface of the second string selection line, and a bottom surface of the second cutting line is higher than or equal to an upper surface of the first string selection line.

12. The non-volatile memory device according to claim 11, further comprising bit lines on the mold structure and intersecting the first cutting line and the second cutting line, the bit lines being electrically connected to the first to third channel structures.

13. The non-volatile memory device according to claim 11, wherein, The first cutting line and the second cutting line extend side by side in a first direction, and the first to third channel structures are arranged in a row in a second direction intersecting the first direction.

14. The non-volatile memory device according to claim 11, wherein, The mold structure further comprises: a third string selection line on the second string selection line; a fourth channel structure penetrating the mold structure and connected to the substrate, the fourth channel structure being spaced apart from the first to third channel structures; and a third cutting line between the third channel structure and the fourth channel structure, the third cutting line passing through the third string selection line, a bottom surface of the third cutting line being higher than or equal to an upper surface of the second string selection line.

15. The non-volatile memory device according to claim 11, wherein, A bottom surface of the first cutting line is lower than a bottom surface of the first string selection line.

16. The non-volatile memory device according to claim 11, wherein, An upper surface of the first cutting line is higher than an upper surface of the first string selection line.

17. A non-volatile memory device, comprising: a mold structure on a substrate, the mold structure including a plurality of word lines and n string selection lines, the plurality of word lines and the n string selection lines being sequentially stacked on the substrate in that order, n being a natural number of 2 or greater; a first word line cutting region passing through the mold structure; a second word line cutting region passing through the mold structure, the second word line cutting region being spaced apart from the first word line cutting region; and n cutting lines between the first word line cutting region and the second word line cutting region, each of the n cutting lines passing through a corresponding one of the n string selection lines, the n cutting lines being spaced apart from each other in a plan view.

18. The non-volatile memory device according to claim 17, wherein, The first word line cutting region and the second word line cutting region extend side by side in a first direction.

19. The non-volatile memory device according to claim 18, wherein, Each of the n cutting lines extends in the first direction.

20. The non-volatile memory device according to claim 18, further comprising n + 1 channel structures that penetrate the mold structure, are connected to the substrate, and are spaced apart from each other by the n cutting lines, the n + 1 channel structures being arranged in a row in a second direction intersecting the first direction.

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