Image sensor and method of manufacturing an image sensor

Abstract

An image sensor and a method of manufacturing an image sensor, the image sensor including: a semiconductor substrate having a first floating diffusion region; a molding pattern located above the first floating diffusion region and including an opening; a first photoelectric conversion portion located at a surface of the semiconductor substrate; and a first transfer transistor connecting the first photoelectric conversion portion to the first floating diffusion region. The first transfer transistor includes a first transfer gate electrode and a channel pattern located in the opening. The channel pattern includes an oxide semiconductor. The channel pattern further includes a side wall portion covering a side surface of the opening and a center portion extending from the side wall portion to an area above the first transfer gate electrode.

Description

[0001] Cross-reference to related applications

[0002] Priority is claimed to Korean Patent Application No. 10-2019-0063945, filed with the Korean Intellectual Property Office on May 30, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to an image sensor and a method for manufacturing an image sensor. Background Technology

[0004] An image sensor is a semiconductor device configured to convert optical images into electrical signals. Image sensors are generally classified into two types: charge-coupled device (CCD) type and complementary metal-oxide-semiconductor (CMOS) type. CMOS image sensors are often referred to as "CIS". A CIS consists of multiple pixels arranged in a two-dimensional pattern, each pixel including a photodiode (PD) that converts incident light into an electrical signal. Summary of the Invention

[0005] Embodiments of the present invention provide a method for reducing transistor size and suppressing oxide semiconductor material contamination during the manufacture of image sensors.

[0006] Embodiments of the present invention provide a highly integrated image sensor configured to have reduced noise characteristics and improved image quality.

[0007] An embodiment of the present invention provides an image sensor, comprising: a semiconductor substrate including a first floating diffusion region; a molded pattern located above the first floating diffusion region and including an opening; a first photoelectric conversion portion located on the surface of the semiconductor substrate; and a first transmission transistor connecting the first photoelectric conversion portion to the first floating diffusion region. The first transmission transistor includes a first transmission gate electrode and a channel pattern located in the opening. The channel pattern comprises an oxide semiconductor. The channel pattern includes a sidewall portion and a central portion, the sidewall portion covering a side surface of the opening, and the central portion extending from the sidewall portion to a region above the first transmission gate electrode.

[0008] Embodiments of the present invention also provide an image sensor, comprising: a molded pattern located on the semiconductor substrate and including an opening; a channel pattern located in the opening, the channel pattern including sidewall portions covering a side surface of the opening, and a top surface of the channel pattern being at the same horizontal level as the top surface of the molded pattern; a planarization pattern filling the opening; a gate insulating layer located on the channel pattern; and a gate electrode spaced apart from the channel pattern by the gate insulating layer inserted therebetween.

[0009] An embodiment of the present invention also provides an image sensor, comprising: a semiconductor substrate including a first surface and a second surface opposite to the first surface; a first floating diffusion region and a second floating diffusion region disposed on the first surface of the semiconductor substrate; a first photoelectric conversion portion located on the second surface; a second photoelectric conversion portion disposed in the semiconductor substrate; a molded pattern located on the first surface and including an opening; a planarization pattern located in the opening; and a first transmission transistor connecting the first photoelectric conversion portion to the first floating diffusion region. The first transmission transistor includes a first transmission gate electrode and a channel pattern located in the opening. The channel pattern includes an oxide semiconductor. The channel pattern includes a sidewall portion and a central portion, the sidewall portion covering a side surface of the opening, and the central portion extending from the sidewall portion to a region on the first transmission gate electrode.

[0010] Embodiments of the present invention also provide a method for manufacturing an image sensor, comprising: forming a floating diffusion region in a surface of a semiconductor substrate; forming a first interlayer insulating layer covering the floating diffusion region; forming a contact plug in the first interlayer insulating layer and connecting the contact plug to the floating diffusion region; forming a molding layer on the first interlayer insulating layer, the molding layer including an opening; forming a channel layer along a side surface and a bottom surface of the opening, the channel layer including an oxide semiconductor; forming an insulating layer covering the channel layer and filling the opening; and performing a planarization process on the insulating layer to expose the molding layer.

[0011] An embodiment of the present invention provides an image sensor, comprising: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a floating diffusion region located on the first surface of the semiconductor substrate; a photoelectric conversion unit located on the second surface of the semiconductor substrate; a channel layer located above the first surface of the semiconductor substrate and disposed within an opening of a molded pattern, the channel layer having a first end and a second end opposite to the first end, the first end being connected to the photoelectric conversion unit and the second end being connected to the floating diffusion region; and a transmission gate electrode adjacent to the channel layer. Attached Figure Description

[0012] Embodiments of the inventive concept will become clearer from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0013] Figure 1 A block diagram of an image sensor according to an embodiment of the present invention is shown.

[0014] Figure 2 A top view of an image sensor according to an embodiment of the present invention is shown.

[0015] Figure 3 It shows along Figure 2 The cross-sectional view taken by line I-I' in the figure illustrates an image sensor according to an embodiment of the present invention.

[0016] Figure 4A It shows Figure 3 Enlarged cross-sectional view of part "II".

[0017] Figure 4B A top view of the channel pattern is shown.

[0018] Figure 5A A circuit diagram of an image sensor according to an embodiment of the present invention is shown.

[0019] Figure 5B A circuit diagram of another image sensor according to an embodiment of the present invention is shown.

[0020] Figure 5C A circuit diagram of yet another image sensor according to an embodiment of the present invention is shown.

[0021] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H It shows along Figure 2 The sequence of cuts along line I-I' in the diagram illustrates a cross-sectional view of the process of manufacturing an image sensor.

[0022] Figure 7 It shows along Figure 2 The cross-sectional view taken by line I-I' in the figure illustrates an image sensor according to an embodiment of the present invention.

[0023] Figure 8A It shows Figure 7 Enlarged cross-sectional view of part "III" in the diagram.

[0024] Figure 8B It shows Figure 7 Circuit diagram of the image sensor.

[0025] Figure 9A , Figure 9B and Figure 9C The manufacturing process is shown in sequence. Figure 7 A cross-sectional view of the image sensor process.

[0026] Figure 10 An embodiment of the invention is shown. Figure 7 Enlarged cross-sectional view of part "III" in the diagram.

[0027] Figure 11 It shows Figure 10 Circuit diagram of the image sensor.

[0028] Figure 12 An embodiment of the invention is shown. Figure 7 Enlarged cross-sectional view of part "III" in the diagram.

[0029] Figure 13 It shows Figure 12 Circuit diagram of the image sensor.

[0030] Figure 14 A top view of an image sensor according to an embodiment of the present invention is shown.

[0031] Figure 15 It shows along Figure 14 The cross-sectional view taken from line VIII-VIII' in the diagram.

[0032] Figure 16 A top view of an image sensor according to an embodiment of the present invention is shown.

[0033] Figure 17 It shows along Figure 16 The cross-sectional view taken from line XI-XI' in the diagram.

[0034] Figure 18A cross-sectional view of an image sensor according to an embodiment of the present invention is shown. Detailed Implementation

[0035] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0036] It should be understood that the accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and are intended to supplement the written description. However, these drawings are not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the range of values ​​or characteristics covered by the exemplary embodiments. For example, the relative thickness and location of molecules, layers, regions, and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features.

[0037] Figure 1 A block diagram of an image sensor according to an embodiment of the present invention is shown.

[0038] Reference Figure 1 The image sensor may include a first photoelectric conversion unit PD1, a second photoelectric conversion unit PD2, and a third photoelectric conversion unit PD3, as well as a first color filter CF1 and a second color filter CF2. The first photoelectric conversion unit PD1 and the second photoelectric conversion unit PD2 may be disposed in a semiconductor substrate 110. The third photoelectric conversion unit PD3 may be disposed on the surface of the semiconductor substrate 110, and the first color filter CF1 and the second color filter CF2 may be disposed between the third photoelectric conversion unit PD3 and the semiconductor substrate 110.

[0039] Light of a first wavelength L1, light of a second wavelength L2, and light of a third wavelength L3 can be incident on the third photoelectric conversion unit PD3. The first and second wavelengths can be different from the third wavelength. For example, light of the first wavelength L1 can correspond to red light, light of the second wavelength L2 can correspond to blue light, and light of the third wavelength L3 can correspond to green light.

[0040] The third photoelectric conversion unit PD3 can generate a third photoelectric signal S3 from light of the third wavelength L3. The third photoelectric conversion unit PD3 can be configured to allow light of the first wavelength L1 and light of the second wavelength L2 to pass through it. The third photoelectric conversion unit PD3 can be shared by multiple first pixels PX1 and multiple second pixels PX2.

[0041] Light L1 and L2 passing through the third photoelectric conversion unit PD3 can be incident on the first color filter CF1 and the second color filter CF2. The first pixel PX1 may include the first color filter CF1 and the first photoelectric conversion unit PD1. The second pixel PX2 may include the second color filter CF2 and the second photoelectric conversion unit PD2. The first photoelectric conversion unit PD1 may be disposed below the first color filter CF1, and the second photoelectric conversion unit PD2 may be disposed below the second color filter CF2.

[0042] Light of wavelength L1 can pass through the first color filter CF1 but not the second color filter CF2. Light of wavelength L2 can pass through the second color filter CF2 but not the first color filter CF1. Light of wavelength L1 passing through the first color filter CF1 can be incident on the first photoelectric conversion unit PD1. The first photoelectric conversion unit PD1 can generate a first photoelectric signal S1 from the first wavelength light L1. Light of wavelength L2 passing through the second color filter CF2 can be incident on the second photoelectric conversion unit PD2. The second photoelectric conversion unit PD2 can generate a second photoelectric signal S2 from the second wavelength light L2.

[0043] Figure 2 A top view of an image sensor according to an embodiment of the present invention is shown. Figure 3 It shows along Figure 2 The cross-sectional view taken by line I-I' in the figure illustrates an image sensor according to an embodiment of the present invention. Figure 4A It shows Figure 3 Enlarged cross-sectional view of part "II" in the diagram. Figure 4B A top view of the channel pattern is shown.

[0044] Reference Figure 2 , Figure 3 , Figure 4A and Figure 4B The semiconductor substrate 110 may include a first pixel PX1 and a second pixel PX2. The semiconductor substrate 110 may be a single-crystal silicon wafer or an epitaxial silicon layer. The semiconductor substrate 110 may be doped with an impurity of a first conductivity type. For example, the first conductivity type may be p-type. The impurity of the first conductivity type may be, for example, boron. The semiconductor substrate 110 may include a first surface 110a and a second surface 110b facing each other. The first surface 110a may be the front surface on which transistors are disposed. The second surface 110b may be the back surface on which light is incident. In one embodiment, the image sensor may be an image sensor that receives incident light through its back surface.

[0045] A deep device isolation portion DI may be disposed in the semiconductor substrate 110 to separate the first pixel PX1 and the second pixel PX2 from each other. The deep device isolation portion DI may include an extension portion DI_E extending in a first direction X, and a protruding portion DI_P protruding from the extension portion DI_E in a second direction Y intersecting the first direction X or in a direction opposite to the second direction. The deep device isolation portion DI may be formed of at least one of, for example, silicon oxide, metal oxide (e.g., hafnium oxide and aluminum oxide), or polycrystalline silicon, or may include at least one of, for example, silicon oxide, metal oxide (e.g., hafnium oxide and aluminum oxide), or polycrystalline silicon.

[0046] When viewed in a top view, the through electrode 120 may be disposed between adjacent protrusions DI_P of the deep device isolation portion DI in the second direction Y. The through electrode 120 may extend in a third direction Z intersecting the first direction X and the second direction Y. The through electrode 120 may comprise doped polysilicon or a conductive material (e.g., tungsten). A via insulating layer 122 may be inserted between the through electrode 120 and the semiconductor substrate 110. The via insulating layer 122 may be formed of, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, or may comprise, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure.

[0047] The shallow device isolation portion 3 may be disposed in the first surface 110a of the semiconductor substrate 110 to define the active region of the first pixel PX1 and the active region of the second pixel PX2. The shallow device isolation portion 3 may be formed of at least one of silicon oxide, silicon nitride, or silicon oxynitride, or may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0048] The top surface of the through electrode 120 and the top surface of the via insulating layer 122 may be located at a horizontal height equal to or lower than the bottom surface of the shallow device isolation portion 3. An insulating gap filling layer 5 may be disposed on the through electrode 120 and the via insulating layer 122. The insulating gap filling layer 5 may be formed of at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride, or may include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The bottom surface of the through electrode 120 and the bottom surface of the via insulating layer 122 may be substantially coplanar with the second surface 110b of the semiconductor substrate 110.

[0049] In the first pixel PX1, a first photoelectric conversion unit PD1 can be disposed in the semiconductor substrate 110. In the second pixel PX2, a second photoelectric conversion unit PD2 can be disposed in the semiconductor substrate 110. The first photoelectric conversion unit PD1 and the second photoelectric conversion unit PD2 can be impurity regions doped to have a second conductivity type different from the first conductivity type. For example, the second conductivity type can be n-type, and the impurity of the second conductivity type can be phosphorus or arsenic. The first photoelectric conversion unit PD1, the second photoelectric conversion unit PD2, and the adjacent semiconductor substrate 110 can form a pn junction used as a photodiode.

[0050] In the first pixel PX1, a first transfer gate electrode TG1 may be disposed on a first surface 110a of the semiconductor substrate 110. In the second pixel PX2, a second transfer gate electrode TG2 may be disposed on the first surface 110a of the semiconductor substrate 110. A first gate insulating layer 7 may be inserted between the first transfer gate electrode TG1 and the semiconductor substrate 110, and between the second transfer gate electrode TG2 and the semiconductor substrate 110. The gate insulating layer 7 may include, for example, a silicon oxide layer.

[0051] In the first pixel PX1, a first floating diffusion region FD1 may be disposed adjacent to the first transmission gate electrode TG1 in the semiconductor substrate 110. A third floating diffusion region FD3 may be disposed in the region of the semiconductor substrate 110 adjacent to the first surface 110a. The third floating diffusion region FD3 may be spaced apart from the first floating diffusion region FD1 by a shallow device isolation portion 3. In the second pixel PX2, a second floating diffusion region FD2 may be disposed adjacent to the second transmission gate electrode TG2 in the semiconductor substrate 110. A third floating diffusion region FD3 may be disposed in the region of the semiconductor substrate 110 adjacent to the first surface 110a. The third floating diffusion region FD3 may be spaced apart from the second floating diffusion region FD2 by a shallow device isolation portion 3. The first floating diffusion region FD1, the second floating diffusion region FD2, and the third floating diffusion region FD3 may be impurity regions doped with impurities of a second conductivity type.

[0052] The first surface 110a of the semiconductor substrate 110 may be covered by a first interlayer insulating layer 9. The first interlayer insulating layer 9 may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, or porous oxide materials, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or porous oxide materials. A first recessed region RS, a second recessed region RG, and a third recessed region RD spaced apart from each other may be formed on the upper part of the first interlayer insulating layer 9. A first contact hole RC1 may be formed below the first recessed region RS, and a second contact hole RC2 may be formed below the third recessed region RD. A source electrode 13s may be disposed in the first recessed region RS. A third transfer gate electrode TG3 may be disposed in the second recessed region RG. A drain electrode 13d may be disposed in the third recessed region RD. A first-stage first contact plug 13c1 may be disposed in the first contact hole RC1 to electrically connect the source electrode 13s to the through electrode 120. The first-stage first contact plug 13c1 may extend into the insulating gap filling layer 5 and may be connected to the through electrode 120. A first-stage second contact plug 13c2 may be disposed in a second contact hole RC2 to electrically connect the drain electrode 13d to a third floating diffusion region FD3. A first-stage third contact plug 13c3, spaced apart from the first-stage second contact plug 13c2 and electrically connected to either the first floating diffusion region FD1 or the second floating diffusion region FD2, may be disposed in a first interlayer insulating layer 9. The first-stage contact plugs 13c1, 13c2, and 13c3, the source electrode 13s, the drain electrode 13d, and the third transfer gate electrode TG3 may be formed of the same conductive material (e.g., tungsten), or may include the same conductive material (e.g., tungsten). A first diffusion barrier layer 11 may be disposed covering the side and bottom surfaces of the first-stage contact plugs 13c1, 13c2, and 13c3, the source electrode 13s, the drain electrode 13d, and the third transfer gate electrode TG3. The first diffusion barrier layer 11 may include, for example, a titanium nitride layer. The top surfaces of the third contact plug 13c3, the source electrode 13s, the drain electrode 13d, and the third transmission gate electrode TG3 can be substantially coplanar with the top surface of the first interlayer insulating layer 9.

[0053] The first etch stop layer 12 may be disposed on the third transfer gate electrode TG3. The first etch stop layer 12 may be formed of an insulating layer having etch selectivity relative to the first interlayer insulating layer 9. For example, the first etch stop layer 12 may be formed of a silicon nitride layer.

[0054] The second gate insulating layer 14 may be disposed on the third transmission gate electrode TG3. The second gate insulating layer 14 may be formed of at least one of, for example, silicon oxide or a metal oxide material with a dielectric constant higher than silicon oxide (e.g., aluminum oxide), or may include at least one of, for example, silicon oxide or a metal oxide material with a dielectric constant higher than silicon oxide (e.g., aluminum oxide). A portion of the first etch stop layer 12 may be inserted between the second gate insulating layer 14 and the third transmission gate electrode TG3, and may serve as an additional gate insulating layer.

[0055] A molded pattern MP may be disposed on the second gate insulating layer 14. The molded pattern MP may be disposed on the third transfer gate electrode TG3. More specifically, the molded pattern MP may extend from a region on the third transfer gate electrode TG3 to regions on the source electrode 13s and the drain electrode 13d. In one embodiment, the molded pattern MP may be formed of at least one of silicon nitride or silicon oxynitride, or may include at least one of silicon nitride or silicon oxynitride. The side surface of the second gate insulating layer 14 may be aligned with the side surface of the molded pattern MP. The side surface of the first etch stop layer 12 may be aligned with the side surface of the molded pattern MP. The molded pattern MP may include an opening OP. The opening OP may be formed to expose the source electrode 13s and the drain electrode 13d.

[0056] The channel pattern CHL can be placed within the opening OP. The channel pattern CHL can be locally confined within the opening OP. The channel pattern CHL can cover the source electrode 13s, the drain electrode 13d, and the second gate insulating layer 14. The channel pattern CHL can be formed of or include an oxide semiconductor material. For example, the oxide semiconductor material can include at least one of indium (In), gallium (Ga), zinc (Zn), or tin (Sn). In one embodiment, the oxide semiconductor material can be indium gallium zinc oxide (IGZO) containing indium (In), gallium (Ga), and zinc (Zn). In one embodiment, the oxide semiconductor material can be amorphous IGZO. The third transfer gate electrode TG3, the source electrode 13s, the drain electrode 13d, the second gate insulating layer 14, and the channel pattern CHL can constitute... Figure 5C The third transmission transistor Tx3. The channel pattern CHL can penetrate the second gate insulating layer 14 and the first etch stop layer 12. The remaining gate insulating layer 14r can extend laterally from the side surface of the channel pattern CHL.

[0057] The channel pattern CHL may include a sidewall portion SP covering the side surface of the opening OP and a central portion CP extending from the sidewall portion to a region defining the bottom surface of the opening OP on the first interlayer insulation layer 9. The sidewall portion SP may contact the molded pattern MP. As an example, the channel pattern CHL may be a structure that conformally extends along the side and bottom surfaces of the opening OP. When viewed in a top view, the sidewall portion SP may be an annular ring extending along the edge of the central portion CP. Figure 4B In the illustration, the sidewall portion SP is shown as having a rectangular ring shape, but the inventive concept is not limited to this example. For example, when viewed in a top view, the sidewall portion SP can be configured to have a circular ring shape.

[0058] The central portion CP may include a first central portion CP1 connected to the sidewall portion SP and a second central portion CP2 protruding from the first central portion CP1 in a direction away from the semiconductor substrate 110 (i.e., the third direction Z). The first central portion CP1 may contact the top surface of the source electrode 13s and the top surface of the drain electrode 13d. The second central portion CP2 may cover the second gate insulating layer 14.

[0059] A planarization pattern BP can be formed on a channel pattern CHL to fill an opening OP. The planarization pattern BP can be formed of at least one of silicon oxide or oxynitride, or include at least one of silicon oxide or oxynitride. As a result of the planarization process described below, the top surface BT of the planarization pattern BP can be planar. The top surface BT of the planarization pattern BP can be coplanar with the top surface CT of the channel pattern CHL. As an example, the top surface BT of the planarization pattern BP and the top surface CT of the channel pattern CHL can be located at substantially the same height. The top surface BT of the planarization pattern BP can be coplanar with the top surface MT of the molded pattern MP. In this specification, the term "coplanar" will be used to indicate that, due to the planarization process, the components have substantially the same height within a small difference given by the process margin.

[0060] An intermediate layer CL can be disposed between the channel pattern CHL and the planarization pattern BP. As an example, the intermediate layer CL may include a metal nitride layer (e.g., TiN) or a silicon nitride layer. The top surface LT of the intermediate layer CL may be coplanar with the top surface BT of the planarization pattern BP and the top surface CT of the channel pattern CHL. In some embodiments, the intermediate layer CL may be omitted, and the channel pattern CHL and the planarization pattern BP may be in contact with each other.

[0061] An upper insulating pattern 81 can be provided to cover the molded pattern MP, the channel pattern CHL, and the planarization pattern BP. As an example, the upper insulating pattern 81 can be configured to conformally (i.e., with substantially the same thickness) cover the top surface MT of the molded pattern MP, the top surface CT of the channel pattern CHL, and the top surface BT of the planarization pattern BP, which are coplanar with each other. The side surfaces of the upper insulating pattern 81 can be aligned with the outer surface of the molded pattern MP. The upper insulating pattern 81 can be formed of at least one of silicon nitride or silicon oxynitride, or include at least one of silicon nitride or silicon oxynitride.

[0062] The second interlayer insulation layer 17 can be disposed on the upper insulation pattern 81. The second-stage line 21w and the second-stage contact plug 21c can be disposed within the second interlayer insulation layer 17. The side and bottom surfaces of the second-stage line 21w and the second-stage contact plug 21c can be covered by the second diffusion barrier layer 19. The second-stage line 21w and the second-stage contact plug 21c can contain a metal material different from the metal material of the source electrode 13s, the third transfer gate electrode TG3, and the drain electrode 13d. As an example, the second-stage line 21w and the second-stage contact plug 21c can contain copper.

[0063] The third etch stop layer 23 and the third interlayer insulating layer 25 can be sequentially formed on the second interlayer insulating layer 17. The third-level line 29w and the third-level contact plug 29c can be disposed in the third interlayer insulating layer 25. The side and bottom surfaces of the third-level line 29w and the third-level contact plug 29c can be covered by the third diffusion barrier layer 27. The fourth etch stop layer 31 and the fourth interlayer insulating layer 33 can be sequentially stacked on the third interlayer insulating layer 25. The fourth-level line 37 and the fourth diffusion barrier layer 35 can be disposed in the fourth interlayer insulating layer 33, and here, the fourth diffusion barrier layer 35 can be configured to cover the side and bottom surfaces of the fourth-level line 37. The fourth interlayer insulating layer 33 can be covered by the first passivation layer 39. The third etch stop layer 23 and the fourth etch stop layer 31 can include, for example, silicon nitride layers. The third interlayer insulating layer 25 and the fourth interlayer insulating layer 33 can include, for example, silicon oxide layers or porous insulating layers. The third-level line 29w, the third-level contact plug 29c, and the fourth-level line 37 may include, for example, copper. The third diffusion barrier layer 27 and the fourth diffusion barrier layer 35 may include, for example, metal nitride layers (e.g., titanium nitride layers). The passivation layer 39 may include, for example, a silicon nitride layer or a polyimide layer.

[0064] A protective layer 50 may be disposed on a second surface 110b of the semiconductor substrate 110. The protective layer 50 may include an insulating layer (e.g., a silicon oxide layer). In one embodiment, the protective layer 50 may be in contact with the second surface 110b and may have a negative fixed charge. Here, the protective layer 50 may be formed of a metal oxide or metal fluoride comprising at least one metallic element selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), and lanthanides. For example, the protective layer 50 may be formed of, or comprise hafnium oxide or aluminum oxide.

[0065] In the first pixel PX1, a first color filter CF1 can be disposed on the protective layer 50. In the second pixel PX2, a second color filter CF2 can be disposed on the protective layer 50. The first color filter CF1 and the second color filter CF2 can include pigments or dyes of different colors. A first insulating pattern 54 can be inserted between the first color filter CF1 and the second color filter CF2. In one embodiment, the first insulating pattern 54 can be formed of a material with a refractive index lower than that of the first color filter CF1 and the second color filter CF2, or can include a material with a refractive index lower than that of the first color filter CF1 and the second color filter CF2. In this case, the amount of light incident on pixels PX1 and PX2 can be increased, and the photosensitivity of pixels PX1 and PX2 can be improved.

[0066] Pixel electrodes 58 can be disposed on the first color filter CF1 and the second color filter CF2, respectively. A second insulating pattern 52 can be inserted between the pixel electrode 58 and each of the first color filter CF1 and the second color filter CF2. The second insulating pattern 52 can be formed of at least one of insulating materials (e.g., silicon oxide or silicon nitride), or include at least one of insulating materials (e.g., silicon oxide or silicon nitride). Pixel electrodes 58 can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or organic transparent conductive materials. Pixel electrodes 58 can be electrically connected to the through electrode 120 via a first through-hole plug 56 penetrating the first insulating pattern 54. A third insulating pattern 60 can be inserted between the pixel electrodes 58.

[0067] The third photoelectric conversion unit PD3 can be disposed on the pixel electrode 58. The third photoelectric conversion unit PD3 can be, for example, an organic photoelectric conversion layer. The third photoelectric conversion unit PD3 can include p-type organic semiconductor materials and n-type organic semiconductor materials, and the p-type organic semiconductor materials and n-type organic semiconductor materials can form a pn junction. In one embodiment, the third photoelectric conversion unit PD3 can be formed of at least one of quantum dots or chalcogenide materials, or include at least one of quantum dots or chalcogenide materials.

[0068] A common electrode 62 can be disposed on the third photoelectric conversion unit PD3. The common electrode 62 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or an organic transparent conductive material. Pixel electrodes 58 can be disposed in each pixel, while the third photoelectric conversion unit PD3 and the common electrode 62 can be continuous and disposed on the entire second surface 110b of the semiconductor substrate 110. A second passivation layer 64 can be disposed on the common electrode 62. A microlens ML can be disposed on the second passivation layer 64.

[0069] Figure 5A , Figure 5B and Figure 5C Various circuit diagrams of an image sensor according to an embodiment of the present invention are shown.

[0070] Reference Figures 1 to 3 , Figure 4A , Figure 4B and Figures 5A to 5C A first transmission transistor Tx1, including a first transmission gate electrode TG1 and a first floating diffusion region FD1, can be provided in the first pixel PX1. A first reset transistor Rx1, including a first reset gate electrode RG1, a first source follower transistor SFx1, including a first source follower gate electrode SF1, and a first selection transistor SELx1, including a first selection gate electrode SEL1, can be provided in the first pixel PX1. A second transmission transistor Tx2, including a second transmission gate electrode TG2 and a second floating diffusion region FD2, can be provided in the second pixel PX2. A second reset transistor Rx2, including a second reset gate electrode RG2, a second source follower transistor SFx2, including a second source follower gate electrode SF2, and a second selection transistor SELx2, including a second selection gate electrode SEL2, can be provided in the second pixel PX2. Both the first pixel PX1 and the second pixel PX2 can include a third transmission transistor Tx3, which includes a third transmission gate electrode TG3 and a third floating diffusion region FD3.

[0071] A third reset transistor Rx3, including a third reset gate electrode RG3, a third source follower transistor SFx3, including a third source follower gate electrode SF3, and a third select transistor SELx3, including a third select gate electrode SEL3, can be provided in the first pixel PX1 or the second pixel PX2. The first to third reset transistors Rx1, Rx2, and Rx3, and the first to third source follower transistors SFx1, SFx2, and SFx3 can be connected to a voltage V. DD The first pixel PX1 and the second pixel PX2 can share the first to third reset transistors Rx1, Rx2, and Rx3. For example, a reset transistor can be electrically connected to the first to third transmission transistors Tx1, Tx2, and Tx3, and can also serve as the first to third reset transistors Rx1, Rx2, and Rx3. Similarly, the first pixel PX1 and the second pixel PX2 can share the first to third source follower transistors SFx1, SFx2, and SFx3, and the first to third select transistors SELx1, SELx2, and SELx3.

[0072] The color information obtained by the first photoelectric conversion unit PD1 can be output as a first signal Vout1 through the first transmission transistor Tx1, the first reset transistor Rx1, the first source follower transistor SFx1, and the first selection transistor SELx1. The color information obtained by the second photoelectric conversion unit PD2 can be output as a second signal Vout2 through the second transmission transistor Tx2, the second reset transistor Rx2, the second source follower transistor SFx2, and the second selection transistor SELx2. The color information obtained by the third photoelectric conversion unit PD3 can be output as a third signal Vout3 through the third transmission transistor Tx3, the third reset transistor Rx3, the third source follower transistor SFx3, and the third selection transistor SELx3.

[0073] According to the embodiments described above based on the present invention, the image sensor may include a third transfer transistor Tx3 for transferring the charge generated in the third photoelectric conversion unit PD3. That is, the image sensor may include a 4-transistor CDS (correlated double sampling) circuit with four transistors for transmitting each color information. This can reduce reset noise. Furthermore, the third transfer transistor Tx3 allows for faster transfer of the charge generated in the third photoelectric conversion unit PD3 to the third floating diffusion region FD3. Therefore, a highly integrated image sensor capable of achieving improved image quality can be provided.

[0074] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H The manufacturing process with [the following text is incomplete and likely refers to a process or method] is shown sequentially. Figure 2 The process of capturing the image sensor's vertical cross-section from line I-I'.

[0075] Reference Figure 2 and Figure 6A A semiconductor substrate 110 comprising a first pixel PX1 and a second pixel PX2 can be fabricated. The semiconductor substrate 110 may be doped with impurities of a first conductivity type (e.g., p-type conductivity). The first photoelectric conversion portion PD1 and the second photoelectric conversion portion PD2 can be formed in the semiconductor substrate 110 by performing several ion implantation processes and a heat treatment process. The first photoelectric conversion portion PD1 and the second photoelectric conversion portion PD2 may be doped to have a second conductivity type different from the first conductivity type (e.g., n-type conductivity). A shallow trench isolation (STI) process can be performed to form a shallow device isolation portion 3 in the semiconductor substrate 110 and near the first surface 110a. A device isolation portion 3 can be formed between pixels PX1 and PX2 in the following manner. Figure 2 Deep device isolation section DI: Deep trenches are formed by patterning the shallow device isolation section 3 and the semiconductor substrate 110 below it, and an insulating layer and a polysilicon layer are sequentially formed to fill the deep trenches, and then a polishing or etching-back process is performed on the insulating layer and the polysilicon layer.

[0076] The protruding portion DI_P of the deep device isolation portion DI can be partially removed to form a through-hole. Then, a via insulating layer 122 and a conductive layer can be formed to fill the through-hole. A polishing or etching process can then be performed to form a through electrode 120 in the through-hole. The upper portion of the through electrode 120 can be recessed, and an insulating gap filling layer 5 can be formed to fill the recessed portion. In the first pixel PX1 and the second pixel PX2, a first gate insulating layer 7 and a first transfer gate electrode TG1 and a second transfer gate electrode TG2 can be formed on a first surface 110a of the semiconductor substrate 110. Both the first transfer gate electrode TG1 and the second transfer gate electrode TG2 can be formed to have portions extending into the semiconductor substrate 110. An ion implantation process can be performed to form a first floating diffusion region FD1 and a second floating diffusion region FD2 in the portions of the semiconductor substrate 110 surrounding the first transfer gate electrode TG1 and the second transfer gate electrode TG2. In one embodiment, during this step, a third floating diffusion region FD3 can be formed in the region of the semiconductor substrate 110 defined by the shallow device isolation portion 3. A first interlayer insulating layer 9 can be formed to cover the first surface 110a of the semiconductor substrate 110.

[0077] Reference Figure 6BThe first interlayer insulating layer 9 can be etched to form a first recessed region RS, a second recessed region RG, and a third recessed region RD, as well as a first contact hole RC1, a second contact hole RC2, and a third contact hole RC3. The first recessed region RS and the first contact hole RC1 can be formed with a dual-damascene structure, and the third recessed region RD and the second contact hole RC2 can be formed with a dual-damascene structure. During the formation of the first contact hole RC1, a portion of the insulating gap filling layer 5 can be etched to expose a portion of the top surface of the through electrode 120. The second contact hole RC2 can be formed to expose a third floating diffusion region FD3. The third contact hole RC3 can be formed to expose the first floating diffusion region FD1 and the second floating diffusion region FD2, respectively. The first diffusion barrier layer 11 and the conductive layer (e.g., tungsten) can be sequentially formed on the first interlayer insulating layer 9 and the insulating gap filling layer 5 to fill the first recessed region RS, the second recessed region RG and the third recessed region RD, as well as the first contact hole RC1, the second contact hole RC2 and the third contact hole RC3. Then, a polishing or etching process can be performed to form the source electrode 13s, the third transfer gate electrode TG3, the drain electrode 13d and the first-stage contact plugs 13c1, 13c2 and 13c3.

[0078] Reference Figure 6C A first etch stop layer 12 and a second gate insulating layer 14 may be sequentially formed on the first interlayer insulating layer 9. The first etch stop layer 12 may be formed of, for example, silicon nitride, or may include, for example, silicon nitride. The second gate insulating layer 14 may be formed of, for example, aluminum oxide or silicon oxide, or may include, for example, aluminum oxide or silicon oxide. A molding layer MLL may be formed on the second gate insulating layer 14. The molding layer MLL may be formed of at least one of silicon nitride or silicon oxynitride, or may include at least one of silicon nitride or silicon oxynitride. The molding layer MLL may be patterned to form an opening OP in the region overlapping with the source electrode 13s, the third transfer gate electrode TG3, and the drain electrode 13d.

[0079] Reference Figure 6D The second gate insulating layer 14 and the first etch stop layer 12, exposed through the opening OP, can be etched to expose the top surfaces of the source electrode 13s and the drain electrode 13d. As a result, the opening OP can be expanded to expose both the source electrode 13s and the drain electrode 13d. During this etching, the portions of the second gate insulating layer 14 covering the third transfer gate electrode TG3 and the portions of the first etch stop layer 12 covering the third transfer gate electrode TG3 are not removed.

[0080] Reference Figure 6EA channel layer 140, an intermediate layer CL, and a planarization layer BL can be formed sequentially. As described above, the intermediate layer CL can be omitted. The channel layer 140 can be conformally formed along the side and bottom surfaces of the opening OP. The channel layer 140 can be formed of an oxide semiconductor material (e.g., IGZO), or include an oxide semiconductor material (e.g., IGZO). The channel layer 140 is formed to contact the source electrode 13s and the drain electrode 13d. The intermediate layer CL can include a metal nitride layer (e.g., TiN) or a silicon nitride layer. The planarization layer BL can include at least one of a silicon oxide layer or an oxynitride layer.

[0081] Reference Figure 6F A planarization process can be performed. As an example, the planarization process can be a chemical mechanical polishing process. A planarization process can be performed to expose the top surface of the molding layer MLL. As a result of the planarization process, the upper portion of the channel layer 140 on the molding layer MLL can be removed to form a channel pattern CHL in the opening OP. In other words, the channel pattern CHL can be formed by a damascene process. Similarly, the upper portion of the planarization layer BL can be removed to form a planarization pattern BP in the opening OP. After the planarization process, an upper insulating layer 80 can be formed to cover the molding layer MLL and the planarization pattern BP. The upper insulating layer 80 can be formed of at least one of silicon nitride or silicon oxynitride, or includes at least one of silicon nitride or silicon oxynitride.

[0082] Reference Figure 6G The upper insulating layer 80 and the molding layer MLL can be patterned sequentially to form an upper insulating pattern 81 and a molding pattern MP. In one embodiment, the second gate insulating layer 14 and the first etch stop layer 12 can also be patterned in this step. As a result, the remaining gate insulating layer 14r can be formed. The patterning process can be performed until the first-stage third contact plug 13c3 is exposed. However, in some embodiments, a portion of the first etch stop layer 12 may remain on the first-stage third contact plug 13c3. After the patterning process, an etch stop layer can be formed to cover the exposed portion of the first interlayer insulating layer 9 and the upper insulating pattern 81. However, in some embodiments, the formation of the etch stop layer covering the exposed portion of the first interlayer insulating layer 9 and the upper insulating pattern 81 may be omitted.

[0083] Reference Figure 6H The second interlayer insulating layer 17, the third interlayer insulating layer 25 and the fourth interlayer insulating layer 33, the third etch stop layer 23, the fourth etch stop layer 31, the second-level line 21w, the second-level contact plug 21c, the third-level line 29w, the third-level contact plug 29c, the fourth-level line 37 and the first passivation layer 39 can be formed by conventional back-end-of-line (BEOL) processes.

[0084] Return to reference Figure 3 A polishing process can be performed on the second surface 110b of the semiconductor substrate 110 to remove a portion of the semiconductor substrate 110 and expose the through electrode 120. A protective layer 50, color filters CF1 and CF2, a first insulating pattern 54, a first via plug 56, a pixel electrode 58, a third insulating pattern 60, a third photoelectric conversion unit PD3, a common electrode 62, a second passivation layer 64, and a microlens ML can be formed on the second surface 110b of the semiconductor substrate 110.

[0085] In a method for manufacturing an image sensor according to an embodiment of the present invention, a channel pattern CHL comprising an oxide semiconductor material can be formed by a damascene process. Therefore, the size of the transistors in the image sensor can be reduced. Additionally, contamination problems that may occur, for example, when performing etching and cleaning processes on the oxide semiconductor layer, can be prevented. In a method for manufacturing an image sensor according to an embodiment of the present invention, the channel pattern CHL made of oxide semiconductor material can be formed prior to the BEOL process. Most interconnects in the BEOL process can be formed of copper; therefore, it is important to prevent copper contamination of the device in the BEOL process. When using oxide semiconductor materials such as IGZO in the BEOL process, the device may be contaminated by IGZO, and in some cases, it may be necessary to change the process sequence in the conventional BEOL process, thus increasing process complexity. In contrast, in a method for manufacturing an image sensor according to an embodiment of the present invention, since the channel pattern CHL made of oxide semiconductor material is formed prior to the BEOL process, these problems can be avoided and process failures can be reduced or suppressed.

[0086] Figure 7 It shows along Figure 2 A cross-sectional view taken from line I-I' in the diagram. Figure 2 An image sensor according to an embodiment of the present invention is shown. Figure 8A It shows Figure 7 Enlarged cross-sectional view of part "III" in the diagram. Figure 8B It shows Figure 7 The circuit diagram of the image sensor. For the sake of simplicity, the previously described components may be identified by the same reference numerals or characters without repeating their descriptions.

[0087] Reference Figure 7 and Figure 8AThe image sensor according to this embodiment may include a first-stage source electrode 13s, a first-stage third transfer gate electrode TG31, and a first-stage drain electrode 13d, which are spaced apart from each other in the first interlayer insulating layer 9. A third gate insulating layer 16 may be disposed on a channel pattern CHL. The third gate insulating layer 16 may be an aluminum oxide layer or a silicon oxide layer. A second-stage third transfer gate electrode TG32 may be disposed on (above) the third gate insulating layer 16. The second-stage third transfer gate electrode TG32 may perpendicularly overlap with the first-stage third transfer gate electrode TG31. The first-stage third transfer gate electrode TG31 may have a first width W1. The second-stage third transfer gate electrode TG32 may have a second width W2. The first width W1 may be greater than the second width W2.

[0088] The second-stage source electrode 21s and the second-stage drain electrode 21d can be disposed on (above) the channel pattern CHL and can be spaced apart from the second-stage third transfer gate electrode TG32. The third gate insulating layer 16 can extend to include a portion inserted between the channel pattern CHL and the second-stage source electrode 21s and a portion located between the channel pattern CHL and the second-stage drain electrode 21d. When viewed in a top view, the second-stage source electrode 21s can overlap with the first-stage source electrode 13s. When viewed in a top view, the second-stage drain electrode 21d can overlap with the first-stage drain electrode 13d.

[0089] The second-stage source electrode 21s, the second-stage drain electrode 21d, and the second-stage third transfer gate electrode TG32 may comprise metallic materials different from those of the first-stage source electrode 13s, the first-stage drain electrode 13d, and the first-stage third transfer gate electrode TG31. For example, the first-stage source electrode 13s, the first-stage drain electrode 13d, and the first-stage third transfer gate electrode TG31 may comprise tungsten, while the second-stage source electrode 21s, the second-stage drain electrode 21d, and the second-stage third transfer gate electrode TG32 may comprise copper.

[0090] The side and bottom surfaces of the second-stage source electrode 21s, the second-stage drain electrode 21d, and the second-stage third transmission gate electrode TG32 may be covered by the second diffusion barrier layer 19. A first cover pattern 18s may be inserted between the second-stage source electrode 21s and the third gate insulating layer 16. A second cover pattern 18g may be inserted between the second-stage third transmission gate electrode TG32 and the third gate insulating layer 16. The second cover pattern 18g may have a third width W3. The third width W3 may be greater than the second width W2. A third cover pattern 18d may be inserted between the second-stage drain electrode 21d and the third gate insulating layer 16. The first cover pattern 18s, the second cover pattern 18g, and the third cover pattern 18d may be spaced apart from each other and may have substantially the same thickness and substantially the same material. In one embodiment, the first cover pattern 18s, the second cover pattern 18g, and the third cover pattern 18d may be formed of at least one of a metal nitride material (e.g., titanium nitride), or may include at least one of a metal nitride material (e.g., titanium nitride).

[0091] In one embodiment, the first-stage third transfer gate electrode TG31 and the second-stage third transfer gate electrode TG32 can be electrically connected to each other via an additional via plug (not shown). Here, the first-stage third transfer gate electrode TG31 and the second-stage third transfer gate electrode TG32 can behave like a single transfer gate electrode (e.g., Figure 5C The third transmission gate electrode TG3).

[0092] In one embodiment, only the second-stage third transfer gate electrode TG32 can behave like Figure 5C Similar to the third transmission gate electrode TG3, the first-stage third transmission gate electrode TG31 can be without applied voltage and can be in an electrically floating state. In this case, the first-stage third transmission gate electrode TG31 can be used as a light-shielding pattern instead of a gate electrode. Since the first width W1 is greater than the second width W2, light incident through the second surface 110b can be prevented from entering the channel pattern CHL located below the second-stage third transmission gate electrode TG32. Therefore, it is possible to prevent... Figure 5C The threshold voltage of the third transmission transistor Tx3 changes.

[0093] In some embodiments, voltages can be applied to the first-stage third transfer gate electrode TG31 and the second-stage third transfer gate electrode TG32, and the first-stage third transfer gate electrode TG31 and the second-stage third transfer gate electrode TG32 can be used to control the movement of charges in the channel pattern CHL. In this case, the third transfer transistor Tx3 can be... Figure 8BThe third transfer transistor Tx3 is essentially the same. The first-stage third transfer gate electrode TG31 or the second-stage third transfer gate electrode TG32 can be used as the back gate electrode. Furthermore, a voltage can be applied to the second-stage source electrode 21s and the second-stage drain electrode 21d. The second-stage source electrode 21s and the second-stage drain electrode 21d can be disposed on the third gate insulating layer 16 and can be used as additional auxiliary gate electrodes. In this case, the movement of charge in the channel pattern CHL can be controlled by the first-stage third transfer gate electrode TG31, the second-stage third transfer gate electrode TG32, the second-stage source electrode 21s, and the second-stage drain electrode 21d. Other components and their operation can be referenced. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B The components and their operations are basically the same or similar, so these descriptions are omitted for the sake of brevity.

[0094] Figure 9A , Figure 9B and Figure 9C The manufacturing process is shown in sequence. Figure 7 A cross-sectional view of the image sensor process.

[0095] Reference Figure 9A , can Figure 6D A channel layer 140 is formed on the resulting structure, and then a third gate insulating layer 16 and a capping layer can be sequentially and conformally stacked on the channel layer 140. The capping layer can be formed of, for example, titanium nitride, or include, for example, titanium nitride. The third gate insulating layer 16 can be formed of, for example, aluminum oxide or silicon oxide, or include, for example, aluminum oxide or silicon oxide. A patterning process can be performed on the capping layer to form a first capping pattern 18s, a second capping pattern 18g, and a third capping pattern 18d. Subsequently, a planarization layer BL can be formed to cover the structure including the first capping pattern 18s, the second capping pattern 18g, and the third capping pattern 18d.

[0096] Reference Figure 9B , can execute reference Figure 6F and Figure 6G The process is described. As a result, a channel pattern CHL, an upper insulating pattern 81, a planarization pattern BP, and a molding pattern MP can be formed. The planarization pattern BP is shown as filling the area between the first cover pattern 18s, the second cover pattern 18g, and the third cover pattern 18d, but in one embodiment, the planarization pattern BP may extend into the area between the second cover pattern 18g and the upper insulating pattern 81.

[0097] Reference Figure 9CThe second interlayer insulating layer 17 can be stacked on the semiconductor substrate 110 and can be etched to form trenches that expose the first cover pattern 18s, the second cover pattern 18g, and the third cover pattern 18d, respectively. In this etching process, the first cover pattern 18s, the second cover pattern 18g, and the third cover pattern 18d can be used as etch stop layers, so the third gate insulating layer 16 can be protected by the first cover pattern 18s, the second cover pattern 18g, and the third cover pattern 18d. Then, a second diffusion barrier layer 19 can be conformally formed on the second interlayer insulating layer 17, and conductive layers can be stacked to fill the trench regions 17s, 17g, and 17d and the second-stage contact hole 17c. Then, a polishing process can be performed to form the second-stage source electrode 21s, the second-stage third transfer gate electrode TG32, the second-stage drain electrode 21d, and the second-stage contact plug 21c. Next, it can be compared with a reference... Figure 6H and Figure 3 The subsequent processes are performed in the same or similar manner as described.

[0098] Figure 10 An embodiment of the invention is shown. Figure 7 Enlarged cross-sectional view of part "III" in the diagram. Figure 11 It shows Figure 10 Circuit diagram of the image sensor.

[0099] Reference Figure 10 and Figure 11 In the image sensor according to this embodiment, the third gate insulating layer 16 is not inserted between the channel pattern CHL and the second-stage source electrode 21s, and is not inserted between the channel pattern CHL and the second-stage drain electrode 21d. Below the second-stage source electrode 21s and below the second-stage drain electrode 21d, the second diffusion barrier layer 19 can penetrate the first cover pattern 18s, the third cover pattern 18d, and the third gate insulating layer 16, and can directly contact the channel pattern CHL. In other words, the second-stage source electrode 21s and the second-stage drain electrode 21d can be electrically connected to the channel pattern CHL. In this case, with Figure 7 , Figure 8A and Figure 8B Compared to previous embodiments, the second-stage source electrode 21s and the second-stage drain electrode 21d are not used as auxiliary gate electrodes. Therefore, Figure 10 In this embodiment, the movement of charges in the channel pattern CHL can be controlled by the first-stage third transfer gate electrode TG31 and the second-stage third transfer gate electrode TG32. Other components and their operation can be referenced. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5BThe components and their operations described are basically the same or similar, and these descriptions are omitted for the sake of brevity.

[0100] Figure 12 An embodiment of the invention is shown. Figure 7 Enlarged cross-sectional view of part "III". Figure 13 It shows Figure 12 Circuit diagram of the image sensor.

[0101] Reference Figure 12 and Figure 13 In the image sensor according to this embodiment of the present invention, the third transmission gate electrode TG3', the source electrode 37s, and the drain electrode 37d are disposed in the second interlayer insulating layer 17. (See Figure 4.) Figure 8A and Figure 10 Compared to previous embodiments, the third transfer gate electrode TG3' is disposed in the second interlayer insulating layer 17. In some embodiments, the third transfer gate electrode TG3', source electrode 37s, and drain electrode 37d may be disposed in the third interlayer insulating layer 25 or the fourth interlayer insulating layer 33. In this embodiment, the first-stage contact plugs 13c1, 13c2, and 13c3 may be formed of, for example, tungsten, or may include, for example, tungsten. The third transfer gate electrode TG3', drain electrode 37d, and source electrode 37s may all be formed of copper, or may include, copper.

[0102] The source electrode 37s and drain electrode 37d can be used as auxiliary gate electrodes. For example, the movement of charge in the channel pattern CHL of the third transfer transistor Tx3 can be controlled by the source electrode 37s, the third transfer gate electrode TG3', and the drain electrode 37d. Other components and their operation can be referenced. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B The components and their operations described are basically the same or similar, and these descriptions are omitted for the sake of brevity.

[0103] Figure 14 A top view of an image sensor according to an embodiment of the present invention is shown. Figure 15 It shows along Figure 14 The cross-sectional view taken from line VIII-VIII' in the diagram.

[0104] Reference Figure 14 and Figure 15In the image sensor according to this embodiment, each pixel PX1 or PX2 can be configured to simultaneously acquire information about three different colors. In each pixel PX1 or PX2, a first photoelectric conversion unit PD1 can be disposed in the semiconductor substrate 110. The first photoelectric conversion unit PD1 can be, for example, an impurity region doped with n-type impurities. A first through-electrode 120a and a second through-electrode 120b, spaced apart from each other, can be disposed in the semiconductor substrate 110. A first through-electrode insulating layer 122a can be inserted between the first through-electrode 120a and the semiconductor substrate 110. A second through-electrode insulating layer 122b can be inserted between the second through-electrode 120b and the semiconductor substrate 110.

[0105] A protective layer 50, a first color filter CF1, a second insulating pattern 52, a first pixel electrode 58, a second photoelectric conversion unit PD2, a first common electrode 62, a third insulating pattern 63, a second pixel electrode 84, a third photoelectric conversion unit PD3, a second common electrode 86, a second passivation layer 64, and a microlens ML can be sequentially stacked on the second surface 110b of the semiconductor substrate 110. The first insulating pattern 54 can be disposed between the first color filters CF1. A first through electrode 120a can be electrically connected to the first pixel electrode 58 via a first through-hole plug 56 formed to penetrate the first insulating pattern 54 and the protective layer 50. A second through electrode 120b can be electrically connected to the second pixel electrode 84 via a second through-hole plug 89. The side surface of the second through-hole plug 89 can be covered by a third through-hole insulating layer 82.

[0106] The first pixel electrode 58, the second pixel electrode 84, the first common electrode 62, and the second common electrode 86 can all comprise indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or organic transparent conductive materials. Even when light of various wavelengths is incident on the second photoelectric conversion unit PD2 and the third photoelectric conversion unit PD3, the second photoelectric conversion unit PD2 and the third photoelectric conversion unit PD3 can sense only light of a specific wavelength and generate an electric charge. In one embodiment, the second photoelectric conversion unit PD2 and the third photoelectric conversion unit PD3 can be organic photoelectric conversion layers, and can respectively comprise p-type organic semiconductor materials and n-type organic semiconductor materials, or can comprise quantum dot or chalcogenide materials.

[0107] In each pixel PX1 or PX2, a second floating diffusion region FD2 and a third floating diffusion region FD3, spaced apart from the first floating diffusion region FD1, can be disposed in the first surface 110a of the semiconductor substrate 110. A first source electrode 13s1, a second transfer gate electrode TG2, and a first drain electrode 13d1, spaced apart from each other, can be disposed in the first interlayer insulating layer 9. Additionally, a second source electrode 13s2, a third transfer gate electrode TG3, and a second drain electrode 13d2, spaced apart from each other, can be disposed in the first interlayer insulating layer 9. A second gate insulating layer 14a and a first channel pattern CHL1 can be sequentially stacked on the second transfer gate electrode TG2. The first channel pattern CHL1 extends laterally to contact the first source electrode 13s1 and the first drain electrode 13d1. A third gate insulating layer 14b and a second channel pattern CHL2 can be sequentially disposed on the third transfer gate electrode TG3. The second channel pattern CHL2 extends laterally to contact the second source electrode 13s2 and the second drain electrode 13d2.

[0108] The first photoelectric conversion unit PD1 can be configured to generate charge from light of a first wavelength passing through the first color filter CF1. Such charge can be transferred to the first floating diffusion region FD1 via the first transfer gate electrode TG1.

[0109] The second photoelectric conversion unit PD2 can be configured to generate charge from light of a second wavelength. When a voltage is applied to the second transfer gate electrode TG2, such charge can be transferred to the first channel pattern CHL1 through the first pixel electrode 58, the first pass plug 56, the first through electrode 120a, the first-stage first contact plug 13c1, and the first source electrode 13s1, and can be transferred to the second floating diffusion region FD2 through the first drain electrode 13d1 and the first-stage second contact plug 13c2.

[0110] The third photoelectric conversion unit PD3 can be configured to generate charge from light of a third wavelength. When a voltage is applied to the third transfer gate electrode TG3, such charge can be transferred to the second channel pattern CHL2 through the second pixel electrode 84, the second path plug 89, the second through electrode 120b, the first-stage third contact plug 13c3, and the second source electrode 13s2, and can be transferred to the third floating diffusion region FD3 through the second drain electrode 13d2 and the first-stage fourth contact plug 13c4. Other components and their operation can be referenced. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B The components and their operations described are basically the same or similar, and these descriptions are omitted for the sake of brevity.

[0111] Figure 16A top view of an image sensor according to an embodiment of the present invention is shown. Figure 17 It shows along Figure 16 The cross-sectional view taken from line XI-XI' in the diagram.

[0112] Reference Figure 16 and Figure 17 In the image sensor according to this embodiment, each pixel PX1 or PX2 can be configured to simultaneously acquire information about three different colors. In each pixel PX1 or PX2, a first photoelectric conversion unit PD1 and a second photoelectric conversion unit PD2 can be disposed at different depths in the semiconductor substrate 110 and can be perpendicularly spaced apart from each other. The first photoelectric conversion unit PD1 and the second photoelectric conversion unit PD2 can be, for example, impurity regions doped with n-type impurities. A deep device isolation unit DI can be disposed in the semiconductor substrate 110 to separate the first pixel PX1 and the second pixel PX2 from each other. The deep device isolation unit DI can include a polysilicon pattern 90 and an insulating pattern 92. In each pixel PX1 or PX2, a first transfer gate electrode TG1 and a second transfer gate electrode TG2, spaced apart from each other, can be disposed on a first surface 110a of the semiconductor substrate 110. A portion of the first transfer gate electrode TG1 can extend into the semiconductor substrate 110 and can be located adjacent to the first photoelectric conversion unit PD1. A portion of the second transfer gate electrode TG2 can extend into the semiconductor substrate 110 and can be located adjacent to the second photoelectric conversion unit PD2. The second photoelectric conversion unit PD2 may be deeper than the first photoelectric conversion unit PD1, and the bottom surface of the second transmission gate electrode TG2 may be deeper than the bottom surface of the first transmission gate electrode TG1. The first floating diffusion region FD1 may be disposed in the region of the semiconductor substrate 110 adjacent to the first transmission gate electrode TG1. The second floating diffusion region FD2 may be disposed in the region of the semiconductor substrate 110 adjacent to the second transmission gate electrode TG2. A third floating diffusion region FD3, spaced apart from the first floating diffusion region FD1 and the second floating diffusion region FD2, may be disposed in the first surface 110a of the semiconductor substrate 110.

[0113] In each pixel PX1 or PX2, a color filter is not disposed on the second surface 110b of the semiconductor substrate 110. The protective layer 50, pixel electrode 58, third photoelectric conversion unit PD3, common electrode 62, second passivation layer 64 and microlens ML can be sequentially disposed on the second surface 110b of the semiconductor substrate 110.

[0114] The first photoelectric conversion unit PD1 can be configured to generate charge from light of a first wavelength (in response to a first wavelength). This charge can be transferred to the first floating diffusion region FD1 via the first transfer gate electrode TG1. The second photoelectric conversion unit PD2 can be configured to generate charge from light of a second wavelength (in response to a second wavelength). This charge can be transferred to the second floating diffusion region FD2 via the second transfer gate electrode TG2. Because of the difference in their wavelengths, the penetration depths of the first and second wavelengths of light into the semiconductor substrate 110 can be different. Therefore, even without a color filter, the first photoelectric conversion unit PD1 and the second photoelectric conversion unit PD2 can sense light of different wavelengths. The third photoelectric conversion unit PD3 can be configured to generate charge from light of a third wavelength (in response to a third wavelength). This charge can be transferred to the third floating diffusion region FD3 via the third transfer gate electrode TG3. Other components and their operation can be referenced. Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B The components and their operations described are basically the same or similar, and these descriptions are omitted for the sake of brevity.

[0115] Figure 18 A cross-sectional view of an image sensor according to an embodiment of the present invention is shown. The image sensor according to this embodiment can be a front-side light-receiving image sensor, in which an interconnect layer is disposed between a semiconductor substrate 110 and a microlens ML. In other words, second-level lines 21w and third-level lines 29w can be sequentially disposed on a first surface 110a of the semiconductor substrate 110, which includes a first photoelectric conversion unit and a second photoelectric conversion unit, and the microlens ML can be disposed above the third-level line 29w.

[0116] A third transfer transistor Tx3, including a third transfer gate electrode TG3, can be disposed between the microlens ML and the third-stage line 29w. As an example, a molded pattern MP can be disposed in the fourth interlayer insulating layer 33. The molded pattern MP can include an opening OP and can cover the source electrode 13s and the drain electrode 13d. The opening OP can partially expose the source electrode 13s and the drain electrode 13d. A channel pattern CHL and a second gate insulating layer 14 can be sequentially disposed to cover the source electrode 13s and the drain electrode 13d exposed through the opening OP. The channel pattern CHL can be formed of an oxide semiconductor material, or include an oxide semiconductor material. The third transfer gate electrode TG3 can be disposed on the second gate insulating layer 14. The remaining portion of the opening OP can be filled with a planarization pattern BP. An upper insulating pattern 81 can be disposed to cover the planarization pattern BP and the molded pattern MP.

[0117] The third transfer gate electrode TG3 may include a lower portion LP and an upper portion UP. The lower portion LP of the third transfer gate electrode TG3 may be configured to penetrate the upper insulating pattern 81 and the planarization pattern BP. The upper portion UP of the third transfer gate electrode TG3 may be a portion protruding from the top surface of the upper insulating pattern 81. The side surfaces of the lower portion LP and the upper portion UP may be inclined at different angles to each other. As an example, the width of the lower portion LP may decrease in the downward direction, while the width of the upper portion UP may decrease in the upward direction. The lower portion LP may have an inclination angle determined by the side surface of the recessed area formed in the planarization pattern BP, while the upper portion UP may have an inclination angle determined by the side surface formed by the etching process.

[0118] The third photoelectric conversion unit PD3 can be disposed between the third transmission gate electrode TG3 and the microlens ML. The third photoelectric conversion unit PD3 can be, for example, an organic photoelectric conversion layer. Each pixel electrode 58 can be disposed below the third photoelectric conversion unit PD3, and the common electrode 62 can be disposed on the third photoelectric conversion unit PD3. The pixel electrode 58 can be connected to the source electrode 13s through the first path plug 56. As shown in the figure, a color filter is not provided in this embodiment, but in other embodiments, the color filter can be disposed between the third photoelectric conversion unit PD3 and the microlens ML, or between the third photoelectric conversion unit PD3 and the fourth interlayer insulating layer 33.

[0119] In a method for manufacturing an image sensor according to an embodiment of the present invention, a channel pattern comprising an oxide semiconductor material can be formed by a mosaic process. Therefore, the size of the transistor can be reduced and contamination of the oxide semiconductor material can be suppressed.

[0120] According to embodiments of the present invention, the image sensor may include a separate transport transistor formed on an interlayer insulating layer for transporting charges generated in the organic photoelectric conversion unit. Therefore, reset noise can be reduced and charge transport speed can be improved. Furthermore, a highly integrated image sensor capable of achieving improved image quality can be provided.

[0121] In a method for manufacturing an image sensor according to an embodiment of the present invention, a channel pattern can be formed using an oxide semiconductor material before the back-end (BEOL) process, thereby reducing or preventing contamination problems caused by the oxide semiconductor material during the BEOL process and the resulting process failures.

[0122] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made without departing from the spirit and scope of the inventive concept.

Claims

1. An image sensor comprising: a semiconductor substrate including a first floating diffusion region; a mold pattern located above the first floating diffusion region and including an opening; a first photoelectric conversion portion located at a surface of the semiconductor substrate; a first transfer transistor connecting the first photoelectric conversion portion to the first floating diffusion region, and including a first transfer gate electrode and a channel pattern located in the opening, the channel pattern including an oxide semiconductor, the channel pattern including a side wall portion covering a side surface of the opening and a center portion extending from the side wall portion to an area above the first transfer gate electrode, wherein the channel pattern and the first photoelectric conversion portion are spaced apart from each other by the semiconductor substrate interposed therebetween; a through electrode provided in the semiconductor substrate and connecting the first photoelectric conversion portion to the first transfer transistor; a first contact plug connecting the through electrode to a first end of the channel pattern; and a second contact plug connecting the first floating diffusion region to a second end of the channel pattern opposite to the first end.

2. The image sensor of claim 1, wherein, a top surface of the mold pattern is coplanar with a top surface of the side wall portion.

3. The image sensor of claim 1, wherein, the side wall portion has a ring shape extending along an edge of the center portion.

4. The image sensor according to claim 1, further comprising a planarization pattern located in the opening and covering the center portion.

5. The image sensor of claim 4, wherein, a top surface of the planarization pattern, a top surface of the mold pattern, and a top surface of the side wall portion are coplanar.

6. The image sensor according to claim 4, further comprising an upper insulating pattern covering the planarization pattern, the mold pattern, and the side wall portion, wherein a side surface of the upper insulating pattern is aligned with an outer side surface of the mold pattern.

7. The image sensor according to claim 1, further comprising a first gate insulating layer located in the opening and located below the center portion, wherein the first transfer gate electrode is provided below the first gate insulating layer.

8. The image sensor according to claim 1, further comprising: a second gate insulating layer extending along a top surface of the channel pattern; and a second transfer gate electrode located on the second gate insulating layer. the first photoelectric conversion portion includes an organic semiconductor material.

9. The image sensor of claim 1, wherein, 10. The image sensor according to claim 1, further comprising: a first conductive pattern spaced apart from the first contact plug by the channel pattern interposed therebetween; and a second conductive pattern spaced apart from the second contact plug by the channel pattern interposed therebetween. ​ ​ 11. The image sensor according to claim 1, further comprising: a second photoelectric conversion section provided in the semiconductor substrate; a second floating diffusion region provided in an upper portion of the semiconductor substrate; and a second transfer transistor connecting the second photoelectric conversion section to the second floating diffusion region.

12. An image sensor comprising: a semiconductor substrate including a first floating diffusion region; a mold pattern on a first surface of the semiconductor substrate and including an opening; a trench pattern in the opening, the trench pattern including a sidewall portion covering a side surface of the opening, and a top surface of the sidewall portion of the trench pattern being at a same level as a top surface of the mold pattern; a planarization pattern filling the opening; a gate insulating layer on the trench pattern; a gate electrode spaced apart from the trench pattern by the gate insulating layer interposed therebetween; a photoelectric conversion section on a second surface of the semiconductor substrate opposite the first surface; a through electrode provided in the semiconductor substrate and connecting the photoelectric conversion section to the trench pattern; a first contact plug connecting the through electrode to a first end of the trench pattern; and a second contact plug connecting the first floating diffusion region to a second end of the trench pattern opposite the first end. The trench pattern and the planarization pattern are partially provided in the opening of the mold pattern.

14. The image sensor according to claim 12, further comprising an interlayer insulating layer defining a bottom surface of the opening, 13. The image sensor of claim 12, wherein, the trench pattern including: the sidewall portion; and wherein a center portion extending from the sidewall portion to an area of the bottom surface of the opening. The trench pattern has a conformal shape extending along the side surface of the opening and the bottom surface of the opening. The sidewall portion has a ring shape extending along an edge of the center portion.

15. The image sensor of claim 14, wherein, The center portion includes a first center portion connected to the sidewall portion and a second center portion protruding from the first center portion in a direction away from the semiconductor substrate.

16. The image sensor of claim 15, wherein, A top surface of the second center portion is lower than a top surface of the sidewall portion.

17. The image sensor of claim 14, wherein, The gate insulating layer is in the opening, and the second center portion covers the gate insulating layer.

18. The image sensor of claim 17, wherein, 20. An image sensor comprising:

19. The image sensor of claim 17, wherein, a semiconductor substrate including a first surface and a second surface opposite the first surface; first and second floating diffusion regions provided on the first surface of the semiconductor substrate; a first photoelectric conversion section on the second surface; and a second photoelectric conversion section provided in the semiconductor substrate. ​ a second photoelectric conversion portion provided in the semiconductor substrate; a molded pattern on the first surface and including an opening; a planarization pattern in the opening; a first transfer transistor connecting the first photoelectric conversion portion to the first floating diffusion region, and including a channel pattern including an oxide semiconductor, and a first transfer gate electrode, the channel pattern including a side wall portion covering a side surface of the opening, and a center portion extending from the side wall portion to an area on the first transfer gate electrode; a through electrode provided in the semiconductor substrate and connecting the first photoelectric conversion portion to the first transfer transistor; a first contact plug connecting the through electrode to a first end of the channel pattern; and a second contact plug connecting the first floating diffusion region to a second end of the channel pattern opposite to the first end. a top surface of the planarization pattern, a top surface of the molded pattern, and a top surface of the side wall portion are coplanar.

21. The image sensor of claim 20, wherein, 22. The image sensor according to claim 20, further comprising an upper insulating pattern covering the planarization pattern, the molded pattern, and the side wall portion, a side surface of the upper insulating pattern is aligned with an outer side surface of the molded pattern. wherein ​

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