H-bridge integrated laser driver

Abstract

An H-bridge integrated laser driver optimizes power consumption, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and direct modulated laser diode (DML) applications, VCSEL / silicon photonics, and other applications requiring high-swing drivers or control of impedance. The laser driver includes a retimer for converting low-speed parallel data into a high-speed serial bit stream and an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protection device is coupled between the M-bit DAC and the N-bit DAC. A first DC level shift pre-driver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level shift pre-driver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protection device. The laser driver can be integrated on a CMOS communication chip.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Application 62 / 854,219, filed May 29, 2019, the entire contents of which are incorporated herein by reference. This application also relates to U.S. Patent Application 16 / 855,945, the entire contents of which are also incorporated herein by reference. Technical Field

[0003] This invention relates generally to digital communication systems, and more specifically, to the electronic architecture of an integrated laser driver for a CMOS PAM4 communication chip for applications such as electro-absorption modulated lasers (EMLs), direct modulated laser diodes (DMLs), silicon photonics, VCSELs, or other non-optical applications requiring high-swing voltage / current modulation. Background Technology

[0004] With increasing internet bandwidth demands and the development of mobile phone connectivity to 5G, mobile data communications, especially fiber optic communications from cell towers to base stations and for data center interconnects (DCI) or other inter-device communication within data centers, require higher transmission speeds. Conventional digital communication systems use NRZ or PAM2 schemes to modulate signals, such that information bits are represented by one of two possible signal levels corresponding to binary 0 or 1. To increase the bit rate, the PAM4 scheme has been proposed for signal modulation, such that bits are represented by one of four possible signal levels corresponding to binary 00, 01, 10, or 11. The PAM4 scheme thus effectively doubles the bit rate in serial data transmission by increasing the number of pulse amplitude modulation levels, but this comes at the cost of reduced noise sensitivity, with the signal-to-noise ratio decreasing by approximately two-thirds.

[0005] Therefore, high-speed optical PAM4 systems, such as those transmitting at 56 Gb / s, require sophisticated digital signal processing (DSP) to operate within circuits with low signal-to-noise ratios. Due to limitations in integration, cost, and power, only modern CMOS technology makes the practical implementation of such systems possible. Advanced design concepts in this field envision integrating PAM4 laser drivers onto CMOS chips.

[0006] Integration of PAM4 laser drivers on PAM4 DSP chips would advantageously reduce power consumption, lower total material cost, and reduce the size of the laser module. However, laser drivers for EML and DML applications require high current modulation (up to 60 mA) and high voltage swing up to 2.2V single ended peak-to-peak (ppse) with high bandwidth (>10 GHz) and high linearity for PAM4 schemes. Due to these high swing voltages and large modulation current requirements, it is very difficult to implement laser drivers in modern CMOS technology, which requires high speed performance without suffering from over-voltage and reliability. For example, modern core device MOSFETs can only tolerate about 1V across all of its terminals (VGS, VGD, and VDS). For these reasons, laser drivers are typically implemented as external (i.e., non-integrated) drivers in non-CMOS technologies such as silicon germanium (SiGe) and indium phosphide (InP) heterojunction bipolar transistor (HBT) technologies. This implementation is shown in a typical PAM4 optical system 10 of FIG. 1. In system 10, a PAM4 communication chip 11 receives incoming signals from an external transimpedance amplifier 13 and sends output signals to a non-integrated laser driver 15. Laser driver 15 is an external chip that is electrically coupled to communication chip 11.

[0007] A typical PAM4 optical system with external drivers requires the PAM4 communication IC to provide signals with up to 1V differential peak-to-peak (ppd) swing into a 100-ohm system (differential measurement), then the signals are sent into a 50-ohm EML load as single ended 1.5Vpp, or the signals are sent into a <25-ohm DML load differentially with up to 60mA modulation current. By integrating the laser driver directly into the PAM4 IC to drive the EML or DML, the two-stage PAM4 transmission is avoided, which can be more efficient in bandwidth, power consumption, and linearity. Two known methods for implementing high speed transmitter drivers are current mode drivers (CML) and voltage mode drivers (SST).

[0008] One limitation of using CML to implement optical drivers is its low current efficiency, where the differential swing is determined by [current / 2] x [Rdiff]. To provide 1.5Vppse, a CML driver would require 60mA of current. Furthermore, for single ended applications, it is very difficult to ensure that the impedance towards the power supply (when high swing) and towards GND (when low swing) are well matched unless the power supply is very high. This asymmetry can result in poor linearity and cannot meet the PAM4 transmitter specification. Increasing the power supply voltage also does not solve the problem as it typically results in excessive voltage, poor reliability, and very high power consumption.

[0009] SST drivers can achieve the same swing as CML drivers and have about 75% less power consumption; however, there are two issues with using SST that make it difficult to implement in an integrated PAM4 laser driver. The main issue is reliability. When the swing > 1 Vppse, the VDS voltage of the device becomes too large. It is difficult to place protection such as cascode devices to protect the SST driver because it uses switches with very low impedance to implement the target output impedance. The second issue is the difficulty to implement different output impedances required by different applications, for example 25 ohms for DML and 50 ohms for EML. To provide this flexibility, a significant redesign of the traditional SST driver would be required. At the low 25 ohm impedance, the size of the NMOS and PMOS devices would have to be scaled significantly to minimize their impedance and this would increase the power consumption of the pre-driver stage and significantly increase the parasitic capacitance of the driver.

[0010] There is a need to improve the design of PAM4 modulated laser drivers so that they can be integrated on CMOS communication chips, thereby optimizing power consumption, output impedance matching, and low and high swing reliability for EML, DML, and the like applications. SUMMARY

[0011] The foregoing objects are achieved by the apparatus and method of the present invention, which embodies a laser driver integrated in an NRZ / PAM4 CMOS communication chip suitable for EML, DML, and the like applications. Generally, the present invention employs an improved H-bridge architecture as a current mode driver. The driver circuit includes two digital-to-analog converters (DACs) - a NMOS DAC and a PMOS DAC - cascode protection, common mode feedback (CMFB), a dual rail pre-driver, on-chip termination, and a T-coil. An optional DC bias can be added to bias the laser device.

[0012] In one embodiment, the H-bridge integrated laser driver according to the present application includes a plurality of stages or elements: a retimer element configured to convert low speed parallel data into a first, high speed serial bit stream and an inverted representation of a high speed parallel bit stream. An M-bit PMOS DAC is configured to receive the first buffered bit stream, and an N-bit NMOS DAC is configured to receive the second buffered bit stream. A protection device, such as a cascode stage, is coupled between the M-bit DAC and the N-bit DAC. A first DC level shift pre-driver array is coupled between the retimer and the M-bit DAC for receiving the high speed parallel bit stream and the inverted high speed parallel bit stream. A second DC level shift pre-driver array is coupled between the retimer and the N-bit DAC for receiving the high speed parallel bit stream and the inverted high speed parallel bit stream. Additionally, an impedance matching module is coupled to the output of the cascode stage. The aforementioned elements are further configured such that the first buffered bit stream is substantially synchronized with the second buffered bit stream. In one embodiment, the first buffered bit stream and the second buffered bit stream are substantially identical.

[0013] Many other elaborations on the present application are also presented herein. In one embodiment, the retimer can include a serializer. In other embodiments, M can be set equal to N, or M can be set to one. In other implementations of the present application, the signal inversion can occur at the input of the pre-driver array, or at the output of the pre-driver array. The protection device can be configured to limit |VGD|, |VGS|, and |VDS| to be less than the breakdown voltage of the PMOS DAC, or alternatively, less than the breakdown voltage of the NMOS DAC. In another embodiment, the protection stage is configured to reduce the capacitance at the output of the laser driver. In other embodiments, the impedance matching module can be configured to match the impedance of a 25 ohm system, a 50 ohm system, or any impedance system. The impedance matching module can also include a resistor across the differential terminals of the laser driver. Alternatively or additionally, the impedance matching module can include a T-coil or inductor coupled between the on-chip impedance and the driver output terminals. Alternatively, the impedance matching module can include a center tap between the differential terminals of the driver, a resistor coupled between each differential terminal and the center tap, and an AC ground capacitor coupled to the center tap. In the latter embodiment, a T-coil or inductor can be coupled between each resistor and the driver output to improve high frequency impedance matching and output bandwidth.

[0014] Any of the various embodiments of the laser driver according to the present invention can be implemented as a driver for a DML (e.g., a DML formed as a transmitter optical subassembly). The laser driver can operate as a single-ended driver or a differential driver for NMOS or PMOS bias circuits. Methods for incorporating laser drivers and associated components according to the configurations described herein as integrated circuits for CMOS PAM4 communication chips are also disclosed. BRIEF DESCRIPTION OF DRAWINGS

[0015] Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. Portions of the components shown in the drawings can not be drawn to scale and can be exaggerated to better illustrate the important features of the present invention. The sizes shown in the drawings are only meant to be exemplary. In the drawings, like numerals can be used to refer to like parts throughout the various illustrations, in which:

[0016] FIG. 1 is a top level block diagram of a conventional PAM4 communication system showing driver modules externally coupled to a PAM4 communication chip.

[0017] Figure 2 is a top level block diagram of one embodiment of a system for an advanced PAM4 communication system having a PAM4 communication chip with integrated laser drivers according to the present invention.

[0018] Figure 3 is a block diagram of one embodiment of an H-bridge integrated laser driver according to the present invention.

[0019] Figure 4 is a circuit diagram of one embodiment of an H-bridge integrated laser driver according to the present invention.

[0020] Figure 5 is a block diagram of one embodiment of an H-bridge integrated laser driver according to the present invention.

[0021] Figure 6 is a block diagram of one embodiment of an output termination using common mode feedback to set the DC output according to the present invention.

[0022] Figure 7 is a block diagram of another embodiment of an output termination using an AB class buffer to set the DC output according to the present invention.

[0023] Figure 8 is a block diagram of an alternative embodiment of an H-bridge integrated laser driver configured for AC coupling at a lower speed according to the present invention.

[0024] Figure 9 is a block diagram of an exemplary application of the present invention as a driver for EML single ended 50 ohm system.

[0025] Figure 10 is a block diagram of an exemplary application of the present invention as a driver with NMOS biasing circuit in differential DML system.

[0026] Figure 11 is a block diagram of another exemplary application of the present invention as a driver with PMOS biasing circuit in differential DML system.

[0027] Figure 12 is a block diagram of another exemplary application of the present invention as a driver with NMOS biasing circuit in single ended DML system.

[0028] Figure 13 is a block diagram of another embodiment of the present invention where an analog based FFE replaces the PMOS DAC and NMOS DAC in an H-bridge integrated laser driver.

[0029] Figure 14 is a process flow diagram showing the main steps of a method for fabricating an H-bridge integrated laser driver according to one embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following disclosure presents apparatuses and methods of the present invention that embody integrated laser drivers in applications suitable for EML, DML, and the like, as well as other applications requiring high voltage or current swing, such as silicon photonics, NRZ / PAM4 CMOS communication chips for vertical cavity surface emitting lasers (VCSEL). Although the embodiments described herein show the present invention in PAM4 optical communication applications, it should be understood that the principles of the present invention can be equally applied to communication systems using other transmission media (such as copper) transmission lines, as well as systems that convert NRZ or PAM2 modulation schemes to PAM4 modulation. In general, the present invention employs an improved H-bridge architecture as a current mode driver. The driver circuit includes two digital-to-analog converters (DACs) - a NMOS DAC and a PMOS DAC - cascode protection, common mode feedback (CMFB), dual rail predriver, on-chip termination, and T-coil. An optional DC bias can be added to bias the laser device. The circuit elements described herein and shown in the accompanying drawings can be fabricated on one or more integrated circuit chips using techniques known in the art.

[0031] The following table of acronym terms used herein is provided as a quick reference guide to facilitate understanding of the present disclosure:

[0032] 5G - Fifth generation wireless cellular technology

[0033] AB - AB class amplifier

[0034] BW - Bandwidth

[0035] CML - Current mode logic, herein denoting current mode logic driver

[0036] CMFB - Common mode feedback

[0037] CMOS - Complementary metal-oxide-semiconductor

[0038] DAC - Digital-to-analog converter

[0039] DCI - Data center interconnect

[0040] DFF - Delay flip-flop

[0041] DML - Directly modulated laser diode

[0042] DSP - Digital signal processing

[0043] EML - Electro-absorption modulated laser

[0044] ESD - Electrostatic discharge

[0045] FFE - Feed forward equalizer

[0046] FIR - Finite impulse response

[0047] GND - Ground

[0048] HBT - Heterojunction bipolar transistor

[0049] IC - Integrated circuit

[0050] InP - Indium phosphide

[0051] MOSFET - Metal-oxide-semiconductor field effect transistor

[0052] NMOS - N-type metal-oxide-semiconductor

[0053] NRZ - Non-return-to-zero

[0054] OTA - Operational transconductance amplifier

[0055] PAM4 - Four-level pulse amplitude modulation

[0056] PAM2 - Two-level pulse amplitude modulation

[0057] PMOS - P-type metal-oxide-semiconductor

[0058] pp - Peak-to-peak

[0059] ppd - peak-to-peak difference

[0060] ppse - single-ended peak-to-peak

[0061] Rdiff - differential resistance

[0062] SiGE - silicon germanium

[0063] SST - source series termination, herein denoting a voltage-mode driver

[0064] T line - transmission line

[0065] TOSA - transmitter optical subassembly

[0066] VDD - positive supply voltage

[0067] VDS - drain-source voltage

[0068] VGD - gate-drain voltage

[0069] VDS - drain-source voltage

[0070] Figure 2 A top level block diagram showing one embodiment of a system 20 for advanced PAM4 communication according to the present invention is shown. The system is characterized by having a PAM4 communication chip 21 with integrated laser driver. The integrated laser driver portion of the chip will be described in further detail herein. According to the present invention, by removing the external driver chip 15, and integrating the laser driver into the PAM4 communication chip 21, the bill of materials (BoM) cost is reduced.

[0071] Figure 3 A block diagram showing one embodiment of an H-bridge integrated laser driver 30 suitable for PAM4 implementation according to the present invention is shown. In this embodiment, the integrated PAM4 laser driver 30 includes: an optional serializer 31 for converting low speed parallel data to high speed serial data; two copies of a timing matched equivalent pre-driver array 32 and 33; a push-pull H-bridge 34 including two M-bit DACs (one PMOS and one NMOS); an optional protection device 35; and an output terminal stage 36 for impedance adjustment through optional common mode feedback (CMFB) and bandwidth (BW) enhancement. The pre-driver arrays 32, 33 can be provided with different supply rails. For example, a first supply rail [VSS = V IO -V CORE +V LOW ; VDD = V IO ] can be provided to the pre-driver array 32 interfacing with the PMOS DAC, and a second supply rail [VSS = V LOW; VDD = Vcore] can be provided to a pre-driver array 33 interfaced with the NMOS DAC. The pre-driver arrays 32, 33 can be configured as DC level shift pre-driver arrays that amplify the voltage level of the output signal sent to the H-bridge 34. An example of such a DC shift pre-driver is disclosed in co-pending U.S. Patent Application 16 / 855,945, the entirety of which is incorporated herein by reference. In an alternative embodiment, the H-bridge 34 can be a single driver rather than a DAC (i.e., M = 1). In another embodiment, the protection device 35 can be implemented as a cascode stage.

[0072] In a preferred mode of operation of the H-bridge integrated laser driver 30, the serializer 31 receives parallel data 37 from an on-chip digital core or digital signal processor (DSP) integrated on the same chip as the laser driver 30. To achieve optimal power consumption, the digital core operates around 500 MHz - 2 GHz in a sub-28 nm CMOS technology. The serializer 31 converts the low-speed parallel data into a high-speed serial stream. In one exemplary embodiment, the serializer 31 converts 32 x 1 Gbps x M-bit parallel data into a 1 x 32 Gbps x M-bit data stream.

[0073] Figure 4 A circuit diagram illustrating one embodiment of an H-bridge integrated laser driver 40 according to the present invention is shown. The laser driver 40 is characterized by a PMOS M-bit current steering DAC 41 coupled with an NMOS M-bit current steering DAC 42 in a push-pull configuration. The M-bit DAC 41 includes a PMOS switch stage 43 controlled by binary DATA_P (PMOS) and DATA_N (PMOS) at the input gates of 44 and 45. The M-bit DAC 42 includes an NMOS switch stage 46 controlled by binary DATA_P (PMOS) and DATA_N (NMOS) at the input gates of 47 and 48. In one embodiment, the DACs 41 and 42 are configured to have equal output impedance and / or equal loading. A PMOS current source 49 provides a desired current from a positive supply VDD. Similarly, an NMOS current source 51 provides a desired current source to ground. These desired currents 49, 51 are preferably equal. In other embodiments of the invention, additional current sources (commonly referred to as current sinks) can be connected to the drains of the switch devices 43, 46 to improve the bandwidth and performance of the driver at the expense of additional power consumption. For example, such optional current sinks would be modeled as a current source connected from VDD for the PMOS DAC 41 and as a current source connected to GND for the NMOS DAC 42. In general, the output impedances seen on the PMOS side and the NMOS side at node 73 should be matched for optimal performance.

[0074] The first cascode stage 52 can be used as a protection device to limit over-stress of the PMOS switch stage 43. The cascode stage 52 can also be configured to isolate the total capacitance at the output of the drain node of the switch device 43. Similarly, the second cascode stage 53 can be used to limit over-stress at the NMOS switch stage 46 and isolate the total capacitance at the output of the drain node of the switch device 46. The bias voltage 54 or 55 at the gate of each cascode ensures high reliability and performance. A resistor 56 provides on-chip termination to match system impedance and minimize reflections. In an exemplary embodiment, the resistor 56 can be 50 ohms or 25 ohms. As shown, an optional on-chip T-pad 57 can be connected to extend the bandwidth of the driver and improve return loss. In this example, to achieve optimal group delay, return loss, and transmitter bandwidth, the T-pad 57 is connected between the resistor 56 and the output of the driver (at 59), with the center tap of the T-pad connected via node 64 or 65 to shield the output capacitance of the cascode devices and electrostatic discharge (ESD) loads 58. An optional common mode capacitor 61 can be included to provide AC ground.

[0075] As disclosed herein, the single-ended configuration has a symmetric response to high swing by ensuring equal PMOS and NMOS impedance. Advantageously, the H-bridge or push-pull configuration requires only half the current of a CML driver to achieve the same swing. Preferably, the same number of bits are input to the PMOS DAC and NMOS DAC 41, 42. However, in operation, different numbers of bits can be input to the PMOS DAC and NMOS DAC. An optional CMFB circuit 61 ensures that the DC voltage is set to a fixed value (e.g., VDD / 2) to maximize the voltage margin and provide greater tolerance for device mismatch. In another embodiment, the cascode devices 52, 53 can include multiple cascode stages by stacking more than one NMOS or PMOS cascode device. Generally, more cascode devices enable a higher voltage swing without degrading reliability.

[0076] Figure 5 A block diagram of one embodiment of an H-bridge integrated laser driver 50 according to the present application is shown. In this embodiment, the M-bit PMOS DAC and NMOS DAC 62 and 63 are sized to match, such that the timing between the serializer 31 and the DACs also matches. The same pre-driver arrays 32, 33 have substantially the same power supply voltage level (VDD / 2) to ensure that the same amount of current is available to drive the laser diode 34. The output of the PMOS DAC 62 is connected to the gate of the PMOS switch 43, and the output of the NMOS DAC 63 is connected to the gate of the NMOS switch 46. The output of the PMOS switch 43 is connected to the positive supply rail (VDD / 2), and the output of the NMOS switch 46 is connected to the negative supply rail (0V). The output of the PMOS switch 43 is also connected to the input of the first cascode stage 52, and the output of the NMOS switch 46 is also connected to the input of the second cascode stage 53. The output of the first cascode stage 52 is connected to the positive supply rail (VDD / 2), and the output of the second cascode stage 53 is connected to the negative supply rail (0V). The output of the first cascode stage 52 is also connected to the input of the optional T-pad 57, and the output of the second cascode stage 53 is also connected to the input of the optional T-pad 57. The output of the T-pad 57 is connected to the input of the optional CMFB circuit 61, and the output of the CMFB circuit 61 is connected to the input of the laser diode 34. CORE -V LOW), to enable timing matching and enable the array to be connected correctly with the PMOS / NMOS DACs 62, 63. N-stacks (typically N=l or 2) of common-gate stages 35p, 35n are provided to protect each DAC from over-stressing, and the PMOS / NMOS pairs [62 and 35p, 63 and 35n] are preferably configured to have matched output impedances to enable single-ended performance.

[0077] Figure 6 A block diagram showing one embodiment of an output terminal 60 that sets the DC output using common mode feedback, in accordance with the present application, is shown. The output terminal has an impedance 66 that is tunable for EML (50 ohm) or DML (<25 ohm) applications. By providing an AC ground, an optional common mode capacitance C CM 67 is added for low frequency (<1 GHz) single-ended impedance termination. A CMFB loop that utilizes a class AB OTA 68 to save power can set the output common mode (CM) of the driver to the ideal CM output, typically about VDD DRIVER / 2. The CM sensor 69 is typically configured as a resistive divider to sense the CM from the differential output. The negative feedback loop is formed by coupling the OTA 68 between the node 69 and a reference voltage (e.g., V DD / 2). The H-bridge center tap node 73 is forced to equal (TAP p + TAP n ) / 2 by the negative feedback to equal the DC CM OUT 71.

[0078] Figure 7 A block diagram showing another embodiment of an output terminal stage 70 that sets the DC output using a class AB OTA 72 configured as a unity gain buffer, in accordance with the present application, is shown. The terminal stage 70 uses a class AB OTA 72 configured as a unity gain buffer (rather than common mode feedback) to set the DC output. Configuring the class AB OTA 72 in this manner ensures that the DC CM stage is set approximately. This configuration can improve the phase margin, and can provide lower single-ended termination at low frequencies. Further, by configuring the OTA 72 as a unity gain buffer, the H-bridge center tap node 73 (connected to the CCM 67) is forced to equal the DC CM OUT This advantageously results in low frequency single-ended impedance. Similarly, using a class AB OTA can reduce power consumption.

[0079] Figure 8A block diagram of an alternative embodiment of the H-bridge integrated laser driver 80 according to the present application is shown. In this embodiment, AC coupling is configured for low speed operation. Here, the AC coupling buffers operate at a lower frequency (Fs / N) data rate, rather than at full data rate (Fs) as in the case of AC coupling buffers 32, 33. After AC coupling, the data is serialized by two repeating serializers 82, 83. After the serializers, pre-drivers 84, 85 interface between 82 and 62, and between 83 and 63, for PMOS and NMOS, respectively. However, this configuration can require more power consumption because there are more circuitry connected to the higher VDD power supply, which makes the laser driver more susceptible to timing mismatch between the NMOS DAC and PMOS DAC.

[0080] Figure 9 A block diagram of an exemplary application 90 of the present application as a laser driver 30, 40, 50, or 80 for an EML 50 ohm system 91 is shown. This scheme implements a PAM4 communication chip 21 with integrated laser driver for driving EML single-ended to 50 ohm impedance with voltage swing reaching the practical EML voltage limit, e.g., 2Vpp single-ended. An optional bias-T 92 can be provided with NMOS or PMOS bias current 95. A short impedance matching transmission line 93 can be implemented on a printed circuit board (PCB) to minimize reflections and insertion loss between the PAM4 chip 21 and the EML 91. In this and subsequent embodiments, the bias-T 92 can be integrated into the PAM4 chip 21 itself or the PAM4 chip 21 package. The bias-T 92 is configured to block AC signals and pass only the DC bias current 95. An optional virtual load 94 (e.g., 50 ohm load) can be connected to terminate and balance the unused side of the driver. Optional AC coupling capacitors 152 and 153 can be added to isolate the DC CM of the driver and laser.

[0081] Figure 10A block diagram of an exemplary differential embodiment 100 of the present application as a laser driver 30, 40, 50 or 80 of an NMOS circuit in a DML system 101 is shown. Typically, the DML system 101 is implemented as a transmitter optical subassembly (TOSA). The differential embodiment can be optionally AC coupled through capacitors 149 and 150 to a short differential impedance matched transmission line 96 implemented on a printed circuit board (PCB). The transmission line 96 is typically rated at 50 ohm differential (25 ohm single ended) impedance or 100 ohm differential (50 ohm single ended) impedance. The load in this embodiment is a differential DML laser 97, which typically has an impedance between 10 ohm differential and 50 ohm differential. Specifically, the DML laser 97 is provided on a TOSA connected to the transmission line 96 through a bond wire 98. A bias current 99 can be connected through a bias-T 92 to provide a laser bias current from a voltage source to the DML driver as shown, and another bias-T 92 can be connected to a supply voltage VDD. In another embodiment, the bias-T 92 connections can be made on the right side of the transmission line 96 and connected directly to the TOSA.

[0082] Figure 11 A block diagram of another exemplary embodiment 110 of the present application as a driver 30, 40, 50 or 80 of a PMOS bias circuit in a DML system 101 is shown. The embodiment 110 operates similarly to the previous embodiment 100, except that the bias current 109 is sent to GND instead of being taken from a supply voltage.

[0083] Figure 12 A block diagram of another exemplary embodiment 120 of the present application as a driver 30, 40, 50 or 80 of an NMOS circuit in a DML system 121 is shown. Here, the DML 121 is driven single ended. The transmission line 96 can present a single ended impedance, for example, an impedance of 25 ohms. A resistor 122 can be provided to achieve proper load balancing, for example, 25 ohms. All other elements of the embodiment 120 operate as in the previously described embodiments.

[0084] Figure 13Analog-based feed forward equalizer (FFE) driver implementation 130 is shown as an alternative to the previously proposed DAC-based driver. Instead of using a DAC-based driver with DSP (e.g. finite impulse response (FIR) filtering), an analog filter approach can be used. For this approach, the driver is split into two or more slices. In the example implementation 130, three slices are shown: (1) a pre-tap, (2) a main-tap, and (3) a post-tap, which are denoted as “pre, main, post” in the figure. Other configurations can also be implemented, such as main, post 1, post 2, or main, post 1, etc. Each tap can use multiple slices, and the amplitude of the slices can be adjusted by adjusting the bias current of each tap. In an example operation, data sources 131 and 132 will generate M-tap digital FFE data streams to control PMOS 133 and NMOS 134 M-tap current slices, respectively. In one example, this can be achieved by using a delay flip-flop (DFF) to delay the data by 1 clock period and generate pre-main-post data. The amplitude or weight of each M-tap can be adjusted by modifying the bias 135 and 136 for the PMOS and NMOS M-tap current slices 133 and 134, respectively. The amount of amplitude sets the amount of FIR filtering.

[0085] The H-bridge integrated laser driver according to the present application is believed to exhibit better overall operation compared to drivers with CML or SST technology. The following table qualitatively compares the operability of all three options:

[0086] Table 1

[0087] Qualitative comparison of driver solutions

[0088]

[0089] In view of the above description, those skilled in the relevant art will appreciate that a laser driver according to any of the various embodiments herein can be fabricated as an integrated circuit including any of the various components and devices presented herein, a group of those components, or substantially all of the components, or substantially all of the components of any particular embodiment, in accordance with known fabrication techniques. An example method of fabricating a laser driver according to the configurations described herein embodies the present application as an integrated circuit for a CMOS PAM4 communication chip.

[0090] Figure 14A process flow diagram illustrating the main steps of a method 140 for fabricating an H-bridge integrated laser driver according to one embodiment of the present application is shown. The steps of method 140 can be performed in any desired order. For example, the method can begin with step 141 in which a retimer is formed and configured to convert a low speed parallel data into a high speed serial bit stream and an inverted representation of the high speed parallel bit stream. Next, in step 142, an M-bit PMOS DAC is formed and configured to receive the first buffered bit stream, and in step 143, an N-bit NMOS DAC is formed and configured to receive the second buffered bit stream. In step 144, a protection device is coupled between the M-bit DAC and the N-bit DAC. In step 145, a first DC level shift pre-driver array is coupled between the retimer and the M-bit DAC to receive the high speed parallel bit stream and the inverted high speed parallel bit stream. In step 146, a second DC level shift pre-driver array is coupled between the retimer and the N-bit DAC to receive the high speed parallel bit stream and the inverted high speed parallel bit stream. In the final step, an impedance matching module is coupled to the output of the protection device. In other embodiments, additional processing steps disclosed herein can supplement method 140.

[0091] Exemplary embodiments of the present application have been disclosed in illustrative form. Accordingly, the terms used throughout the text should be read in a non-limiting manner. While those skilled in the art will make minor modifications to the teachings herein, it is understood that all such embodiments are intended to be within the scope of the patent granted herein, which is reasonably commensurate with the technological progress made by the present application, and that the scope is not limited other than by the claims and their equivalents, unless otherwise specified.

Claims

1. An H-bridge integrated laser driver, comprising: a retimer configured to convert low-speed parallel data into a high-speed serial bitstream and an inverted representation of a high-speed parallel bitstream; an M-bit PMOS DAC configured to receive a first buffered bitstream; an N-bit NMOS DAC configured to receive a second buffered bitstream; a protection device coupled between the M-bit DAC and the N-bit DAC; a first DC level shift pre-driver array coupled between the retimer and the M-bit DAC for receiving the high-speed parallel bitstream and the inverted high-speed parallel bitstream; a second DC level shift pre-driver array coupled between the retimer and the N-bit DAC for receiving the high-speed parallel bitstream and inverted high-speed parallel bitstream; and an impedance matching module coupled to an output of the protection device; wherein the first buffered bitstream and the second buffered bitstream are substantially synchronized. The retimer comprises a serializer.

2. The laser driver of claim 1, wherein, M = N.

3. The laser driver of claim 1, wherein, Signal inversion occurs at an input of one or both of the pre-driver arrays.

4. The laser driver of claim 1, wherein, M＝1。 5. The laser driver of claim 1, wherein, Signal inversion occurs at an output of one or both of the pre-driver arrays.

6. The laser driver of claim 1, wherein, The first buffered bitstream and the second buffered bitstream are substantially identical.

7. The laser driver of claim 1, wherein, The protection device limits VGD, VGS, and VDS to less than a breakdown voltage of the PMOS DAC.

8. The laser driver of claim 1, wherein, The protection device limits VGD, VGS, and VDS to less than a breakdown voltage of the NMOS DAC.

9. The laser driver of claim 1, wherein, The protection device reduces capacitance at an output of the laser driver.

10. The laser driver of claim 1, wherein, The protection device comprises one or more cascode stages.

11. The laser driver of claim 1, wherein, The impedance matching module is configured to match an impedance of a 25 ohm or 50 ohm system.

12. The laser driver of claim 1, wherein, The impedance matching module comprises a resistor coupled across differential terminals of the laser driver.

13. The laser driver of claim 1, wherein, The impedance matching module comprises a T-coil coupled between an on-chip impedance and output terminals of the driver, wherein the T-coil comprises a center tap connected to an output of the protection device.

14. The laser driver of claim 1, wherein, The impedance matching module comprises a center tap between differential terminals of the driver, a resistor coupled between each differential terminal and the center tap, and an AC ground capacitor coupled to the center tap.

15. The laser driver of claim 1, wherein, 16. The laser driver of claim 15, further comprising a T-coil or inductor that can be coupled between each resistor and the driver output to improve high frequency impedance matching and output bandwidth.

17. The laser driver of claim 1, formed as a system on an integrated circuit chip.

18. The laser driver of claim 1, implemented as a driver for DML or EML.

19. The laser driver of claim 18, implemented as a differential driver for an NMOS bias circuit.

20. The laser driver of claim 18, implemented as a single-ended driver.

21. The laser driver of claim 20, implemented as a PMOS bias circuit. ​ 22. A method for fabricating an integrated laser driver for a CMOS PAM4 communication chip for electro-absorption modulated laser (EML), direct modulated laser diode (DML) applications, VCSEL, photonic silicon sub or other optical devices that require high voltage / current modulation, the method comprising: forming a retimer configured to convert low speed parallel data to a high speed serial bit stream and an inverted representation of a high speed parallel bit stream; forming an M-bit PMOS DAC configured to receive a first buffered bit stream; forming an N-bit NMOS DAC configured to receive a second buffered bit stream; coupling a protection device between the M-bit DAC and the N-bit DAC; coupling a first DC level shift predriver array between the retimer and the M-bit DAC for receiving the high speed parallel bit stream and the inverted high speed parallel bit stream; coupling a second DC level shift predriver array between the retimer and the N-bit DAC for receiving the high speed parallel bit stream and the inverted high speed parallel bit stream; and coupling an impedance matching module to an output of the protection device. Coupling the protection device reduces capacitance at an output of the laser driver.

23. The method of claim 22, wherein, Coupling the protection device includes coupling one or more cascode stages between the M-bit DAC and the N-bit DAC.

24. The method of claim 22, wherein, ​

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