Handling Reference Clock Frequency Variation in Phase-Locked Loops

Abstract

A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate an output signal of the loop filter. The feedback clock signal is based on the output signal of the loop filter. The method includes changing the frequency of the output clock signal of the phase-locked loop from a first frequency to a target frequency in response to detecting a catastrophic cycle miss event in the absence of an overclock event.

Description

Technical Field

[0001] The present invention relates to integrated circuits, and in particular to clock generator integrated circuits. Background Art

[0002] High-speed communication systems require high-speed clock signals to send and receive information. In a typical clock generation circuit, a phase-locked loop (PLL) receives a synchronous input reference clock signal and generates one or more high-speed clock signals suitable for sending or receiving data. According to one aspect of the communication system, when the synchronous input reference clock signal is lost, the system enters a mode called "holdover" mode and continues to output clock signals.

[0003] The accuracy with which a clock generation circuit provides a clock signal in a hold mode is usually specified in the system standard of the target application. The clock generation circuit attempts to maintain the output clock signal at a frequency based on a previous reference clock signal during the hold mode. When switching from a free-running clock signal to a locked clock signal, entering a hold mode, exiting from a hold mode, or switching an input clock signal from one clock source to another clock source to provide another input clock signal with a different frequency, the application may need to change the frequency and phase of the output clock signal in a controlled manner. Some applications specify a phase slope limit and a frequency slope limit for the output clock signal. An exemplary specification requires that the maximum frequency change rate during the introduction process (i.e., the process of locking a clock signal to another clock signal) be limited to a predetermined value. For example, the specification for the target application has a frequency slope limit of 2.9ppm / second within a measurement interval of 1 second. However, in some cases, meeting the frequency slope limit specification causes the introduction process to take a lot of time and result in a lot of phase accumulation. Therefore, there is a need for a technology that can reduce the time to complete the clock introduction process and reduce the phase establishment of the clock generator circuit in response to an event while meeting the variation specification of the output clock signal. Summary of the invention

[0004] In at least one embodiment, a method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate an output signal of the loop filter. The feedback clock signal is based on the output signal of the loop filter. The method includes changing the frequency of the output clock signal of the phase-locked loop from a first frequency to a target frequency in response to detecting a catastrophic cycle miss event in the absence of an overclock event.

[0005] In at least one embodiment, a phase-locked loop includes a phase detector configured to generate a phase difference signal based on an input clock signal and a feedback clock signal. The phase-locked loop includes a monitor configured to detect a catastrophic cycle miss event in response to the phase difference signal and a predetermined number of update cycles of the phase difference signal in the absence of an overclocking event. The phase-locked loop includes a variation limiting loop filter configured to adjust an output frequency signal in response to the catastrophic cycle miss event. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0007] Figure 1 A functional block diagram of an exemplary clock product is shown.

[0008] Figure 2 A functional block diagram of an exemplary clock generator circuit including a varying limiting loop filter consistent with at least one embodiment of the present invention is shown.

[0009] Figure 3 shows at least one embodiment of the present invention. Figure 2 A functional block diagram of an exemplary variation of a clock generator circuit limiting a loop filter configured for a first mode of operation.

[0010] Figure 4 shows at least one embodiment of the present invention. Figure 2 A functional block diagram of an exemplary variation of a clock generator circuit limiting loop filter configured to respond to an event in a second operating mode.

[0011] Figure 5 FIG. 1 shows an exemplary waveform of an output signal of a loop filter over time consistent with at least one embodiment of the present invention, which is generated by a variable limit loop filter, and implements Figure 2 The frequency of the output clock signal gradually increases.

[0012] Figure 6 FIG. 1 shows an exemplary waveform of an output signal of a loop filter over time consistent with at least one embodiment of the present invention, which is generated by a variable limit loop filter, and implements Figure 2 The frequency of the output clock signal gradually decreases.

[0013] Figure 7 A functional block diagram of an exemplary variation limit loop filter consistent with at least one embodiment of the present invention is shown. Figure 2 The frequency step of the output clock signal and the frequency gradually increase.

[0014] Figure 8 FIG. 1 shows an exemplary waveform of an output signal of a loop filter over time consistent with at least one embodiment of the present invention, which is generated by a variable limit loop filter, and implements Figure 2 The output clock signal has a frequency step and the frequency increases gradually.

[0015] Fig. 9 FIG. 1 shows an exemplary waveform of an output signal of a loop filter over time consistent with at least one embodiment of the present invention, which is generated by a variable limit loop filter, and implements Figure 2 The frequency of the output clock signal is stepped and the frequency gradually decreases.

[0016] Fig.10 Shows Figure 2 A functional block diagram of an exemplary event / hold controller for a clock generator.

[0017] Fig.11 shows at least one embodiment of the present invention. Figure 2 An exemplary timing diagram of events in a clock generator circuit.

[0018] Fig.12 shows at least one embodiment of the present invention. Figure 2 1. Exemplary information flow and control flow of a clock generator circuit.

[0019] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0020] refer to Figure 1 , an embodiment of the clock product 100 includes a controller 102 and a clock generator 104, which monitors at least one received clock signal (e.g., CLKIN (N: 1)) using a clock signal REFCLK (e.g., a clock signal generated using a crystal oscillator including an external crystal coupled to an XA / XB input terminal) and provides at least one output clock signal CLKOUT and at least one clock quality signal. The controller 102 provides configuration information to the clock generator 104 using interface signals USABLE_CLKIN and PRIORITY. The clock generator 104 provides clock quality information (e.g., LOSXA_XB or CLK_STATUS) to the controller 102, and the controller 102 outputs one or more alarm signals (e.g., CLK_FAULT) based on the clock quality information.

[0021] Figure 2A functional block diagram of an exemplary clock generator circuit including a variable limiting loop filter is shown. In at least one embodiment, the clock generator 104 includes a dual-loop phase-locked loop that generates an output clock signal CLKOUT with low jitter using an internal phase-locked loop 108 by locking to an input clock signal (e.g., a clock signal selected from the input clock signal CLKIN (N:1)), which is configured as digitally controlled low jitter. In one embodiment, the reference clock source 106 is a fixed source, such as a crystal oscillator, a microelectromechanical structure (MEMS) oscillator, or other suitable low jitter source. The internal phase-locked loop 108 includes a phase / frequency detector (PD) 112, which generates a phase difference signal based on the reference clock signal REFCLK and a feedback signal provided by a divider 118. The phase / frequency detector 112 provides the phase difference signal to a voltage-controlled oscillator via a loop filter 114. The voltage-controlled oscillator 116 can be implemented as a ring oscillator, an LC oscillator, or other suitable oscillator structure.

[0022] The external phase-locked loop 204 includes a time-to-digital converter 130 that generates a clock signal CLKIND (N: 1) that is a digital representation of the input clock signal CLKIN (N: 1). The selection circuit 154 selects one of those digital input clock signals according to the control signal CLK_SEL and provides the selected digital input clock signal to the phase / frequency detector 158 as the clock signal REFCLK2D, which is a digital reference clock signal for the external phase-locked loop 204. The external phase-locked loop 204 includes the phase / frequency detector 158, the change-limiting loop filter 120 and the divider 162, and uses the internal phase-locked loop 108 as a digitally controlled oscillator responsive to the digital division ratio DIVM, which is an integer division value or a fractional division value. The phase / frequency detector 158 receives the clock signal REFCLK2D and the feedback clock signal FBCLKD. The time-to-digital converter 152 provides a feedback clock signal FBCLKD, which is a digital version of the feedback clock signal FBCLK. The feedback clock signal FBCLK is a frequency-divided version of the clock signal CLKVCO. The phase / frequency detector (PFD) 158 provides a phase difference signal RAW_PFD_OUT generated based on the difference between the clock signal REFCLK2D and the feedback clock signal FBCLKD, and another phase difference signal PFD_OUT also generated based on the difference between the clock signal REFCLK2D and the feedback clock signal FBCLKD. The range of the phase difference signal PFD_OUT is + / -1 / fPFD Within, where f PFD is the update rate of the phase / frequency detector 158. The range of the phase difference signal RAW_PFD_OUT can be greater than + / - 1 / f PFD , and is the sum of the phase differences between the clock signal REFCLK2D and the feedback clock signal FBCLKD starting from a time, for example, starting from the start of locking to the clock signal REFCLK2D. In at least one embodiment, the phase / frequency detector 158 is a digital phase detector that provides a digital difference signal PFD_OUT to the variation limit loop filter 120, which generates an output signal LF_OUT of the loop filter. The variation limit loop filter 120 provides the output signal LF_OUT of the loop filter to the inner loop 108 as a control frequency division ratio DIVM of the divider 118. In at least one embodiment, the time-to-digital converters 130 and 152 are implemented using the technology of U.S. Patent No. 10,067,478, entitled "Use of a Recirculating Delay Line with a Time-to-Digital Converter" issued on September 4, 2018, inventor Raghunandan Kolar Ranganathan, which is incorporated herein by reference.

[0023] The frequency of the reference clock signal REFCLK and the division ratio DIVM of the frequency divider 118 in the feedback path provided by the external phase-locked loop 204 to the internal phase-locked loop 108 determine the frequency of the clock signal CLKVCO. The external phase-locked loop 204 adjusts the division ratio DIVM so that the clock signal CLKVCO (f CLKVCO ) matches the frequency of the input clock signal CLKIN (N: 1) by a multiple of the frequency of the selected input clock signal (division ratio DIVN) (e.g. f CLKIN(n) =f CLKVCO / DIVN, where f CLKIN(n) is the frequency of the selected input clock signal CLKIN(n), which corresponds to the clock signal REFCLK2D). In embodiments of the clock generator 104, the external phase-locked loop 204 provides the clock signal CLKVCO to the output divider 166, which is responsive to the divider control signal DIVP. In at least one embodiment of the output divider 166, the divider control signal DIVP is a digital frequency ratio converted from a code (e.g., a code provided by a non-volatile memory or other storage element). In other embodiments of the clock generator 104, the voltage controlled oscillator (VCO) 116 provides the clock signal CLKVCO as the output clock signal CLKOUT, and the output divider 166 is disabled or excluded.

[0024] In at least one embodiment of the clock generator 104, the event / hold controller 224 determines whether the input clock signal CLKIN(n) is selected (which is selected from the input clock signal CLKIN(N:1)) and whether the frequency of the input clock signal CLKIN(n) digitized by the time-to-digital converter (TDC) 130 and / or selected is within a target frequency range. If the frequency of the selected input clock signal CLKIN(n) is outside the target frequency range, a loss of signal condition is detected, or a substantial phase difference is detected, the event / hold controller 224 determines that the selected input clock signal CLKIN(n) is invalid. If the selected input clock signal CLKIN(n) is invalid and the event / hold controller 224 determines that no other input clock signal is valid, the event / hold controller 224 triggers a hold mode. The event / hold controller 224 freezes the output signal LF_OUT of the loop filter provided by the variation limit loop filter 120 to prevent the frequency division ratio DIVM from tracking further changes of the clock signal REFCLK2D, and selects the stored average output of the variation limit loop filter 120 or a stored value based on the output signal of the variation limit loop filter 120 as the target value FREQ_TARGET to be provided as an input to the variation limit loop filter 120, thereby maintaining the frequency of the clock signal CLKVCO at a stable frequency value. For example, the event / hold control 224 of the external phase-locked loop 204 maintains the output signal of the variation limit loop filter 120 at a value corresponding to the output of the phase / frequency detector 158 received by the variation limit loop filter 120 before entering the hold mode to prevent updating DIVM. In at least one embodiment of the clock generator 104, in the hold mode, the event / hold controller 224 provides the target value FREQ_TARGET to the variation limit loop filter 120, which makes the output clock signal CLKOUT reach the target frequency and is an average value or other function of the output of the phase / frequency detector 158. The stored value is stored before entering the hold mode. The frozen division ratio DIVM provided to the divider 118 causes the output frequency of the clock signal CLKVCO to change only based on the frequency change of the clock signal REFCLK. At the same time, the event / hold controller 224 also updates the control signal CLK_SEL to select the output of the time-to-digital converter 130 to provide as the input clock signal CLKIN for use when exiting the hold mode.

[0025] In at least one embodiment, the variation limit loop filter 120 limits the phase change and frequency change of the output clock signal in response to an introduction event (e.g., after switching from the selected input clock signal CLKIN(n) selection circuit (SEL) 154 to another input clock signal CLKIN(N:1), or after a sudden change in the frequency of the selected input clock signal CLKIN(n)). The target application specifies a maximum frequency change rate and a maximum phase change rate of the output clock signal CLKOUT during the introduction process. For a one-second measurement interval, an exemplary predetermined frequency slope limit PREDET_FSL is 2.9 ppm / second, and an exemplary predetermined phase slope limit PREDET_PSL is 0.3125 μs / second within 164 milliseconds. In response to the introduction event, the variation limit loop filter 120 limits the phase change rate of the output clock signal CLKOUT and limits the frequency change rate of the output clock signal CLKOUT so that the frequency of the output clock signal CLKOUT becomes gradually transitioned between frequencies. Figure 3 1 shows a functional block diagram of an exemplary variation limit loop filter 120. In at least one embodiment, the variation limit loop filter 120 includes a gain circuit 302 that applies a gain factor to the output of the phase / frequency detector 158 during closed-loop operation of the clock generator 104. The phase slope limiter 304 compares the obtained phase difference signal with a predetermined phase slope limit PREDET_PSL. If the obtained phase difference signal is less than the predetermined phase slope limit PREDET_PSL, the phase slope limiter 304 provides the obtained phase difference signal to the summing circuit 314. If the obtained phase difference signal is greater than the predetermined phase slope limit PREDET_PSL, the phase slope limiter 304 provides the predetermined phase slope limit PREDET_PSL to the summing circuit 314, thereby limiting the phase variation of the output clock signal CLKOUT.

[0026] In a signal path coupled in parallel with the phase slope limiter 304, an integrator gain 306 applies another gain factor (e.g., a power of two) to the obtained phase difference signal received from the gain circuit 302. If the obtained phase difference value is greater than a predetermined frequency slope limit PREDET_FSL, a frequency slope limiter (FSL) 308 provides the predetermined frequency slope limit PREDET_FSL to an accumulator (ACC) 310. If the obtained phase difference value is less than the predetermined frequency slope limit PREDET_FSL, the frequency slope limiter 308 provides the obtained phase difference signal to the accumulator 310. In closed-loop operation, the accumulator 310 sums the value of the obtained phase difference signal over time to obtain a frequency shift value. The scaler 312 adjusts the output of the accumulator 310 and provides the scaled accumulator output to a summing circuit 314 to be combined with the output of the phase slope limiter 304. The summing circuit 314 provides the resulting combination to a low pass filter (LPF) 138, which low pass filters the phase variation limited and frequency variation limited output signals to generate corresponding digital control signals for the inner loop 108. The event / hold controller 224 updates the stored values ​​based on the output of the variation limited loop filter 120 for later use in other operating modes (e.g., open loop operating mode).

[0027] refer to Figure 2 , Figure 4 and Figure 5In at least one embodiment, in response to detecting an event, the event / hold controller 224 configures the external phase-locked loop 204 to an open-loop configuration and allows a gradual transition (e.g., switching from a free-running clock signal to a locked clock signal, entering a hold mode of operation, exiting from a hold mode of operation, switching the input clock signal from one clock source to another clock source to provide another input clock signal with a different frequency, or a catastrophic cycle slip event (CCS) in the absence of an overclocking event). In response to the control signal RAMP, the external phase-locked loop 204 gradually transitions the output clock CLKOUT to the new frequency. In open-loop operation, when gradually transitioning the frequency of the output clock signal CLKOUT, the event / hold controller 224 effectively disables the phase slope limiter 304 (e.g., the phase slope limiter 304 provides a zero output or separates the phase slope limiter 304 from the summing circuit 314). The variation limit loop filter 120 gradually changes the frequency of the output clock signal CLKOUT from the current frequency of the output clock signal CLKOUT to the target value FREQ_TARGET based on the selected input clock signal CLKIN(n) or based on the stored value corresponding to the historical input clock average frequency data entering the hold mode. At the beginning of the gradual change (i.e., time FREQ_RAMP_STARTS), the event / hold controller 224 loads the appropriately scaled loop filter output LF_OUT to the accumulator 310.

[0028] During the gradual transition, the event / hold controller 224 continuously drives the frequency slope limiter 308 with an updated difference between the target value FREQ_TARGET and a signal corresponding to the frequency of the reference clock signal (e.g., the output of the accumulator 310). When the magnitude of the difference is less than a predetermined frequency slope limit PREDET_FSL, the frequency slope limiter 308 provides the difference to the accumulator 310. When the magnitude of the difference is greater than the predetermined frequency slope limit PREDET_FSL, the frequency slope limiter 308 provides the predetermined frequency slope limit PREDET_FSL as an operand of the accumulator 310 until the magnitude of the difference is less than the predetermined frequency slope limit PREDET_FSL. When the magnitude of the difference is less than the predetermined frequency slope limit PREDET_FSL, the frequency slope limiter 308 provides the difference to the accumulator 310. When the frequency of the input clock signal CLKIN(n) is selected to be greater than the frequency of the feedback clock signal FBCLK, as Figure 5 As shown, the output of the loop filter gradually increases (e.g., linearly or monotonically) to the target value FREQ_TARGET over time. When the frequency of the input clock signal is less than the frequency of the feedback clock signal FBCLK, as shown in FIG. Figure 6As shown, the output of the limit loop filter 120 gradually decreases to a lower target value FREQ_TARGET (eg, linearly or monotonically) over time. For a predetermined frequency slope limit PREDET_FSL, the transition time 1 may be very long and may result in a large phase accumulation (ie, a large constant phase difference).

[0029] A technique for reducing transition time and phase accumulation caused by a gradual phase or frequency transition consists of introducing a frequency step at the beginning of the gradual frequency transition, as permitted by the specifications of the target application. Figure 2 , 7 , 8 and 9, in at least one embodiment, in response to an event (e.g., switching from a free-running clock signal to a locked clock signal, entering a hold mode of operation, exiting from a hold mode of operation, or switching an input clock signal from one clock source to another clock source to provide another input clock signal with a different frequency), the event / hold controller 224 configures the external phase-locked loop 204 to an open-loop configuration and enables a gradual frequency transition with a frequency step (e.g., setting the step control signal ENABLE to = "1"). The variation-limited loop filter 120 introduces a frequency step by initializing the accumulator 310 at time FREQ_RAMP_STARTS and combining the loop filter output LF_OUT and the frequency step value STEP. If the frequency transition increases the frequency of the output clock signal CLKOUT, the frequency step value STEP is added to the loop filter output LF_OUT, and if the frequency transition decreases the frequency of the output clock signal CLKOUT, the frequency step value STEP is subtracted from the loop filter output LF_OUT. In at least one embodiment, the frequency step value STEP has a predetermined value corresponding to a frequency step whose amplitude is less than or equal to the phase slope limit PREDET_PSL. If the frequency step value STEP is greater than the absolute value of the loop filter output LF_OUT, the accumulator 310 directly loads the target value FREQ_TARGET to avoid frequency overshoot. After the initialization of the frequency step value is applied, if the target frequency has not been reached by the output clock signal CLKOUT, the accumulator 310 applies the operand provided by the frequency slope limiter 308. The sign of the applied operand is determined by the variation limit loop filter 120 based on the value of the loop filter output LF_OUT and the target value FREQ_TARGET. In at least one embodiment, the operand has a value corresponding to the frequency slope limit PREDET_FSL.

[0030] Since the output of the accumulator 310 is indirectly coupled to the low pass filter (LPF) 138 , the varying limit loop filter 120 provides a non-linear but continuous signal to the inner loop 108 . Figure 8An exemplary loop filter output over time is shown when frequency translation is enabled in response to a target frequency being greater than the frequency of the output clock signal CLKOUT (ie, the current frequency). Fig. 9 2 shows an exemplary loop filter output over time in response to the frequency of the output clock signal CLKOUT being greater than the target frequency when frequency translation is enabled. Figure 5 , 6 , 8 and 9, the transition time 12 achieved by the gradual frequency transition with frequency steps is significantly shorter than the transition time 2 achieved by the gradual frequency transition without frequency steps, and the applied operands introduce a nonlinear change in the output signal of the loop filter, whose amplitude is less than or equal to the corresponding predetermined phase slope limit PREDET_PSL, and introduce a linear transition with a slope less than or equal to the predetermined frequency slope limit PREDET_PSL.

[0031] refer to Figure 2 and 10 In at least one embodiment, the clock generator 104 includes an event / hold controller 224 that detects events and generates control signals associated with those events. For example, in at least one embodiment of the clock generator 104, the event / hold controller 224 monitors the clock signal REFCLK2D and detects an overclock (OOF) event, a phase error event, and a loss of signal (LOS) event and generates associated control signals (e.g., a control signal for selecting a source that provides the clock signal REFCLK2D, enabling a hold mode, disabling a hold mode, or enabling a gradual frequency transition). The frequency monitor 113 generates an indication of whether the input clock signal CLKIN (N: 1) has a frequency within a range associated with the clock signal REFCLK2D based on corresponding digital values ​​(e.g., the input clock signal CLKIND (N: 1) and the clock signal REFCLK2D) and a predetermined frequency difference threshold OOF_THRESH. If the frequency difference associated with the clock signal CLKIND (n) and the clock signal REFCLK2D is greater than the predetermined frequency difference threshold OOF_THRESH, the frequency monitor indicates that an overclock event is detected. Phase monitor 111 generates an indication that a phase error between a selected input clock signal CLKIND(n) and a feedback clock signal represented by digital value REFCLK2D exceeds a predetermined phase difference threshold PM_THRESH.

[0032] A loss-of-signal detector (LOS) 117 determines whether a selected input clock signal CLKIN(n) is present based on the clock signal CLKIND(n) and a threshold value LOS_THRESH. If the frequency of the selected input clock signal CLKIN(n) exceeds the target frequency range or a signal loss condition is detected, the control signal generator 121 generates a corresponding control signal or indication to indicate that the selected input clock signal CLKIN(n) has failed. If the event / hold controller 224 detects an event and triggers the hold mode, the frequency target calculator 123 generates a target value FREQ_TARGET based on the historical input clock average frequency data stored in the storage element. The event / hold controller 224 configures the variation limit loop filter 120 to an open-loop mode and provides the target value FREQ_TARGET to the variation limit filter 120. In some cases, the event / hold controller 224 enters the hold mode instead of responding to the event, updates the clock selection signal CLK_SEL to the next input clock signal, which can be the same clock signal or another clock signal received by the selection circuit 154. If the event / hold controller 224 detects an event and updates the clock selection signal CLK_SEL to switch the input clock signal to another valid clock signal received by the selection circuit 154, the frequency target calculator 123 generates a target value FREQ_TARGET based on the average frequency of the selected input clock signal CLKIN(n). The event / hold controller 224 configures the variation limit loop filter 120 to an open-loop mode and provides the target value FREQ_TARGET to the variation limit filter 120. If the event / hold controller 224 does not detect an event, the event / hold controller 224 configures the variation limit loop filter 120 to provide a dynamically updated output to the internal phase-locked loop 108. In one embodiment, the event / hold controller 224 is implemented using software (including firmware) executed on a processor or by a combination of software and hardware. As described herein, the software may be encoded in at least one tangible (i.e., non-transitory) computer-readable medium. As referred to herein, a tangible computer-readable medium includes at least a disk, tape, or other magnetic, optical, or electronic storage medium.

[0033] In at least one embodiment of the clock generator 104, the selected input clock signal CLKIN(n) is within the target frequency range (i.e., the frequency monitor has not detected an overclocking event), but the selected input clock signal CLKIN(n) has experienced a clock frequency nonlinear change, including a substantial change in frequency (i.e., the frequency change is large enough to cause a catastrophic cycle slip event). The catastrophic cycle slip monitor (CCS) 115 compares the phase difference signal RAW_PFD_OUT with the update rate f of the phase / frequency detector 158. PFD The predetermined number corresponds to a frequency variation of the selected input clock signal CLKIN(n) that is too large for the external phase-locked loop 204, i.e., a frequency difference outside the loop bandwidth of the external phase-locked loop 204. A catastrophic cycle miss event occurs at Fig.11 As shown in . The frequency F_CLK of the selected input signal CLKIN(n) jumps from f1 to f2, where f2-f1 is within the range of OOF_THRESH. Therefore, the event / hold controller 224 does not trigger an overclocking event. At the same time, the frequency monitor 113 measures the selected clock cycle in the background (for example, using a time-to-digital converter and a comparator controlled by a frequency-stable input clock signal) and provides an update value for each occurrence of an overclocking update event. The measured value is the average value of the frequency F_CLK between two adjacent overclocking update events. Note that the frequency F_CLK is not a measured value. As the frequency F_CLK changes between the first and second overclocking update events, over time, if the bandwidth of the external phase-locked loop 204 is narrow enough, the phase difference between the feedback clock signal FBCLKD and the clock signal REFCLKD will increase. When the phase difference signal RAW_PFD_OUT exceeds a predetermined number of update cycles of the phase difference signal (for example, 1 / f PFD ×UI, where UI is a programmed integer), the catastrophic cycle failure monitor 115 triggers a catastrophic cycle failure event.

[0034] In response to detecting a catastrophic cycle miss event in the absence of an overclock event (i.e., F_CLK is within a predetermined frequency range), the event / hold controller 224 triggers a clock switch event to the same active clock (i.e., the selected input clock signal CLKIN(n)). Note that in response to a catastrophic cycle miss event in the absence of an overclock event, the control signal CLK_SEL does not change, but the event / hold controller 224 configures the change limit loop filter 120 to shift the frequency of the feedback clock signal FBCLK from frequency f1 to frequency f2. In response to detecting an overclock event, the event / hold controller 224 triggers a clock switch to another clock signal (e.g., changes the control signal CLK_SEL to select another input clock signal CLKIN(N:1)) or triggers a hold mode, and may eventually return to the currently selected active clock signal.

[0035] refer to Figure 2 , 10 In at least one embodiment, the event / hold controller 224 generates control signals to configure the clock generator 104 in accordance with the information and control flow 1200. When the clock generator 104 operates in a closed-loop operation, the phase / frequency detector 158 updates the phase difference signal RAW_PFD_OUT and the phase difference signal PFD_OUT (1202). The event / hold controller 224 determines whether a catastrophic cycle miss event has occurred in the absence of an overclocking event (e.g., by comparing the phase difference signal RAW_PFD_OUT with the phase difference signal corresponding to the f of the phase / frequency detector 158). PFD The event / hold controller 224 maintains the clock generator 104 in closed-loop operation in the absence of a catastrophic cycle miss event and in the absence of any other events (1202). The hold controller 224 detects a catastrophic cycle miss event in the absence of an overclock event, the event / hold controller 224 indicates to the variation limit loop filter 120 that a catastrophic cycle miss event has occurred, and the event / hold controller 224 determines a target value FREQ_TARGET (1206) when an overclock update event next occurs based on a next measurement of the average frequency of the selected input clock signal CLKIN(n).

[0036] The frequency target calculator 123 determines whether the retraining of the clock generator 104 should include a gradual frequency transition (with or without frequency steps) based on a comparison of the target value FREQ_TARGET and the difference between the loop filter output and the threshold RAMP_THRESH, which is a predetermined transition threshold (1208). If the frequency target calculator 123 determines that a gradual frequency transition is not required (e.g., the difference is less than the threshold RAMP_THRESH and the difference is within the bandwidth of the external phase-locked loop 204), the external phase-locked loop 204 continues to operate in a closed-loop configuration (1202).

[0037] If the event / hold controller 224 determines that a gradual frequency transition should occur (eg, the difference is greater than a predetermined transition threshold and the difference exceeds the bandwidth of the external phase locked loop 204), the event / hold controller 224 turns on the external phase locked loop 204 and, as described above, Figure 7 The configuration changes the limit loop filter 120 to gradually change the frequency of the output clock signal CLKOUT from the current frequency to the target value FREQ_TARGET.

[0038] Reference again Fig.12 , after the output clock signal CLKOUT reaches the target frequency, the event / hold controller 224 saves the value of the phase difference in the storage element 153, which is a counter in at least one embodiment, and resets the phase difference signal provided to the variation limit loop filter 120 to zero before resuming closed-loop operation. Then, if the target application requires, the event / hold controller 224 gradually aligns the clock signal REFCLKD and the feedback clock signal FBCLKD by gradually adding the phase difference stored in the storage element 153 to the input of the phase / frequency detector 158 (1210). In at least one embodiment, the event / hold controller 224 gradually aligns the clock signals by incrementally adding the stored phase difference to the clock signal REFCLKD and decrementing the memory 153 until the memory 153 is equal to zero (e.g., using the control signal PHASE_BO). In other embodiments, the phase difference is applied to the feedback path (i.e., the feedback clock signal FBCLKD), and the memory 153 is decremented with each increment to the feedback clock signal FBCLKD until the memory 153 is equal to zero. As a result, the edges of the input clock signal CLKIN and the clock signal FBCLK are gradually aligned and any phase accumulation is reduced or eliminated.

[0039] Based on Fig.11 In the second event, the measured selected input clock period calculates the target value FREQ_TARGET, introducing an error into the target value FREQ_TARGET. Again referring to Fig.12, in some cases, the error of the target value FREQ_TARGET is large enough, and the magnitude of the frequency difference between the selected input clock signal and the clock signal FBCLK is still large enough. Therefore, the event / hold controller 224 can detect a second catastrophic cycle miss (1212) after restoring the closed-loop operation of the external phase-locked loop 204. Therefore, the event / hold controller 224 executes a second catastrophic cycle miss response sequence (1206, 1208, 1210, 1212). If the event / hold controller 224 does not detect a second catastrophic cycle miss event, the closed-loop operation continues (1202). Fig.12 The information and control flows of FIG. 1 are exemplary only, and other embodiments of the clock generator 104 use other sequences of steps or additional steps that do not affect the data dependencies.

[0040] Typically, the predetermined values ​​(e.g., phase slope limits, frequency slope limits, predetermined steps, and thresholds) are fixed or defined by a user during manufacturing or production testing of the clock product 100. As referred to herein, a user is an application (e.g., configuration software) executing on a processor (e.g., executing on the controller 102 or a controller external to the clock product 100) to configure the clock product 100 or the clock generator 104, or a person manually configures the clock product 100 for operation. Thus, techniques for clock product handling of relatively large variations in the frequency of the effective input clock signal have been described. In certain applications, the techniques described herein improve phase continuity or reduce the number of open-loop operations.

[0041] Although circuits and physical structures have been generally assumed in describing embodiments of the present invention, it is well known that in modern semiconductor design and manufacturing, physical structures and circuits can be embodied in the form of computer-readable descriptions suitable for subsequent design, simulation, testing or manufacturing stages. The structures and functions represented as discrete components in the exemplary configuration can be implemented as combined structures or components. Various embodiments of the present invention are expected to include circuits, circuit systems, related methods, and tangible computer-readable media of the circuits, systems and methods having encoding (e.g., VHSIC hardware description language (VHDL), Verilog, GDSII data, electronic design exchange format (EDIF) and / or Gerber files) thereon, all as described herein and as defined in the appended claims. In addition, computer-readable media can store instructions and data that can be used to implement the present invention. Instructions / data can be related to hardware, software, firmware or a combination thereof.

[0042] The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the appended claims. For example, although the invention has been described in an embodiment in which the clock generator 104 uses a dual-loop phase-locked loop, those skilled in the art will appreciate that the teachings herein may be used with clock generators that include other numbers of cascaded phase-locked loops. In addition, although the invention has been described in an embodiment in which the external phase-locked loop 204 of the clock generator 104 controls the divider value used by the divider 118 of the internal loop 108, and the output divider 166 receives the divider control signal DIVP, those skilled in the art will appreciate that the teachings herein may be used with the external phase-locked loop 204 to control the divider control signal DIVP of the output divider in response to CLKVCO, and the divider 118 is responsive to a predetermined divider value.

[0043] Unless the context clearly indicates otherwise, the terms "first", "second", "third", etc. used in the claims are used to distinguish different terms in the claims, and do not otherwise indicate or imply any order of time, position, or quality. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the present invention as set forth in the appended claims.

Claims

1. A method for operating a phase-locked loop, comprising: generating a phase difference signal based on an input clock signal and a feedback clock signal; filtering an input signal of a loop filter based on the phase difference signal to generate an output signal of the loop filter, wherein the feedback clock signal is based on the output signal of the loop filter; as well as In response to detecting a catastrophic cycle miss event in the absence of an overclocking event, shifting the frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency, The method further comprises: Periodically generating a digital frequency signal; as well as An overclocked signal is generated based on another frequency-stable input clock signal and the digital frequency signal.

2. The method according to claim 1, wherein: The catastrophic cycle miss event is detected in response to a substantial frequency variation of the input clock signal.

3. The method according to claim 1, wherein: The catastrophic cycle miss event is detected in response to the phase difference signal exceeding a predetermined number of update cycles of the phase difference signal.

4. The method according to claim 3, further comprising: comparing the value of the phase difference signal with a predetermined number of update periods of the phase difference signal; as well as A catastrophic cycle misfire detection signal is generated based on the comparison.

5. The method according to claim 1, 2, 3 or 4, further comprising: In response to detecting a catastrophic cycle miss event, storing a value of the phase difference signal after the frequency of the output clock signal reaches the target frequency; as well as The phase difference signal is incrementally adjusted and the stored value of the phase difference signal is decremented to gradually return the phase difference between the input clock signal and the feedback clock signal to zero.

6. The method according to claim 5, further comprising: Resuming closed-loop operation after setting the phase difference signal to zero; as well as In the absence of an overclocking event and immediately after resuming the closed loop operation, another cycle miss event is detected.

7. The method according to claim 1, 2, 3 or 4, further comprising: The catastrophic cycle miss event is detected based on the phase difference signal and a predetermined number of update cycles of the phase difference signal.

8. The method according to claim 1, 2, 3 or 4, wherein: The transformation includes: calculating an output of a target loop filter based on a next measured average input clock frequency; and The loop filter output is selectively ramped up to the target loop filter output based on a comparison of the target loop filter output with the loop filter output.

9. The method according to claim 8, wherein: The transformation includes: The phase difference signal is reset to zero after the loop filter output reaches the target loop filter output and before the phase locked loop is configured for closed loop operation.

10. A phase-locked loop, comprising: a phase detector configured to generate a phase difference signal based on an input clock signal and a feedback clock signal; a monitor configured to detect a catastrophic cycle miss event in response to the phase difference signal and a predetermined number of update cycles of the phase difference signal in the absence of an overclocking event; a variable limit loop filter configured to adjust an output signal in response to a catastrophic cycle miss event; a time-to-digital converter configured to periodically generate a digital frequency signal; as well as A comparator is configured to generate an overclocking signal based on another frequency-stable input clock signal and the digital frequency signal.

11. The phase-locked loop according to claim 10, wherein: The variation limit loop filter is configured to increase the output signal from a value associated with the first frequency of the phase-locked loop output signal to a target value associated with the target frequency of the phase-locked loop output signal in response to a difference between the target frequency and the first frequency being greater than a predetermined frequency threshold.

12. A phase locked loop as claimed in claim 10 or 11, wherein the catastrophic cycle miss event is detected in response to a substantial frequency variation of the input clock signal.

13. The phase-locked loop according to claim 10 or 11, wherein: The comparator is further configured to generate a catastrophic cycle miss detection signal based on a comparison of the value of the phase difference signal and a predetermined number of update cycles of the phase difference signal.

14. The phase-locked loop according to claim 10 or 11, further comprising: A counter is configured to load the value of the phase difference signal after the frequency of the output signal reaches a target frequency in response to detecting a catastrophic cycle miss event, and is configured to decrement the value in response to an incremental adjustment of the phase difference signal.

15. The phase-locked loop according to claim 10 or 11, wherein: The monitor is further configured to detect the overclocking event based on a frequency difference between a frequency of the input clock signal and a frequency threshold.

16. The phase locked loop according to claim 15, wherein: For an overclocking event, the frequency difference is less than a threshold frequency difference.

17. The phase-locked loop according to claim 10 or 11, wherein: The time-to-digital converter comprises: a first time-to-digital converter configured to generate a first digital signal indicative of a first frequency of the input clock signal; and a second time-to-digital converter configured to generate a second digital signal indicative of a second frequency of the feedback clock signal, The monitor detects the absence of the overclocking event based on the first digital signal, and The phase detector generates a phase difference signal using the first digital signal and the second digital signal.

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