Electronic device package and method of manufacturing the package

Abstract

A package for an electronic device is proposed based on a substrate (SU, SU1, SU2) comprising at least one piezoelectric layer. The device structure is enclosed in a cavity of an integrally formed encapsulation layer structure (PK) of a thin film package applied on a first surface (SI). A first contact pad (PI) is arranged on the first surface of the substrate and is electrically connected to the device structure. A second contact pad (P2) is arranged on a second surface (S2) of the substrate opposite to the first surface (SI). A guide via (V) passes through the substrate and electrically interconnects the first contact pad and the second contact pad. The packages can be stacked on top of each other and connected to each other via two pads of different kinds. The first substrate (SU1) is connected to a first pad of a second substrate (SU2) via its second pad (P2) on its second surface by means of a connecting device (CM).

Description

Technical Field

[0001] The present invention relates to an electronic device package with improved external connections and a method for manufacturing the package. The package can be used as a cavity package for SAW devices and BAW devices, and can contact the device chip from the back and can build a multi-layer SiP (=system-in-package) using WLP (=wafer-level packaging) technology. Background Art

[0002] The continued miniaturization of electrical devices in microelectronic devices and nanoelectronic devices requires that the area consumption of electrical conductors and contact pads of devices and device chips be as small as possible. On the other hand, the highest flexibility in device design is required to allow the devices to be integrated into electronic systems without difficulty. The problem is exacerbated by the upcoming 3D packaging methods such as system-in-package (SiP). In SiP packaging, electronic device chips are not only arranged next to each other, but also stacked on top of each other to form multi-level device modules.

[0003] Thin Film Packaging (also called TFP or Thin Film Capping) is a technology that offers the lowest package height, smallest area, low thermal budget, and relatively low cost compared to other packaging technologies.

[0004] The smallest device packages on the market can be achieved with wafer-level packaging technology (WLP). In this technology, the device structures to be protected are arranged in a cavity produced in one piece on the wafer level. This can be done, for example, by covering the device structures with a structured sacrificial layer. After structuring, only those device structures that need to be enclosed in the cavity are covered with the sacrificial material. A mechanical stabilization layer is deposited onto this material to form a mechanically stable cover. Through the opening in the cover, the sacrificial material is removed before the opening is closed again. In an alternative process, a capping layer with pre-formed grooves can be used to form the cavity.

[0005] To hermetically seal the pores, a polymer layer may be deposited over the cover to close the release holes. Alternatively, a PSG (phosphorus doped silicate glass) layer may be used for this purpose. Other encapsulation layers may be applied to the mechanical stabilization layer.

[0006] This technology allows different chips to be mechanically and electrically connected together through wafer bonding and integrate them into a common system. With this technology, the most compact SiP can be produced at this time. In view of designing such a device and designing the manufacturing process, the most urgent task in forming such a SiP is to create three-dimensional electrical connections.

[0007] According to the international patent application WO 2015 / 082952 A1, a MEMS device and another electronic device packaged by wafer-level packaging technology and a manufacturing method thereof are disclosed.

[0008] In current solutions, special contact pads are required, which must be provided on the top surface of the chip adjacent to the device structure. Known methods of forming SiP packages treat individual chips to build a three-dimensional chip arrangement. These techniques do not allow the construction of SiPs on a wafer level, but only on a chip level.

[0009] Current TFP packages for SAW and BAW filters and duplexers have the following weaknesses:

[0010] -UBM pad requires a large area on the active surface of the SAW chip.

[0011] - Limited flexibility in UBM pad location, resulting in reduced design flexibility.

[0012] - Hermeticity is limited by the openings in the SiN layer of the UBM.

[0013] - Large domes cannot be supported by pillars and are prone to cracking.

[0014] - Low stand-off due to dome shape.

[0015] - No metal shielding for active structures is available. Summary of the invention

[0016] The purpose of the present application is to provide an electronic device that can be processed at the wafer level and a method for manufacturing the package thereof. Another purpose is to provide a packaging technology that can be performed at the wafer level.

[0017] These and other objects are achieved by the packaging and methods of embodiments of the present disclosure.

[0018] The proposed package for electronic devices is based on a substrate comprising at least one piezoelectric layer. In addition to the piezoelectric layer, various other layers may be present to form a multilayer substrate. The substrate may be a bulk piezoelectric material, or may include a carrier substrate and a functional piezoelectric layer. Such a substrate is suitable for forming a SAW device or a BAW device thereon.

[0019] Structures are formed on a first surface of the substrate, the first surface being located on a surface of the piezoelectric layer device. The device structures are enclosed in an integrally formed encapsulation layer structure, which is applied to the first surface and includes at least one mechanical support layer, the at least one mechanical support layer covering the first surface of the substrate and enclosing the device structure in the cavity. A first contact pad is arranged on the first surface of the substrate and electrically connected to the device structure. A second contact pad is arranged on a second surface of the substrate opposite the first surface. A via is guided through the substrate to electrically interconnect the first contact pad and the second contact pad.

[0020] The proposed package bonding combines the advantages of the used thin film encapsulation comprising an encapsulation layer applied directly on the top surface of the device, wherein contact pads provided on the opposite surface of the substrate can be used. Those different kinds of contact pads allow to build a stack by simply connecting these pads for forming an electrically and mechanically connected stack of different substrates.

[0021] In one embodiment, the mechanically stable support layer comprises a silicon oxide layer, which forms a dome that encloses the cavity together with the device structure arranged therein. Above the dome, a protective layer is applied, which covers at least the support layer. As the topmost layer, a barrier layer can cover the protective layer.

[0022] According to a first embodiment, the first contact pad is covered by the encapsulation layer structure and external contacting of the device structure is only provided by the second contact pad.

[0023] According to a second embodiment, the first pad is exposed from the first surface side in the encapsulation layer structure. Thus, the encapsulated device can be contacted from the first surface side and / or the second surface side.

[0024] The silicon oxide layer provides enough mechanical stability to build a suspended dome providing a closed cavity. Other layers applied on the silicon oxide layer provide additional mechanical stability and allow planarization of the top surface. A planar surface is beneficial and makes it easy to stack different substrates one after another.

[0025] The package can be used for SiP packaging. In a third embodiment, a second similar package is provided, which has at least one first pad, which is exposed on the first surface side according to the second embodiment; or has a second contact pad on the second surface of the substrate. The first package according to the first embodiment as described above is connected to the second package by connecting the second pad of the first package to the first pad or the second pad of the second package via bonding of solder bumps, pillars or stud bumps.

[0026] This stacked package can be formed on a wafer level by stacking corresponding wafers with a plurality of such electrical devices on each other. The first package and the second package can be stacked in the same orientation, which means that the two packages have the same first surface or the same second surface as the top surface. The bottom package only needs to expose one type of contact pad, which is preferably a second contact pad, wherein the first contact pad is covered by an integrated packaging layer structure, and the top package in the stack only needs the second contact pad. A third package with a first contact pad and a second contact pad exposed on its first surface and second surface can be inserted between the first package and the second package to form a stack of three or more packages. Via their contact pads, different packages in the stack are electrically and mechanically connected to each other. External electrical contact can be made on the bottom surface of the bottom package or on the top surface of the top package.

[0027] In a preferred embodiment, the device structure is part of a SAW device or a BAW device, which requires a cavity for interference-free operation. Such a cavity is provided by an integrally formed packaging layer structure. However, other MEMS devices or any other electronic devices can be used for the proposed package. In a preferred embodiment, such a substrate stack includes a wafer stack as a first substrate, a second substrate or any higher substrate. Thin electrical devices can be separated from such a stack, for example, by dicing using a saw or similar separation tool. Other methods suitable for dicing include dicing before grinding (DBG), laser cutting, plasma etching and similar methods.

[0028] According to the present invention, a method for manufacturing such a package for an electronic device is proposed. The method comprises the following steps:

[0029] A) providing a first wafer, the first wafer comprising a piezoelectric layer;

[0030] B) simultaneously forming a plurality of device structures of electronic devices and first pads connected to the device structures on a first surface of a first wafer;

[0031] C) applying an integral encapsulation layer structure over the device structure, the integral encapsulation layer structure being sealed to the first surface and forming a cavity between the layer structure and the first surface of the wafer to enclose the device structure within the cavity;

[0032] D) reducing the thickness of the wafer from a second surface opposite to the first surface;

[0033] E) forming a hole of a certain depth on the second surface until a bottom portion of the first pad is exposed;

[0034] F) depositing a metallization layer on the second surface in electrical contact with the first pad in the hole;

[0035] G) forming a second pad from the metallization layer on or on the second surface of the metallization layer.

[0036] To form a BAW device, steps A) and B) include: providing a carrier substrate; forming a first (bottom) electrode layer; forming a piezoelectric layer as a first functional layer; and forming a second (top) electrode layer on top of the piezoelectric layer.

[0037] After forming the integrated encapsulation layer structure, the substrate provides sufficient mechanical stability to be thinned in step D). Using a thinner substrate can facilitate the formation of holes. A hole is formed in the second surface directly below the first contact pad so that the first contact pad can be used as a stop layer in the hole formation process.

[0038] The metallization layer deposited in step F) forms a conductive connection between the first contact pad in the bottom of the hole and the metallization layer applied on the second surface of the substrate. The metallization layer may include one or more layers of the same metal or different metals. The second pad formed on the second surface by the metallization layer or by the metallization layer may be thickened by an electroplating process or any other metal deposition technique.

[0039] In a preferred embodiment, forming the hole in step E) comprises ablating material from the wafer by a drilling process, by an etching process or by ablating material from the wafer using a laser beam. In all cases, it is advantageous to provide the first contact pad with a thickness greater than the thickness of a normal contact pad in order to facilitate the hole forming process without compromising the functionality of the first contact pad.

[0040] According to another embodiment, a second wafer is provided by performing steps A) to G) at a second wafer. Then, the first wafer and the second wafer are stacked and arranged so that their second surfaces face each other and contact each other. Then, the second contact pads of the first wafer and the second wafer are directly connected to each other.

[0041] In this arrangement, the first contact pads of the first wafer and the second wafer are not necessary for external contact and can remain covered by the packaging layer structure. However, one of the first wafer and the second wafer can provide an exposed first contact for external contact of the arrangement. On the first surface, the area of ​​the first contact pad that remains unexposed can be made smaller than the area of ​​the pad used for external contact through bumps or any other solder connection. Therefore, the proposed arrangement has less area consumption on the first surface of the contact pads and provides or leaves more area for the device structure. Alternatively, the total surface area required for the electronic device structure is smaller, and therefore, a smaller electronic device can be realized.

[0042] According to an alternative stacking method, a second wafer is provided by performing steps A) to D). Then, in step H2), the first pad of the second wafer is exposed. In step J2), the first wafer and the second wafer are stacked in an arrangement, wherein the second surface of the first wafer faces the first surface of the second wafer. Then, the second pad of the first wafer is directly connected to the first pad of the second wafer. The connection can be accomplished by solder bumps, stud bumps, pillars, or any other wafer or chip connection method.

[0043] Singulating individual electronic devices from the wafer stack may be facilitated by the following steps performed after step C):

[0044] C1) forming grooves in the first surfaces of the first wafer and the second wafer to divide different areas of a subsequent single device;

[0045] C2) temporarily bonding the first surface of the first wafer to a temporary carrier;

[0046] D) reducing the thickness of the first wafer from the second surface to expose the trench from the bottom;

[0047] E) forming a hole of a certain depth on a second surface of the first wafer opposite to the first pad until a bottom portion of the first pad is exposed;

[0048] F) depositing a metallization layer on the second surface of the first wafer to make electrical contact with the first pad in the hole;

[0049] G) forming a second pad on or from the metallization layer on the second surface of the first wafer;

[0050] H2) exposing the first pad of the second wafer;

[0051] J2) arranging the first wafer and the second wafer in a stack in which the second surface of the first wafer faces the first surface of the second wafer, and then directly connecting the second pad of the first wafer to the first pad of the second wafer;

[0052] K2) reducing the thickness of the second wafer from the second surface to expose the trench from the bottom.

[0053] The depth of the groove formed in step C1) is less than the thickness of the wafer. Therefore, the wafer still has sufficient mechanical stability for handling. In step D), the thickness reduction consists in removing wafer material from the second surface until the groove is exposed. Then, all the individual devices are separated from each other, but still mounted together on the temporary carrier. Therefore, all other steps of the manufacturing process can be applied to all the individual devices in parallel with each other, just as on the wafer, although these individual devices are separated from each other but only connected by the temporary carrier to which they are mounted.

[0054] In one embodiment, step C) of the manufacturing method comprises: forming a barrier layer as the topmost layer of the encapsulation layer structure, wherein the barrier layer is selected from a metal layer, a SiN layer, and any other layer that can be used as a moisture barrier. The encapsulation layer structure can be sealed to the corresponding first surface of the wafer between the domes that enclose the cavity on the device structure. A perfect seal can be achieved if the barrier layer is also sealed to the surface of the wafer so that all other encapsulation layers are covered and sealed between the surface of the wafer and the barrier layer. Then, grooves are arranged in those areas where the barrier layer is sealed to the surface and the formation of the grooves has no effect on the sealing properties of the barrier layer.

[0055] According to other developments, steps F) and G) include the following steps: forming a redistribution layer in or on a metallization layer on a second surface of the respective wafer. forming a second pad laterally offset relative to the first pad. The conductive line of the redistribution layer electrically connects the second pad to the metallization layer in the hole, thereby connecting the second pad to the respective first pad.

[0056] The advantage of a redistribution layer is that the footprint on the second surface does not need to conform to the "footprint" of the first pad on the first surface. Thus, the placement of the second contact pad can be done independently of the placement of the first contact pad, which is controlled by the device structure and cannot be freely chosen. Within such a redistribution layer, electrical connections of different first pads of one and the same electronic device can be made, saving additional surface area on the first surface that does not require such connections.

[0057] The proposed method allows the formation of wafer stacks and substrate stacks of more than two wafers. Thus, the method comprises the steps of preparing a third wafer or a fourth wafer and bonding the third wafer or the fourth wafer to the corresponding second pad of the already formed stack of the first wafer, the second wafer or a higher numbered wafer. In such a higher stack, any intermediate wafer (that is, a wafer between two adjacent wafers on the top and the bottom of the wafer) needs to have two types of pads, that is, a first contact pad on the first surface and a second contact pad on the second surface to allow electrical connection to the upper wafer and the lower wafer, respectively.

[0058] If the wafer having the grooves prepared on its first surface is bonded to a temporary carrier having a first surface, it is advantageous to select carriers having identical or similar thermal expansion properties. Only in this way can stresses due to different thermal expansion coefficients be avoided, which could damage the device structure and thus the partitioning of the device.

[0059] After finishing the fabrication of the devices which are still bonded to the temporary carrier, the already separated individual devices can be picked up or debonded from the temporary wafer and further mounted onto a reel. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In the following, the invention is further explained by means of specific embodiments and drawings. The drawings are only schematic and not drawn to scale, so that features may be exaggerated or reduced in size, so that the relative sizes of different features cannot be taken from the drawings.

[0061] Figure 1 A first embodiment of a package is shown in cross-sectional view;

[0062] Figure 2 A second embodiment of the package is shown in cross-section;

[0063] Figure 3 A stack of two packages is shown;

[0064] Figure 4 A stack of three packages is shown;

[0065] Figure 5 The different steps of a method for manufacturing such a package are shown;

[0066] Figure 6 The stage after the grooves are created is shown;

[0067] Figure 7 shows a wafer with grooves dividing the total surface area into smaller regions, each region being used for a single electronic device;

[0068] Figure 8 shows packaging at the wafer level after thinning the substrate; and

[0069] Fig. 9 The second embodiment of the package is shown after a second pad and bumps are formed thereon. DETAILED DESCRIPTION

[0070] Figure 1 A cross section of a first embodiment of the package 1 is shown. The substrate SU comprises at least one piezoelectric layer or may be made entirely of a piezoelectric material. On top of the substrate SU, that is, on its first surface S1, a device structure for an electronic device is arranged and connected to a first contact pad P1. For simplicity, the device structure is not shown in the figure. The entire device structure or part of the device structure is arranged in a cavity between the encapsulation layer structure PK and the first surface S1 of the substrate SU. The encapsulation layer structure PK is applied to the first surface S1 and forms a dome, which encloses the cavity between the encapsulation layer structure PK and the first surface S1. The cavity allows device structures that are sensitive to mechanical shocks to operate freely.

[0071] The encapsulation layer structure PK comprises at least one mechanical support layer SL, at least one dome, and may comprise other layers deposited thereon to further mechanically stabilize the encapsulation layer structure PK. The outermost layer of the encapsulation layer structure may be a barrier layer BL forming a moisture barrier. The barrier layer may also comprise a metal used to shield electromagnetic fields.

[0072] On the second surface S2 of the substrate SU, a metallization layer is applied to form at least one second contact pad P2. A via V is directed through the substrate SU opposite the first pad P1 and connects the first pad to the metallization layer on the second surface S2. On the metallization layer, at least one second contact pad is formed.

[0073] In this figure, two cavities are shown. However, depending on the size and number of device structures, the electronic device may include any number of domes / cavities, for example, one or more than two domes. Because during the manufacture of the package, the first contact pad P1 must be used as a blocking layer when forming the hole, the thickness of the first contact pad P1 is greater than the thickness of a normal contact pad. The device structure may require two or more electrical terminals and therefore be connected to two or more first pads P1. Each first pad P1 is connected to a second pad P2 on the second surface S2 by means of a through hole V formed through the substrate SU.

[0074] The figure shows a section of a substrate carrying a device structure of an electronic device. Preferably, the substrate SU is a wafer carrying a plurality of such device structures, each of which is covered by a packaging layer structure. Alternatively, the packaging layer structure may be a common structure for all device structures on the same wafer.

[0075] Figure 2 A second embodiment of a package 1 ' is shown which is similar to the package 1 of the first embodiment, except that an opening OP is formed above the first pad P1 and its surface is exposed. The barrier layer BL may or may not be sealed to the surface of the first pad P1 at the sidewalls of the opening OP. Thus, the depicted package 1 ' provides free access to the first pad P1 and the second pad P2 and allows connection of the package to the pads on the first surface S1 or the second surface S2.

[0076] Figure 3 A third embodiment of the invention is shown, in which the package of the first embodiment and the package 2 of the second embodiment are stacked on each other and connected via two different kinds of pads. The first substrate SU1 is connected to the first pad P1 of the second substrate SU2 via the second pad P2 on its second surface S2. The second substrate SU2 still has a freely accessible second pad P2 on the second surface. The electrical connection between the first substrate and the second substrate is made with the aid of connecting means CM, which are formed as solder balls, bumps, stud bumps or pillars. The first substrate SU1 is mounted to the second substrate SU2 by connecting all the second pads P2 of the first substrate SU1 simultaneously to the corresponding first pads P1 of the second substrate SU2. Thus, the two packages can be stacked and mounted on wafer level.

[0077] Figure 3 An advantage of the arrangement shown is that the first substrate SU1 on top of the arrangement does not need to expose the freely accessible first pads P1 on its topmost surface. Thus, the first substrate or first package saves surface area that might otherwise be required for accessible solderable pads. The surface area saved on the first surface can be advantageously used to arrange device structures there or to reduce the first package by a corresponding amount.

[0078] and Figure 2The packaging structure of the second embodiment shown is different. Figure 3 The second substrate SU2 does not have to have the second pad P2 and therefore does not need to have a through-hole V for connecting the first pad to the second pad. External contacting of the arrangement may be done by another contact or contact structure.

[0079] Figure 4 Another arrangement is shown, where Figure 1 and Figure 2 As shown, three packages are stacked one on top of another and are electrically and mechanically connected by connecting means CM. The stacking can be accomplished by connecting the two packages via the second pads of the second substrate SU2. Figure 3 The stack is installed according to Figure 2 Furthermore, herein, the topmost package on the first substrate SU1 does not provide access to the first contact pad covered by the package layer structure PK. Figure 3 The arrangement provides the same benefits.

[0080] Furthermore, in this arrangement, the bottom package / substrate SU3 requires neither the second pads P2 nor the vias connecting the second pads to the corresponding first pads P1.

[0081] Figure 3 and Figure 4 The stacked arrangement shown forms a system in a package and allows three-dimensional integration of electronic devices which saves space and can be miniaturized relative to arrangements including only lateral arrangements of devices.

[0082] Figure 5 Shown as Figure 1 Different stages of a method for manufacturing a package are shown. The process starts with a substrate SU, which comprises at least one piezoelectric layer or is a piezoelectric material. A device structure is arranged on its first surface S1 and is connected to a first pad P1. The device structure and the first pad P1 are made of different metallization layers, or at least have different heights, since the thickness of the first pad P1 is substantially higher than the thickness of the metallization layer of the device structure.

[0083] In case of a SAW device, the device structure may be covered with a layer which reduces the TCF (= Thermal Coefficient of Frequency). Such a layer may be formed as a SiO2 layer of about 1.5 μm thick. The TCF reducing layer may be covered by a trimming layer of, for example, SiN.

[0084] The structure is then covered with a sacrificial layer SC, which may be applied to the entire first surface S1 and then structured to cover only the device structure to be protected thereunder. Alternatively, the sacrificial layer SC may be applied only at those locations where it is needed. Figure 5 a shows such a structured sacrificial layer.

[0085] In a next step, the structured sacrificial layer SC is covered by a mechanically stable supporting layer SL. The supporting layer can be deposited over the entire surface of the first surface of the substrate SU, but can be constructed to cover only the sacrificial material of the sacrificial layer SL and the edges of these islands surrounding the sacrificial material SC. In a preferred example, the supporting layer SL comprises a SiO2 layer of about 3 μm thick applied in a sputtering process. If necessary, the supporting layer SL can be structured by photolithography and dry etching processes.

[0086] In the next step, a release hole is formed through the support layer SL, and the sacrificial material through the release hole is removed, for example, by wet etching. Figure 5 B shows the arrangement in this state.

[0087] In the next step, the release hole is closed by applying a suitable closing material on the release hole, thereby closing the cavity CV. Then, the other layers of the encapsulation layer structure can be applied. One of these layers can be a polymer layer of about 9 μm thick, such as BCB, which can be easily planarized so that a flat surface remains on top of the encapsulation layer structure PK. The topmost layer is a barrier layer BL, which is preferably sealed to the first surface S1 of the substrate SU. The barrier layer may include SiN or a metal. Figure 5 C shows the arrangement of this stage.

[0088] In a next step, the substrate SU can be thinned in a suitable process, for example by grinding. The resulting final thickness of the substrate is selected to provide reliable device operation and further maintain sufficient mechanical stability to handle the substrate / package. If the substrate SU is a piezoelectric layer and there is a device structure for a SAW device or a BAW device, the thickness of an exemplary thinned substrate is selected to be 60 μm to 70 μm. Figure 5 D shows an arrangement with a respectively thinned substrate SU.

[0089] In the next step, holes HL are formed through the substrate from the second surface side S2 to expose the bottom side of the first contact pad P1. These holes HL can be formed by a wet etching process or a dry etching process, or directly by using a laser beam. In the latter case, the sidewalls of the holes HL are inclined relative to the surface to have a smaller cross section at the first contact pad side on the first surface S1. Figure 5 E shows the arrangement of this stage.

[0090] In the next step, a metallization layer is applied to the second surface S2 to at least cover the sidewalls and contact the first contact pad from the bottom from the side of the second surface S2, respectively. The metallization layer ME can be applied to the entire second surface S2 and then structured. Alternatively, the first partial layer of the metallization layer can include a sputtering deposition bonding layer of Ti and a sputtering seed layer of copper. A photoresist mask can be applied to the entire metallization surface, and then, an electroplating process is performed to thicken the metallization layer in the exposed area of ​​the resist mask. Thus, a second contact pad P2 preferably formed by Cu and having a thickness of about 5 μm is formed on the metallization layer. The pad can be completed by applying a sub-bump metallization layer including a solderable metal as a top layer (e.g., Au). Instead, other solderable layers including one of Ni and Ag can be used. On such a solderable layer, solder bumps or copper pillars or columnar bumps can be applied to make electrical contact. Figure 5 F shows the arrangement at this stage.

[0091] The metallization layer may include one or more layers, and at least one of them is a conductive layer. Other useful deposition techniques include PVD, CVD, electroplating deposition, or chemical deposition. Another method is to spray a suspension of conductive nanoparticles and then evaporate the solvent. The metallization layer can be directly applied in a structured form using a suitable mask applied on the substrate surface.

[0092] If photoresist is used, it can be removed by a wet chemical process or plasma.

[0093] In a next step, solder bumps, stop bumps or other connection means are applied on the second surface by means of stencil printing (eg with subsequent reflow) or via photographic techniques in an electroplating process.

[0094] The electronic device is now ready for installation into the desired final circuit or for storage and transportation.

[0095] Figures 6 to 8 Process steps are shown that may be used to singulate individual electrical devices from a wafer containing multiple such devices.

[0096] Figure 6 FIG. 4 shows a portion of a wafer substrate SU with a packaging layer structure PK applied on a first surface S1 of a device structure covering an electronic device. As shown in this embodiment, a further planarization layer PL may be applied to the device structure. Figure 5 F or Figure 1 In order to facilitate the singulation process, trenches are formed from the first surface side through all layers of the encapsulation layer structure PK and through a portion of the layer thickness of the substrate SU. The trenches TR follow the separation lines that separate the individual devices from each other. Figure 6The arrangement after trench formation is shown. For simplicity, only one device is shown from the entire wafer.

[0097] Figure 7 A larger cross section of such a wafer is shown, in which the packaging layer structure is only schematically depicted and simplified. All trenches are cut into the substrate to the same depth. In this article, other planarization layers are omitted.

[0098] In a next step, the arrangement is stabilized by bonding it to a temporary carrier TC in a suitable bonding process. Figure 8 A connection by means of a thermal adhesive layer AL is shown. The package is embedded in the thermal adhesive layer AL on the temporary carrier TC, which thermal adhesive layer AL has been softened in the thermal step.

[0099] The temporary carrier TC is preferably adapted to the substrate material in view of its coefficient of thermal expansion, in order to avoid thermal stresses when the arrangement is heat treated during further processing.

[0100] In a next step, the thickness of the substrate is reduced by thinning the substrate wafer from the second surface until the trenches are exposed from the bottom. This can be done by a possible step of grinding followed by chemical mechanical polishing (CMP). Figure 8 The arrangement of this stage is shown.

[0101] Alternatively, in the case where only a thin piezoelectric layer is arranged on a carrier substrate such as a Si wafer, the step of forming the grooves may comprise forming grooves in the first surface of the substrate, the grooves only cutting through the piezoelectric layer. After thinning the substrate from the second surface side, the grooves are not yet exposed.

[0102] In a further alternative method variant, in which only a thin piezoelectric layer is arranged on a carrier substrate, the step of forming the trenches is completely omitted.

[0103] In two alternative variants, without grooves or with grooves that only pass through the piezoelectric layer, after the second surface has been completely processed, the substrate is separated into individual devices from the second surface side by laser cutting or plasma etching, such as for later incorporation into Figure 8 Such further processing includes forming a redistribution layer on the second surface, further structuring the redistribution layer, and forming a UBM on the second pad. In this case, the second surface can be further processed before the singulation step, so no temporary carrier or mounting foil is required.

[0104] Now, we can Figure 8 The arrangement shown is combined Figure 5 E and Figure 5The process step shown in F is to form a hole through the substrate to expose the first pad on the first surface from the bottom, deposit a metallization layer on the second surface, and form a second pad on or in the metallization layer.

[0105] When the second pads P2 are finished, the entire wafer arrangement which has been bonded to the temporary carrier can be mounted to another wafer by connecting it to the first pads or the second pads of the other wafer.

[0106] Although the devices have been singulated, a mounting foil or another temporary carrier can still be attached and fixed to the first surface, and the substrate can then be singulated from the second surface for further processing at the "wafer level". With the mounting foil, a number of individual devices can be processed in parallel, just like the wafer. On the mounting foil, the same mutual arrangement of the individual devices as on the wafer is maintained.

[0107] Fig. 9 The package according to the first embodiment is shown after the bump or after applying the connection means to the metallization layer ME at the second pad. Between the pad and the connection means / bump, the under-bump metallization layer UBM is applied. The barrier layer can be a metal that forms an electromagnetic shield. The barrier layer then seals and contacts the first exposed pad.

[0108] The proposed package has at least the following advantages:

[0109] - The smallest possible physical size of the device / chip.

[0110] - The smallest contact pads on the first surface are the functional wafer side.

[0111] - Maximum possible flexibility for arranging contact pads and tile layout due to the redistribution layer RDL.

[0112] - When multiple packages are stacked, the package is absolutely hermetic due to the unstructured SiN or metal outer layer on the top or topmost package.

[0113] - A metal shield may be formed as the topmost packaging layer or stack for preventing electromagnetic fields and heat transfer.

[0114] - Compatible with standard bump and 180μm bump pitch technology and copper pillar process.

[0115] - Copper pillars or frames can be used as auxiliary supporting metal structures to enhance dome strength and package stability, which can be formed in the same step and together with the pads.

[0116] - The standoff of existing SAW packages is highest when the second pad is contacted to an external circuit such as a PCB etc. This high standoff is advantageous in a subsequent optional molding or underfilling step.

[0117] -Packages can be stacked with the same or similar packages (DSSP, TFAP1, TFAP2). Packages of different types can be stacked on the same substrate.

[0118] - If the same package is used, several different layer stacks can use the same approach.

[0119] -The package can be used for any wafer material: LN, LT, Si.

[0120] - In case the substrate comprises a Si wafer for a BAW device or a thin film SAW device, further integration with a semiconductor chip is possible.

[0121] Although only some embodiments are shown, the invention is not limited to the embodiments and the drawings.The broadest definition of the invention can be obtained from the independent claims.

[0122] List of reference symbols used

[0123]

[0124]

Claims

1. A package for an electronic device, comprising: a substrate comprising at least one piezoelectric layer; an operating device structure located on the first surface of the piezoelectric layer; an integrally formed packaging layer structure, located on the first surface, comprising at least one mechanical support layer, the at least one mechanical support layer covering the first surface of the substrate and enclosing the operating device structure in the cavity; a first contact pad, located on the first surface of the substrate and electrically connected to the operating device structure; a second contact pad located on a second surface opposite to the first surface; a through-hole leading through the substrate and electrically interconnecting the first contact pad and the second contact pad; as well as A barrier layer is at least above the mechanical support layer and has an opening for coupling the first contact pad to another substrate.

2. The package according to claim 1, wherein The mechanical support layer includes a silicon oxide layer, the silicon oxide layer forming a dome enclosing the operating device structure; A protective layer covering the mechanical support layer; The barrier layer covers the protective layer; and The first contact pad is exposed on the first surface.

3. The package according to claim 1 or 2, wherein the first contact pad is covered by the packaging layer structure, and The external contact of the operating device structure is provided only by the second contact pad.

4. The package according to claim 1 or 2, wherein The package is connected to the other substrate by connecting the first contact pad to a third contact pad of the other substrate via solder bump, pillar or stud bump bonding through the opening of the barrier layer.

5. The package according to claim 1 or 2, wherein The operating device structure is part of a SAW device or a BAW device.

6. The package according to claim 1 or 2, The substrate is a wafer including the electronic device.

7. A method for manufacturing a package, comprising: forming a device structure of an electronic device on a first surface of a first wafer and forming a first pad connected to the device structure, the first wafer including a piezoelectric layer; applying an integral packaging layer structure on the device structure, the integral packaging layer structure being sealed to the first surface and forming a cavity between the integral packaging layer structure and the first surface of the first wafer to enclose the device structure within the cavity, wherein the integral packaging layer includes a mechanical support layer; reducing a thickness of the first wafer from a second surface opposite to the first surface; forming a hole of a certain depth on the second surface until a bottom portion of the first pad is exposed; depositing a metallization layer on the second surface in electrical contact with the first pad in the hole; A second pad is formed on the second surface, wherein applying the integrated encapsulation layer structure includes forming a barrier layer at least over the mechanical support layer and having an opening for coupling the first pad to another substrate.

8. The method according to claim 7, Wherein forming the hole comprises: Material is ablated from the first wafer by drilling, by etching or by using a laser beam.

9. The method according to claim 7, further comprising: The first wafer and the second wafer are arranged in a stack, wherein the second surface of the first wafer faces a surface of the second wafer, and the second pads of the first wafer are directly connected to pads of the second wafer.

10. The method according to claim 7, further comprising: exposing the pads of the second wafer; arranging the first wafer and the second wafer in a stack, wherein the second surface of the first wafer faces a surface of the second wafer, and The second pad of the first wafer and the pad of the second wafer are directly connected.

11. The method according to claim 7, further comprising: forming grooves in the first surface of the first wafer and in a surface of a second wafer; bonding the first surface of the first wafer to a temporary carrier, wherein reducing the thickness of the first wafer from the second surface exposes the trench; forming the second pad on the second surface on or from the metallization; exposing the first pad of the second wafer; arranging the first wafer and the second wafer in a stack in which the second surface of the first wafer faces the first surface of the second wafer, and directly connecting the second pad of the first wafer and the first pad of the second wafer; and The thickness of the second wafer is reduced from the second surface to expose the trenches in the second wafer.

12. The method according to claim 7, wherein the first wafer comprises a thin piezoelectric layer on a carrier substrate, The method further comprises: After applying the unitary encapsulation layer structure, a groove is formed which cuts through only the piezoelectric layer.

13. The method according to claim 7, Wherein applying the integrated encapsulation layer structure comprises: forming the barrier layer as the topmost layer of the integrated encapsulation layer structure, and The barrier layer is a metal layer, a SiN layer, or any other layer capable of serving as a moisture barrier.

14. The method according to claim 7, Wherein depositing the metallization layer and forming the second pad comprises: forming a redistribution layer in or on the metallization layer and forming the second pad laterally offset relative to the first pad, The conductive line of the redistribution layer electrically connects the second pad to the metallization layer in the hole.

15. The method according to claim 7, Also includes: A second wafer is prepared and bonded to the second pad.

16. The method according to claim 11, wherein the temporary carrier comprises the same material as the first wafer, After reducing the thickness of the second wafer, the temporary carrier is separated from the first wafer.

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