Semiconductor device

Abstract

A semiconductor device is provided, including: an active region located on a substrate and including a first sidewall and a second sidewall extending in a first direction; and an epitaxial pattern located on the active region, wherein the epitaxial pattern includes a first epitaxial sidewall and a second epitaxial sidewall extending from the first sidewall and the second sidewall respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first epitaxial upper sidewall and the second epitaxial upper sidewall decreases away from the active region, and the first epitaxial lower sidewall and the second epitaxial lower sidewall extend parallel to a top surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0067746, filed on June 10, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to semiconductor devices having a gate-ring structure. Background Technology

[0004] As a scaling technique for increasing the density of semiconductor devices, a ring gate structure has been proposed, in which a nanowire silicon body is formed on a substrate and a gate is formed around the silicon body.

[0005] Because the gate-to-ring structure uses a three-dimensional (3D) channel, it can be easily scaled. Furthermore, current control capability can be improved without increasing the gate length. Additionally, the short-channel effect (SCE), the phenomenon where the channel potential is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device capable of improving performance and reliability by controlling the shape of epitaxial patterns in a transistor having a gate-ring structure.

[0007] However, the embodiments of the inventive concept are not limited to those described herein. The above and other embodiments of the inventive concept will become more apparent to those skilled in the art from the following detailed description of the inventive concept.

[0008] According to an example of the concept of the present invention, this disclosure relates to a semiconductor device comprising: an active region disposed on a substrate and including a first sidewall and a second sidewall extending in a first direction; and an epitaxial pattern disposed on the active region, wherein the epitaxial pattern includes a first epitaxial sidewall and a second epitaxial sidewall extending from the first sidewall and the second sidewall of the active region, respectively, wherein the first epitaxial sidewall includes a first lower epitaxial sidewall, a first upper epitaxial sidewall, and a first epitaxial connecting sidewall connecting the first lower epitaxial sidewall and the first upper epitaxial sidewall, wherein the second epitaxial sidewall includes a second lower epitaxial sidewall, a second upper epitaxial sidewall, and a second epitaxial connecting sidewall connecting the second lower epitaxial sidewall and the second upper epitaxial sidewall, wherein the distance between the first upper epitaxial sidewall and the second upper epitaxial sidewall in a second direction perpendicular to the first direction decreases as the distance from the active region increases in a third direction perpendicular to the first and second directions, and wherein the first lower epitaxial sidewall and the second lower epitaxial sidewall extend parallel to the top surface of the substrate.

[0009] According to an example of the concept of the present invention, this disclosure relates to a semiconductor device comprising: an active region including a first sidewall and a second sidewall extending in a first direction; and an epitaxial pattern disposed on the active region, wherein the epitaxial pattern includes a first epitaxial sidewall and a second epitaxial sidewall extending from the first sidewall and the second sidewall of the active region, wherein the first epitaxial sidewall includes a first lower epitaxial sidewall, a first upper epitaxial sidewall, and a first epitaxial connecting sidewall connecting the first lower epitaxial sidewall and the first upper epitaxial sidewall, wherein the second epitaxial sidewall includes a second lower epitaxial sidewall, a second upper epitaxial sidewall, and a second epitaxial connecting sidewall connecting the second lower epitaxial sidewall and the second upper epitaxial sidewall, wherein the first upper epitaxial sidewall and the second upper epitaxial sidewall are formed by crystal planes included in a first family of crystal planes, and wherein the first epitaxial connecting sidewall and the second epitaxial connecting sidewall are formed by crystal planes included in a second family of crystal planes different from the first family of crystal planes.

[0010] According to an example of the concept of the present invention, this disclosure relates to a semiconductor device comprising: a first active region disposed in a first region of a substrate and including a first sidewall and a second sidewall extending in a first direction; a second active region disposed in a second region of the substrate and including a third sidewall and a fourth sidewall extending in a second direction; a first epitaxial pattern disposed on the first active region; and a second epitaxial pattern disposed on the second active region, wherein the first epitaxial pattern includes a first epitaxial sidewall and a second epitaxial sidewall extending from the first sidewall and the second sidewall of the active region, respectively, wherein the first epitaxial sidewall includes a first lower epitaxial sidewall, a first upper epitaxial sidewall, and a first epitaxial connecting sidewall connecting the first lower epitaxial sidewall and the first upper epitaxial sidewall, wherein the second... The epitaxial sidewalls include a second lower epitaxial sidewall, a second upper epitaxial sidewall, and a second epitaxial connecting sidewall connecting the second lower epitaxial sidewall and the second upper epitaxial sidewall. The second epitaxial pattern includes a third epitaxial sidewall and a fourth epitaxial sidewall extending from the third sidewall and the fourth sidewall of the second active region, respectively. The third epitaxial sidewall includes a third lower epitaxial sidewall and a third upper epitaxial sidewall directly connected to the third lower epitaxial sidewall. The fourth epitaxial sidewall includes a fourth lower epitaxial sidewall and a fourth upper epitaxial sidewall directly connected to the fourth lower epitaxial sidewall. The first upper epitaxial sidewall to the fourth upper epitaxial sidewall, as well as the third lower epitaxial sidewall and the fourth lower epitaxial sidewall, are formed by crystal planes included in the first family of crystal planes. The first lower epitaxial sidewall and the second lower epitaxial sidewall are formed by crystal planes included in the second family of crystal planes. Attached Figure Description

[0011] The above and other embodiments and features of the present invention will become clearer by referring to the accompanying drawings, which describe in detail the embodiments of the present invention.

[0012] Figure 1This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0013] Figure 2 , Figure 3 and Figure 4 They are along Figure 1 A sectional view taken from lines AA, BB, and CC;

[0014] Figure 5A , Figure 5B , Figure 5C and Figure 5D yes Figure 1 Cross-sectional views of various examples of the first nanosheet taken along line BB;

[0015] Figure 6A , Figure 6B and Figure 6C yes Figure 1 Cross-sectional views of various examples of the first nanosheet taken along line AA;

[0016] Figure 7 yes Figure 1 A cross-sectional view of the first nanosheet taken along line AA;

[0017] Figure 8 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0018] Figure 9 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0019] Figure 10A , Figure 10B , Figure 10C and Figure 10D This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0020] Figure 11 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0021] Figure 12 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0022] Figure 13 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0023] Figure 14 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0024] Figure 15This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0025] Figure 16 and Figure 17 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0026] Figure 18 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0027] Figure 19 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0028] Figure 20 It is along Figure 19 A sectional view taken from line DD;

[0029] Figure 21 It is along Figure 19 A cross-sectional view taken by line EE;

[0030] Figure 22 These are cross-sectional views illustrating some embodiments of a semiconductor device according to the present invention; and

[0031] Figure 23 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention. Detailed Implementation

[0032] The accompanying drawings illustrate a gate-all-around field-effect transistor (GAAFET) that includes a nanowire-type channel region or a nanosheet-type channel region, but the inventive concept is not limited thereto.

[0033] The following text will refer to Figures 1 to 7 A semiconductor device according to some embodiments of the concept of the present invention is described.

[0034] Figure 1 This is a plan view illustrating some example embodiments of a semiconductor device according to the present invention. Figures 2 to 4 They are along Figure 1 A sectional view taken from lines AA, BB, and CC. Figures 5A to 5D yes Figure 1 Cross-sectional views of various examples of the first nanosheet taken along line BB. Figures 6A to 6C and Figure 7 yes Figure 1 Cross-sectional views of various examples of the first nanosheet taken along line AA. For convenience, Figure 1 The interlayer insulating film 190 is not shown in the figure.

[0035] Reference Figures 1 to 4 Figures 1 to 4 According to some example embodiments of the inventive concept, a semiconductor device may include a first fin pattern 110, first nanosheets 115_1 and 115_2, first gate structures 120_1 and 120_2, and a first epitaxial pattern 150.

[0036] The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a silicon (Si) substrate, or may include another material, such as, for example, silicon germanium (SiGe), SiGe-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the inventive concept is not limited thereto.

[0037] The first fin pattern 110 may protrude from the substrate 100 (e.g., in a third direction Z1 perpendicular to the first direction X1 and the second direction Y1). The first fin pattern 110 may be disposed on the top surface of the substrate 100. The first fin pattern 110 may extend longitudinally in the first direction X1. The first fin pattern 110 may include a first fin sidewall 110a and a second fin sidewall 110b. The first fin sidewall 110a and the second fin sidewall 110b may extend longitudinally in the first direction X1. The first fin sidewall 110a and the second fin sidewall 110b may define a long side of the first fin pattern 110. As used herein, an item, layer, or a part of an item or layer described as extending "longitudinally" in a particular direction has a length in the particular direction and a width perpendicular to the direction, where the length is greater than the width.

[0038] The first fin pattern 110 may be formed by etching a part of the substrate 100, or may include an epitaxial layer grown from the substrate 100. The first fin pattern 110 may include an elemental semiconductor material such as silicon (Si) or germanium (Ge). The first fin pattern 110 may include a compound semiconductor such as, for example, a group-IV-IV compound semiconductor or a group-III-V compound semiconductor.

[0039] The group-IV-IV compound semiconductor may be a binary or ternary compound including at least two of, for example, carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or may be a compound obtained by doping the binary or ternary compound with a group-IV element. The group-III-V compound semiconductor may be a binary, ternary, or quaternary compound obtained by combining a group-III element such as aluminum (Al), gallium (Ga), and indium (In) with a group-V element such as phosphorus (P), arsenic (As), and antimony (Sb).

[0040] The first fin pattern 110 can be a Si fin pattern including Si. Alternatively, the first fin pattern 110 can be an active region. For example, the first fin sidewall 110a and the second fin sidewall 110b can be sidewalls of an active region.

[0041] Figure 3 and Figure 4 The first fin pattern 110 is shown to be formed as a single-layer film, but the inventive concept is not limited thereto. For example, the upper part of the first fin pattern 110 may include a layer formed of a material other than Si.

[0042] A field insulating film 105 may be formed on the substrate 100. The field insulating film 105 may at least partially cover the first fin sidewall 110a and the second fin sidewall 110b. For example, the field insulating film 105 may contact the first fin sidewall 110a and the second fin sidewall 110b. The first fin pattern 110 may be defined by the field insulating film 105. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, and combinations thereof. The field insulating film 105 may also include at least one field film formed between the first fin pattern 110 and the field insulating film 105. In this case, the field film may include at least one of polycrystalline silicon, amorphous silicon, silicon oxynitride, silicon nitride, and silicon oxide.

[0043] In some embodiments, the field insulating film 105 may substantially cover the first fin sidewall 110a and the second fin sidewall 110b. As used herein, unless the context otherwise indicates, the term “contact” means direct contact (touch).

[0044] First nanosheets 115_1 and 115_2 can be formed on substrate 100. First nanosheets 115_1 and 115_2 can be arranged on a first fin pattern 110. Each of the first nanosheets 115_1 and 115_2 can include multiple nanosheet layers arranged sequentially in the thickness direction (e.g., third direction Z1) of substrate 100. The multiple nanosheet layers can be arranged sequentially on the first fin pattern 110. For example, multiple nanosheet layers of first nanosheet 115_1 and multiple nanosheet layers of first nanosheet 115_2 can be stacked on the first fin pattern 110 in the third direction Z1.

[0045] Figure 2 and Figure 3The illustration shows three nanosheets arranged in the thickness direction (e.g., third direction Z1) of the substrate 100, but the inventive concept is not limited thereto. For example, the first nanosheets 115_1 and 115_2 may comprise one first nanosheet 115_1 and one first nanosheet 115_2. As another example, the first nanosheets 115_1 and 115_2 may comprise two first nanosheets 115_1 and two first nanosheets 115_2. As yet another example, the first nanosheets 115_1 and 115_2 may comprise more than three first nanosheets 115_1 and more than three first nanosheets 115_2.

[0046] The first nanosheets 115_1 and 115_2 may be spaced apart from each other and may be arranged along the top surface of the first fin pattern 110 in a first direction X1. A first epitaxial pattern 150 may be arranged between the first nanosheets 115_1 and 115_2, which are spaced apart from each other in the first direction X1. The first epitaxial pattern 150 may contact the side surface of each of the first nanosheets 115_1 and 115_2.

[0047] The first fin pattern 110 and the first nanosheets 115_1 and 115_2 can be formed by selectively removing a portion of the fin structure, including the first fin pattern 110 and the first nanosheets 115_1 and 115_2. Therefore, the width of the first nanosheets 115_1 and 115_2 in the second direction Y1 can be equal to or less than the width of the first fin pattern 110 in the second direction Y1.

[0048] The first nanosheets 115_1 and 115_2 may comprise elemental semiconductor materials such as Si or Ge. Alternatively, the first nanosheets 115_1 and 115_2 may comprise compound semiconductors such as, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0049] The first nanosheets 115_1 and 115_2 can be used as channel regions of transistors including the first nanosheets 115_1 and 115_2. Each of the first nanosheets 115_1 and 115_2 stacked in the thickness direction of the substrate 100 can include the same material or different materials. For example, the nanosheet layers of the first nanosheets 115_1 and 115_2 closest to the first fin pattern 110 and the second nanosheet layers of the first nanosheets 115_1 and 115_2 closest to the first fin pattern 110 can include the same material or different materials.

[0050] The first nanosheets 115_1 and 115_2 may be made of the same material or a different material from the first fin pattern 110.

[0051] The first nanosheets 115_1 and 115_2 can be used as the channel region of a P-type metal-oxide-semiconductor (PMOS) transistor.

[0052] The first gate structures 120_1 and 120_2 may extend longitudinally in the second direction Y1. The first gate structures 120_1 and 120_2 may intersect with the first fin pattern 110. The first gate structures 120_1 and 120_2 may intersect with the first nanosheets 115_1 and 115_2 that are spaced apart from each other in the first direction X1, respectively. The first gate structures 120_1 and 120_2 may surround the first nanosheets 115_1 and 115_2 that are spaced apart from each other in the first direction X1.

[0053] Each of the first gate structures 120_1 and 120_2 may include a first gate electrode 125, a first gate insulating film 130, a first gate spacer 140, and a first gate trench 140t.

[0054] The first gate spacer 140 may extend longitudinally in the second direction Y1. The first gate spacer 140 may intersect with the first nanosheets 115_1 and 115_2. The first gate spacer 140 may define a first gate trench 140t intersecting with the first nanosheets 115_1 and 115_2. The first gate spacer 140 may be disposed at both ends of the first nanosheets 115_1 and 115_2 extending in the first direction X1. The first gate spacer 140 may be formed such that the two sides of the first nanosheets 115_1 and 115_2 face each other. The first gate spacer 140 may include holes through which the first nanosheets 115_1 and 115_2 can pass.

[0055] Each of the first nanosheets 115_1 and 115_2 can pass through the first gate spacer 140. The first gate spacer 140 can contact the outer peripheral portions of the corresponding first nanosheets 115_1 and 115_2. For example, the first gate spacer 140 can contact portions of the upper and lower surfaces at the outer edges of each of the first nanosheets 115_1 and 115_2.

[0056] The first gate spacer 140 may include a first internal spacer 142 and a first external spacer 141. The first internal spacer 142 may be disposed between the first fin pattern 110 and the lowermost nanosheets of the first nanosheets 115_1 and 115_2, and between each of the first nanosheets 115_1 and 115_2.

[0057] The first internal spacer 142 can be arranged at a position that vertically overlaps with the corresponding first nanosheets 115_1 and 115_2. The first internal spacer 142 may not be formed on some portions of the field insulating film 105 that do not overlap with the first nanosheets 115_1 and 115_2. For example, the first external spacer 141 can be formed on the top surface of the field insulating film 105. The first external spacer 141 can be formed on the uppermost nanosheet layer of the first nanosheets 115_1 and 115_2.

[0058] For example, the first external spacer 141 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), and combinations thereof. For example, the first internal spacer 142 may include at least one of SiN, SiON, SiO2, SiOCN, silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. See also... Figure 2 The first outer spacer 141 and the first inner spacer 142 may be formed of the same material or different materials.

[0059] The first gate insulating film 130 may be formed along the edges of the corresponding first nanosheets 115_1 and 115_2. The first gate insulating film 130 may surround the corresponding first nanosheets 115_1 and 115_2. The first gate insulating film 130 may also be formed on the top surface of the field insulating film 105 and on the first fin pattern 110. The first gate insulating film 130 may extend along the interior of the first gate spacer 140.

[0060] The first gate insulating film 130 may extend along the sidewalls and bottom of the first gate trench 140t and the edges of the corresponding first nanosheets 115_1 and 115_2.

[0061] Although not specifically shown, interface layers can be formed between the first gate insulating film 130 and the corresponding first nanosheets 115_1 and 115_2, and between the first gate insulating film 130 and the first fin pattern 110. Depending on how the interface layer is formed, the interface layer can have the same contour as the first gate insulating film 130.

[0062] The first gate insulating film 130 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material with a dielectric constant greater than that of silicon oxide. Examples of high dielectric constant materials include hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0063] The first gate electrode 125 may intersect with the first nanosheets 115_1 and 115_2, which are separated from the substrate 100, and the first fin pattern 110. The first gate electrode 125 may surround the corresponding first nanosheets 115_1 and 115_2. The first gate electrode 125 may also be formed in the gap between the first nanosheets 115_1 and 115_2 and the first fin pattern 110. The first gate electrode 125 may be formed between the first gate spacers 140. The first gate electrode 125 may be formed on the first gate insulating film 130. The first gate electrode 125 may fill the first gate trench 140t to extend longitudinally in the second direction Y1.

[0064] The first gate electrode 125 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (TaC). The first gate electrode 125 may comprise at least one of the following: N, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0065] For example, the first gate electrode 125 can be formed by a replacement process (or a post-gate process), but the inventive concept is not limited thereto.

[0066] The first epitaxial pattern 150 can be formed between adjacent first gate structures 120_1 and 120_2. The first epitaxial pattern 150 can be formed on the first fin pattern 110. The first epitaxial pattern 150 can be formed by epitaxial growth.

[0067] The first nanosheets 115_1 and 115_2 can be arranged on both sides of the first epitaxial pattern 150. The first epitaxial pattern 150 can be connected to the first nanosheets 115_1 and 115_2.

[0068] The first epitaxial pattern 150 can be included in the source / drain of the channel region using the first nanosheets 115_1 and 115_2. For example, since the first nanosheets 115_1 and 115_2 can be used as the channel region of the PMOS transistor, the first epitaxial pattern 150 can be included in the source / drain of the PMOS transistor.

[0069] The first epitaxial pattern 150 may include a compressive stress material. The compressive stress material may be a material with a lattice constant greater than that of Si, such as, for example, SiGe. By applying compressive stress to the first nanosheets 115_1 and 115_2, the compressive stress material can increase the mobility of charge carriers in the channel region.

[0070] The first epitaxial pattern 150 may include a p-type dopant. For example, the first epitaxial pattern 150 may include at least one of boron (B), in, gallium (Ga), and al. The first epitaxial pattern 150 may include carbon (C) to prevent p-type impurities from diffusing into the channel region.

[0071] Figure 4 The first epitaxial pattern 150 is shown to be a single-layer film, but the inventive concept is not limited thereto.

[0072] The first extensional pattern 150 may include a first extensional sidewall 151s and a second extensional sidewall 152s extending from the first fin pattern 110. The first extensional sidewall 151s may extend from the first fin sidewall 110a of the first fin pattern 110. The second extensional sidewall 152s may extend from the second fin sidewall 110b of the first fin pattern 110.

[0073] The first extensional sidewall 151s may include a first extensional lower sidewall 151sl, a first extensional connecting sidewall 151sc, and a first extensional upper sidewall 151su. The first extensional lower sidewall 151sl, the first extensional connecting sidewall 151sc, and the first extensional upper sidewall 151su may be arranged sequentially from the first fin sidewall 110a of the first fin pattern 110.

[0074] The first lower extensional sidewall 151sl may extend from the first fin sidewall 110a of the first fin pattern 110. The first lower extensional sidewall 151sl may be connected to the first fin sidewall 110a of the first fin pattern 110. The first extensional connecting sidewall 151sc may connect the first lower extensional sidewall 151sl and the first upper extensional sidewall 151su.

[0075] The second extensional sidewall 152s may include a second extensional lower sidewall 152sl, a second extensional connecting sidewall 152sc, and a second extensional upper sidewall 152su. The second extensional lower sidewall 152sl, the second extensional connecting sidewall 152sc, and the second extensional upper sidewall 152su may be arranged sequentially from the second fin sidewall 110b of the first fin pattern 110.

[0076] The second lower extensional sidewall 152sl can extend from the second fin sidewall 110b of the first fin pattern 110. The second lower extensional sidewall 152sl can be connected to the second fin sidewall 110b of the first fin pattern 110. The second extensional connecting sidewall 152sc can be connected to the second lower extensional sidewall 152sl and the second upper extensional sidewall 152su.

[0077] The first extensional connecting sidewall 151sc can be directly connected to the first extensional lower sidewall 151sl and the first extensional upper sidewall 151su. The second extensional connecting sidewall 152sc can be directly connected to the second extensional lower sidewall 152sl and the second extensional upper sidewall 152su.

[0078] At the location where the first fin pattern 110 and the field insulating film 105 meet, the top surface of the first fin pattern 110 can be flush with the top surface of the field insulating film 105. The first epitaxial sidewall 151s and the second epitaxial sidewall 152s can be left uncovered by the field insulating film 105.

[0079] The first epitaxial pattern 150 may include a first epitaxial top surface 150ts and a first epitaxial bottom surface 105bs that connect the first epitaxial sidewall 151s and the second epitaxial sidewall 152s.

[0080] The first epitaxial bottom surface 150bs can be disposed between the first epitaxial sidewall 151s and the second epitaxial sidewall 152s. The first epitaxial bottom surface 150bs can connect the first epitaxial sidewall 151s and the second epitaxial sidewall 152s. The first epitaxial bottom surface 150bs can be directly connected to the first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl. The first epitaxial bottom surface 150bs can contact the top surface of the first fin pattern 110. The first epitaxial bottom surface 150bs can face the top surface of the first fin pattern 110. The first epitaxial bottom surface 150bs can be the portion of the first epitaxial pattern 150 that vertically overlaps with the top surface of the first fin pattern 110.

[0081] The first epitaxial top surface 150ts can be disposed between the first epitaxial sidewall 151s and the second epitaxial sidewall 152s. The first epitaxial top surface 150ts can connect the first epitaxial sidewall 151s and the second epitaxial sidewall 152s.

[0082] The first epitaxial top surface 150ts can be directly connected to the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su.

[0083] The first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su can be inclined surfaces that are inclined with respect to the top surface of the substrate 100. The distance between the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su can decrease in a direction extending away from the first fin pattern 110 (e.g., the third direction Z1). For example, the distance between the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su measured in the second direction Y1 can decrease as the distance from the first fin pattern 110 increases in the third direction Z1. For example, the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su can be formed by crystal planes included in the first crystal plane family.

[0084] The first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl can be inclined surfaces that are inclined with respect to the top surface of the substrate 100. The distance between the first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl can increase in a direction extending away from the first fin pattern 110 (e.g., the third direction Z1). For example, the distance between the first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl measured in the second direction Y1 can increase as the distance from the first fin pattern 110 increases in the third direction Z1. For example, the first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl can be formed by crystal planes included in the second crystal plane family.

[0085] The first epitaxial connecting sidewall 151sc and the second epitaxial connecting sidewall 152sc can be parallel to the thickness direction of the substrate 100. For example, each of the first epitaxial connecting sidewall 151sc and the second epitaxial connecting sidewall 152sc can be perpendicular to the top surface of the substrate 100. The distance between the first epitaxial connecting sidewall 151sc and the second epitaxial connecting sidewall 152sc can decrease in a direction extending away from the first fin pattern 110 (e.g., the third direction Z1). For example, the distance between the first epitaxial connecting sidewall 151sc and the second epitaxial connecting sidewall 152sc measured in the second direction Y1 can remain substantially unchanged as the distance from the first fin pattern 110 increases in the third direction Z1. For example, the first epitaxial connecting sidewall 151sc and the second epitaxial connecting sidewall 152sc can be formed by crystal planes included in the third crystal plane family. The first epitaxial top surface 150ts can be formed by crystal planes included in the fourth crystal plane family.

[0086] The first crystal plane family and the second crystal plane family can be the same. The first crystal plane family can be different from the third crystal plane family and the fourth crystal plane family.

[0087] The first family of crystal planes can be the {111} family of crystal planes. For example, the first family of crystal planes can include one of the following: (1 1 1) crystal plane, (1 1 -1) crystal plane, (1 -1 1) crystal plane, (1 -1 -1) crystal plane, (-1 1 1) crystal plane, (-1 1 -1) crystal plane, (-1 -1 1) crystal plane, and (-1 -1 -1) crystal plane.

[0088] The third family of crystal planes can be the {110} family of crystal planes. For example, the third family of crystal planes can include one of the following: (1 1 0) crystal plane, (1 -10) crystal plane, (-1 1 0) crystal plane, (-1 -1 0) crystal plane, (1 0 1) crystal plane, (1 0 -1) crystal plane, (-1 0 1) crystal plane, (-1 0 -1) crystal plane, (0 1 1) crystal plane, (0 1 -1) crystal plane, (0 -1 1) crystal plane, and (0 -1 -1) crystal plane.

[0089] The fourth family of crystal planes can be the {100} family of crystal planes. The fourth family of crystal planes can include one of the (1 0 0) crystal plane, (-1 0 0) crystal plane, (0 1 0) crystal plane, (0 -1 0) crystal plane, (0 0 1) crystal plane, and (0 0 -1) crystal plane. The {100} family of crystal planes can include crystal planes parallel to the top surface of the substrate 100.

[0090] Figure 4 The top surface of the first fin pattern 110 is shown to be parallel to the first epitaxial top surface 150ts, but the inventive concept is not limited thereto.

[0091] An interlayer insulating film 190 may be formed on the first epitaxial pattern 150. The interlayer insulating film 190 may surround the first gate spacer 140. The interlayer insulating film 190 may include a lower interlayer insulating film 191 and an upper interlayer insulating film 192. The upper interlayer insulating film 192 may be formed on the top surface of the first gate spacer 140 and the top surface of the first gate electrode 125. For example, the lower interlayer insulating film 191 and the upper interlayer insulating film 192 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0092] The following text will refer to Figures 5A to 5D A cross-section of the first nanosheet 115_1 taken in the first direction X1 is described.

[0093] Reference Figure 5A The cross-section 115s of the first nanosheet 115_1A can have a shape formed by a combination of four straight lines 115m and four curves 115n. For example, the cross-section 115s of the first nanosheet 115_1A can be a square with rounded corners. On the cross-section 115s of the first nanosheet 115_1A, the width L1 and the height L2 of the first nanosheet 115_1A can be different from each other. Figure 5AIn the example, the width L1 can be greater than the height L2. For example, the cross-section 115s of the first nanosheet 115_1A can be a rectangle with rounded corners, but the inventive concept is not limited thereto.

[0094] Reference Figure 5B On the cross-section 115s of the first nanosheet 115_1B, the width L1 and the height L2 of the first nanosheet 115_1B can be the same. For example, the cross-section 115s of the first nanosheet 115_1B can be a square with rounded corners, but the inventive concept is not limited thereto.

[0095] Reference Figure 5C On the cross-section 115s of the first nanosheet 115_1C, the length L11 of one side of the first nanosheet 115_1C and the length L11 of the other side of the first nanosheet 115_1C can be different from each other. For example, the cross-section 115s of the first nanosheet 115_1C can have a trapezoid with rounded corners, but the inventive concept is not limited thereto.

[0096] Reference Figure 5D ,and Figure 5A Unlike other examples, the cross-section 115s of the first nanosheet 115_1D can have a shape consisting entirely of curves 115n. For example, the first nanosheet 115_1D can be circular.

[0097] In some embodiments, with Figures 5A to 5D As shown, the cross-section 115s of the first nanosheet 115_1 can be a shape formed by a combination of straight lines 115m (e.g., a polygon). For example, the cross-section 115s of the first nanosheet 115_1 can be a shape formed by four line segments that intersect each other (e.g., a square with non-rounded corners). As another example, the cross-section 115s of the first nanosheet 115_1 can be a shape formed by three line segments that intersect each other (e.g., a triangle).

[0098] The following text will refer to Figures 6A to 6C The longitudinal section of the first nanosheet 115_1 taken in the first direction X1 is described.

[0099] Reference Figure 6A The thickness of the first nanosheet 115_1E is substantially constant in the direction in which the first gate spacer 140 extends away from the first epitaxial pattern 150 and the first gate structure 120_1 (e.g., in the first direction X1). For example, the thickness t1_a of the first nanosheet 115_1E adjacent to the first epitaxial pattern 150 may be substantially the same as the thickness t1_b of the middle portion of the first nanosheet 115_1E. Thickness may refer to the thickness or height measured in a direction perpendicular to the top surface of the substrate 100 (e.g., the third direction Z1).

[0100] Reference Figure 6B The thickness of the first nanosheet 115_1F can decrease in a direction extending away from the first epitaxial pattern 150 and the first gate spacer 140 of the first gate structure 120_1. For example, the thickness t1_a of the opposite end of the first nanosheet 115_1F adjacent to the first epitaxial pattern 150 can be greater than the thickness t1_b of the middle portion of the first nanosheet 115_1F. In some embodiments, the upper surface of the first nanosheet 115_1F can be concave relative to the top surface of the substrate 100, and the lower surface of the first nanosheet 115_1F can be convex relative to the top surface of the substrate 100.

[0101] Reference Figure 6C The thickness of the first nanosheet 115_1G can increase in a direction extending away from the first epitaxial pattern 150 and the first gate spacer 140 of the first gate structure 120_1. For example, the thickness t1_a of the opposite ends of the first nanosheet 115_1G adjacent to the first epitaxial pattern 150 can be less than the thickness t1_b of the middle portion of the first nanosheet 115_1G. In some embodiments, the upper surface of the first nanosheet 115_1G can be convex relative to the top surface of the substrate 100, and the lower surface of the first nanosheet 115_1G can be concave relative to the top surface of the substrate 100.

[0102] Reference Figure 6B and Figure 6C The thickness of the first nanosheet 115_1 can vary continuously away from the first epitaxial pattern 150 and the first gate spacer 140 of the first gate structure 120_1.

[0103] The following text will refer to Figure 7 Example description: A longitudinal section of the first nanosheet 115_1H taken in the first direction X1.

[0104] Reference Figure 7 The first nanosheet 115_1H can be a trimmed sheet pattern. The first nanosheet 115_1H can include a first portion 115a and a second portion 115b. The second portion 115b of the first nanosheet 115_1H can be disposed on both sides of the first portion 115a of the first nanosheet 115_1H. The second portion 115b of the first nanosheet 115_1H can overlap with the first gate spacer 140 of the first gate structure 120_1, and the first portion 115a of the first nanosheet 115_1H can be the portion of the first nanosheet 115_1H that overlaps with the first gate insulating film 130 and the first gate electrode 125 of the first gate structure 120_1.

[0105] The thickness t1_c of the second portion 115b of the first nanosheet 115_1H can be greater than the thickness t1_d of the first portion 115a of the first nanosheet 115_1H. The change from thickness t1_c to thickness t1_d (and from thickness t1_d to thickness t1_c) can be abrupt, allowing internal vertical sidewalls to be formed in the first nanosheet 115_1H. The internal vertical sidewalls can include an upper internal vertical sidewall 115c_u and a lower internal vertical sidewall 115c_l of the second portion 115b. The upper internal vertical sidewall 115c_u can connect the planar upper surface of the second portion 115b to the planar upper surface of the first portion 115a, and the lower internal vertical sidewall 115c_l can connect the planar lower surface of the second portion 115b to the planar lower surface of the first portion 115a.

[0106] As in Figure 7 As shown in the alternative, in some embodiments, the corner at the junction of the first portion 115a and the second portion 115b of the first nanosheet 115_1H may be rounded. Figure 7 The first portion 115a of the first nanosheet 115_1H is shown to have a uniform width, but the inventive concept is not limited thereto. For example, the width of the first portion 115a of the first nanosheet 115_1H can be as follows: Figure 6B or Figure 6C The changes shown.

[0107] Figure 8 This is a cross-sectional view illustrating some example embodiments of a semiconductor device according to the present invention. Figure 9 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figure 8 and Figure 9 Semiconductor devices, with a focus on describing and Figures 1 to 7 The difference lies in the semiconductor devices.

[0108] Reference Figure 8 The first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su can be formed from crystal planes of different crystal plane families compared to the first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl. The first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl can be parallel to the top surface of the substrate 100.

[0109] For example, the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su can be formed by crystal planes included in the first family of crystal planes, the first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl can be formed by crystal planes included in the second family of crystal planes, and the first family of crystal planes and the second family of crystal planes can be different.

[0110] For example, the first family of crystal planes can be the {111} family of crystal planes, and the second family of crystal planes can be the {100} family of crystal planes.

[0111] Reference Figure 9 The first epitaxial connecting sidewall 151sc and the second epitaxial connecting sidewall 152sc may not be surfaces where crystal planes appear.

[0112] For example, the first extensional connecting sidewall 151sc and the second extensional connecting sidewall 152sc can be curved surfaces. The first extensional upper sidewall 151su and the first extensional lower sidewall 151sl can be connected by the first extensional connecting sidewall 151sc, which is a curved surface. The second extensional upper sidewall 152su and the second extensional lower sidewall 152sl can be connected by the second extensional connecting sidewall 152sc, which is a curved surface.

[0113] Figures 10A to 10D This is a cross-sectional view illustrating some example embodiments of a semiconductor device according to the present invention. Figure 11 This is a cross-sectional view illustrating some example embodiments of a semiconductor device according to the present invention. Figure 12 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figures 10A to 10D , Figure 11 and Figure 12 Semiconductor devices, with a focus on describing and Figures 1 to 7 The difference lies in the semiconductor devices.

[0114] Reference Figures 10A to 10D The first epitaxial sidewall 151s and the second epitaxial sidewall 152s can be partially covered by the field insulating film 105.

[0115] The first epitaxial lower sidewall 151sl may include a first portion 151sl1 and a second portion 151sl2. The second portion 151sl2 may be a portion of the first epitaxial lower sidewall 151sl extending from the first fin sidewall 110a of the first fin pattern 110. In some embodiments, the second portion 151sl2 may be perpendicular to the top surface of the substrate 100. The first portion 151sl1 may be disposed between the second portion 151sl2 and the first epitaxial connection sidewall 151sc. The second portion 151sl2 may be a portion of the first epitaxial lower sidewall 151sl covered by the field insulating film 105. For example, the field insulating film 105 may contact the second portion 151sl2 of the first epitaxial lower sidewall 151sl. The first portion 151sl1 may be a portion of the first epitaxial lower sidewall 151sl extending beyond the top surface of the field insulating film 105.

[0116] The second epitaxial lower sidewall 152sl may include a first portion 152sl1 and a second portion 152sl2. The second portion 152sl2 may be a portion of the second epitaxial lower sidewall 152sl extending from the second fin sidewall 110b of the first fin pattern 110. In some embodiments, the second portion 152sl2 may be perpendicular to the top surface of the substrate 100. The first portion 152sl1 may be disposed between the second portion 152sl2 and the second epitaxial connection sidewall 152sc. The second portion 152sl2 may be a portion of the second epitaxial lower sidewall 152sl covered by the field insulating film 105. For example, the field insulating film 105 may contact the second portion 152sl2 of the second epitaxial lower sidewall 152sl. The first portion 152sl1 may be a portion of the second epitaxial lower sidewall 152sl extending beyond the top surface of the field insulating film 105.

[0117] Reference Figure 10A The first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be inclined surfaces that are tilted relative to the top surface of the substrate 100. For example, the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be formed by crystal planes included in the {111} family of crystal planes. The family of crystal planes forming the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be the same as the family of crystal planes forming the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su.

[0118] Reference Figures 10B to 10D The first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl may be parallel to the top surface of the substrate 100. The first epitaxial lower sidewall 151sl and the second epitaxial lower sidewall 152sl may include portions parallel to the top surface of the substrate 100. For example, the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl may be formed by crystal planes included in the {100} family of crystal planes. The family of crystal planes forming the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl may be different from the family of crystal planes forming the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su.

[0119] Reference Figure 10C The first epitaxial top surface 150ts can be circular. (Refer to...) Figure 10DThe corners where the first epitaxial top surface 150ts and the first epitaxial upper sidewall 151su meet, and the corners where the first epitaxial top surface 150ts and the second epitaxial upper sidewall 152su meet, can be rounded. Additionally, the corners where the first epitaxial upper sidewall 151su and the first epitaxial connecting sidewall 151sc meet, and the corners where the first epitaxial connecting sidewall 151sc and the first portion 151sl1 of the first epitaxial lower sidewall 151sl meet, can also be rounded. Furthermore, the corners where the second epitaxial upper sidewall 152su and the second epitaxial connecting sidewall 152sc meet, and the corners where the second epitaxial connecting sidewall 152sc and the first portion 152sl1 of the second epitaxial lower sidewall 152sl meet, can also be rounded.

[0120] Reference Figure 11 Some portions of the first fin sidewall 110a and the second fin sidewall 110b of the first fin pattern 110 may protrude beyond the top surface of the field insulating film 105. For example, the upper surface of the first fin pattern 110 may be located at a higher vertical level than the top surface of the field insulating film 105 (e.g., in the third direction Z1).

[0121] The field insulating film 105 may not cover some portions of the first fin sidewall 110a and the second fin sidewall 110b of the first fin pattern 110. The first epitaxial pattern 150 may cover the portions of the first fin sidewall 110a and the second fin sidewall 110b of the first fin pattern 110 that are not covered by the field insulating film 105.

[0122] The first epitaxial sidewall 151s can extend upward from the position where the first fin sidewall 110a of the first fin pattern 110 meets the field insulating film 105. The second epitaxial sidewall 152s can extend upward from the position where the second fin sidewall 110b of the first fin pattern 110 meets the field insulating film 105.

[0123] Reference Figure 12 The corners where the first extension connecting sidewall 151sc and the first extension lower sidewall 151sl meet, and the corners where the first extension connecting sidewall 151sc and the first extension upper sidewall 151su meet, can be round.

[0124] In addition, the corners where the second extension connecting sidewall 152sc and the second extension lower sidewall 152sl meet, as well as the corners where the second extension connecting sidewall 152sc and the second extension upper sidewall 152su meet, can be rounded.

[0125] In addition, the corners where the first epitaxial top surface 150ts and the first epitaxial upper sidewall 151su meet, and the corners where the first epitaxial top surface 150ts and the second epitaxial upper sidewall 152su meet, can be rounded.

[0126] Figure 13This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figure 13 Semiconductor devices, with a focus on describing and Figures 1 to 7 The differences between semiconductor devices.

[0127] Reference Figure 13 The semiconductor device may also include a first epitaxial spacer 110f disposed at the first fin sidewall 110a and the second fin sidewall 110b of the first fin pattern 110.

[0128] The height of the top surface of the first epitaxial spacer 110f can be lower than or the same as the height at the point where the first fin sidewall 110a of the first fin pattern 110 meets the field insulating film 105. The height of the top surface of the first epitaxial spacer 110f can be lower than or the same as the height at the point where the second fin sidewall 110b of the first fin pattern 110 meets the field insulating film 105. For example, the height of the top surface of the first epitaxial spacer 110f can be lower than or the same as the height of the upper surface of the first fin pattern 110.

[0129] The first epitaxial spacer 110f may be disposed on the field insulating film 105. For example, the first epitaxial spacer 110f may include at least one of SiN, SiON, SiO2, SiOCN and combinations thereof.

[0130] Figure 14 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figure 14 Semiconductor devices, with a focus on describing and Figure 13 The difference lies in the semiconductor devices.

[0131] Reference Figure 14 The first extensional sidewall 151s and the second extensional sidewall 152s can be partially covered by the first extensional spacer 110f.

[0132] The height of the top surface of the first epitaxial spacer 110f can be greater than the height of the position where the first fin sidewall 110a of the first fin pattern 110 meets the field insulating film 105. The height of the top surface of the first epitaxial spacer 110f can be greater than the height of the position where the second fin sidewall 110b of the first fin pattern 110 meets the field insulating film 105. For example, the height of the top surface of the first epitaxial spacer 110f can be greater than the height of the upper surface of the first fin pattern 110.

[0133] The first epitaxial lower sidewall 151sl may include a first portion 151sl1 and a second portion 151sl2. The second portion 151sl2 of the first epitaxial lower sidewall 151sl may be a portion of the first epitaxial lower sidewall 151sl extending from the first fin sidewall 110a of the first fin pattern 110. The first portion 151sl1 of the first epitaxial lower sidewall 151sl may be disposed between the second portion 151sl2 of the first epitaxial lower sidewall 151sl and the first epitaxial connecting sidewall 151sc. The second portion 151sl2 of the first epitaxial lower sidewall 151sl may be a portion of the first epitaxial lower sidewall 151sl covered by the first first epitaxial spacer 110f of the first epitaxial spacers 110f. In some embodiments, the first first epitaxial spacer 110f of the first epitaxial spacers 110f may contact the second portion 151sl2 of the first epitaxial lower sidewall 151sl. The first portion 151sl1 of the first lower extensional sidewall 151sl may be the portion of the first lower extensional sidewall 151sl extending beyond the top surface of the first extensional spacer 110f.

[0134] The second extensional lower sidewall 152sl may include a first portion 152sl1 and a second portion 152sl2. The second portion 152sl2 of the second extensional lower sidewall 152sl may be a portion of the second extensional lower sidewall 152sl extending from the second fin sidewall 110b of the first fin pattern 110. The first portion 152sl1 of the second extensional lower sidewall 152sl may be disposed between the second portion 152sl2 of the second extensional lower sidewall 152sl and the second extensional connecting sidewall 152sc. The second portion 152sl2 of the second extensional lower sidewall 152sl may be a portion of the second extensional lower sidewall 152sl covered by a second first extensional spacer 110f in the first extensional spacers 110f. In some embodiments, the second first extensional spacer 110f in the first extensional spacers 110f may contact the second portion 152sl2 of the second extensional lower sidewall 152sl. The first portion 152sl1 of the second extensional lower sidewall 152sl may be the portion of the second extensional lower sidewall 152sl that extends beyond the top surface of the first extensional spacer 110f.

[0135] For example, the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be formed by crystal planes included in the {111} family of crystal planes. The family of crystal planes forming the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be the same as the family of crystal planes forming the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su.

[0136] In another example, the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be formed by crystal planes included in the {100} family of crystal planes. The family of crystal planes forming the first portion 151sl1 of the first epitaxial lower sidewall 151sl and the first portion 152sl1 of the second epitaxial lower sidewall 152sl can be different from the family of crystal planes forming the first epitaxial upper sidewall 151su and the second epitaxial upper sidewall 152su.

[0137] Figures 1 to 14 The first epitaxial pattern 150 with different shapes can be arranged in different portions of the substrate 100.

[0138] Figure 15 This is a cross-sectional view illustrating some example embodiments of a semiconductor device according to the present invention. Figure 16 and Figure 17 This is a cross-sectional view illustrating some example embodiments of a semiconductor device according to the present invention. Figure 18 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figures 15 to 18 Semiconductor devices, with a focus on describing and Figures 1 to 7 The difference lies in the semiconductor devices.

[0139] Reference Figure 15 The first fin pattern 110 can be arranged on the embedded insulating film 102. The first fin pattern 110 can be arranged on the insulating pattern included in the embedded insulating film 102.

[0140] For example, substrate 100 may include a base substrate 101 and a buried insulating film 102 disposed on the base substrate 101. The base substrate 101 may include a semiconductor material. For example, the buried insulating film 102 may include at least one of SiN, SiON, and SiO2.

[0141] For example, substrate 100 can be an SOI substrate or an SGOI substrate, but the concept of the present invention is not limited thereto.

[0142] Reference Figure 16 and Figure 17 The semiconductor device may also include a contact 195 connected to the first epitaxial pattern 150.

[0143] Contact 195 may pass through upper interlayer insulating film 192 and may be formed in lower interlayer insulating film 191. Contact 195 may be formed on first epitaxial pattern 150. During the formation of contact 195, a portion of first epitaxial pattern 150 may be etched. Contact 195 may be inserted into the etched portion of first epitaxial pattern 150. Upper surface of contact 195 may be coplanar with upper surface of upper interlayer insulating film 192. Terms such as “same,” “equal to,” “unchanged,” “planar,” or “coplanar” used herein with reference to orientation, layout, position, shape, size, quantity, or other measures do not necessarily refer to exactly the same orientation, layout, position, shape, size, quantity, or other measures, but are intended to cover substantially the same orientation, layout, position, shape, size, quantity, or other measures within an acceptable range of variation, for example, due to manufacturing processes.

[0144] For example, contact 195 may include at least one of Ta, TaN, Ti, TiN, WN, tungsten carbonitride (WCN), W, Co, Ru, Mo, Ni, Al, Cu, and doped polycrystalline silicon. As in Figure 16 and Figure 17 As shown in the figure, a silicide film may be formed between the contact 195 and the first epitaxial pattern 150.

[0145] Reference Figure 18 Each of the first gate structures 120_1 and 120_2 may include a first gate electrode 125, a first gate insulating film 130, a first gate spacer 140 and a first gate trench 140t, and may also include a capping pattern 145.

[0146] The first gate electrode 125 may fill a portion of the first gate trench 140t. A capping pattern 145 may be formed on the first gate electrode 125. The capping pattern 145 may fill the remaining portion of the first gate trench 140t that is not filled by the first gate electrode 125.

[0147] Figure 18 It is shown that the first gate insulating film 130 is not formed between the first gate spacer 140 and the capping pattern 145, but the inventive concept is not limited thereto.

[0148] Figure 18The illustration shows a capping pattern 145 formed between the first gate spacers 140, but the inventive concept is not limited thereto. In some embodiments, not only can the top surface of the first gate electrode 125 be recessed below the top surface of the lower interlayer insulating film 191, but the top surface of the first gate spacer 140 can also be recessed below the top surface of the lower interlayer insulating film 191. In this case, the capping pattern 145 can be formed on the top surfaces of both the first gate spacer 140 and the first gate electrode 125.

[0149] The top surface of the capping pattern 145 may be coplanar with the top surface of the lower interlayer insulating film 191. For example, the top surface of the capping pattern 145 may be coplanar with the upper surface of the first outer spacer 141 and the top surface of the lower interlayer insulating film 191. The capping pattern 145 may include a material that is etch-selective relative to the lower interlayer insulating film 191. For example, the capping pattern 145 may include at least one of SiN, SiON, SiO2, SiCN, SiOCN, and combinations thereof.

[0150] Figure 19 This is a cross-sectional view illustrating some example embodiments of a semiconductor device according to the present invention. Figure 20 It is along Figure 19 The sectional view taken by line DD. Figure 21 It is along Figure 19 The sectional view taken by the line EE.

[0151] Apart from the width W1 of the first fin pattern 110, the pattern formed in Figure 19 The first fin pattern 110, the first gate structures 120_1 and 120_2, the first nanosheets 115_1 and 115_2, and the first epitaxial pattern 150 in the first region I and their... Figures 1 to 14 The corresponding parts in each of them are substantially the same. Therefore, the following will describe... Figure 19 Semiconductor devices, with a focus on description Figure 19 Zone II.

[0152] Along Figure 19 The sectional view taken by line AA can be substantially as follows Figure 2 As shown, and along Figure 19 The cross-sectional view taken by the CC line can be substantially as follows: Figure 4 and Figures 8 to 14 Any one of them is shown.

[0153] Reference Figures 19 to 21The semiconductor device may include a first fin pattern 110, a second fin pattern 210, first nanosheets 115_1 and 115_2, second nanosheets 215_1 and 215_2, a first gate structure 120_1 and 120_2, a second gate structure 220_1 and 220_2, a first epitaxial pattern 150, and a second epitaxial pattern 250.

[0154] The substrate 100 may include a first region I and a second region II. The first region I may be a logic region or an input / output (I / O) region. The second region II may be a static random access memory (SRAM) region.

[0155] The first fin pattern 110, the first nanosheets 115_1 and 115_2, the first gate structures 120_1 and 120_2, and the first epitaxial pattern 150 can be arranged in the first region I. The second fin pattern 210, the second nanosheets 215_1 and 215_2, the second gate structures 220_1 and 220_2, and the second epitaxial pattern 250 can be arranged in the second region II.

[0156] The first nanosheets 115_1 and 115_2 and the second nanosheets 215_1 and 215_2 can be used as the channel region of a PMOS transistor.

[0157] The second fin pattern 210 may protrude from the substrate 100 (e.g., in a sixth direction Z2 perpendicular to the fourth direction X2 and the fifth direction Y2). The second fin pattern 210 may extend longitudinally in the fourth direction X2.

[0158] The second fin pattern 210 may include a first fin sidewall 210a and a second fin sidewall 210b facing each other. The first fin sidewall 210a and the second fin sidewall 210b may extend longitudinally in a fourth direction X2. The first fin sidewall 210a and the second fin sidewall 210b may define the long side of the second fin pattern 210. In some embodiments, the first direction X1, the second direction Y1, and the third direction Z1 may be the same as the fourth direction X2, the fifth direction Y2, and the sixth direction Z2, respectively. In other embodiments, the first direction X1, the second direction Y1, and the third direction Z1 may be different from the fourth direction X2, the fifth direction Y2, and the sixth direction Z2, respectively.

[0159] The second fin pattern 210 may be formed by etching a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100. The second fin pattern 210 may include elemental semiconductor materials such as Si or Ge. The second fin pattern 210 may include compound semiconductors such as, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0160] The field insulating film 105 may at least partially surround the first fin sidewall 210a and the second fin sidewall 210b. For example, the field insulating film 105 may substantially cover the first fin sidewall 210a and the second fin sidewall 210b. For example, the field insulating film 105 may contact the first fin sidewall 210a and the second fin sidewall 210b.

[0161] Second nanosheets 215_1 and 215_2 can be disposed on the second fin pattern 210. Each of the second nanosheets 215_1 and 215_2 may include a plurality of nanosheet layers arranged in sequence along the thickness direction of the substrate 100. The plurality of nanosheet layers can be arranged in sequence on the second fin pattern 210. For example, the plurality of nanosheet layers of the second nanosheet 215_1 and the plurality of nanosheet layers of the second nanosheet 215_2 can be stacked on the second fin pattern 210 in the sixth direction Z2.

[0162] Second nanosheets 215_1 and 215_2, spaced apart from each other, can be arranged along the top surface of the second fin pattern 210 in the fourth direction X2. A second epitaxial pattern 250 can be arranged between the second nanosheets 215_1 and 215_2, which are spaced apart from each other in the fourth direction X2. The second epitaxial pattern 250 can contact the side surface of each of the second nanosheets 215_1 and 215_2.

[0163] The second fin pattern 210 and the second nanosheets 215_1 and 215_2 can be formed by selectively removing a portion of the fin structure, including the second fin pattern 210 and the second nanosheets 215_1 and 215_2. Therefore, the width of the second nanosheets 215_1 and 215_2 in the fifth direction Y2 can be equal to or less than the width W2 of the second fin pattern 210 in the fifth direction Y2.

[0164] The width W1 of the first fin pattern 110 in the second direction Y1 can be greater than the width W2 of the second fin pattern 210. Additionally, the widths of the first nanosheets 115_1 and 115_2 in the second direction Y1 can be greater than the widths of the second nanosheets 215_1 and 215_2 in the fifth direction Y2. For example, the first direction X1 can intersect the second direction Y1, and the fourth direction X2 can intersect the fifth direction Y2.

[0165] The second nanosheets 215_1 and 215_2 may comprise elemental semiconductor materials such as Si or Ge. Alternatively, the second nanosheets 215_1 and 215_2 may comprise compound semiconductors such as, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0166] The second gate structures 220_1 and 220_2 may extend in the fifth direction Y2. The second gate structures 220_1 and 220_2 may intersect with the second fin pattern 210. The second gate structures 220_1 and 220_2 may intersect with the second nanosheets 215_1 and 215_2 that are spaced apart from each other in the fourth direction X2. The second gate structures 220_1 and 220_2 may surround the second nanosheets 215_1 and 215_2 that are spaced apart from each other in the fourth direction X2.

[0167] Each of the second gate structures 220_1 and 220_2 may include a second gate electrode 225, a second gate insulating film 230, a second gate spacer 240, and a second gate trench 240t.

[0168] The second gate spacer 240 may extend longitudinally in the fifth direction Y2. The second gate spacer 240 may define a second gate trench 240t intersecting with the second nanosheets 215_1 and 215_2. The second gate spacer 240 may include a second inner spacer 242 and a second outer spacer 241.

[0169] The second gate insulating film 230 can be formed along the edges of the corresponding second nanosheets 215_1 and 215_2. The second gate insulating film 230 can surround the corresponding second nanosheets 215_1 and 215_2.

[0170] The second gate electrode 225 may intersect with the second fin pattern 210 and the second nanosheets 215_1 and 215_2 separated from the substrate 100. The second gate electrode 225 may surround the corresponding second nanosheets 215_1 and 215_2. The second gate electrode 225 may also be formed in the gap between the second nanosheets 215_1 and 215_2 and the second fin pattern 210.

[0171] The second epitaxial pattern 250 can be formed between adjacent second gate structures 220_1 and 220_2. The second epitaxial pattern 250 can be formed on the second fin pattern 210. The second epitaxial pattern 250 can be formed by epitaxial growth.

[0172] The second nanosheets 215_1 and 215_2 can be arranged on both sides of the second epitaxial pattern 250. The second epitaxial pattern 250 can be connected to the second nanosheets 215_1 and 215_2.

[0173] The second epitaxial pattern 250 can be included in the source / drain of the channel region using second nanosheets 215_1 and 215_2. For example, since the second nanosheets 215_1 and 215_2 can be used as the channel region of a PMOS transistor, the second epitaxial pattern 250 can be included in the source / drain of the PMOS transistor.

[0174] The second extensional pattern 250 may include a third extensional sidewall 251s and a fourth extensional sidewall 252s extending from the second fin pattern 210. The third extensional sidewall 251s may extend from the first fin sidewall 210a of the second fin pattern 210. The fourth extensional sidewall 252s may extend from the second fin sidewall 210b of the second fin pattern 210.

[0175] The third extensional sidewall 251s may include a third extensional lower sidewall 251sl and a third extensional upper sidewall 251su. The third extensional lower sidewall 251sl and the third extensional upper sidewall 251su may be arranged sequentially from the first fin sidewall 210a of the second fin pattern 210.

[0176] The third extensional lower sidewall 251sl can extend from the first fin sidewall 210a of the second fin pattern 210. The third extensional lower sidewall 251sl can be connected to the first fin sidewall 210a of the second fin pattern 210.

[0177] The fourth extensional sidewall 252s may include a fourth extensional lower sidewall 252sl and a fourth extensional upper sidewall 252su. The fourth extensional lower sidewall 252sl and the fourth extensional upper sidewall 252su may be arranged sequentially from the second fin sidewall 210b of the second fin pattern 210.

[0178] The fourth extensional lower sidewall 252sl can extend from the second fin sidewall 210b of the second fin pattern 210. The fourth extensional lower sidewall 252sl can be connected to the second fin sidewall 210b of the second fin pattern 210.

[0179] The lower sidewall 251sl of the third extension can be directly connected to the upper sidewall 251su of the third extension. The lower sidewall 252sl of the fourth extension can be directly connected to the upper sidewall 252su of the fourth extension.

[0180] At the location where the second fin pattern 210 meets the field insulating film 105, the top surface of the second fin pattern 210 can be flush with the top surface of the field insulating film 105.

[0181] The third epitaxial sidewall 251s and the fourth epitaxial sidewall 252s may not be covered by the field insulating film 105.

[0182] The second extensional pattern 250 may include a second extensional bottom surface 250bs that connects the third extensional sidewall 251s and the fourth extensional sidewall 252s.

[0183] The second epitaxial bottom surface 250bs can be disposed between the third epitaxial lower sidewall 251sl and the fourth epitaxial lower sidewall 252sl. The second epitaxial bottom surface 250bs can connect the third epitaxial lower sidewall 251sl and the fourth epitaxial lower sidewall 252sl. The second epitaxial bottom surface 250bs can contact the top surface of the second fin-shaped pattern 210. The second epitaxial bottom surface 250bs can face the top surface of the second fin-shaped pattern 210. The second epitaxial bottom surface 250bs can be the portion of the second epitaxial pattern 250 that vertically overlaps with the top surface of the second fin-shaped pattern 210.

[0184] The third epitaxial upper sidewall 251su and the fourth epitaxial upper sidewall 252su can be inclined surfaces relative to the top surface of the substrate 100. The distance between the third epitaxial upper sidewall 251su and the fourth epitaxial upper sidewall 252su can decrease in a direction away from the extension of the second fin pattern 210 (e.g., the sixth direction Z2). For example, the distance between the third epitaxial upper sidewall 251su and the fourth epitaxial upper sidewall 252su, measured in the fifth direction Y2, can decrease as the distance from the second fin pattern 210 increases in the sixth direction Z2. The third epitaxial lower sidewall 251sl and the fourth epitaxial lower sidewall 252sl can be inclined surfaces relative to the top surface of the substrate 100. The distance between the third epitaxial lower sidewall 251sl and the fourth epitaxial lower sidewall 252sl can increase in a direction away from the extension of the second fin pattern 210 (e.g., the sixth direction Z2). For example, the distance between the third lower extensional sidewall 251sl and the fourth lower extensional sidewall 252sl, measured in the fifth direction Y2, can increase as the distance to the second fin pattern 210 increases in the sixth direction Z2.

[0185] The third epitaxial upper sidewall 251su and the fourth epitaxial upper sidewall 252su can be formed by crystal planes included in the fifth crystal plane family. The third epitaxial lower sidewall 251sl and the fourth epitaxial lower sidewall 252sl can be formed by crystal planes included in the sixth crystal plane family.

[0186] The fifth and sixth crystal plane families can be the same. For example, the fifth crystal plane family can be the {111} crystal plane family, and the sixth crystal plane family can be the {111} crystal plane family.

[0187] Unlike the first epitaxial pattern 150, the second epitaxial pattern 250 may not include epitaxial connecting sidewalls having crystal planes included in the {110} family of crystal planes. The second epitaxial pattern 250 may not include the epitaxial top surface having crystal planes included in the {100} family of crystal planes.

[0188] The first epitaxial sidewall 151s and the second epitaxial sidewall 152 of the first epitaxial pattern 150 may include unsaturated crystal planes.

[0189] As in Figures 19 to 21 As shown in the alternative, the corners where the third extensional upper sidewall 251su and the third extensional lower sidewall 251sl meet, and the corners where the fourth extensional upper sidewall 252su and the fourth extensional lower sidewall 252sl meet, can be rounded. Additionally, the corners where the third extensional upper sidewall 251su and the fourth extensional upper sidewall 252su meet can also be rounded.

[0190] This is not necessarily because the third epitaxial sidewall 251s and the fourth epitaxial sidewall 252s include unsaturated crystal planes, but because the corners of the second epitaxial pattern 250 are trimmed during the formation of the second epitaxial pattern 250.

[0191] As in Figures 19 to 21 As shown in the alternative, in some embodiments, substrate 100 may be an SOI substrate or an SGOI substrate having an insulating film formed on a semiconductor substrate.

[0192] As in Figures 19 to 21 As shown in the alternative, in some embodiments, the first gate structures 120_1 and 120_2 and the second gate structures 220_1 and 220_2 may each further include a capping pattern formed on the first gate electrode 125 or the second gate electrode 225 (e.g., Figure 18 (The cover pattern 145).

[0193] Figure 22 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figure 22 Semiconductor devices, with a focus on describing and Figures 19 to 21 The difference lies in the semiconductor devices.

[0194] Reference Figure 22 The third epitaxial sidewall 251s and the fourth epitaxial sidewall 252s can be partially covered by the field insulating film 105.

[0195] The third lower extensional sidewall 251sl may include a first portion 251sl1 and a second portion 251sl2. The second portion 251sl2 of the third lower extensional sidewall 251sl may be a portion of the third lower extensional sidewall 251sl extending from the first fin sidewall 210a of the second fin pattern 210. The first portion 251sl1 of the third lower extensional sidewall 251sl may be arranged between the second portion 251sl2 of the third lower extensional sidewall 251sl and the third upper extensional sidewall 251su.

[0196] The second portion 251sl2 of the third epitaxial lower sidewall 251sl may be the portion of the third epitaxial lower sidewall 251sl covered by the field insulating film 105. For example, the field insulating film 105 may contact the second portion 251sl2 of the third epitaxial lower sidewall 251sl. The first portion 251sl1 of the third epitaxial lower sidewall 251sl may be the portion of the third epitaxial lower sidewall 251sl extending beyond the top surface of the field insulating film 105.

[0197] The fourth lower extensional sidewall 252sl may include a first portion 252sl1 and a second portion 252sl2. The second portion 252sl2 of the fourth lower extensional sidewall 252sl may be a portion of the fourth lower extensional sidewall 252sl extending from the second fin sidewall 210b of the second fin pattern 210. The first portion 252sl1 of the fourth lower extensional sidewall 252sl may be disposed between the second portion 252sl1 of the fourth lower extensional sidewall 252sl and the second upper extensional sidewall 252sc.

[0198] The second portion 252sl2 of the fourth epitaxial lower sidewall 252sl may be the portion of the fourth epitaxial lower sidewall 252sl covered by the field insulating film 105. For example, the field insulating film 105 may contact the second portion 252sl2 of the fourth epitaxial lower sidewall 252sl. The first portion 252sl1 of the fourth epitaxial lower sidewall 252sl may be the portion of the fourth epitaxial lower sidewall 252sl extending beyond the top surface of the field insulating film 105.

[0199] For example, the first portion 251sl1 of the third epitaxial lower sidewall 251sl and the first portion 252sl1 of the fourth epitaxial lower sidewall 252sl can be formed by crystal planes included in the {111} family of crystal planes.

[0200] The family of crystal planes forming the first portion 251sl1 of the third epitaxial lower sidewall 251sl and the first portion 252sl1 of the fourth epitaxial lower sidewall 252sl can be the same as the family of crystal planes forming the third epitaxial upper sidewall 251su and the fourth epitaxial upper sidewall 252su.

[0201] Figure 23 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention. For convenience, it will be described below. Figure 23 Semiconductor devices, with a focus on describing and Figures 19 to 21 The difference lies in the semiconductor devices.

[0202] Reference Figure 23 The semiconductor device may also include a second epitaxial spacer 210f disposed on the field insulating film 105. Some portions of the second epitaxial spacer 210f may be disposed at the first fin sidewall 210a and the second fin sidewall 210b of the second fin pattern 210.

[0203] The second portion 251sl2 of the third epitaxial lower sidewall 251sl may be a portion of the third epitaxial lower sidewall 251sl covered by the first second epitaxial spacer 210f among the second epitaxial spacers 210f. In some embodiments, the first second epitaxial spacer 210f may contact the second portion 251sl2 of the third epitaxial lower sidewall 251sl. The first portion 251sl1 of the third epitaxial lower sidewall 251sl may be a portion of the third epitaxial lower sidewall 251sl extending beyond the top surface of the second epitaxial spacer 210f.

[0204] The second portion 252sl2 of the fourth lower epitaxial sidewall 252sl may be the portion of the fourth lower epitaxial sidewall 252sl covered by the second second epitaxial spacer 210f. In some embodiments, the second second epitaxial spacer 210f may contact the second portion 252sl2 of the fourth lower epitaxial sidewall 252sl. The first portion 252sl1 of the fourth lower epitaxial sidewall 252sl may be the portion of the fourth lower epitaxial sidewall 252sl extending beyond the top surface of the second epitaxial spacer 210f.

[0205] As a summary of the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed in this invention are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A semiconductor device, comprising: A first active region is disposed in a first region of a substrate and includes a first sidewall and a second sidewall extending in a first direction; The second active region is disposed in the second region of the substrate and includes a third sidewall and a fourth sidewall extending in the second direction. A first epitaxial pattern is arranged on the first active region; as well as The second epitaxial pattern is arranged on the second active region. The first epitaxial pattern includes a first epitaxial sidewall and a second epitaxial sidewall extending from the first sidewall and the second sidewall of the first active region, respectively. The first extensional sidewall includes a first extensional lower sidewall, a first extensional upper sidewall, and a first extensional connecting sidewall connecting the first extensional lower sidewall and the first extensional upper sidewall. The second extensional sidewall includes a second extensional lower sidewall, a second extensional upper sidewall, and a second extensional connecting sidewall connecting the second extensional lower sidewall and the second extensional upper sidewall. The second epitaxial pattern includes a third epitaxial sidewall and a fourth epitaxial sidewall extending from the third sidewall and the fourth sidewall of the second active region, respectively. The third extensional sidewall includes a third extensional lower sidewall and a third extensional upper sidewall directly connected to the third extensional lower sidewall. The fourth extensional sidewall includes a lower fourth extensional sidewall and an upper fourth extensional sidewall directly connected to the lower fourth extensional sidewall. Wherein, the first epitaxial upper sidewall to the fourth epitaxial upper sidewall, as well as the third epitaxial lower sidewall and the fourth epitaxial lower sidewall, are formed by crystal planes included in the first family of crystal planes, and Wherein, at least a portion of the first epitaxial lower sidewall and at least a portion of the second epitaxial lower sidewall are formed by crystal planes included in the second family of crystal planes. The first crystal plane family is the {111} crystal plane family. The second crystal plane family is one of the {111} crystal plane family and the {100} crystal plane family. The first region and the second region are P-type metal-oxide-semiconductor regions.

2. The semiconductor device according to claim 1, wherein, The first epitaxial connection sidewall and the second epitaxial connection sidewall are formed by crystal planes included in a third crystal plane family, which is different from the first crystal plane family and the second crystal plane family.

3. The semiconductor device according to claim 1, wherein, The width of the first active region in the third direction intersecting the first direction is greater than the width of the second active region in the fourth direction intersecting the second direction.

4. The semiconductor device according to claim 1, in, The distance between the first and second epitaxial sidewalls in a third direction intersecting the first direction decreases as the distance from the first active region increases in a fourth direction perpendicular to both the first and third directions. The distance between the third and fourth extensional sidewalls in the fifth direction intersecting the second direction decreases as the distance to the second active region increases in the sixth direction perpendicular to both the second and fifth directions.

5. The semiconductor device according to claim 4, wherein, Each of the first epitaxial lower sidewall and the second epitaxial lower sidewall is parallel to the top surface of the substrate.

6. The semiconductor device according to claim 1, wherein, The first active region includes a planar top surface connecting the first sidewall and the second sidewall.

7. The semiconductor device according to claim 1, in, The first epitaxial connection sidewall and the second epitaxial connection sidewall are formed by crystal planes included in the third family of crystal planes, and The third crystal plane family is the {110} crystal plane family.

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