Switching power converter and controller for the same

Abstract

A switching power supply includes a power converter having a transformer, a low-side switch and a high-side switch, wherein the low-side switch is configured to draw current from a power supply voltage through a primary winding of the transformer, and the high-side switch is configured to couple the primary winding of the transformer to a buffer capacitor. A controller is configured to synchronously control the opening and closing of the low-side switch and the high-side switch, wherein the low-side switch and the high-side switch are repeatedly opened and closed in a series of switching cycles, respectively, to form an adjusted output voltage. A first voltage is generated at a node between the low-side switch and the high-side switch. The controller is also configured to disconnect the high-side switch when the first voltage drops to a determined level during each switching cycle. The determined level is higher than the power supply voltage by an amount adjusted according to the level of the monitored power supply voltage.

Description

Technical Field

[0001] The present invention relates to the field of switching power converters. More particularly, the present invention relates to switching power converters and controllers for switching power converters. Background Art

[0002] An offline switching power supply receives power from an alternating current (AC) source and provides a voltage-regulated direct current (DC) output that can be used to power a load. An exemplary offline power supply includes a power factor correction (PFC) stage and a DC to DC power converter stage. The PFC stage receives an AC input signal, performs rectification and keeps the current drawn from the AC source substantially in phase with the AC voltage, so that the power supply appears to be a resistive load to the AC source. The DC to DC converter stage receives the rectified output of the PFC stage and generates a voltage-regulated DC output that can be used to power a load. A voltage rectifier (e.g., a full-bridge rectifier) ​​and a smoothing capacitor can be used instead of the PFC stage, in which case the DC to DC stage can receive a rectified voltage from the voltage rectifier as its input. In either case, the input to the DC to DC stage is typically at a higher voltage and is more loosely regulated than the output of the DC to DC stage.

[0003] A flyback power converter (or more simply, a flyback converter) can be used in a DC to DC power converter. A flyback converter employs a transformer that transfers energy from the input of the flyback converter to its output and provides electrical isolation between the input and output of the flyback converter. By closing the switch, an input voltage, such as the rectified output voltage of the PFC stage, is applied across the primary winding of the transformer; as a result, the primary winding current flows and the magnetic flux in the transformer increases, storing energy in the transformer. When the switch is opened, the voltage is removed and the primary winding current drops while the magnetic flux drops. As a result, a current is induced in the secondary winding of the transformer. This induced current charges the output capacitor to generate an output voltage for powering the load.

[0004] Switching power supplies may be subject to a variety of input voltages and load conditions. It is important for such power supplies to operate efficiently to minimize power usage. Therefore, there is a need for an improved technique for switching power supplies that accommodates varying operating conditions and enables efficient operation. There is a further need for such a technique for a switching power supply that employs a flyback power converter. Summary of the invention

[0005] According to an embodiment, a switching power supply includes a power converter having a transformer, a low-side switch and a high-side switch, wherein the low-side switch is configured to draw current from a power supply voltage through a primary winding of the transformer, and the high-side switch is configured to couple the primary winding of the transformer to a buffer capacitor. A controller is configured to synchronously control the opening and closing of a low-side switch and a high-side switch, wherein the low-side switch and the high-side switch are repeatedly opened and closed in a series of switching cycles, respectively, to form an adjusted output voltage. A first voltage is generated at a node between the low-side switch and the high-side switch. The controller is also configured to disconnect the high-side switch when the first voltage drops to a determined level during each switching cycle. The determined level is higher than the power supply voltage by an amount adjusted according to the level of the monitored power supply voltage.

[0006] These and other embodiments are disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention has been described with respect to specific exemplary embodiments thereof, and accordingly reference is made to the accompanying drawings, in which:

[0008] Figure 1 A schematic block diagram of a two-stage off-line power supply according to an embodiment of the present invention is shown;

[0009] Figure 2 A flyback converter suitable for a DC to DC converter according to an embodiment of the present invention is shown;

[0010] Figure 3 shows a voltage waveform of a flyback converter according to an embodiment of the present invention;

[0011] Figure 4 shows a voltage waveform of a flyback converter according to an embodiment of the present invention;

[0012] Figure 5 A flyback converter and a control circuit according to an embodiment of the present invention are shown;

[0013] Figure 6 A control circuit for a flyback converter according to an embodiment of the present invention is shown;

[0014] Figure 7 An additional control circuit for a flyback converter according to an embodiment of the present invention is shown; and

[0015] Figure 8 A differential signal converter used in a control circuit of a flyback converter according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0016] The present invention relates to a power converter and a controller for a switching power supply and an operation method thereof. The converter may be, for example, a flyback power converter used in an offline switching power supply. According to an embodiment of the present invention, the power converter uses two synchronously operated transistor switches on the primary side of the transformer. The first transistor switch of the transistor switches couples the primary winding of the transformer to a ground node and is referred to as a "low-side" switch in this article. The second transistor switch of the two transistor switches couples the primary winding of the transformer to an input power supply voltage via a buffer capacitor and is referred to as a "high-side" switch in this article. The switch is controlled in a feedback loop to generate an adjusted DC output voltage on the secondary side of the transformer. According to an embodiment of the present invention, the moment of disconnecting the high-side switch in each switching cycle is adjusted according to the level of the input power supply voltage.

[0017] According to another embodiment, a controller for a switching power supply is provided. The controller is configured to control a power converter having a transformer, a low-side switch, and a high-side switch. The low-side switch draws current from an input power supply voltage through a primary winding of the transformer. The high-side switch releases current from the primary winding of the transformer to a buffer capacitor. The controller synchronously controls the opening and closing of the low-side switch and the high-side switch to generate an adjusted output voltage. The controller is also configured to adjust the moment of opening the high-side switch in each switching cycle according to the level of the input power supply voltage.

[0018] Embodiments of the present invention may be used in the power converter systems and methods disclosed in US Pat. Nos. 9,716,437 and 10,103,637, each of which is incorporated herein by reference in its entirety.

[0019] The term "continuous conduction mode" or "CCM" refers to the fact that the current in the primary winding of the transformer of the power converter flows continuously in successive switching cycles. The term "discontinuous conduction mode" or "DCM" refers to the fact that the current in the primary winding of the transformer is allowed to drop to zero during a period of time (i.e., the "dead" time) during each switching cycle. The term "critical conduction mode" or "CRM" refers to operation at or near the boundary between the CCM and DCM operating modes. In other words, during CRM, the current in the primary winding is allowed to drop to zero just before the current rises again.

[0020] Operation in CRM is useful during high load conditions to achieve high efficiency. However, when the load decreases, the current level in the primary winding required to maintain the regulated output voltage also decreases. As a result, operation at lower load levels tends to revert to DCM. The level of the input voltage also affects the operation. For example, the duration of the "dead zone" in DCM tends to increase when the input voltage is higher, and tends to decrease when the input voltage is lower. The input voltage level can vary based on the level of the AC line voltage. For example, different countries have adopted different AC line voltage levels as their respective standards. The load also affects the input voltage level; for example, an increased current drawn from an AC source decreases its voltage level.

[0021] Operation in DCM tends to be less efficient than other operating modes due in part to the "dead" time. According to an embodiment of the present invention, the moment to turn off the high-side switch is adjusted within each switching cycle according to the level of the input supply voltage. More specifically, when the input voltage decreases, the high-side switch can be turned off earlier in the switching cycle than would otherwise be the case. Conversely, when the input voltage increases, the high-side switch can be turned off later in the switching cycle than would otherwise be the case. As a result, the duration of the "dead" within the switching cycle is reduced. This tends to improve efficiency.

[0022] In an embodiment, the moment to disconnect the high-side switch is continuously adjusted based on the monitored input voltage level. For example, the input voltage level can be monitored by sampling the input voltage at an appropriate time during each switching cycle. For example, the input voltage can be sampled with a predetermined delay after the high-side switch is disconnected during each switching cycle. The level of the input voltage may fluctuate during the switching cycle. By sampling the input voltage at the same time during each switching cycle, sampling errors caused by these fluctuations can be reduced.

[0023] When the input voltage is low, the efficiency improvement obtained by disconnecting the high side earlier in the switching cycle tends to be more obvious under higher load conditions. Therefore, according to another embodiment of the present invention, when the load condition is light, the above-mentioned adjustment of the time of disconnecting the high side switch can be prohibited. For example, this can be achieved by monitoring the output voltage of the power converter. When the output voltage drops below a threshold, this indicates that a light load condition exists, and the adjustment of the time of disconnecting the high side switch can be prohibited. When the output voltage rises above the threshold, this indicates that the light load condition has ended and the adjustment of the time of disconnecting the high side switch can be enabled.

[0024] Figure 1 FIG. 1 is a schematic block diagram of a two-stage off-line power supply 100 according to an embodiment of the present invention. Figure 1As shown, the first stage 102 has an input coupled to an alternating current (AC) source. The first stage 102 performs rectification on the AC input signal. The first stage 102 may also perform power factor correction (PFC), in which case the first stage 102 also keeps the current drawn from the AC source substantially in phase with the AC voltage so that the power supply 100 presents a resistive load to the AC source.

[0025] The first stage 102 generates a loosely regulated voltage V DC , which is provided as input to the DC to DC converter 104. Using the input power supply V DC , the DC to DC converter stage 104 generates a voltage regulated DC output V O , which can be used to power the load. V DC The level is preferably at a level lower than the output V of the DC to DC converter stage 104. O The nominal level V at the output of the first stage 102 is higher and is more loosely regulated than V. DC may be, for example, approximately 380 V DC, while the voltage regulated output V of the DC to DC converter stage 104 is O This may be, for example, approximately 15.0 V DC.

[0026] Figure 2 FIG. 1 shows a flyback converter 150 according to an embodiment of the present invention. The flyback converter 150 is suitable for use as a DC to DC converter of a switching power supply, such as Figure 1 The DC to DC converter 104. The flyback converter 150 is from the source V IN Receives input voltage, which can be the rectifier output or the PFC stage output V DC Or it may be received from some other source, such as an electromagnetic interference (EMI) filter.

[0027] like Figure 2 As shown, the input voltage source V IN Coupled to capacitor C SN The first terminal and the transformer T 1 The first terminal of the primary winding. Capacitor C SN Used as a buffer capacitor. The capacitor C SN The two ends form Figure 2 The voltage V shown has polarity CSN . Transformer T 1 The second terminal of the primary winding is coupled to the switch SW 1 The first terminal of the switch SW 2 The first terminal of the low-side switch SW 1 and high side switch SW 2 At the nodes between and at the transformer T 1The voltage V is formed at the second terminal of the primary winding L . Switch SW 1 The second terminal of the switch SW is coupled to the first ground node. 2 The second terminal is coupled to the capacitor C SN The second terminal of the switch SW 1 The switch SW is controlled by the signal LOWOUT. 2 Controlled by signal HIGHOUT.

[0028] Low side switch SW 1 and high side switch SW 2 Each is preferably implemented by a respective power MOSFET. Thus, the body diode is shown as being connected to the switch SW 1 and SW 2 Each one is associated with.

[0029] Transformer 1 The first terminal of the secondary winding is coupled to a Zener diode D 1 The anode of diode D 1 The cathode of the capacitor is coupled to 1 The first terminal of the transformer T 1 The second terminal of the secondary winding is coupled to the capacitor C 1 The first ground node and the second ground node are preferably electrically isolated from each other.

[0030] By opening and closing the switch SW 1 and SW 2 To operate the flyback converter 150. Transformer T 1 The flyback converter 150 transfers energy from its input to its output and provides isolation between the input and output of the flyback converter 150. 1 When the switch is closed (turned “ON”), the voltage source V IN In the transformer T 1 As a result, the current in the primary winding and the transformer T 1 The magnetic flux in the transformer increases, which stores energy in the transformer T. 1 Then, when the switch SW is turned off 1 When the switch turns OFF, the current and magnetic flux in the primary winding decrease. As a result, the transformer T 1 A current is induced in the secondary winding of the capacitor C 1 The power is charged to generate an output voltage V for powering the load. O .

[0031] By adjusting the switch SW 1The switching duty cycle of the switch SW 1 The level of power delivered to the load is controlled by controlling the duty cycle, the switching frequency, or both. Controlling the duty cycle is referred to herein as peak current control, while controlling the switching frequency is referred to herein as frequency control.

[0032] When the switch SW 1 Open and switch SW 2 In the closed position (switch SW 2 When the transformer T 1 The current in the primary winding can be 2 Arrives at the buffer capacitor C SN Alternatively, when switch SW 1 Open and switch SW 2 In the open position (switch SW 2 When the transformer T 1 The current in the primary winding can be 2 The body diode reaches the buffer capacitor C SN .

[0033] High side switch SW 2 is preferably controlled so that when the low-side switch SW 1 When the switch SW is closed (ON), it is opened (OFF). 1 Disconnect (OFF) and from transformer T 1 The energy has been released to the output capacitor C 1 When the voltage V L will be equal to V CSN Under these conditions, switch SW 2 is briefly closed (ON). Therefore, the switch SW 2 It can operate under zero voltage switching (ZVS) condition. Close switch SW 2 V L The level is discharged to V IN Then, once V L Basically equal to V IN , switch SW 2 Then it can be turned off (OFF). 2 After disconnection, the voltage V L Continue to decrease so that when the switch SW 1 When closed, the voltage across it is zero or close to zero. 1 It is also possible to operate under zero voltage switching (ZVS) conditions. The cycle is then repeated.

[0034] In summary, during the switching cycle, the low-side switch SW1 is disconnected; then, the high-side switch SW 2 Turn on, then the low side switch SW 1 The cycle then repeats (i.e. SW 1 Shutdown, SW 2 On, SW 2 Shutdown, SW 1 On, SW 1 Therefore, at each low-side switch SW 1 Before turning on, the high-side switch SW 2 Similarly, for the low-side switch SW 1 In each cycle, the high-side switch SW 2 Switch on and then off once (while the low-side switch SW 1 In other words, each switch turns on and then off while the other switch turns off.

[0035] In one embodiment, the switch SW 1 and SW 2 All of them operate under ZVS. Therefore, they can all operate under ZVS from no load to full load. In other embodiments, the switch SW 1 and SW 2 Not operating under ZVS or partially operating under ZVS. For example, according to an embodiment of the present invention, the high-side switch SW 2 is opened at a time depending on the level of VIN. In this case, the switch SW 2 can be disconnected under non-ZVS conditions because it L The level is equal to V IN Disconnected before.

[0036] The flyback converter 150 has a resonant switching frequency. The resonant frequency depends on the physical characteristics of the flyback converter 150, including the transformer T 1 The inductance of the primary winding and the switch SW 1 and SW 2 When the switch SW 2 When closed, this introduces a snubber capacitor C SN capacitance, and therefore the switch SW 2 When closed, it effectively changes the resonant frequency of the flyback converter 150.

[0037] Coupled to transformer T 1 The secondary winding diode D 1 operates as a freewheeling diode, allowing the transformer T 1 The current in the secondary winding of capacitor C 1 charging and prevents capacitor C1 Through the transformer T 1 Discharge. Diode D 1 can be controlled by switching SW 1 and SW 2 Synchronously operated switches (synchronous rectification) are used instead.

[0038] Figure 3 1 shows a voltage waveform illustrating the quasi-resonant operation of a flyback converter according to an embodiment of the present invention. The waveform represents V L Level. Figure 3 As shown, switch SW 1 At time t 0 Initially closed (ON), V L The level is essentially zero volts. This causes the current to flow through the transformer T 1 flows in the primary winding of the transformer T 1 The primary winding is full of energy. Then at time t 1 Disconnect (OFF) switch SW 1 As a result, V L The level rises rapidly to above V IN Then, the current flows through the switch SW 2 The body diode from the transformer T 1 The energy in the transformer T 1 A current is induced in the secondary winding of the output capacitor C 1 Then, when the voltage V L Equal to V CSN or almost equal to V CSN When the switch SW 2 At time t 2 is briefly closed (ON). This causes V L The level is towards V IN Then at time t 3 , switch SW 2 Disconnect (OFF). And at time t 4 , switch SW 1 This causes V L The level drops to zero volts and current again flows through transformer T 1 of the primary winding, and the switching cycle is repeated.

[0039] Because when the switch SW 2 When closed, the voltage V L Preferably equal to or almost equal to V CSN , so the switch SW can be closed under zero voltage switching (ZVS) conditions 2 By synchronously controlling the high-side switch SW 2With ZVS, more efficient operation can be provided, for example, by avoiding the losses caused by non-ZVS switching and allowing operation at higher switching frequencies, which also tends to improve the efficiency of the flyback converter.

[0040] Figure 3 The waveform shown assumes that once the voltage V L First, equal to V CSN or almost equal to V CSN , switch SW 2 is closed (ON). In this article, this is called "quasi-resonant" or "first hill" switching. If the switch SW 2 The closing of is delayed, then the voltage V L Will tend to oscillate. If the voltage V L During the oscillation period, when V L Equal to or almost equal to V CSN Time switch SW 2 If the switch is closed, zero voltage switching can be maintained under these conditions. This is referred to as "valley switching" in this article. Figure 4 shown.

[0041] Figure 4 1 shows a voltage waveform showing the valley switching operation of the flyback converter according to an embodiment of the present invention. 2 Voltage before closing V L Besides oscillation, Figure 4 The voltage V L The waveform and Figure 3 The waveforms shown are identical. Figure 4 It shows that at time t 2 Close switch SW 2 The two oscillations that occurred before. Obviously, as long as V L Equal to or almost equal to V CSN The switch SW is closed at the moment 2 , more or less oscillations can occur while maintaining zero voltage switching.

[0042] like Figure 3 and 4 As shown, the high-side switch SW 2 At time t 2 closed, and at time t 3 Therefore, at t 2 With t 3 During the time period between 2 Keep it closed. Figure 3 The duration of the time period t2-t3 shown may represent V IN The maximum expected level is, for example, 380 volts DC. However, as described herein, it is possible to INFor example, when V IN When the voltage is lower than 380V DC (for example, 240V DC), the switch SW 2 can be turned off faster in the switching cycle, thus reducing the time t 3 Move closer to 2 And shortened t 2 and t 3 The duration of the time period between.

[0043] Switch SW 2 Preferably closed under ZVS. Switch SW 2 It can also be disconnected under ZVS. In the above example, when the power supply voltage V IN When the voltage is 380V DC, the switch SW 2 However, when the supply voltage V IN Lower and time t 3 When the switching cycle occurs faster, the switch SW 2 can be disconnected under non-ZVS conditions. In this condition, this is done by SN ( Figure 2 ) to help improve efficiency. 2 -t 3 The amount is preferably related to V IN is proportional to the change in level.

[0044] The flyback converter 150 can be configured to operate in a quasi-resonant manner (e.g., Figure 3 as shown) or valley switch (as shown Figure 4 ) selectively operates to adjust the output voltage.

[0045] Figure 5 A flyback converter 150 and a control circuit according to an embodiment of the present invention are shown. Figure 5 Shows Figure 2 The flyback converter 150 and the control circuit and the second output stage. In particular, the "low driver" controller 152 generates the control (opening and closing) switch SW 1 The low driver controller 152 may control the switch SW using frequency control and / or peak current control in a feedback loop. 1 , in order to adjust the output voltage V O The "high driver" controller 154 generates a signal HIGHOUT which controls (opens and closes) the switch SW 2 . Figure 5 The flyback converter 150 and the control circuit are preferably configured according to Figure 3 and Figure 4 The waveform controls the high-side switch SW 2 and low side switch SW 1 , and is preferably configured based on the monitored V IN The level adjustment disconnects the high-side switch SW 2 moment (i.e., Figure 3 and Figure 4 The time t shown 3 ), as described herein.

[0046] like Figure 5 As shown, the resistor divider and optical coupling network 156 is coupled to the output of the flyback converter 150 and includes a resistor R 1 , R 2 and R 3 、Capacitor C 2 , Photodiode P 1A and shunt regulator U 1 . Photodiode P 1A Optically coupled to the phototransistor P 1B . Phototransistor P 1B Coupled to the compensation resistor R 4 and capacitor C 3 The compensation resistor R 4 and capacitor C 3 The voltage signal V is generated at both ends EAO Signal V EAO Represents the error signal (V O The level of V O The signal V represents the difference between the expected level of V and the expected level of V, and also represents the level of the input power of the flyback converter 150. EAO With output voltage V O Galvanic isolation and replaces the ground reference transformer T 1 Ground level on the primary side.

[0047] Transformer 1 A second secondary winding may be included. Figure 5 As shown, the transformer T 1 The first terminal of the second secondary winding is coupled to a diode D 2 The cathode of diode D2 is coupled to capacitor C 4 The first terminal of the transformer T 1 The second terminal of the second secondary winding is coupled to the capacitor C 4 The second terminal of the voltage V CC The capacitor C 4 The resistor divider includes a resistor R 5 and R6 , and generate a representation of V CC The voltage signal ZCD of the level. Signal ZCD also represents V L level.

[0048] Likewise Figure 5 As shown, the current sensing resistor R SENSE The transistor switch SW is coupled to 1 between the second terminal and the first ground node. SENSE The current sensing signal I is formed at both ends SENSE .

[0049] The low driver controller 152 receives the signals ZCD, I SENSE 、V EAO and oscillator signal OSC as inputs and uses these signals to generate a signal LOWOUT to control the transistor switch SW 1 , as described herein. Signal V EAO Represents the load power and is used to adjust the output voltage in the feedback loop based on peak current control or switching frequency control. Signal I SENSE Represents transformer T 1 The current in the transformer is used to control the peak current in the transformer primary winding during switching. The oscillator signal OSC is used to control the timing of the switch. The signal ZCD represents V L level and is used to turn on the switch SW 1 .

[0050] The low driver controller 152 generates a differential signal READYHIGHON, which the high driver controller 154 uses to control the transistor switch SW 2 , as described herein. Although the high driver controller 154 determines to turn on the switch SW 2 The timing of the READYHIGHON signal notifies the high driver controller 154 that it can (ie, is allowed to) turn on the switch SW 2 Signal READYHIGHON is preferably a differential signal because low driver controller 152 and high driver controller 154 have different ground reference nodes. In particular, low driver controller 152 references a first ground node, while high driver controller 154 preferably uses voltage V L As its reference.

[0051] Likewise Figure 5 As shown, the first high voltage resistor R HV1 The first terminal is coupled to the capacitor C SN The second terminal of the resistor R HV1 The second terminal of is coupled to the high driver controller 154. This provides a representative voltage V to the high driver controller 154.CSN The second high voltage resistor R HV2 The first terminal is coupled to the input voltage V IN . Resistor R HV2 The second terminal of capacitor C is coupled to the high driver controller 154. RVIN Preferably with resistor R HV2 This provides a representative voltage V IN The signal R VIN . Capacitor C RVIN Helps smooth the signal R VIN , especially at light load. Voltage V L The signal is also coupled to the high driver controller 154. The high driver controller 154 uses the signal R VIN ,CS,V L and READYHIGHOUT to generate a signal HIGHOUT which controls (opens and closes) the switch SW 2 , as described in this article. In short, when V L Greater than V IN And CS is basically equal to V L When the high driver controller 154 turns on the switch SW 2 . Switch SW 2 Normally remains on until V L Basically equal to V IN , then turn on switch SW 2 However, as described herein, the switch SW 2 The time of shutdown can also depend on the input voltage V IN The level of.

[0052] Also in Figure 5 As shown in the figure, the voltage V CC Can be used as a power supply to power components of the low driver controller 152. Voltage V BOOT Can be used as a power source to power components of the high driver controller 154. Voltage V BOOT can be connected via a diode from V CC The diode then draws current to obtain the capacitor C VBOOT Charging. Voltage V BOOT It may also be used to indicate the load level of power converter 150 , as explained herein.

[0053] The switching cycle is performed as follows. The low-side switch SW 1 Then, once the transformer T 1 The peak current in the primary winding, such as the current sensing signal I SENSE As shown, the low-side switch SW1 The peak current depends on V EAO Level: (1) When V EAO When V is less than a threshold value (e.g., 2.5 V), the flyback converter is in frequency control mode and the peak current is essentially fixed (although the peak current preferably increases with V EAO (2) When V EAO When V is greater than a threshold (e.g., 2.5 V), the flyback converter is in current control mode and the peak current depends on V EAO (and the switching frequency is clamped). Once the low-side switch SW 1 Shutdown, voltage V L It rises rapidly and eventually reaches a value higher than the input voltage V IN Then, the low-side driver 152 activates and sends a READYHIGHON signal to the high-side driver 154. The READYHIGHON signal is activated at a time that depends on the switching frequency. After receiving the READYHIGHON signal, the high-side driver 154 determines V L V IN higher by an appropriate margin, and in response to this determination, the high-side driver 154 turns on the high-side switch SW 2 . High side switch SW 2 Keep on until V L The level drops to V IN At this time, the high-side driver 154 turns off the high-side switch SW 2 The high-side driver 154 turns off the high-side switch SW 2 The moment can also be based on V IN More specifically, at V L Depends on V IN The level drops to V IN Before the high-side switch SW 2 can be disconnected. When V L When the level drops to zero, the low-side switch SW 1 Can be reconnected.

[0054] Figure 3 and Figure 4 The waveforms are equally applicable to current control and frequency control modes, although the time scale ratios change depending on the mode of operation.

[0055] Figure 6 FIG. 1 shows a control circuit of the high driver 154 according to an embodiment of the present invention. The comparator 158 converts the input power supply voltage V IN The signal R VINand a pair of reference currents I generated by current sources 160 and 162, respectively. 1 and I 2 Current sources 160 and 162 are coupled to V as a reference voltage. L In one embodiment, the current I 1 is set to 2μA (2 microamperes), and the current I 2 is set to 60 μA (60 microamperes). For example, in order to compensate for signal path delays during high frequency operation, the signal at the input of comparator 158 may be additionally conditioned.

[0056] The output of comparator 158 is a logic signal I LIMIT When the comparator 158 is switched from R VIN The level of the current received is I 1 and I 2 When the level is between LIMIT is the first logic level, otherwise, I LIMIT Is the second logic level. Signal I LIMIT Used to control the high-side switch SW 2 More specifically, R VIN The current level must be within I 1 and I 2 between the levels of 1 and 2 in order to turn on the high-side switch SW during the switching cycle. 2 (and the signal READYHIGHON must be activated.) Therefore, comparator 158 is a window comparator whose output indicates R VIN Is the current signal at I 1 and I 2 The comparator 158 determines the level of V L V IN higher by an appropriate margin, and in response to this determination, the high-side driver 154 turns on the high-side switch SW 2 Therefore, the comparison window implemented by the comparator 158 determines the time required to turn on SW 2 moment (at Figure 3 and Figure 4 Time t 2 Providing a comparison window helps to offset the noise effects associated with high signal change rates and accommodates R VIN Resistor R VH2 The parasitic capacitance ( Figure 2 ), and avoid IN and V L The moment they cross each other (when one rises and the other falls, or vice versa) changes the logic level of ILIMIT.

[0057] The output of comparator 158 is inverted by inverter 164 to form a logic signal ILIMIT -bar. Signal I LIMIT -bar is coupled to the input of NAND gate 166, flip-flop FF 1 The inverting setting input S-bar, the input of the NAND gate 168, and the flip-flop FF 2 The inverting setting of the input S-bar. Signal I LIMIT Coupled to flip-flop FF 3 The inverting setting input S-bar. Flip-flop FF 3 The output Q of the one-shot circuit 170 is coupled to the input of the one-shot circuit 170. The inverting output of the one-shot circuit 170 is coupled to the flip-flop FF. 2 The inverting reset input R-bar of the flip-flop FF 2 The inverted output Q-bar is coupled to the input of NAND gate 166.

[0058] Signal READYHIGHON is coupled to the input of NAND gate 166, flip-flop FF 1 The first inverting reset input R 1 -bar, the input of the delay 172, and the input of the NAND gate 168. The inverted undervoltage lockout signal U VLO -bar coupled to flip-flop FF 3 The first inverting reset input R 1 -bar, and coupled to the flip-flop FF 1 The second inverting reset input R s -bar. Trigger FF 1 The output Q of the delay circuit 168 is coupled to the input of the NAND gate 168. The output of the delay circuit 168 is coupled to the input of the NAND gate 168.

[0059] The output of NAND gate 166 is coupled to flip-flop FF 4 The first inverting setting input S 1 -bar. The output of NAND gate 168 is coupled to flip-flop FF 4 The second inverting setting input S 2 -bar. Trigger FF 4 The output Q of AND gate 174 is coupled to the input of AND gate 174. The inverting output of gate 174 is coupled to flip-flop FF 3 The non-inverting output of gate 174 forms a signal HIGHOUT. The generated signal HIGHOUT is used to control switch SW 2 .

[0060] Signal R VIN Also by comparator 176 and current I 3 Compare. Current I 3is generated by an adjustable current source 178. Current source 178 is coupled to V L Current I 3 Based on V IN The output of comparator 176 is coupled to a first input of NAND gate 180. The signal HIGHOUT is coupled to a second input of NAND gate 180. The output of NAND gate 180 is coupled to a first input of NAND gate 182. The inverted undervoltage lockout signal U VLO -bar is coupled to a second input of NAND gate 182. The output of NAND gate 182 is coupled to flip-flop FF 4 of the inverting reset input R-bar, and the first input of the sampling circuit 184.

[0061] Signal R VIN is coupled to a second input of sampling circuit 184. NAND gate 182 generates a signal High Side Off, which is used by sampling circuit 184 to IN More specifically, each time the high-side switch SW 2 When the sampling circuit is turned off (i.e., disconnected), it is preferred that the sampling circuit waits for a delay time of about 250 to 300 nanoseconds before applying a voltage to V IN Therefore, approximately at V L The sample is taken when V IN The continuous samples are averaged to ensure that the monitored V IN The level of V IN The signal level is ~V IN (steady state). This signal is used to generate the current I 3 , which also represents V IN level.

[0062] Figure 6 The components are detected as Figure 3 The occurrence of the "first hill" for performing quasi-resonant switching is shown. The signal READYHIGHON notifies the high driver controller 154 that it can (ie, is allowed to) turn on the switch SW 2 Then, the high driver controller 154 determines to turn on the switch SW 2 Timing: When V L Greater than V IN (Signal I LIMIT As shown), the high driver controller 154 turns on the switch SW 2 .

[0063] Flip-Flop FF 1 and the delay block 172 is used to delay the turning on of the switch SW 2, to avoid premature switching. In the case of undervoltage, U VLO Signal inhibit switch.

[0064] Switch SW 2 remains on until switch SW is turned on based on the comparison made by comparator 176. 2 More specifically, when V IN biased by an amount substantially equal to V L When the switch SW 2 Shutdown (disconnected), the bias is ~V IN The comparator 176 preferably performs its comparison with hysteresis to avoid multiple changes in the level of its output at crossings of the input signal level of the comparator 176.

[0065] like Figure 6 As shown, the voltage source V BOOT can be coupled to a third input of sampling circuit 184. This can be used to determine whether power converter 150 is under light load or heavy load conditions. For example, V BOOT Adjust to approximately 15 volts DC. When V BOOT When V rises above the 15V threshold level, it indicates a light load. BOOT When V drops below the threshold level of 15 volts, it indicates that the load is no longer lightly loaded. According to an embodiment of the present invention, when the converter 150 is in a lightly loaded condition, the V based IN The level is used to turn off the switch SW 2 More specifically, when V BOOT When the level is higher than the threshold, the IN (steady state) level for current I 3 When this happens, comparator 176 can set V IN The level (such as R VIN Represented by) and V L The level is compared to determine when to turn off the switch SW 2 Under these conditions, switch SW 2 It can be disconnected under ZVS. In addition, when V IN When the level is at the maximum threshold (e.g. 380 volts DC), based on ~V IN (steady state) level for current I 3 The regulation can also be equal to zero. However, when V BOOT The level is higher than the threshold (and V IN When the level is lower than its maximum threshold, the current I 3 The level can represent V IN level so that the switch SW 2Based in part on the monitored V IN (i.e. ~V IN (steady state)) level to disconnect.

[0066] Figure 7 FIG. 2 shows a control circuit of the low driver 152 according to an embodiment of the present invention. Figure 8 As shown, the low driver 152 includes a current control portion 186 , a frequency control portion 188 , a timer portion 190 , a switching logic 192 , and a switch driver 194 .

[0067] In the current control portion 186 of the low driver 152, the signal V EAO is coupled to a first input of a comparator 196. A second input of the comparator 196 receives a first reference voltage (e.g., 2.5 volts), and a third input of the comparator 196 receives a second reference voltage (e.g., 2.0 volts). The comparator 196 generates a voltage signal V EAO is compared with the first and second reference voltages to generate a signal "V EAO >2.5v-bar”; when V EAO When the signal “V EAO >2.5v-bar" is activated; when V EAO When the signal “V EAO >2.5v-bar” is disabled. Therefore, comparator 196 performs its comparison with hysteresis. Comparator 196 determines whether low driver controller 154 performs switching based on peak current control or frequency control. When V EAO When it rises above 2.5V, it switches by peak current control; when V EAO When it drops below 2.0V, it switches by frequency control. Therefore, “V EAO >2.5v-bar" logic level determines whether the switch is based on peak current control or frequency control.

[0068] Signal I SENSE is coupled to the input of the first amplifier 198 and to the input of the second amplifier 200. For example, amplifier 1982 may have a gain of 15, while amplifier 200 may have a gain of, for example, 7.5. The output of amplifier 198 is connected to the input of the first amplifier 198 and to the input of the second amplifier 200. For example, amplifier 1982 may have a gain of 15, while amplifier 200 may have a gain of 1 is coupled to a first input of a comparator 202. The output of the amplifier 200 is coupled to a first input of a comparator 202 via a switch S 2 is coupled to the first input of the comparator. The signal V EAO is coupled to the second input of the comparator CMP4. The signal “V EAO >2.5v-bar" is coupled to control the switch S 2 The switch S is controlled by the inverter 204.1 Therefore, depending on the signal “V EAO >2.5v-bar", switch S 1 and S 2 One of them is closed and the other is open. Therefore, depending on V EAO The outputs of amplifiers 198 and 200 are selectively coupled to a first input of a comparator 202. The output of comparator 202 is coupled to an input of switch logic 192.

[0069] Under current control, the amplifier 198 with higher gain is active to amplify the current that is compared with V by the comparator 202. EAO In comparison SENSE Under frequency control, amplifier 200 is active, which uses a lower gain to reduce the I SENSE effect, which makes the frequency control part 188 mainly control the switch.

[0070] In the frequency control section 188 of the low driver 152, the signal I SENSE is coupled to an input of amplifier 206. Amplifier 206 may have a gain of, for example, 7.5. The output of amplifier 206 is coupled to a first input of comparator 208. A second input of the comparator is coupled to a reference voltage, which may be, for example, approximately 2.5 volts. The output of comparator 208 is coupled to an input of switch logic 178.

[0071] The current control part 186 and the frequency control part 188 control the low-side switch SW to be turned off in each switching cycle via the switching logic 192. 1 Timing.

[0072] The timer section 190 of the low driver 152 controls the switching frequency and turns on the low-side switch SW in each switching cycle. 1 In the timer section 190, the signal V EAO is coupled to a first input of oscillator 210. The signal “V EAO >2.5v-bar” is coupled to a second input of the oscillator 210 . The oscillator 210 generates a periodic ramp signal, which is coupled to an input of the timer block 212 .

[0073] The timer block 212 generates a logic signal HON and a logic signal ONSET, which are coupled to the switch logic 192. The signal HON is used to generate a signal READYHIGHON for the high driver controller 154. For peak current control, the signal HON is generated at fixed intervals. The signal ONSET is used to turn on the low side switch SW 1For example, a 3.33 microsecond timer may be reset for each switching cycle; 500 nanoseconds before the timer expires, the signal HON is activated. Also, upon expiration of the timer, and once ZCD is greater than zero, the signal ONSET may be activated. Once ONSET is activated, the low-side switch SW may be closed at the valley value of the signal ZCD. 1 (Because ZCD represents V L ) in order to operate the switch SW under zero voltage switching (ZVS) conditions 1 The 500 nanosecond difference ensures that HON is activated before ONSET.

[0074] Signal ZCD is referenced to the same ground level as low-side driver controller 152. Signal ZCD also represents V L Therefore, the signal ZCD is used by the low-side driver controller 152 as V L In order to operate the switch SW under ZVS conditions 1 .

[0075] For current control, instead of a fixed timer interval of 3.33 microseconds, for example, the timer interval is based on V EAO Therefore, the timer interval affects the switching frequency used to regulate the output voltage in the feedback loop.

[0076] The timer interval of 3.33 microseconds corresponds to a switching frequency of 300 kHz for peak current control. In an embodiment, the switching frequency f can be set to 300 kHz by appropriately selecting the timing components. clamp Clamp at 500kHz, 300kHz, 145kHz or some other selected frequency.

[0077] The output of switch logic 192 is coupled to driver 194. Driver 194 generates a signal LOWOUT.

[0078] In switch SW 1 and SW 2 During the switching cycle, immediately before turning off the low-side switch SW 1 After that, V L The level rises to V IN Under light load conditions, the voltage stored in the transformer T 1 The energy on the primary side cannot be effectively transferred to its secondary side. Therefore, in each switching cycle, the snubber capacitor C SN The energy stored in the low-side switch SW will increase, so that the energy becomes overcharged, thereby disconnecting the low-side switch SW 1 Time V L By turning on the high-side switch SW earlier in the switching cycle, 2, these effects of light load conditions can be mitigated. Therefore, according to an embodiment of the present invention, under certain light load conditions, the high-side switch SW 2 is turned on earlier in the switching cycle than it would otherwise be. Similarly, when the input supply voltage V IN When at a high level, this also causes the buffer capacitor C SN This can also be done by turning on the high-side switch SW earlier in the switching cycle. 2 To reduce. When the input voltage V IN Using frequency control to control the switch, rather than current control, at high levels can also help alleviate these problems.Thus, according to an embodiment of the present invention, frequency control is used under certain high input voltage conditions.

[0079] In an embodiment, comparator 214 is included in Figure 7 In the current control section 186, the comparator 214 converts the signal R VIN The level (representing the voltage V IN ) is compared with the reference level. Figure 7 As shown, the signal R VIN can be gradually reduced by a voltage divider, which includes a resistor R 11 and R 12 The gradually decreasing voltage is compared with the reference voltage V REF2 When the comparison indicates V IN When the level of S is greater than a threshold value (e.g., 226 volts DC), the output of comparator 214 disables comparator 196. As a result, switch S 1 Open and switch S 2 186. IN greater than a threshold of 226 volts DC) operates in frequency control mode.

[0080] Figure 8 1 shows a differential signal converter 300 in a control circuit for a flyback converter according to an embodiment of the present invention. The differential signal converter 300 converts a single-ended signal HON into a differential logic signal READYHIGHON. The logic signal HON is coupled to the input of a first inverter 302. The output of the first inverter 302 is coupled to the input of a second inverter 304 and controls the MOSFET M 5 The output of the second inverter 304 is coupled to control the MOSFET M 6 MOSFET M 7 and current source 306 and MOSFET M5 Series coupled. MOSFET M 8 and current source 308 and MOSFET M 6 The current source 310 and the MOSFET M are coupled in series. 9 and MOSFET M 10 The reference current flows through MOSFET M 9 and M 10 The signal HON activates the MOSFET M depending on the level of HON. 5 or M 7 One of them. Depends on MOSFET M 5 or M 7 Which of the two is active, the reference current is in MOSFET M 8 or MOSFET M 7 The state of the differential signal READYHIGHON depends on the MOSFET M 5 or M 7 Therefore, the converter 300 converts the logic signal HON into a differential logic signal READYHIGHON.

[0081] The foregoing detailed description of the present invention is provided for the purpose of illustration and is not intended to be exhaustive or to limit the present invention to the disclosed embodiments. Accordingly, the scope of the present invention is defined by the appended claims.

Claims

1. A controller configured to control a power converter having a transformer, a low-side switch for drawing current from a supply voltage through a primary winding of the transformer, and a high-side switch for coupling the primary winding of the transformer to a buffer capacitor, wherein: The controller is configured to generate drive signals to control the opening and closing of the low-side switch and the high-side switch to form a regulated output voltage, and wherein the controller is configured to open the high-side switch during each of a series of switching cycles when a first voltage generated at a node between the low-side switch and the high-side switch reaches a determined level, the determined level being higher than the power supply voltage by an amount adjusted according to the level of the monitored power supply voltage.

2. The controller according to claim 1, wherein: The controller is configured to control a flyback converter that performs DC to DC power conversion.

3. The controller according to claim 1, wherein: The controller is configured to control the power converter such that an output voltage is formed by the current induced in the secondary winding of the transformer, and wherein the output voltage is regulated in a feedback loop.

4. The controller according to claim 1, wherein: The controller is configured to adjust the determined level only when the power converter is not in a light load condition.

5. The controller according to claim 4, wherein: The controller is configured to detect the light load condition by detecting that the output voltage rises above a threshold.

6. The controller according to claim 1, wherein: The controller is configured to keep the high-side switch open while the low-side switch is closed and then opened during each switching cycle, and wherein the controller is configured to keep the low-side switch open while the high-side switch is closed and then opened.

7. The controller according to claim 1, wherein: The high-side switch is closed according to zero voltage switching.

8. The controller according to claim 1, wherein: The controller is configured to close the high-side switch during each of the series of switching cycles based on a window comparison.

9. The controller according to claim 8, wherein: The window comparison compares the first voltage generated at the node between the low-side switch and the high-side switch with the power supply voltage.

10. The controller according to claim 1, wherein: The determined level is adjusted according to the level of the monitored power supply voltage so that the high-side switch is turned off earlier in the switching cycle when the power supply voltage decreases and the high-side switch is turned off later in the switching cycle when the power supply voltage increases.

11. The controller according to claim 10, wherein: The duration of the dead time within the switching cycle is thereby reduced.

12. The controller according to claim 1, wherein: The supply voltage is monitored by sampling at appropriate times during each switching cycle.

13. The controller according to claim 1, wherein: The timing for opening the high-side switch is continuously adjusted based on the level of the monitored supply voltage.

14. A switching power supply comprising: a power converter having a transformer, a low-side switch configured to draw current from a supply voltage through a primary winding of the transformer, and a high-side switch configured to couple the primary winding of the transformer to a snubber capacitor; as well as A controller configured to synchronously control the opening and closing of the low-side switch and the high-side switch, wherein the low-side switch and the high-side switch are repeatedly opened and closed in a series of switching cycles, respectively, to form a regulated output voltage, wherein a first voltage is generated at a node between the low-side switch and the high-side switch, and wherein the controller is further configured to open the high-side switch when the first voltage drops to a determined level during each switching cycle, and wherein the determined level is higher than the power supply voltage by an amount adjusted according to the level of the monitored power supply voltage.

15. The switching power supply according to claim 14, wherein: The power converter is a flyback converter configured to perform DC to DC power conversion.

16. The switching power supply according to claim 14, wherein: The output voltage is formed by a current induced in a secondary winding of the transformer, and wherein the output voltage is regulated in a feedback loop.

17. The switching power supply according to claim 14, wherein: The controller is configured to adjust the determined level only when the power converter is not in a light load condition.

18. The switching power supply according to claim 17, wherein: The light load condition is detected by the output voltage rising above a threshold.

19. The switching power supply according to claim 14, wherein: During each switching cycle, the high-side switch remains open while the low-side switch is closed and then opened, and wherein the low-side switch remains open while the high-side switch is closed and then opened.

20. The switching power supply according to claim 14, wherein: The high-side switch is closed according to zero voltage switching.

21. The switching power supply according to claim 14, wherein: The determined level is adjusted according to the level of the monitored power supply voltage so that the high-side switch is turned off earlier in the switching cycle when the power supply voltage decreases and the high-side switch is turned off later in the switching cycle when the power supply voltage increases.

22. The switching power supply according to claim 21, wherein: The duration of the dead time within the switching cycle is thereby reduced.

23. The switching power supply according to claim 14, wherein: The supply voltage is monitored by sampling at appropriate times during each switching cycle.

24. The switching power supply according to claim 14, wherein: The timing for opening the high-side switch is continuously adjusted based on the level of the monitored supply voltage.

25. A controller configured to control a power converter, the power converter having a transformer, a low-side switch for drawing current from a power supply voltage through a primary winding of the transformer, and a high-side switch for coupling the primary winding of the transformer to a snubber capacitor, wherein the controller is configured to generate drive signals to control the opening and closing of the low-side switch and the high-side switch to form a regulated output voltage, and wherein the controller is configured to operate in a first mode, wherein during each switching cycle, when a first voltage generated at a node between the low-side switch and the high-side switch drops to a level of the power supply voltage, the high-side switch is opened, and wherein the controller is configured to operate in a second mode, wherein during each switching cycle, when the first voltage drops to a determined level, the high-side switch is opened, the determined level being higher than the power supply voltage by an amount adjusted according to the level of the monitored power supply voltage.

26. The controller according to claim 25, wherein: The controller is configured to control a flyback converter that performs DC to DC power conversion.

27. The controller according to claim 25, wherein: The controller is configured to control the power converter such that an output voltage is formed by the current induced in the secondary winding of the transformer, and wherein the output voltage is regulated in a feedback loop.

28. The controller of claim 25, wherein: The controller is configured to operate in the first mode when the power converter is in a light load condition, otherwise, the controller is configured to operate in the second mode.

29. The controller according to claim 28, wherein: The controller is configured to detect the light load condition by detecting that the output voltage rises above a threshold.

30. The controller of claim 25, wherein: The controller is configured to keep the high-side switch open while the low-side switch is closed and then opened during each switching cycle, and wherein the controller is configured to keep the low-side switch open while the high-side switch is closed and then opened.

31. The controller of claim 25, wherein: The high-side switch is closed according to zero voltage switching.

32. The controller of claim 25, wherein: In the second mode, the determined level is adjusted according to the level of the monitored power supply voltage so that when the power supply voltage decreases, the high-side switch is turned off earlier in the switching cycle, and when the power supply voltage increases, the high-side switch is turned off later in the switching cycle.

33. The controller according to claim 32, wherein: The duration of the dead time within the switching cycle is thereby reduced.

34. The controller of claim 25, wherein: The supply voltage is monitored by sampling at appropriate times during each switching cycle.

35. The controller of claim 25, wherein: The timing for opening the high-side switch in the second mode is continuously adjusted based on the level of the monitored supply voltage.

36. A switching power supply comprising: a power converter having a transformer, a low-side switch configured to draw current from a supply voltage through a primary winding of the transformer, and a high-side switch configured to couple the primary winding of the transformer to a snubber capacitor; as well as A controller configured to synchronously control the opening and closing of the low-side switch and the high-side switch, wherein the low-side switch and the high-side switch are repeatedly opened and closed in a series of switching cycles, respectively, to form a regulated output voltage, wherein a first voltage is generated at a node between the low-side switch and the high-side switch, and wherein the controller is configured to operate in a first mode, wherein during each switching cycle, when the first voltage drops to a level of the power supply voltage, the high-side switch is opened, and wherein the controller is configured to operate in a second mode, wherein during each switching cycle, when the first voltage drops to a determined level, the high-side switch is opened, and wherein the determined level is higher than the power supply voltage by an amount adjusted according to the level of the monitored power supply voltage.

37. The switching power supply according to claim 36, wherein: The power converter is a flyback converter configured to perform DC to DC power conversion.

38. The switching power supply according to claim 36, wherein: The output voltage is formed by a current induced in a secondary winding of the transformer, and wherein the output voltage is regulated in a feedback loop.

39. The switching power supply according to claim 36, wherein: The controller is configured to operate in the first mode when the power converter is in a light load condition, otherwise, the controller is configured to operate in the second mode.

40. The switching power supply according to claim 39, wherein: The light load condition is detected by the output voltage rising above a threshold.

41. The switching power supply according to claim 36, wherein: During each switching cycle, the high-side switch remains open while the low-side switch is closed and then opened, and wherein the low-side switch remains open while the high-side switch is closed and then opened.

42. The switching power supply according to claim 36, wherein: The high-side switch is closed according to zero voltage switching.

43. The switching power supply according to claim 36, wherein: In the second mode, the determined level is adjusted according to the level of the monitored power supply voltage so that when the power supply voltage decreases, the high-side switch is turned off earlier in the switching cycle, and when the power supply voltage increases, the high-side switch is turned off later in the switching cycle.

44. The switching power supply according to claim 43, wherein: The duration of the dead time within the switching cycle is thereby reduced.

45. The switching power supply according to claim 36, wherein: The supply voltage is monitored by sampling at appropriate times during each switching cycle.

46. ​​The switching power supply according to claim 36, wherein: The timing for opening the high-side switch in the second mode is continuously adjusted based on the level of the monitored supply voltage.

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