A variable gain amplifier circuit

Abstract

The present application is applicable to the field of integrated circuit technology, and provides a variable gain amplifier circuit, including a first variable gain amplifier module and a driving buffer module connected in sequence, the driving buffer module including: a fully differential amplifier, a first feedback resistor, a second feedback resistor, a first compensation capacitor and a second compensation capacitor; the variable gain amplifier circuit is used to perform differential amplification processing on the received differential signal according to a preset gain and then output it; wherein the preset gain is adjustable. Since the output end of the first variable gain amplifier module in the variable gain amplifier circuit is connected to the driving buffer module, the variable gain amplifier circuit can drive various types of loads and has a strong load driving capability; and since the driving buffer module is composed of only a fully differential amplifier, two resistors and two capacitors, the power consumption of the entire variable gain amplifier circuit can be reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuits, and in particular, relates to a variable gain amplifier circuit. Background Art

[0002] Variable gain amplifier circuits are often used to amplify electrical signals. Due to their adjustable gain, they have been widely used in various communication, navigation, and signal detection and transmission systems. Many existing applications usually require variable gain amplifier circuits to have strong load driving capabilities, that is, they can drive a variety of different types of loads, such as low impedance loads, large capacitive loads, or high impedance loads. The traditional approach is usually to set a buffer amplifier composed of a single-ended output operational amplifier at the output end of the variable gain amplifier, and the variable gain amplifier and the buffer amplifier constitute a variable gain amplifier circuit. In order to achieve a fully differential output, it is usually necessary to set two single-ended output operational amplifiers at the output end of the variable gain amplifier, which will increase the power consumption of the entire variable gain amplifier circuit. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a variable gain amplifier circuit to solve the problem of high power consumption in the existing variable gain amplifier circuit with output driving function.

[0004] A variable gain amplifier circuit provided in an embodiment of the present application includes a first variable gain amplifier module and a driving buffer module connected in sequence, wherein the driving buffer module includes: a fully differential amplifier, a first feedback resistor, a second feedback resistor, a first compensation capacitor, and a second compensation capacitor;

[0005] The two input ends of the first variable gain amplifier module are used to receive differential signals, the two output ends of the first variable gain amplifier module are respectively connected to the two input ends of the fully differential amplifier, the first feedback resistor is connected between the first input end and the first output end of the fully differential amplifier, the second feedback resistor is connected between the second input end and the second output end of the fully differential amplifier, the first compensation capacitor is connected in parallel with the first feedback resistor, and the second compensation capacitor is connected in parallel with the second feedback resistor;

[0006] The variable gain amplifier circuit is used to perform differential amplification processing on the received differential signal according to a preset gain and then output the result; wherein the preset gain is adjustable.

[0007] Optionally, both the first feedback resistor and the second feedback resistor are adjustable resistors.

[0008] Optionally, the first variable gain amplification module includes a transconductance amplification unit and a common mode feedback unit;

[0009] The first input end of the transconductance amplification unit is the first input end of the first variable gain amplification module, the second input end of the transconductance amplification unit is the second input end of the first variable gain amplification module, the first output end of the transconductance amplification unit and the first input end of the common-mode feedback unit are connected together as the first output end of the first variable gain amplification module, the second output end of the transconductance amplification unit and the second input end of the common-mode feedback unit are connected together as the second output end of the first variable gain amplification module, and the feedback end of the common-mode feedback unit is connected to the feedback end of the transconductance amplification unit.

[0010] Optionally, the transconductance amplification unit includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a third compensation capacitor and a first adjustable resistor array;

[0011] The gate of the first NMOS tube is the first input end of the transconductance amplifying unit, the gate of the second NMOS tube is the second input end of the transconductance amplifying unit, the source of the first NMOS tube is connected to the first end of the first adjustable resistor array, the drain of the first PMOS tube and the drain of the third NMOS tube, the drain of the first NMOS tube is connected to the gate of the first PMOS tube, the gate of the third PMOS tube, the first end of the third compensation capacitor and the drain of the sixth PMOS tube; the source of the second NMOS tube is connected to the second end of the first adjustable resistor array, the drain of the second PMOS tube and the drain of the fourth NMOS tube, the drain of the second NMOS tube is connected to the gate of the second PMOS tube, the gate of the fourth PMOS tube, the second end of the third compensation capacitor and the drain of the seventh PMOS tube; the gate of the third NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are connected to the first power supply for providing a bias voltage; the third NMOS tube The source of the S tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are connected to the ground; the drain of the fifth NMOS tube is connected to the drain of the fifth PMOS tube, the gate of the fifth PMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube; the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube, the source of the sixth PMOS tube and the source of the seventh PMOS tube are connected to a second power supply for providing a working power supply; the drain of the third PMOS tube and the drain of the sixth NMOS tube are connected to the first output end of the transconductance amplification unit; the drain of the fourth PMOS tube and the drain of the seventh NMOS tube are connected to the second output end of the transconductance amplification unit; the gate of the sixth NMOS tube and the gate of the seventh NMOS tube are connected to the feedback end of the transconductance amplification unit.

[0012] Optionally, the first adjustable resistor array includes multiple impedance branches in parallel; the first common end of the multiple impedance branches is the first end of the first adjustable resistor array, and the second common end of the multiple impedance branches is the second end of the first adjustable resistor array; each of the impedance branches includes at least one impedance device and a switching device connected in series with the impedance device, and the sum of the resistance values ​​of the impedance devices in different impedance branches is different.

[0013] Optionally, the common-mode feedback unit includes: an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, an eighth PMOS tube, a ninth PMOS tube, a zero adjustment resistor and a fourth compensation capacitor;

[0014] The gate of the eighth NMOS tube is the second input terminal of the common-mode feedback unit, the gate of the ninth NMOS tube is the first input terminal of the common-mode feedback unit, the source of the eighth NMOS tube is connected to the drain of the tenth NMOS tube and the source of the twelfth NMOS tube, the drain of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, the drain of the eighth PMOS tube, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube, the source of the ninth NMOS tube is connected to the drain of the eleventh NMOS tube and the source of the thirteenth NMOS tube, the gate of the tenth NMOS tube is connected to the gate of the eleventh NMOS tube The first power supply for providing a bias voltage is connected to the first power supply, the source of the tenth NMOS tube, the source of the eleventh NMOS tube and the negative electrode of the fourth compensation capacitor are connected to the ground, the source of the eighth PMOS tube and the source of the ninth PMOS tube are connected to the second power supply for providing an operating voltage, the drain of the ninth PMOS tube, the drain of the twelfth NMOS tube, the drain of the thirteenth NMOS tube and the first end of the zero adjustment resistor are connected to serve as the feedback end of the common-mode feedback unit, the second end of the zero adjustment resistor is connected to the positive electrode of the fourth compensation capacitor, and the gate of the twelfth NMOS tube and the gate of the thirteenth NMOS tube are connected to the third power supply for providing a reference voltage.

[0015] Optionally, the variable gain amplification circuit further includes at least one second variable gain amplification module disposed at the front end of the first variable gain amplification module, and the gain of the second variable gain amplification module is adjustable.

[0016] Optionally, the second variable gain amplifier module includes: a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a second adjustable resistor array, a first output load, and a second output load;

[0017] The gate of the fourteenth NMOS tube is the first input end of the second variable gain amplifier module, the gate of the fifteenth NMOS tube is the second input end of the second variable gain amplifier module, the source of the fourteenth NMOS tube is connected to the first end of the second adjustable resistor array, the drain of the tenth PMOS tube and the drain of the sixteenth NMOS tube, the drain of the fourteenth NMOS tube is connected to the gate of the tenth PMOS tube, the gate of the twelfth PMOS tube and the drain of the fifteenth PMOS tube; the source of the fifteenth NMOS tube is connected to the second end of the second adjustable resistor array, the drain of the eleventh PMOS tube and the drain of the seventeenth NMOS tube, the drain of the fifteenth NMOS tube is connected to the gate of the eleventh PMOS tube, the gate of the thirteenth PMOS tube and the drain of the sixteenth PMOS tube; the gate of the sixteenth NMOS tube, the gate of the seventeenth NMOS tube and the gate of the eighteenth NMOS tube are connected to the first electrode for providing a bias voltage. source; the source of the sixteenth NMOS tube, the source of the seventeenth NMOS tube, the source of the eighteenth NMOS tube, the second end of the first output load and the second end of the second output load are connected to the ground; the drain of the eighteenth NMOS tube is connected to the drain of the fourteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube and the gate of the sixteenth PMOS tube; the source of the tenth PMOS tube, the source of the eleventh PMOS tube, the source of the twelfth PMOS tube, the source of the thirteenth PMOS tube, the source of the fourteenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube are connected to a second power supply for providing a working power supply; the drain of the twelfth PMOS tube and the first end of the first output load are connected together as the first output end of the second variable gain amplifier module; the drain of the thirteenth PMOS tube and the first end of the second output load are connected together as the second output end of the second variable gain amplifier module.

[0018] Optionally, the second adjustable resistor array includes multiple impedance branches in parallel; the first common end of the multiple impedance branches is the first end of the second adjustable resistor array, and the second common end of the multiple impedance branches is the second end of the second adjustable resistor array; each of the impedance branches includes at least one impedance device and a switching device connected in series with the impedance device, and the sum of the resistance values ​​of the impedance devices in different impedance branches is different.

[0019] Optionally, the switching device is a triode or a MOS tube.

[0020] Implementing a variable gain amplifier circuit provided by an embodiment of the present application has the following beneficial effects:

[0021] A variable gain amplifier circuit provided by an embodiment of the present application includes a first variable gain amplifier module and a driving buffer module connected in sequence, wherein the driving buffer module includes: a fully differential amplifier, a first feedback resistor, a second feedback resistor, a first compensation capacitor and a second compensation capacitor; the two input ends of the first variable gain amplifier module are used to receive differential signals, the two output ends of the first variable gain amplifier module are respectively connected to the two input ends of the fully differential amplifier, the first feedback resistor is connected between the first input end and the first output end of the fully differential amplifier, the second feedback resistor is connected between the second input end and the second output end of the fully differential amplifier, the first compensation capacitor is connected in parallel with the first feedback resistor, and the second compensation capacitor is connected in parallel with the second feedback resistor; the variable gain amplifier circuit is used to perform differential amplification processing on the received differential signal according to a preset gain and then output it; wherein the preset gain is adjustable. Since the output end of the first variable gain amplifier module in the variable gain amplifier circuit is connected to the driving buffer module, the variable gain amplifier circuit can drive various types of loads and has a strong load driving capability; and since the driving buffer module is only composed of a fully differential amplifier, two resistors and two capacitors, the power consumption of the entire variable gain amplifier circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A schematic diagram of the structure of a variable gain amplifier circuit provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a variable gain amplifier circuit provided in another embodiment of the present application;

[0025] Figure 3 A schematic diagram of the circuit structure of a first variable gain amplifier module in a variable gain amplifier circuit provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the circuit structure of a first adjustable resistor array in a variable gain amplifier circuit provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of a variable gain amplifier circuit provided in another embodiment of the present application;

[0028] Figure 6 A schematic diagram of the circuit structure of a second variable gain amplifier module in a variable gain amplifier circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0030] It should be understood that the term "and / or" used in the specification of this application and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. In addition, in the description of the specification of this application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0031] It should also be understood that references to "one embodiment" or "some embodiments" etc. described in the specification of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in the specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0032] See also Figure 1 , Figure 1 Schematic diagram of a variable gain amplifier circuit provided in an embodiment of the present application. Figure 1 As shown, the variable gain amplifier circuit may include a first variable gain amplifier module 11 and a driving buffer module 12 connected in sequence. The driving buffer module 12 includes: a fully differential amplifier AMP1, a first feedback resistor R1, a second feedback resistor R2, a first compensation capacitor C1 and a second compensation capacitor C2.

[0033] The two input ends of the first variable gain amplifier module 11 are used to receive differential signals, the two output ends of the first variable gain amplifier module 11 are respectively connected to the two input ends of the full differential amplifier AMP1, the first feedback resistor R1 is connected between the first input end and the first output end of the full differential amplifier AMP1, the second feedback resistor R2 is connected between the second input end and the second output end of the full differential amplifier AMP1, the first compensation capacitor C1 is connected in parallel with the first feedback resistor R1, and the second compensation capacitor C2 is connected in parallel with the second feedback resistor R2. Specifically, the upper plate of the first compensation capacitor C1 is connected to the first output end of the full differential amplifier AMP1, the lower plate of the first compensation capacitor C1 is connected to the first input end of the full differential amplifier AMP1, the upper plate of the second compensation capacitor C2 is connected to the second output end of the full differential amplifier AMP1, and the lower plate of the second compensation capacitor C2 is connected to the second input end of the full differential amplifier AMP1.

[0034] The variable gain amplifier circuit is used to perform differential amplification processing on the received differential signals VinP and VinN according to a preset gain and then output the differential signals; wherein the preset gain is adjustable.

[0035] Specifically, the first variable gain amplifier module 11 can be equivalent to a transconductance amplifier, and the driving buffer module 12 can be equivalent to a transimpedance amplifier, and the two are cascaded to form a variable gain amplifier circuit for amplifying voltage. Among them, the first variable gain amplifier module 11 can be a pseudo-differential structure using local source negative feedback, and the resistance value of the source negative feedback resistor in the first variable gain amplifier module 11 is adjustable.

[0036] Based on this, the preset gain can be determined according to the ratio of the resistance value of the first feedback resistor R1 to the resistance value of the source negative feedback resistor in the first variable gain amplifier module 11, or the preset gain can be determined according to the ratio of the resistance value of the second feedback resistor R2 to the resistance value of the source negative feedback resistor in the first variable gain amplifier module 11. Therefore, the preset gain can be adjusted by adjusting the resistance value of the source negative feedback resistor in the first variable gain amplifier module 11.

[0037] In the embodiment of the present application, since the output end of the first variable gain amplifier module in the variable gain amplifier circuit is connected to the driving buffer module, the variable gain amplifier circuit can drive various types of loads and has a strong load driving capability; since the driving buffer module is composed of only a fully differential amplifier, two resistors and two capacitors, the power consumption of the entire variable gain amplifier circuit can be reduced.

[0038] In one embodiment of the present application, the first feedback resistor R1 and the second feedback resistor R2 can both be adjustable resistors, so that the driving buffer module 12 also has the function of adjusting the preset gain, thereby increasing the output voltage swing of the entire variable gain amplifier circuit.

[0039] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a variable gain amplifier circuit provided in another embodiment of the present application. Figure 2 As shown, the first variable gain amplification module 11 in this embodiment includes a transconductance amplification unit 111 and a common mode feedback unit 112. Wherein:

[0040] The first input end of the transconductance amplification unit 111 is the first input end VinP of the first variable gain amplification module 11, the second input end of the transconductance amplification unit 111 is the second input end VinN of the first variable gain amplification module 11, the first output end of the transconductance amplification unit 111 and the first input end of the common-mode feedback unit 112 are connected together as the first output end of the first variable gain amplification module 11, the second output end of the transconductance amplification unit 111 and the second input end of the common-mode feedback unit 112 are connected together as the second output end of the first variable gain amplification module 11, and the feedback end of the common-mode feedback unit 112 is connected to the feedback end of the transconductance amplification unit 111.

[0041] See also Figure 3 , Figure 3 Schematic diagram of the circuit structure of a first variable gain amplifier module provided in an embodiment of the present application. Figure 3 As shown, the transconductance amplification unit 111 in the first variable gain amplification module includes: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a first PMOS tube M6, a second PMOS tube M7, a third PMOS tube M8, a fourth PMOS tube M9, a fifth PMOS tube M10, a sixth PMOS tube M11, a seventh PMOS tube M12, a sixth NMOS tube M13, a seventh NMOS tube M14, a third compensation capacitor C3 and a first adjustable resistor array 1110. Among them:

[0042] The gate of the first NMOS transistor M1 is the first input terminal of the transconductance amplifying unit 111, the gate of the second NMOS transistor M2 is the second input terminal of the transconductance amplifying unit 111, the source of the first NMOS transistor M1 is connected to the first end of the first adjustable resistor array 1110, the drain of the first PMOS transistor M6 and the drain of the third NMOS transistor M3, the drain of the first NMOS transistor M1 is connected to the gate of the first PMOS transistor M6, the gate of the third PMOS transistor M8, the first end of the third compensation capacitor C3 and the drain of the sixth PMOS transistor M11; the second NMOS transistor M2 The source of the third NMOS tube M3 is connected to the second end of the first adjustable resistor array 1110, the drain of the second PMOS tube M7 and the drain of the fourth NMOS tube M4, the drain of the second NMOS tube M2 is connected to the gate of the second PMOS tube M7, the gate of the fourth PMOS tube M9, the second end of the third compensation capacitor C3 and the drain of the seventh PMOS tube M12; the gate of the third NMOS tube M3, the gate of the fourth NMOS tube M4 and the gate of the fifth NMOS tube M5 are connected to the first power supply (not shown in the figure) for providing the bias voltage VB; the ... The source of the fourth NMOS tube M4, the source of the fifth NMOS tube M5, the source of the sixth NMOS tube M13 and the source of the seventh NMOS tube M14 are connected to the ground; the drain of the fifth NMOS tube M5 is connected to the drain of the fifth PMOS tube M10, the gate of the fifth PMOS tube M10, the gate of the sixth PMOS tube M11 and the gate of the seventh PMOS tube M12; the source of the first PMOS tube M6, the source of the second PMOS tube M7, the source of the third PMOS tube M8, the source of the fourth PMOS tube M9, the source of the fifth PMOS tube M10 The source of the sixth PMOS tube M11 and the source of the seventh PMOS tube M12 are connected to a second power supply (not shown in the figure) for providing a working power supply VDD, the drain of the third PMOS tube M8 and the drain of the sixth NMOS tube M13 are connected to serve as a first output terminal of the transconductance amplifying unit 111, the drain of the fourth PMOS tube M9 and the drain of the seventh NMOS tube M14 are connected to serve as a second output terminal of the transconductance amplifying unit 111, and the gate of the sixth NMOS tube M13 and the gate of the seventh NMOS tube M14 are connected to serve as a feedback terminal of the transconductance amplifying unit 111.

[0043] In the embodiment of the present application, the first NMOS tube M1 and the second NMOS tube M2 are input differential pair tubes, and the first adjustable resistor array 1110 is connected between the source of the first NMOS tube M1 and the source of the second NMOS tube M2 to form a negative feedback structure, that is, the first adjustable resistor array 1110 is the source negative feedback resistor in the first variable gain amplifier module 11, and different gains can be selected by adjusting the resistance value of the first adjustable resistor array 1110; the third compensation capacitor C3 has an amplitude-frequency characteristic; the first PMOS tube M6 and the second PMOS tube M7 are devices that play a negative feedback role, and the first PMOS tube M6 and the second PMOS tube M7 can maintain the linear characteristics of the transconductance of the input differential pair tube (that is, the first NMOS tube M1 and the second NMOS tube M2), thereby improving the linearity of the variable gain amplifier circuit; the third NMOS tube M3 and the fourth NMOS tube M4 mirror the current of the fifth NMOS tube M5 to play a current biasing role; the sixth PMOS tube M11 and the seventh PMOS tube M12 The current of the fifth PMOS tube M10 is mirrored, and the sixth PMOS tube M11 and the seventh PMOS tube M12 are current load biases of the first NMOS tube M1 and the second NMOS tube M2 respectively; the current consumed by the load tube sixth PMOS tube M11 is less than 1 / 2 of the current consumed by the bias tube third NMOS tube M3; the fifth PMOS tube M10 is connected to the fifth NMOS tube M5 to form a current path; the third PMOS tube M8 and the fourth PMOS tube M9 are output tubes, the output tube third PMOS tube M8 mirrors the current of the feedback device first PMOS tube M6 as the output current, and the output tube fourth PMOS tube M9 mirrors the current of the feedback device second PMOS tube M7 as the output current; the sixth NMOS tube M13 and the seventh NMOS tube M14 are output load tubes, the gate of the sixth NMOS tube M13 and the gate of the seventh NMOS tube M14 are used to receive the common-mode feedback voltage output by the common-mode feedback unit 112, and the entire transconductance amplification unit 111 can be equivalent to a transconductance amplifier.

[0044] The common-mode feedback unit 112 in the first variable gain amplifier module includes: an eighth NMOS transistor M15, a ninth NMOS transistor M16, a tenth NMOS transistor M17, an eleventh NMOS transistor M18, a twelfth NMOS transistor M19, a thirteenth NMOS transistor M20, an eighth PMOS transistor M21, a ninth PMOS transistor M22, a zero adjustment resistor R4 and a fourth compensation capacitor C4. Wherein:

[0045] The gate of the eighth NMOS tube M15 is the second input terminal of the common-mode feedback unit 112, the gate of the ninth NMOS tube M16 is the first input terminal of the common-mode feedback unit 112, the source of the eighth NMOS tube M15 is connected to the drain of the tenth NMOS tube M17 and the source of the twelfth NMOS tube M19, the drain of the eighth NMOS tube M15 is connected to the drain of the ninth NMOS tube M16, the drain of the eighth PMOS tube M21, the gate of the eighth PMOS tube M21 and the gate of the ninth PMOS tube M22, the source of the ninth NMOS tube M16 is connected to the drain of the eleventh NMOS tube M18 and the source of the thirteenth NMOS tube M20, and the gate of the tenth NMOS tube M17 and the gate of the eleventh NMOS tube M18 are connected to the bias voltage VB for providing The first power supply (not shown in the figure) of the common-mode feedback unit 112 is connected to the first power supply (not shown in the figure), the source of the tenth NMOS tube M17, the source of the eleventh NMOS tube M18 and the negative electrode of the fourth compensation capacitor C4 are connected to the ground, the source of the eighth PMOS tube M21 and the source of the ninth PMOS tube M22 are connected to the second power supply (not shown in the figure) for providing the working voltage VDD, the drain of the ninth PMOS tube M22, the drain of the twelfth NMOS tube M19, the drain of the thirteenth NMOS tube M20 and the first end of the zero adjustment resistor R4 are connected to serve as the feedback end of the common-mode feedback unit 112, the second end of the zero adjustment resistor R4 is connected to the positive electrode of the fourth compensation capacitor C4, and the gate of the twelfth NMOS tube M19 and the gate of the thirteenth NMOS tube M20 are connected to the third power supply (not shown in the figure) for providing the reference voltage Vref.

[0046] In the embodiment of the present application, the eighth NMOS tube M15 and the ninth NMOS tube M16 are common-mode detection differential tubes, which are used to detect the common-mode voltage of the signal output by the transconductance amplification unit 111; the twelfth NMOS tube M19 and the thirteenth NMOS tube M20 are common-mode reference voltage input tubes, which are used to compare the reference voltage Vref with the common-mode voltage detected by the common-mode detection differential tube; the eighth NMOS tube M15 and the twelfth NMOS tube M19 form a differential pair structure, and the ninth NMOS tube M16 and the thirteenth NMOS tube M20 form a differential pair structure; the bias current of the common-mode feedback unit 112 is determined by the tenth NMOS tube M19. The eighth PMOS tube M21 and the ninth PMOS tube M22 form a current mirror, which mainly plays the role of load and current mirror, and is convenient for unit output. The drain of the ninth PMOS tube M22 is connected to the gate of the sixth NMOS tube M13 and the gate of the seventh NMOS tube M14 in the transconductance amplification unit 111 to form a common-mode feedback loop; the fourth compensation capacitor C4 is used to perform phase compensation on the circuit, which can ensure sufficient phase margin and improve the stability of the common-mode feedback loop; the common-mode feedback unit 112 can stabilize the common-mode voltage at the output end of the transconductance amplification unit 111 at the reference voltage Vref.

[0047] In the embodiment of the present application, the gain Gain of the variable gain amplifier circuit composed of the first variable gain amplifier module 11 and the driving buffer module 12 can be expressed as: Gain=K×(2r1 / r3).

[0048] Wherein, K is the ratio of the width to length ratio of the third PMOS tube M8 to the width to length ratio of the fourth PMOS tube M9, r1 is the resistance value of the first feedback resistor R1, and r3 is the equivalent resistance value of the first adjustable resistor array 1110. The width to length ratio is the ratio of the width to length of the conductive channel of the MOS tube.

[0049] In one embodiment of the present application, the first adjustable resistor array 1110 may include a plurality of impedance branches connected in parallel, the first common end of the plurality of impedance branches is the first end of the first adjustable resistor array 1110, the second common end of the plurality of impedance branches is the second end of the first adjustable resistor array 1110, and each impedance branch includes at least one impedance device and a switch device connected in series with the impedance device. The sum of the resistance values ​​of the impedance devices in different impedance branches is different. By controlling the on or off of the switch devices in each impedance branch, the first adjustable resistor array 1110 presents different resistance values, thereby realizing the adjustable gain of the variable gain amplifier circuit.

[0050] The circuit structure of the first adjustable resistor array 1110 is described in detail below using a specific example. Figure 4 , Figure 4The circuit structure diagram of the first adjustable resistor array in a variable gain amplifier circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the first adjustable resistor array 1110 may specifically include three impedance branches, wherein the first impedance branch includes a fifth resistor R5, a first switch device SW1, and a sixth resistor R6 connected in series, the second impedance branch includes a seventh resistor R7, a second switch device SW2, and an eighth resistor R8 connected in series, and the third impedance branch includes a ninth resistor R9, a third switch device SW3, and a tenth resistor R10 connected in series. The three impedance branches are connected in parallel, and the first common end of the three impedance branches is the first end P of the first adjustable resistor array 1110, and the second common end of the three impedance branches is the second end N of the first adjustable resistor array 1110.

[0051] It should be noted that the control terminals S1, S2 and S3 of the above three switch devices are all used to receive switch control signals, and the switch control signals can be provided by a digital logic control circuit. Specifically, when the switch control signal received by the switch device in a certain impedance branch is a conduction control signal, the impedance branch is connected to the circuit, that is, all resistors in the impedance branch are connected to the circuit; when the switch control signal received by the switch device in a certain impedance branch is a shutdown control signal, the impedance branch is disconnected, that is, all resistors in the impedance branch are not connected to the circuit. The equivalent resistance of the first adjustable resistor array 1110 can be determined according to the resistance values ​​of each resistor included in the impedance branch connected to the circuit.

[0052] For example, if the first switch device SW1 receives an on-control signal, and the second switch device SW2 and the third switch device SW3 both receive an off-control signal, then the first impedance branch is connected to the circuit, and the second impedance branch and the third impedance branch are disconnected. In this case, the equivalent resistance of the first adjustable resistor array 1110 is the sum of the resistance of the fifth resistor R5 and the resistance of the sixth resistor R6.

[0053] If the first switch device SW1 and the second switch device SW2 both receive a turn-on control signal, and the third switch device SW3 receives a turn-off control signal, then the first impedance branch and the second impedance branch are connected to the circuit, and the third impedance branch is disconnected. In this case, the equivalent resistance of the first adjustable resistor array 1110 is [(r5+r6)(r7+r8)] / (r5+r6+r7+r8). Among them, r5 is the resistance value of the fifth resistor R5, r6 is the resistance value of the sixth resistor R6, r7 is the resistance value of the seventh resistor R7, and r8 is the resistance value of the eighth resistor R8.

[0054] In this embodiment, the resistance value of the fifth resistor R5, the resistance value of the sixth resistor R6, the resistance value of the seventh resistor R7, the resistance value of the eighth resistor R8, the resistance value of the ninth resistor R9 and the resistance value of the tenth resistor R10 can be set according to actual needs and are not limited here.

[0055] In practical applications, the first switch device SW1 , the second switch device SW2 and the third switch device SW3 may all be switch tubes, and the switch tubes may be triodes or MOS tubes, etc., which are not limited here.

[0056] See also Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a variable gain amplifier circuit provided in another embodiment of the present application. Figure 5 As shown, the variable gain amplifier circuit may further include at least one cascaded (two are taken as an example in the figure) second variable gain amplifier module 13 arranged at the front end of the first variable gain amplifier module, and the at least one second variable gain amplifier module 13 is used to perform differential amplification processing on the input differential signal and then output it, and the gain of the at least one second variable gain amplifier module 13 is adjustable.

[0057] The second variable gain amplifier module 13 is a linear amplifier circuit.

[0058] In this embodiment, by arranging at least one cascaded second variable gain amplifier module at the front end of the first variable gain amplifier module, the entire variable gain amplifier circuit can achieve a wide range of adjustable gain and increase the output voltage swing of the entire variable gain amplifier circuit; and because the first variable gain amplifier module and the second variable gain amplifier module are both linear amplifier circuits, the entire variable gain amplifier circuit can have higher linearity and lower noise.

[0059] See also Figure 6 , Figure 6 Schematic diagram of the circuit structure of a second variable gain amplifier module in a variable gain amplifier circuit provided in an embodiment of the present application. Figure 6 As shown, the second variable gain amplifier module 13 includes: a fourteenth NMOS tube M23, a fifteenth NMOS tube M24, a sixteenth NMOS tube M25, a seventeenth NMOS tube M26, an eighteenth NMOS tube M27, a tenth PMOS tube M28, an eleventh PMOS tube M29, a twelfth PMOS tube M30, a thirteenth PMOS tube M31, a fourteenth PMOS tube M32, a fifteenth PMOS tube M33, a sixteenth PMOS tube M34, a second adjustable resistor array 130, a first output load R11 and a second output load R12.

[0060] The gate of the fourteenth NMOS tube M23 is the first input terminal of the second variable gain amplifier module 13, the gate of the fifteenth NMOS tube M24 is the second input terminal of the second variable gain amplifier module 13, the source of the fourteenth NMOS tube M23 is connected to the first end of the second adjustable resistor array 130, the drain of the tenth PMOS tube M28 and the drain of the sixteenth NMOS tube M25, the drain of the fourteenth NMOS tube M23 is connected to the gate of the tenth PMOS tube M28, the gate of the twelfth PMOS tube M30 and the drain of the fifteenth PMOS tube M33 The source of the fifteenth NMOS tube M24 is connected to the second end of the second adjustable resistor array 130, the drain of the eleventh PMOS tube M29 and the drain of the seventeenth NMOS tube M26, the drain of the fifteenth NMOS tube M24 is connected to the gate of the eleventh PMOS tube M29, the gate of the thirteenth PMOS tube M31 and the drain of the sixteenth PMOS tube M34; the gate of the sixteenth NMOS tube M25, the gate of the seventeenth NMOS tube M26 and the gate of the eighteenth NMOS tube M27 are connected to the first electrode for providing a bias voltage. The source of the sixteenth NMOS tube M25, the source of the seventeenth NMOS tube M26, the source of the eighteenth NMOS tube M27, the second end of the first output load R11 and the second end of the second output load R12 are connected to the ground; the drain of the eighteenth NMOS tube M27 is connected to the drain of the fourteenth PMOS tube M32, the gate of the fourteenth PMOS tube M32, the gate of the fifteenth PMOS tube M33 and the gate of the sixteenth PMOS tube M34; the source of the tenth PMOS tube M28, the source of the eleventh PMOS tube M29, the source of the twelfth The source of the PMOS tube M30, the source of the thirteenth PMOS tube M31, the source of the fourteenth PMOS tube M32, the source of the fifteenth PMOS tube M33 and the source of the sixteenth PMOS tube M34 are connected to the second power supply for providing the working power supply, the drain of the twelfth PMOS tube M30 and the first end of the first output load R11 are connected to serve as the first output end of the second variable gain amplifier module 13, and the drain of the thirteenth PMOS tube M31 and the first end of the second output load R12 are connected to serve as the second output end of the second variable gain amplifier module 13.

[0061] In this embodiment, the fourteenth NMOS tube M23 and the fifteenth NMOS tube M24 are input differential pair tubes, and the second adjustable resistor array 130 is connected between the source of the fourteenth NMOS tube M23 and the source of the fifteenth NMOS tube M24 to form a negative feedback structure. By adjusting the resistance value of the second adjustable resistor array 130, different gains can be selected; the tenth PMOS tube M28 and the eleventh PMOS tube M29 are devices that play a negative feedback role. The tenth PMOS tube M28 and the eleventh PMOS tube M29 can allow the transconductance of the input differential pair tube to maintain a linear characteristic, thereby improving the linearity of the variable gain amplifier circuit; the sixteenth NMOS tube M25 and the seventeenth NMOS tube M26 mirror the current of the eighteenth NMOS tube M27 to play a current biasing role; the fifteenth PMOS tube M33 and the sixteenth PMOS tube M34 mirror the current of the fourteenth PMOS tube M32, and the fifteenth PMOS tube M33 and the sixteenth PMOS tube M34 are respectively the fourteenth NMOS tube M23 and the fifteenth NMOS tube M24. The current load bias of the NMOS tube M24; the current consumed by the load tube 15 PMOS tube M33 is less than 1 / 2 of the current consumed by the bias tube 16 NMOS tube M25; the 14th PMOS tube M32 is connected to the 18th NMOS tube M27 to form a current path; the 12th PMOS tube M30 and the 13th PMOS tube M31 are output tubes, the output tube 12th PMOS tube M30 mirrors the current of the tenth PMOS tube M28 of the feedback device as the output current, and the output tube 13th PMOS tube M31 mirrors the current of the eleventh PMOS tube M29 of the feedback device as the output current; the gain of the second variable gain amplifier module 13 can be determined according to the resistance value of the first output load R11 or the resistance value of the second output load R12, and the gain of the second variable gain amplifier module 13 can be the ratio of the resistance value of the first output load R11 to the equivalent resistance value of the second adjustable resistor array 130, therefore, the gain of the second variable gain amplifier module 13 can be adjusted by adjusting the resistance value of the second adjustable resistor array 130.

[0062] In another embodiment of the present application, the second adjustable resistor array 130 may include a plurality of impedance branches connected in parallel, the first common end of the plurality of impedance branches is the first end of the second adjustable resistor array 130, the second common end of the plurality of impedance branches is the second end of the second adjustable resistor array 130, and each impedance branch includes at least one impedance device and a switch device connected in series with the impedance device. The sum of the resistance values ​​of the impedance devices in different impedance branches is different. By controlling the on or off of the switch devices in each impedance branch, the second adjustable resistor array 130 presents different resistance values, thereby realizing the adjustable gain of the second variable gain amplifier module 13.

[0063] In practical applications, the above-mentioned switching device may be a switching tube, and the switching tube may be a triode or a MOS tube, etc., which is not limited here.

[0064] It should be noted that the specific structure of the second adjustable resistor array 130 is the same as the specific structure of the first adjustable resistor array 1110 , so the above description of the specific structure of the first adjustable resistor array 1110 may be referred to and will not be repeated here.

[0065] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A variable gain amplifier circuit, comprising a first variable gain amplifier module and a driving buffer module connected in sequence, characterized in that: The driving buffer module includes: a fully differential amplifier, a first feedback resistor, a second feedback resistor, a first compensation capacitor and a second compensation capacitor; The two input ends of the first variable gain amplifier module are used to receive differential signals, the two output ends of the first variable gain amplifier module are respectively connected to the two input ends of the fully differential amplifier, the first feedback resistor is connected between the first input end and the first output end of the fully differential amplifier, the second feedback resistor is connected between the second input end and the second output end of the fully differential amplifier, the first compensation capacitor is connected in parallel with the first feedback resistor, and the second compensation capacitor is connected in parallel with the second feedback resistor; The first variable gain amplification module includes a transconductance amplification unit and a common mode feedback unit; The first input end of the transconductance amplification unit is the first input end of the first variable gain amplification module, the second input end of the transconductance amplification unit is the second input end of the first variable gain amplification module, the first output end of the transconductance amplification unit is connected with the first input end of the common mode feedback unit as the first output end of the first variable gain amplification module, the second output end of the transconductance amplification unit is connected with the second input end of the common mode feedback unit as the second output end of the first variable gain amplification module, and the feedback end of the common mode feedback unit is connected with the feedback end of the transconductance amplification unit; The transconductance amplification unit includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a third compensation capacitor and a first adjustable resistor array; The gate of the first NMOS tube is the first input end of the transconductance amplifying unit, the gate of the second NMOS tube is the second input end of the transconductance amplifying unit, the source of the first NMOS tube is connected to the first end of the first adjustable resistor array, the drain of the first PMOS tube and the drain of the third NMOS tube, the drain of the first NMOS tube is connected to the gate of the first PMOS tube, the gate of the third PMOS tube, the first end of the third compensation capacitor and the drain of the sixth PMOS tube; the source of the second NMOS tube is connected to the second end of the first adjustable resistor array, the drain of the second PMOS tube and the drain of the fourth NMOS tube, the drain of the second NMOS tube is connected to the gate of the second PMOS tube, the gate of the fourth PMOS tube, the second end of the third compensation capacitor and the drain of the seventh PMOS tube; the gate of the third NMOS tube, the gate of the fourth NMOS tube and the gate of the fifth NMOS tube are connected to the first power supply for providing a bias voltage; the third NMOS tube The source of the S tube, the source of the fourth NMOS tube, the source of the fifth NMOS tube, the source of the sixth NMOS tube and the source of the seventh NMOS tube are connected to the ground; the drain of the fifth NMOS tube is connected to the drain of the fifth PMOS tube, the gate of the fifth PMOS tube, the gate of the sixth PMOS tube and the gate of the seventh PMOS tube; the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, the source of the fourth PMOS tube, the source of the fifth PMOS tube, the source of the sixth PMOS tube and the source of the seventh PMOS tube are connected to a second power supply for providing a working power supply; the drain of the third PMOS tube and the drain of the sixth NMOS tube are connected to the first output end of the transconductance amplification unit; the drain of the fourth PMOS tube and the drain of the seventh NMOS tube are connected to the second output end of the transconductance amplification unit; the gate of the sixth NMOS tube and the gate of the seventh NMOS tube are connected to the feedback end of the transconductance amplification unit; The variable gain amplifier circuit is used to perform differential amplification processing on the received differential signal according to a preset gain and then output it; wherein the preset gain is adjustable; the preset gain is determined according to the ratio of the resistance value of the first feedback resistor to the resistance value of the source negative feedback resistor in the first variable gain amplifier module; or, the preset gain is determined according to the ratio of the resistance value of the second feedback resistor to the resistance value of the source negative feedback resistor; the first adjustable resistor array is the source negative feedback resistor.

2. The variable gain amplifier circuit according to claim 1, characterized in that: The first feedback resistor and the second feedback resistor are both adjustable resistors.

3. The variable gain amplifier circuit according to claim 1, characterized in that: The first adjustable resistor array includes multiple impedance branches connected in parallel; the first common end of the multiple impedance branches is the first end of the first adjustable resistor array, and the second common end of the multiple impedance branches is the second end of the first adjustable resistor array; each of the impedance branches includes at least one impedance device and a switching device connected in series with the impedance device, and the sum of the resistance values ​​of the impedance devices in different impedance branches is different.

4. The variable gain amplifier circuit according to claim 1, characterized in that: The common mode feedback unit includes: an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, an eighth PMOS tube, a ninth PMOS tube, a zero adjustment resistor and a fourth compensation capacitor; The gate of the eighth NMOS tube is the second input terminal of the common-mode feedback unit, the gate of the ninth NMOS tube is the first input terminal of the common-mode feedback unit, the source of the eighth NMOS tube is connected to the drain of the tenth NMOS tube and the source of the twelfth NMOS tube, the drain of the eighth NMOS tube is connected to the drain of the ninth NMOS tube, the drain of the eighth PMOS tube, the gate of the eighth PMOS tube and the gate of the ninth PMOS tube, the source of the ninth NMOS tube is connected to the drain of the eleventh NMOS tube and the source of the thirteenth NMOS tube, the gate of the tenth NMOS tube is connected to the gate of the eleventh NMOS tube The first power supply for providing a bias voltage is connected to the first power supply, the source of the tenth NMOS tube, the source of the eleventh NMOS tube and the negative electrode of the fourth compensation capacitor are connected to the ground, the source of the eighth PMOS tube and the source of the ninth PMOS tube are connected to the second power supply for providing an operating voltage, the drain of the ninth PMOS tube, the drain of the twelfth NMOS tube, the drain of the thirteenth NMOS tube and the first end of the zero adjustment resistor are connected to serve as the feedback end of the common-mode feedback unit, the second end of the zero adjustment resistor is connected to the positive electrode of the fourth compensation capacitor, and the gate of the twelfth NMOS tube and the gate of the thirteenth NMOS tube are connected to the third power supply for providing a reference voltage.

5. The variable gain amplifier circuit according to any one of claims 1 to 4, characterized in that: The variable gain amplification circuit further includes at least one second variable gain amplification module arranged at the front end of the first variable gain amplification module, and the gain of the second variable gain amplification module is adjustable.

6. The variable gain amplifier circuit according to claim 5, characterized in that: The second variable gain amplifier module includes: a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a second adjustable resistor array, a first output load and a second output load; The gate of the fourteenth NMOS tube is the first input end of the second variable gain amplifier module, the gate of the fifteenth NMOS tube is the second input end of the second variable gain amplifier module, the source of the fourteenth NMOS tube is connected to the first end of the second adjustable resistor array, the drain of the tenth PMOS tube and the drain of the sixteenth NMOS tube, the drain of the fourteenth NMOS tube is connected to the gate of the tenth PMOS tube, the gate of the twelfth PMOS tube and the drain of the fifteenth PMOS tube; the source of the fifteenth NMOS tube is connected to the second end of the second adjustable resistor array, the drain of the eleventh PMOS tube and the drain of the seventeenth NMOS tube, the drain of the fifteenth NMOS tube is connected to the gate of the eleventh PMOS tube, the gate of the thirteenth PMOS tube and the drain of the sixteenth PMOS tube; the gate of the sixteenth NMOS tube, the gate of the seventeenth NMOS tube and the gate of the eighteenth NMOS tube are connected to the first electrode for providing a bias voltage. source; the source of the sixteenth NMOS tube, the source of the seventeenth NMOS tube, the source of the eighteenth NMOS tube, the second end of the first output load and the second end of the second output load are connected to the ground; the drain of the eighteenth NMOS tube is connected to the drain of the fourteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube and the gate of the sixteenth PMOS tube; the source of the tenth PMOS tube, the source of the eleventh PMOS tube, the source of the twelfth PMOS tube, the source of the thirteenth PMOS tube, the source of the fourteenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube are connected to a second power supply for providing a working power supply; the drain of the twelfth PMOS tube and the first end of the first output load are connected together as the first output end of the second variable gain amplifier module; the drain of the thirteenth PMOS tube and the first end of the second output load are connected together as the second output end of the second variable gain amplifier module.

7. The variable gain amplifier circuit according to claim 6, characterized in that: The second adjustable resistor array includes multiple impedance branches connected in parallel; the first common end of the multiple impedance branches is the first end of the second adjustable resistor array, and the second common end of the multiple impedance branches is the second end of the second adjustable resistor array; each of the impedance branches includes at least one impedance device and a switching device connected in series with the impedance device, and the sum of the resistance values ​​of the impedance devices in different impedance branches is different.

8. The variable gain amplifier circuit according to claim 3 or 7, characterized in that: The switch device is a triode or a MOS tube.

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