Method for biasing differential pair transistors and corresponding integrated circuit

Abstract

Embodiments of the present disclosure relate to a method for biasing a differential pair of transistors and a corresponding integrated circuit. The integrated circuit includes at least one differential pair of transistors, a bias current generator configured to generate a bias current at a bias node coupled to a source terminal of each transistor in the differential pair through a corresponding resistive element, and a compensation current generator configured to generate a compensation current in one of two resistive elements to compensate for a difference between the actual values ​​of the threshold voltages of the transistors in the differential pair.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French application No. 1906167, filed on June 11, 2019, which is incorporated herein by reference. Technical Field

[0003] Embodiments and implementations relate to integrated circuits, and in particular to integrated circuits including differential pairs of MOS transistors. Background Art

[0004] Integrated comparator and amplifier devices typically include a differential pair of MOS transistors that are biased by a bias current. The respective conduction of the transistors, controlled by respective input signals, allows the difference in input voltages to be compared or amplified.

[0005] In a comparator, the transistors must respond in the same way to ensure that the comparison is accurate. Therefore, the threshold voltages of the transistors in a differential pair must be equal. In practice, due to manufacturing accidents, the actual threshold voltages of the transistors will show systematic variations between them.

[0006] Additionally, hysteresis is added to the control of the differential pairs in order to avoid unwanted comparisons caused by noise.

[0007] In an amplifier, shifts between threshold voltages can result in significant differences between input and output (for example, in a follower or in an op amp in programmable gain mode); therefore, the difference between threshold voltages must be as small as possible.

[0008] Conventional techniques for compensating for shifts between threshold voltages involve varying the resistance value of a resistive element coupled between the source of each transistor in the pair and a bias node at which the bias current is drawn.

[0009] Additionally, conventional techniques for introducing a hysteresis offset involve adjusting the conduction of transistors by connecting multiple identical transistors in parallel, the coupling of which is controlled by the same number of switches.

[0010] In order to reduce the size of the structure providing hysteresis, French patent application FR1854562 proposes compensating for the shift in threshold voltage and hysteresis by controlling and calibrating a controllable resistive element coupled to a bias node.

[0011] However, compensation is achieved by passing the bias current through the resistive element and is therefore dependent on the behavior of the bias current. In particular, a current is typically provided that exhibits a temperature variation complementary to that of the bias current so that the compensation for the offset remains constant.

[0012] Furthermore, the smaller the increments in which the controllable resistor element can be adjusted, the larger the area occupied by the resistor element and the higher the parasitic capacitance introduced by the regulator switches.

[0013] Additionally, the possible compensation amplitude is larger, the larger the difference between the source voltage of the transistor and the bias node.

[0014] The above disadvantages adversely affect the performance of the differential pair in terms of input voltage dynamics, especially when transitioning from an n-type differential pair to a p-type differential pair (and vice versa), and exist regardless of the adjusted compensation value.

[0015] It is desirable to overcome these shortcomings. Summary of the Invention

[0016] According to implementations and embodiments, an independently adjustable temperature-stabilized structure is proposed with low capacitance and a small voltage difference on the bias nodes of a differential pair for compensating for shifts in the threshold voltage values ​​of the pair of transistors and introducing hysteresis.

[0017] According to one aspect, a method for biasing at least one differential pair of transistors in an integrated circuit is provided, the method comprising the following operations:

[0018] generating a bias current at a bias node coupled to a source terminal of each transistor in the differential pair through a corresponding resistive element;

[0019] A compensation current is generated in one of the two resistance elements to compensate for a difference between actual values ​​of the threshold voltages of the differential pair transistors.

[0020] Thus, unlike conventional methods in which a bias current allows compensation for differences in actual threshold voltages, a compensation current is generated so as to be dedicated to compensating for the difference via one of the two resistance elements.

[0021] Therefore, the intensity of the compensation current allows the compensation to be adjusted, rather than the resistance value of the resistor element. Thus, the disadvantages of the controllable resistor elements described above are avoided. Of course, the two resistor elements have equal resistance values. The resistor element generating the compensation current is naturally selected based on the offset to be compensated.

[0022] According to one implementation, the method further includes the operation of generating a hysteresis current in one of the two resistive elements, the operation being controlled by a hysteresis control signal to introduce a hysteresis offset between actual values ​​of threshold voltages of transistors of the differential pair of transistors.

[0023] In other words, a hysteresis current is generated so as to be dedicated to introducing a hysteresis effect into the command for the differential pair transistors and similarly allows avoiding the structural constraints of the variable resistance element.

[0024] The resistive element conducting the hysteresis current is a resistive element advantageously coupled to the source of the transistor in a stable state according to the polarity of the differential input terminal and according to the conductivity type (n or p) of the transistors of the differential pair.

[0025] According to one implementation, the operation of generating the hysteresis current includes: in response to a hysteresis control signal, the operation of electrically coupling a hysteresis current injection branch and a hysteresis current extraction branch to each terminal of the resistive element, respectively, the operation of injecting the hysteresis current into the hysteresis current injection branch, and the operation of extracting the hysteresis current from the hysteresis current extraction branch.

[0026] In this way, the hysteresis current used to generate the hysteresis voltage across the terminals of the resistive element is well controlled and does not interfere with the bias current.

[0027] For example, the operation of generating the hysteresis current includes the operation of transmitting the hysteresis current through the hysteresis current injection and extraction branches using corresponding current mirror circuits.

[0028] Thus, for example, the generation of current may be advantageously adjusted in small increments and using structures that introduce parasitic capacitances without the conduction terminals of the differential pair transistors being affected by the parasitic capacitances and thus without the performance of the pair being affected.

[0029] Thus, the operation of generating the hysteresis current may generate the hysteresis current at a strength controlled by a hysteresis control signal.For example, the hysteresis control signal is a digital signal that includes commands for setting both the hysteresis and the offset value in small increments.

[0030] According to one implementation, the operation of generating the compensation current includes: an operation of injecting the compensation current into a compensation current injection branch and an operation of extracting the compensation current from a compensation current extraction branch, wherein the compensation current injection branch and the compensation current extraction branch are respectively coupled to the terminals of one of the two resistance elements.

[0031] For example, during the production of the differential pair transistors, the strength of the compensation current is selected and one or the other of the two resistance elements is selected depending on the resistance values ​​of the resistance elements and depending on the difference between the actual values ​​of the threshold voltages of the differential pair transistors, and the compensation current injection branch and the compensation current extraction branch are coupled to the terminals of one or the other of the two resistance elements.

[0032] For example, the operation of generating the compensation current includes the operation of transmitting the compensation current through the compensation current injection branch and the compensation current extraction branch using a corresponding current mirror circuit.

[0033] Similarly, the generation of the compensation current can be adjusted, for example, in small increments, without being affected by parasitic capacitances to the conduction terminals of the differential pair transistors.

[0034] According to one implementation, the hysteresis current and / or the compensation current are transmitted using a corresponding current mirror circuit based on a reference current generated upstream of the corresponding current mirror circuit, and the method further includes adjusting the strength of the reference current in order to adjust the strength of the hysteresis current and / or adjust the strength of the compensation current.

[0035] This implementation makes it possible to benefit from additional parameters, which in particular allow configuring a varying fineness of control of the hysteresis current intensity and / or a varying fineness of selection of the compensation current intensity.

[0036] According to another aspect, an integrated circuit is provided, comprising: at least one differential pair of transistors; a bias current generator configured to generate a bias current on a bias node coupled to a source terminal of each transistor of the differential pair through a corresponding resistive element; and a compensation current generator configured to generate a compensation current in one of two resistive elements so as to compensate for a difference between actual values ​​of threshold voltages of the differential pair transistors.

[0037] According to an embodiment, the integrated circuit further comprises a hysteresis current generator configured to generate a hysteresis current in one of the two resistive elements in response to a hysteresis control signal so as to introduce a hysteresis offset into actual values ​​of threshold voltages of transistors of the differential pair of transistors.

[0038] According to one embodiment, the hysteresis current generator is configured to electrically couple a hysteresis current injection branch and a hysteresis current extraction branch to each terminal of the resistive element, respectively, in response to a hysteresis control signal, and to inject a hysteresis current into the hysteresis current injection branch and extract a hysteresis current from the hysteresis current extraction branch.

[0039] According to one embodiment, the hysteresis current generator comprises current mirror circuits configured to transfer the hysteresis current through the hysteresis current injection and extraction branches.

[0040] According to one embodiment, the hysteresis current generator is configured to generate the hysteresis current with a strength controlled by a hysteresis control signal.

[0041] According to one embodiment, the compensation current generator includes a compensation current injection branch and a compensation current extraction branch, which are respectively coupled to the terminals of one of the two resistance elements and are configured to inject the compensation current into the compensation current injection branch and extract the compensation current from the compensation current extraction branch.

[0042] According to one embodiment, the strength of the compensation current and the one of the two resistance elements are selected depending on the resistance values ​​of the resistance elements and depending on the difference between the actual values ​​of the threshold voltages of the differential pair transistors, and the compensation current injection branch and the compensation current extraction branch are coupled to the terminals of the one of the two resistance elements.

[0043] According to one embodiment, the compensation current generator comprises respective current mirror circuits configured to transmit the compensation current through the compensation current injection branch and the compensation current extraction branch.

[0044] According to one embodiment, the respective current mirror circuit is configured to transmit the hysteresis current and / or the compensation current based on a reference current generated by a reference current generator coupled upstream of the respective current mirror circuit, the reference current generator being configured to generate the reference current with a strength selected to adjust the strength of the hysteresis current and / or to adjust the strength of the compensation current.

[0045] The integrated circuit may include an amplifier or a comparator incorporating the at least one differential pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Other advantages and features of the present invention will become apparent upon review of the detailed description of embodiments and implementations and the accompanying drawings, in which:

[0047] Figure 1 One embodiment of the present invention is illustrated;

[0048] Figure 2 One embodiment of the present invention is illustrated;

[0049] Figure 3 One embodiment of the present invention is shown.

[0050] Figure 1 An exemplary integrated circuit CI is shown, comprising an amplifier AMP incorporating a differential pair of transistors NP, NM. DETAILED DESCRIPTION

[0051] Each transistor NP, NM of the differential pair is controlled by a corresponding input signal INP, INM on its gate.Transistor NP is located at the positive input terminal INP, and transistor NM is located at the negative input terminal INM.

[0052] The sources of the differential pair transistors NP, NM are connected to the bias node Nd via respective resistance elements R1, R2. The respective resistance elements R1, R2 have the same resistance value.

[0053] The drains of transistors NP, NM each form a respective output of the differential pair.

[0054] The integrated circuit CI includes a bias current generator GIdiff configured to generate a bias current 2*Idiff applied to a bias node Nd.

[0055] Therefore, the transistors NP and NM are biased in a balanced manner and each channel has the same differential current Idiff. The output voltage on the drain of the transistors varies according to the conduction of the corresponding transistors NP and NM and according to the input signals INP and INM.

[0056] In order for the differential output signal to accurately represent the difference between the input signals, it is important for both transistors NP and NM of the differential pair to function in the same way. However, during the production of integrated circuits, the characteristics of the transistors (particularly the threshold voltage) may vary slightly due to unpredictable physical accidents.

[0057] The integrated circuit CI comprises a compensation current generator GItrim configured to generate and direct a compensation current Cd*Itrim into one of the two resistive elements R1 , R2 in order to compensate for a difference between actual values ​​of the threshold voltages of the differential pair of transistors NP, NM.

[0058] The first injection switch S1inj allows the compensation current injection branch Binj to be connected to the resistive element R1 on the source side of the transistor NP at the positive input terminal INP.

[0059] The second injection switch S2inj allows the compensation current injection branch Binj to be connected to the resistive element R2 at the source side of the transistor NM of the negative input terminal INM.

[0060] The compensation current extraction branch Bext is connected to the other terminal of one or the other of the resistance elements R1 or R2, ie to the bias node Nd. The extraction switch Sext allows the extraction branch Next to be disconnected if compensation is not required.

[0061] The compensation current generator GItrim is configured to inject the compensation current Cd*Itrim into the compensation current injection branch Binj and extract the compensation current Cd*Itrim from the compensation current extraction branch Bext.

[0062] Thus, as required, a path for guiding the compensation current Cd*Itrim is formed across the terminals of one of the two resistance elements R1 , R2 , and the guiding of the compensation current Cd*Itrim has no influence on the dynamics of the bias current 2*Idiff.

[0063] Furthermore, if, for example, the transistor NP of the positive input terminal INP exhibits a threshold voltage slightly lower than the threshold voltage of the transistor NM of the negative input terminal INM, the compensation current Cd*Itrim is directed into the resistive element R1 coupled to the transistor NP via the closed first injection switch S1inj and the closed extraction switch Sext.

[0064] A voltage Cd*Itrim*R1 is generated across the terminals of resistor R1 and increases the source voltage of transistor NP by the same value. Thus, a slightly higher input signal Cd*Itrim*R1 on the positive input INP will control transistor NP as if its threshold voltage is slightly higher (i.e. compared to the expected value).

[0065] The equation governing this equilibrium is as follows:

[0066] INP–Vgsp–(Cd*Itrim+Idiff)*R=INM–Vgsm–Idiff*R;

[0067] Wherein, INP and INM are the voltages of the corresponding inputs, Vgsp is the gate-source voltage of transistor NP, Vgsm is the gate-source voltage of transistor NM, Cd*Itrim is the compensation current, Idiff is the differential current, and R is the resistance value of the resistor elements R1 and R2;

[0068] And, for the same input voltage INP=INM,

[0069] Vgsm=Vgsp+Cd*Itrim*R.

[0070] Wherein, Cd is an integer code that can be controlled, and Itrim is a fixed basic compensation current. In order to compensate for the potential offset between the threshold voltages of transistors NP and NM, there is a voltage increment equal to Itrim*R.

[0071] Therefore, the magnitude of the intensity of the basic compensation current Itrim can be set according to the resistance value R so as to have increments of larger or smaller magnitudes.

[0072] For example, to have a 1 mV increment, a current Itrim of 1 μA is generated when R=1 kΩ, or a current Itrim of 10 μA is generated when R=100 Ω. The code Cd makes it possible to calibrate the threshold voltage compensation to Cd*1 mV according to the difference between the actual values ​​of the threshold voltages of the differential pair transistors NP, NM to be compensated.

[0073] Of course, the resistance value R of the resistance elements R1 , R2 may be different from the above example, and the increment Itrim*R may also be chosen differently.

[0074] Before producing the differential pair transistors NP, NM, the magnitude value of the basic current Itrim and the resistance value R are selected.

[0075] As far as the code Cd and the injection switches to be closed are concerned, they are selected during a phase of characterizing the components at the time of production of the integrated circuit according to the differences between the threshold voltage values ​​of the transistors NP, NM obtained at the time of production.

[0076] In the examples described herein, the compensation current generator GIltrim comprises a controllable current generator DAC. For example, the controllable current generator DAC can receive a digital command Cdnum that parameterizes the gain on the reference current Iref so that the compensation current Cd*Itrim is delivered with a controlled intensity.

[0077] The reference current Iref is generated by the current mirror circuit MIR and the reference current generator upstream of the compensation current generator GItrim.

[0078] The current mirror circuit MIR is configured to transmit the compensation current Cd*Itrim through the compensation current injection branch and the compensation current extraction branch Binj, Bext respectively.

[0079] The function of the current mirror circuit MIR is to isolate parasitic capacitance that may be introduced into the circuit of the differential pair transistors NP and NM by the controllable current generator DAC.

[0080] A switch S is connected to the output of the controllable current generator DAC in order to disconnect this current generator DAC from the current mirror MIR when no compensation is configured.

[0081] Figure 2 An exemplary integrated circuit CI is illustrated, comprising a comparator device CMP incorporating a differential pair of transistors NP, NM.

[0082] The circuit of the comparator CMP includes a reference Figure 1 The circuit of the operational amplifier AMP is described. The same components carry the same reference numerals and will not be described again in detail.

[0083] In addition to the compensation current generator GIltim, the comparator CMP further includes a hysteresis current generator GIhyst.

[0084] The hysteresis current generator GIhyst is configured to generate a hysteresis current Cdh*Ihyst in a resistive element R1 coupled to the source of the transistor NP in a stable state depending on the polarity of the differential input terminals INP, INM and depending on the n or p conductivity type of the differential pair transistors.

[0085] In other words, the transistors for the n-type transistor pair are coupled to the positive input terminal INP, and the transistors for the p-type transistor pair are coupled to the negative input terminal INM.

[0086] Therefore, the hysteresis current Cdh*Ihyst introduces a hysteresis offset into the actual value of the threshold voltages of the transistors in the differential pair of transistors NP, NM.

[0087] The hysteresis current generator GIhyst is configured to be controlled by a hysteresis command Cmdh. The hysteresis command is typically issued from an output terminal (not shown) of the comparator CMP, which indicates a stable state of the comparison.

[0088] Furthermore, in a manner similar to the injection-extraction of the compensation current Cd*Itrim, the hysteresis current generator GIhyst is configured to electrically couple a hysteresis current injection branch Bhinj and a hysteresis current extraction branch Bhext to each terminal of the resistive element R1 .

[0089] The hysteresis command Cmdh controls the switch Shinj on the hysteresis current injection branch Bhinj and the switch Shext on the hysteresis current extraction branch Bhext.

[0090] Therefore, the hysteresis current Cdh*Ihyst can be injected into the hysteresis current injection branch Bhinj, and the hysteresis current Cdh*Ihyst can be extracted from the hysteresis current extraction branch Bhext.

[0091] In this way, a hysteresis offset voltage equal to Cdh*Ihyst*R1 is generated across the terminals of the resistive element R1 .

[0092] As with the generation of the compensation current Cd*Itrim, the hysteresis current generator GIhyst includes a controllable current generator DAC capable of receiving a digital command Cdnum which parameters the gain of the reference current Iref generated upstream of the current mirror circuit MIR and the hysteresis current generator so that the hysteresis current Cdh*Ihyst is delivered with the desired strength.

[0093] The corresponding current mirror circuit MIR is also configured to transmit the hysteresis current Cdh*Ihyst through the hysteresis current injection branch Bhinj and the hysteresis current extraction branch Bhext.

[0094] A switch Sh is connected to the output of the controllable current generator DAC in order to disconnect this current generator DAC from the current mirror MIR when no hysteresis is required.

[0095] Where Cdh is an integer code that can be controlled, and Ihyst is a fixed basic hysteresis current. In order to introduce hysteresis into the input voltage of the differential pair INP, INM, there is a voltage increment equal to Ihyst*R.

[0096] Therefore, the magnitude of the basic hysteresis current Ihyst can also be set according to the resistance value R so as to have larger or smaller increments, thereby adjusting the hysteresis offset.

[0097] For example, to have a hysteresis increment of 10 mV, a current Ihyst of 10 μA is generated when R=1 kΩ, or a current Ihyst of 100 μA is generated when R=100 Ω. Therefore, the code Cdh can parameterize the hysteresis voltage as Cdh*10 mV.

[0098] For example, a digital command Cdhnum is included in the hysteresis control signal Cmdh so that the value of the hysteresis voltage can be parameterized for use.

[0099] Furthermore, the reference current generator generating the reference current Iref may be configured to generate the reference current Iref at a strength selected, for example, during design of the integrated circuit CI or possibly according to a command during use of the integrated circuit.

[0100] Assuming that the generation of the compensation current Cd*Itrim and the hysteresis current Cdh*Ihyst each causes a gain applied to the reference current Iref, the intensity of the reference current Iref is selected so that the increment for controlling the hysteresis current intensity can be adjusted in particular and the increment for selecting the compensation current intensity can be adjusted.

[0101] Figure 3 The above reference Figure 2 The comparator CMP of the exemplary integrated circuit CI is described, the comparator comprising a second differential pair of transistors PP, PM.

[0102] The above reference Figure 2 The first differential pair of transistors NP, NM are described as exhibiting n-type conductivity, while the second differential pair of transistors PP, PM are described as exhibiting p-type conductivity.

[0103] In the second differential pair PP, PM, the compensation current generator GIltrim is arranged in a symmetrical form to the layout in the first differential pair NP, NM.

[0104] Therefore, the compensation current generator GItrim includes a compensation current injection branch Binj and a compensation current extraction branch Bext, which are coupled to the terminals of one of the two resistor elements R1 and R2 via corresponding switches S1ext and S2ext, respectively. The compensation current Cd*Itrim is injected into the compensation current injection branch Binj and extracted from the compensation current extraction branch Bext.

[0105] However, in the second differential pair PP, PM, switches S1ext, S2ext are positioned on the compensation current extraction branch Bext, which couple the compensation current injection-extraction path Binj, Bext to one or the other of the two resistance elements R1, R2 on the source side of the corresponding transistors PP, PM.

[0106] The compensation current injection branch Binj is also coupled to the bias node Nd via the injection switch Sinj.

[0107] Similarly, in the second differential pair PP, PM, the hysteresis current generator GIhyst is configured in a symmetrical form to the layout in the first differential pair NP, NM.

[0108] Therefore, the hysteresis current generator GIhyst is configured to electrically couple the hysteresis current injection branch Bhinj and the hysteresis current extraction branch Bhext to each terminal of the resistance element R1 through corresponding switches Shinj, Shext in response to the hysteresis control signal Cmdh.

[0109] Therefore, the hysteresis current Cdh*Ihyst can be injected into the hysteresis current injection branch Bhinj and the hysteresis current Cdh*Ihyst can be extracted from the hysteresis current extraction branch Bhext.

[0110] As described above, the hysteresis current Cdh*Ihyst is generated in the resistance element R2 coupled to the source of the transistor PM in the stable state (ie, the transistor coupled to the negative input terminal INM of the second differential pair transistor, the conductivity type of which is the p-type).

[0111] The above reference Figure 2 The described current mirror MIR can advantageously be shared for the compensation current and the hysteresis current of the two differential pairs.

[0112] The above reference Figures 1 to 3The described exemplary integrated circuit CI advantageously makes it possible to compensate for threshold voltage offsets between transistors of a differential pair and, if applicable, to introduce a hysteresis offset into the input of a comparator.

[0113] In the above exemplary integrated circuit, the voltage between the source of the transistor and the bias node is minimized, and particularly due to the limited number of switches connected to the differential pair, the parasitic capacitance is also minimized.

[0114] Furthermore, the compensation and the hysteresis do not depend on the bias current and can therefore be optimally configured, for example with respect to temperature variations and in small increments, and can furthermore be adjusted by generating a reference current Iref.

Claims

1. A method for biasing at least one differential pair of transistors in an integrated circuit, the method comprising: generating a bias current at a bias node coupled to a source terminal of each transistor in the at least one differential pair through a respective one of two resistive elements; as well as A compensation current is generated in a first resistance element of the two resistance elements in order to compensate for a difference between actual values ​​of the threshold voltages of the transistors in the at least one differential pair.

2. The method according to claim 1, further comprising: A hysteresis current is generated in a second of the two resistive elements using a hysteresis control signal to introduce a hysteresis offset between the actual values ​​of the threshold voltages of the transistors in the at least one differential pair of transistors.

3. The method according to claim 2, wherein: The first resistance element and the second resistance element are the same resistance element.

4. The method according to claim 2, wherein: Generating the hysteresis current includes: in response to the hysteresis control signal: electrically coupling a hysteresis current injection branch and a hysteresis current extraction branch to each terminal of the second resistive element; injecting the hysteresis current into the hysteresis current injection branch; and The hysteresis current is extracted from the hysteresis current extraction branch.

5. The method according to claim 4, wherein Generating the hysteresis current includes: using a corresponding current mirror circuit to transmit the hysteresis current through the hysteresis current injection branch and the hysteresis current extraction branch.

6. The method according to claim 5, further comprising: transmitting the hysteresis current using the corresponding current mirror circuit based on a reference current generated upstream of the corresponding current mirror circuit; as well as The intensity of the reference current is adjusted to adjust the intensity of the hysteresis current.

7. The method according to claim 2, wherein: Generating the hysteresis current includes generating the hysteresis current at a strength controlled by the hysteresis control signal.

8. The method according to claim 1, wherein Generating the compensation current includes: injecting the compensation current into the compensation current injection branch; and The compensation current is extracted from a compensation current extraction branch, and the compensation current injection branch and the compensation current extraction branch are respectively coupled to terminals of the first of the two resistance elements.

9. The method according to claim 8, wherein Generating the compensation current includes: using a corresponding current mirror circuit to transmit the compensation current through the compensation current injection branch and the compensation current extraction branch.

10. The method according to claim 9, further comprising: transmitting the compensation current using the corresponding current mirror circuit based on a reference current generated upstream of the corresponding current mirror circuit; as well as The intensity of the reference current is adjusted so as to adjust the intensity of the compensation current.

11. The method according to claim 10, wherein: During the manufacturing of the at least one differential pair transistor, the strength of the compensation current and the first resistance element of the two resistance elements are selected according to the resistance values ​​of the two resistance elements and according to the difference between the actual values ​​of the threshold voltages of the transistors of the at least one differential pair, and the compensation current injection branch and the compensation current extraction branch are coupled to the terminals of the first resistance element of the two resistance elements.

12. An integrated circuit comprising: at least one differential pair transistor; a bias current generator configured to generate a bias current at a bias node coupled to a source terminal of each transistor in the at least one differential pair through a corresponding one of the two resistive elements; as well as A compensation current generator is configured to generate a compensation current in a first resistance element of the two resistance elements so as to compensate for a difference between actual values ​​of threshold voltages of the transistors in the at least one differential pair.

13. The integrated circuit of claim 12, further comprising: A hysteresis current generator is configured to generate a hysteresis current in a second of the two resistive elements in response to a hysteresis control signal so as to introduce a hysteresis offset into the actual value of the threshold voltage of the transistor in the at least one differential pair transistor.

14. The integrated circuit according to claim 13, wherein: The first resistance element and the second resistance element are the same resistance element.

15. The integrated circuit of claim 13, wherein: The hysteresis current generator is configured to electrically couple a hysteresis current injection branch and a hysteresis current extraction branch to each terminal of the second resistive element, respectively, in response to the hysteresis control signal, and inject the hysteresis current into the hysteresis current injection branch and extract the hysteresis current from the hysteresis current extraction branch.

16. The integrated circuit of claim 15, wherein: The hysteretic current generator includes a respective current mirror circuit configured to transfer the hysteretic current through the hysteretic current injection branch and the hysteretic current extraction branch.

17. The integrated circuit of claim 16, wherein: The corresponding current mirror circuit is configured to transmit the hysteresis current based on a reference current generated by a reference current generator, which is coupled upstream of the corresponding current mirror circuit, wherein the reference current generator is configured to generate the reference current with a certain strength, and the certain strength is selected to adjust the strength of the hysteresis current.

18. The integrated circuit of claim 13, wherein: The hysteresis current generator is configured to generate the hysteresis current at a strength controlled by the hysteresis control signal.

19. The integrated circuit of claim 12, wherein: The compensation current generator includes a compensation current injection branch and a compensation current extraction branch, wherein the compensation current injection branch and the compensation current extraction branch are respectively coupled to the terminals of the first of the two resistance elements, and are configured to inject the compensation current into the compensation current injection branch and extract the compensation current from the compensation current extraction branch.

20. The integrated circuit of claim 19, wherein: The compensation current generator includes a corresponding current mirror circuit configured to transmit the compensation current through the compensation current injection branch and the compensation current extraction branch.

21. The integrated circuit of claim 20, wherein: The corresponding current mirror circuit is configured to transmit the compensation current based on a reference current generated by a reference current generator, which is coupled upstream of the corresponding current mirror circuit, wherein the reference current generator is configured to generate the reference current with a certain strength, and the certain strength is selected to adjust the strength of the compensation current.

22. The integrated circuit of claim 21, wherein: The strength of the compensation current and the first of the two resistance elements are selected according to the resistance values ​​of the two resistance elements and according to the difference between the actual values ​​of the threshold voltages of the transistors in the at least one differential pair, and the compensation current injection branch and the compensation current extraction branch are coupled to the terminals of the first of the two resistance elements.

23. The integrated circuit of claim 12, further comprising an amplifier incorporated into the at least one differential pair.

24. The integrated circuit of claim 12, further comprising a comparator incorporated into the at least one differential pair.

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