Phase-locked loop (PLL) circuit containing a voltage-controlled oscillator (VCO) with reduced gain

Abstract

A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency dependent on a control voltage. A current dependent on an amplitude of the VCO circuit is generated. The generated current tracks a temperature behavior of an oscillator within the VCO circuit to some extent. The oscillator is driven by a sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase locked loop (PLL).

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 859,269, filed June 10, 2019, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments relate generally to phase-locked loop (PLL) circuits, and in particular to reducing the gain of a voltage controlled oscillator (VCO) within a PLL circuit. BACKGROUND

[0004] Referring to Figure 1 , a conventional analog phase-locked loop (PLL) circuit 10 includes a phase / frequency detector (PFD) circuit 12, a charge pump circuit 14, a loop filter circuit 16, an oscillator circuit 18 (e.g., of the voltage controlled oscillator (VCO) or current controlled oscillator (CCO) type), and a frequency divider circuit (loop divider) 20. The PFD circuit 12 measures the phase difference between an input signal (in) and a feedback signal (fbk). The PFD circuit 12 generates an error signal (err) proportional to the measured phase difference. The charge pump circuit 14 generates an output current (i) proportional to the error signal. The charge pump output current is input to the loop filter circuit 16, and the loop filter circuit outputs a corresponding control voltage (v) that is applied to a control input of the VCO circuit 18. The frequency of an output signal (out) generated by the VCO circuit 18 depends on the control voltage output from the loop filter circuit 16. The frequency divider circuit 20 receives the output signal and generates the feedback signal (fbk).

[0005] It will be noted that in one embodiment, the frequency divider circuit 20 can be omitted, and the feedback signal (fbk) can comprise the output signal (out) generated by the VCO circuit 18. In this case, the frequency of the output signal (out) will equal the frequency of the input signal (in). For example, when the frequency divider circuit 20 implements a division factor of D, the frequency of the output signal (out) will equal D times the frequency of the input signal (in). In either case, the PLL operates to lock the phase of the output signal to the phase of the input signal.

[0006] It is desirable to reduce the gain of the VCO circuit 18 in order to allow higher currents in the charge pump circuit 14, and to reduce the noise contributed by the loop filter circuit 16. Alternatively, the charge pump current is held constant, and the resistance of the loop filter 16 is increased (by the same factor) as the capacitance of the loop filter capacitor is reduced, to support noise and circuit area reduction. Referring now to Figure 2which shows a block diagram of the VCO circuit 18, which includes a first current (il) within the oscillator that is constant, and a second current (i2) within the oscillator that is controlled by a control voltage (v). As an example, the first current (il) is generated by a constant current source 30, and the second current (i2) is generated by a voltage-to-current (V2I) converter circuit 32 that is responsive to the control voltage (v). The first and second currents are summed at a current summing node 34 to generate a control current (icnt) that is applied to a ring oscillator circuit 36 that generates an output signal (out) having a frequency that is controlled by the amplitude of the control current (icnt).

[0007] Typically, the PLL loop must have sufficient gain to cover the temperature profile of the oscillator circuit 18 and the high frequency effects in the PLL clock frequency. However, there is a problem in that the constant current source 30 has its own variation with temperature. A typical solution is to use a trial-based (open loop) control to force the first current (il) to track the temperature profile of the oscillator. This solution heavily relies on the technology and maturity of the computer-aided design (CAD) models. It would be advantageous if there were a more effective solution. SUMMARY

[0008] The amplitude of the VCO circuit tracks variations in process, voltage, and temperature (PVT) as well as the oscillation frequency. The current that is dependent on the VCO circuit amplitude will then track the temperature behavior of the oscillator to some extent. This current is applied to the ring oscillator circuit that generates the output signal together with a control current that is dependent on the control voltage of the PLL loop.

[0009] In one embodiment, the oscillator circuit includes a first voltage-to-current converter circuit configured to convert a first voltage to a first current, a second voltage-to-current converter circuit configured to convert a second voltage to a second current, a third voltage-to-current converter circuit configured to convert a third voltage to a third current, a ring oscillator circuit configured to generate an output signal having a voltage amplitude and having a frequency that is controlled by a sum of the first current and the second current, a first amplifier circuit configured to generate a voltage that is applied as both the first voltage and the third voltage in response to a difference between a first feedback voltage and the voltage amplitude, and a first resistor across which the third current is applied to generate the first feedback voltage, wherein the first resistor has a resistance that is substantially equal to an effective resistance of the ring oscillator circuit.

[0010] In one embodiment, the oscillator circuit comprises: a first voltage-to-current converter circuit configured to convert a first voltage to a first current; a second voltage-to-current converter circuit configured to convert a second voltage to a second current; a third voltage-to-current converter circuit configured to convert a third voltage to a third current; a ring oscillator circuit configured to generate an output signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; and a calibration circuit configured to determine a voltage applied as both the first voltage and the second voltage that results in the frequency of the output signal from the ring oscillator circuit having a desired frequency.

[0011] In one embodiment, the phase-locked loop circuit comprises: a controlled oscillator having an input configured to receive an oscillation control voltage and an output configured to generate an oscillation signal at a frequency set by the oscillation control voltage; and a loop circuit having a first input that receives the oscillation signal, a second input that receives a reference signal, and an output that generates the oscillation control voltage in dependence on a difference between the oscillation signal and the reference signal. The controlled oscillator comprises: a first voltage-to-current converter circuit configured to convert a current control voltage to a first current; a second voltage-to-current converter circuit configured to convert the oscillation control voltage to a second current; a third voltage-to-current converter circuit configured to convert the current control voltage to a third current; a ring oscillator circuit configured to generate the oscillation signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; a first amplifier circuit configured to generate the current control voltage in response to a difference between a first feedback voltage and the voltage amplitude; and a first resistor across which the third current is applied to generate the first feedback voltage, wherein the first resistor has a resistance substantially equal to an effective resistance of the ring oscillator circuit.

[0012] In one embodiment, the oscillator circuit comprises: a first voltage-to-current converter circuit configured to convert a first voltage to a first current; a second voltage-to-current converter circuit configured to convert a second voltage to a second current; a ring oscillator circuit configured to generate an output signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; wherein the first current is dependent on the voltage amplitude and tracks a temperature behavior of the ring oscillator circuit. BRIEF DESCRIPTION OF DRAWINGS

[0013] For a better understanding of the embodiments, reference will now be made, purely by way of example, to the accompanying drawings in which:

[0014] Figure 1 is a block diagram of a conventional analog phase-locked loop (PLL) circuit;

[0015] Figure 2 is a block diagram of a conventional analog phase-locked loop (PLL) circuit; Figure 1a block diagram of a VCO circuit for use in a PLL circuit of the type shown in

[0016] Figure 3 is a block diagram of a VCO circuit for use in a PLL circuit of the type shown in Figure 1

[0017] Figure 4 Bode plots relating to the operation of a PLL circuit having a VCO circuit of the type shown in Figure 3 DETAILED DESCRIPTION

[0018] Reference is now made to Figure 3 , Figure 3 a block diagram of a VCO circuit 18’ for use in a PLL circuit of the type shown in Figure 1 For example, the VCO circuit 18’ can be used in place of the VCO circuit 18 shown in Figure 1 to provide improved performance of the PLL circuit. Alternatively, the VCO circuit 18’ can be used in place of other prior art VCO circuits as needed in desired circuit applications requiring the generation of a clock signal having a controlled frequency.

[0019] The VCO circuit 18’ includes a first voltage-to-current (V2I) converter circuit 30’ configured to generate a first current (il) in response to (i.e., proportional to) a first control voltage (Vflt), and a second voltage-to-current (V2I) converter circuit 32 configured to generate a second current (i2) in response to (i.e., proportional to) a second control voltage (v). In the context of the PLL circuit implementation as shown in Figure 1 The second control voltage (v) is the control voltage (v) generated by the loop filter circuit 16 for setting the amplitude of the variable current (i2) for the VCO circuit 18’, and the first control voltage (Vflt) is the voltage for setting the amplitude of the constant current (il) for the VCO circuit 18’. The first and second currents are summed at a current summing node 34 to generate a control current (icnt) that is applied to a ring oscillator circuit 36 that generates an output signal (out) having a desired frequency and amplitude.

[0020] ​​In response to a first logic state of the first control signal C1, the first switch circuit 100 is actuated to the switch closed position to selectively connect the control voltage inputs of the first and second voltage-to-current (V2I) converter circuits 30' and 32 to each other such that the first control voltage (Vflt) and the second control voltage (v) have equal voltages. The first control signal C1 is in the first logic state to close the first switch circuit 100 during a calibration mode of operation of the VCO circuit 18', during which the VCO circuit 18' is decoupled from the PLL circuit loop. Conversely, the first control signal C1 is in the second logic state to open the first switch circuit 100 during a normal mode of operation of the VCO circuit 18', during which the VCO circuit 18' is coupled to the PLL circuit loop. The first control signal C1 accordingly assumes the role of the master control signal for VCO circuit 18' calibration.

[0021] The third voltage-to-current (V2I) converter circuit 102 receives a bias voltage (vbi as) and generates a third current (i3) proportional to the bias voltage. The third current (i3) is applied across a first digitally controlled resistor Rd1 to generate a first feedback voltage (Vd1). The differential amplifier circuit 106 generates the bias voltage (vbi as) as an amplified difference between the first feedback voltage (Vd1) and a select voltage (vsel). The select voltage (vsel) is output by a voltage multiplexing circuit 110 that receives both an amplitude voltage (vampl) and a reference voltage (vref). The voltage multiplexing circuit 110 selects between the amplitude voltage (vampl) and the reference voltage (vref) in response to a second control signal C2. The voltage multiplexing circuit 110 outputs the amplitude voltage (vampl) as the select voltage (vsel) in response to a first logic state of the second control signal C2, and conversely, the voltage multiplexing circuit 110 outputs the reference voltage (vref) as the select voltage (vsel) in response to a second logic state of the second control signal C2. The resistance of the first digitally controlled resistor Rd1 is selected in response to a first digital resistance control signal (Rd1ctrl).

[0022] A low pass filter (LPF) circuit 114 filters the bias voltage (vbias) to generate a first control voltage (Vflt). During normal mode of operation of the VCO circuit 18', the LPF circuit 114 is enabled for operation in response to the second logic state of the first control signal C1. In response to the first logic state of the first control signal C1, the LPF circuit 114 is bypassed so that the unfiltered bias voltage (vbias) is applied as the first control voltage (Vflt) during the calibration mode of operation of the VCO circuit 18', as previously described, the first logic state of the first control signal C1 causes the first switch circuit 100 to selectively connect the first and second voltages to the control voltage input of the current (V2I) converter circuit 30' and 32.

[0023] The fourth voltage-to-current (V2I) converter circuit 118 also receives the bias voltage (vbias) and generates a fourth current (i4) proportional thereto. The second switch circuit 120, actuated to the closed position in response to the first logic state of the third control signal C3, selectively applies the fourth current (i4) across the second digitally controlled resistor Rd2 to generate a second feedback voltage (Vd2). In response to the application of the control current (icnt), the ring oscillator circuit 36 produces an output signal (out) and the amplitude voltage (vampl) corresponds to the maximum amplitude of the output signal (out). The differential amplifier circuit 122, as a voltage comparator, generates a difference voltage (vdif) as an amplified difference between the second feedback voltage (Vd2) and the amplitude voltage (vampl). The analog-to-digital converter (ADC) circuit 126 converts the analog difference voltage (vdif) to a multi-bit second digital resistance control signal (Rd2ctrl). In response to the first logic state of the third control signal C3, the differential amplifier circuit 122 and the ADC circuit 126 are enabled for operation (and conversely, in response to the second logic state of the third control signal C3, the differential amplifier circuit 122 and the ADC circuit 126 are disabled). In response to the second digital resistance control signal (Rd2ctrl), the resistance of the second digitally controlled resistor Rd2 is selected. The third switch circuit 130, actuated to the closed position in response to the second logic state of the third control signal C3 (i.e., the logical inverse of the signal C3, C3b), bypasses the second digitally controlled resistor Rd2 and connects the second feedback voltage (Vd2) to ground.

[0024] The multi-bit digital multiplexer circuit 140 has a first input configured to receive a second digital resistance control signal (Rd2ctrl) and a second input configured to receive a calibration digital resistance control signal (Calctrl). Responsive to the second control signal C2, the multi-bit digital multiplexer circuit 140 selects between the second digital resistance control signal (Rd2ctrl) and the calibration digital resistance control signal (Calctrl). Responsive to a first logic state of the second control signal C2, the multi-bit digital multiplexer circuit 140 outputs the second digital resistance control signal (Rd2ctrl) as the first digital resistance control signal (Rd1ctrl), and conversely, responsive to a second logic state of the second control signal C2, the multi-bit digital multiplexer circuit 140 outputs the calibration digital resistance control signal (Calctrl) as the first digital resistance control signal (Rd1ctrl).

[0025] The calibration digital resistance control signal (Calctrl) is generated by the digital calibration logic circuit 144 responsive to the output signal (out) from the ring oscillator circuit 36, the input signal (in) to the PLL circuit, and a division factor D of the divider circuit 20 of the PLL circuit. The digital calibration logic circuit 144 is enabled for operation responsive to the fourth control signal C4.

[0026] The control circuit 148 generates the control signals C1, C2, C3, and C4 to control the following operations:

[0027] To begin the calibration process, the first control signal C1 is set in the first logic state to actuate the switch 100 and selectively connect the first and second voltages to the control voltage inputs of the current (V2I) converter circuits 30' and 32 to equalize the first control voltage (Vflt) and the second control voltage (v). As noted above, this places the VCO circuit 18' in the calibration mode of operation in which the LPF circuit 114 is bypassed so that v = vflt = vbias and the VCO circuit 18' is effectively disconnected from (i.e., not controlled by) the PLL circuit loop, although it should be noted that the input signal (in) to the PLL circuit loop and the loop divider value D are being received by the digital calibration logic 144. Additionally, the second control signal C2 is set in the second logic state so that the voltage multiplexing circuit 110 outputs the reference voltage (vref) as the select voltage (vsel) applied to one input of the differential amplifier circuit 106 and also so that the multi-bit digital multiplexer circuit 140 outputs the calibration digital resistance control signal (Calctrl) generated by the digital calibration logic 144 as the first digital resistance control signal (Rd1ctrl). Furthermore, the fourth control signal C4 is asserted to enable operation of the digital calibration logic circuit 144 to generate the calibration digital resistance control signal (Calctrl). Moreover, the third control signal C3 is set in the second logic state so that the differential amplifier circuit 122 and the ADC circuit 126 are disabled, the switch circuit 120 is opened and the switch circuit 130 is closed.

[0028] With this configuration, a first (frequency) phase of the calibration mode of operation is then performed. A first current (il) is generated in response to the voltage v = vflt and a second current (i2) is also generated in response to the voltage vflt. Thus, the ring oscillator circuit 36 generates an output signal (out) having a frequency controlled by the bias voltage vbias (since v = vflt = vbias). A third current (i3) is also generated by the third voltage-to-current generator 102 in response to the bias voltage vbias. Due to the relative sizing of the voltage-to-current converters 30', 32 and 102 operating in response to the applied bias voltage vbias, the following relative current conditions apply: i3 = icnt = il + i2. The application of the third current (i3) across the first digitally controlled resistor Rd1 generates a first feedback voltage (Vd1) for application to the second input of the differential amplifier circuit 106. The bias voltage vbias is generated in response to the voltage difference between the first feedback voltage (Vd1) and the select voltage (vsel).

[0029] In response to the generated bias voltage (vbias), a control current (icnt) is output, and a ring oscillator generates an output signal (out) with an oscillation frequency dependent on vbias. Digital calibration logic circuitry 144 operates to determine the frequency difference (i.e., out / D-in) between the output signal (out) divided by a factor D and the input signal (in), where it should be noted that the PLL circuit loop is disconnected in this mode. While the first feedback Vd1 is held fixed at Vsel through the feedback loop of amplifier 106, using negative feedback, digital calibration logic circuitry 144 controls the value of the calibration digital resistor control signal (Calctrl), and thus correspondingly controls the value of the first digital resistor control signal (Rd1ctrl) to change the corresponding amplitude of the resistance and current i3 (=Vd1 / Rd1) of the first digital control resistor Rd1. This change results in a corresponding change in the bias voltage (vbias), thereby driving the frequency of the output signal (out) divided by D to be substantially equal to the frequency of the input signal (in) (e.g., within a first threshold frequency). When these operating conditions are met, the first phase of the calibration operation mode ends. It should be noted that at the end of the first (frequency) phase of the calibration operation mode, the resistance of the first digital control resistor, set by the value of the first digital resistor control signal (Rd1ctrl), sets the value of the bias voltage (vbias) necessary to achieve the desired operating frequency of the ring oscillator 36.

[0030] At this point in time, the fourth control signal C4 is deasserted to disable the operation of the digital calibration logic circuit 144. This is an efficient way to save power during additional calibration operations and during normal PLL mode after the calibration process is completed. Then, the third control signal C3 is set in the first logic state, enabling the differential amplifier circuit 122 and the ADC circuit 126, closing the switch circuit 120, and opening the switch circuit 130.

[0031] With this configuration, a second (amplitude) phase of the calibration operating mode is then performed. The bias voltage (vbias) continues to be generated at an amplitude set by the resistance of the first digitally controlled resistor Rd1, and in response to the bias voltage (vbias), the voltage-to-current converter 118 generates a fourth current (i4) such that i4 = i3 = icnt. The application of the fourth current (i4) across the second digitally controlled resistor Rd2 generates a second feedback voltage (Vd2) for application to the second input of the differential amplifier circuit 122. The first input of the differential amplifier circuit 122 receives an amplitude voltage (vampl) for the output signal (out) generated by the ring oscillator circuit 36. A differential voltage Vdif is generated as the voltage difference between the second feedback voltage (Vd2) and the amplitude voltage (vampl). This difference is converted by the ADC circuit 126 into a second digital resistance control signal (Rd2ctrl) that controls the resistance of the second digitally controlled resistor Rd2.

[0032] Using negative feedback, the value of the second digital resistance control signal (Rd2ctrl) is modulated to change the resistance of the second digitally controlled resistor Rd2 and drive the amplitude of the voltage (vd2) towards the amplitude voltage (vampl). When the voltage (vd2) is substantially equal to the amplitude voltage (vampl) (e.g. within a second threshold value of the voltage), the second (amplitude) phase of the calibration operating mode ends. It will be noted that, since the amplitude voltage (vampl) is proportional to the current (i4), the resistance of the second digitally controlled resistor Rd2 set by the value of the second digital resistance control signal (Rd2ctrl) at the end of the second (amplitude) phase of the calibration operating mode is substantially equal to the effective resistance of the ring oscillator circuit 36. In this context, substantially equal resistance values are taken to mean that the values are equal within the resolution capability of the second digitally controlled resistor Rd2 (e.g. equal to each other within the resistance step limitations of the programmability of the second digitally controlled resistor Rd2).

[0033] The third control signal C3 is then returned to the second logic state by disabling the differential amplifier circuit 122 and the ADC circuit 126, opening the switch circuit 120 and closing the switch circuit 130 in order to save power consumption. Now, the second control signal C2 is changed to the first logic state so that the voltage multiplexing circuit 110 instead outputs the amplitude voltage (vampl) as the selection voltage (vsel) applied to the first input of the differential amplifier circuit 106 and the multi-bit digital multiplexer circuit 140 instead outputs the second digital resistance control signal (Rd2ctrl) as the first digital resistance control signal (Rd1ctrl). This effectively results in a change of the resistance of the first digitally controlled resistor Rd1 from the resistance set by the value of the first digital resistance control signal (Rd1ctrl) at the end of the first (frequency) phase of the calibration operating mode to the resistance set by the value of the second digital resistance control signal (Rd2ctrl) at the end of the second (amplitude) phase of the calibration operating mode.

[0034] When the first control signal C1 returns to the second logic state deactivating the switch 100, the calibration operating mode of the VCO circuit 18’ is completed, disconnecting the control voltage inputs of the first and second voltage-to-current (V2I) converter circuits 30’ and 32 and removing the bypass of the LPF circuit 114. With the LPF circuit 114 now activated (enabled), the cut-off frequency of the loop for generating the voltage (vflt) controlling the first voltage-to-current (V2I) converter circuit 30’ is reduced. The disconnection of the control voltage inputs of the first and second voltage-to-current (V2I) converter circuits 30’ and 32 enables the first voltage-to-current (V2I) converter circuit 30’ to generate the first current (il) from a self-tracking loop dependent on the resistance of the first digitally controlled resistor Rd1 and the amplitude of the ring oscillator circuit (vampl) and also enables the second voltage-to-current (V2I) converter circuit 32 to generate the second current (i2) from the control voltage (v) for the PLL circuit loop.

[0035] Because the first current (il) is dependent on the amplitude of the output signal (out) generated by the ring oscillator circuit 36, the first current (il) will track the frequency of the oscillation and to some extent also the temperature behaviour of the oscillator circuit 36. By using the second phase of the calibration operating mode to determine the effective resistance of the ring oscillator circuit 36 for replication using the controlled resistance of the second digitally controlled resistor Rd2 in the third current (i3) path, the process spread of the path for the first current (il) is reduced. As a result, a lower VCO gain can be obtained without difficulties in covering the oscillator temperature distribution and the high frequency effects of the PLL clock frequency.

[0036] In normal mode of operation, the self-tracking loop is part of the PLL path and adds an extra pole (at w p ') and an extra zero (at w z '). The resulting loop transfer function is given by the following equation:

[0037] where

[0038] w′ p = 1 / c * R LPF * C LPF ;

[0039] w′ z = 1 / R LPF * C LPF ; and

[0040] w z = 1 / R LF * C L ;

[0041] where: K VCO is the VCO gain; I CP is the current of the charge pump circuit 14; c is a constant greater than 1 ; R LPF is the resistance of the resistor within the LPF circuit 114; c LPF is the capacitance of the capacitor within the LPF circuit 114; C L is the capacitance of the primary (i.e. large) integrated capacitor of the PLL loop filter 16; R LF is the resistance of the PLL loop filter 16, and N is the division factor D of the loop divider 20.

[0042] A Bode plot of the amplitude and phase for the solution using the VCO circuit 18' after calibration is complete is shown in Figure 4 . At reference numeral 160, Figure 4 it is also shown how the Bode plot would be different if the self-tracking loop was not operating.

[0043] With respect to PLL stability, the unity gain bandwidth (UGB) of the PLL using the VCO circuit 18' is given by the following equation:

[0044]

[0045] It will be noted accordingly that the system has the same UGB as the PLL that does not include the self-tracking loop. When placed substantially before the UGB frequency, the extra pole and extra zero introduced by the self-tracking loop will have no impact on the PLL stability.

[0046] The PLL with the VCO circuit 18' has many advantages with respect to known solutions, including: a) with this technique the VCO gain can be further reduced by a factor of 4 (1 / 8 vs. 1 / 2) compared to a conventional hybrid PLL, with the size ratio of the voltage-to-current converters 32 and 30' being 1:7; and b) there is no need for the use of a digital-to-analog converter in the voltage-to-current converter circuit (as a result, the occupied circuit area is saved and the performance parameters of the VCO, such as the power supply rejection ratio (PSRR), are improved). With respect to advantage a), it ensures that: i) the loop filter resistance is increased by a factor of 4 and the loop filter capacitance is reduced by a factor of 4 without affecting the loop dynamics (as a result, there is a reduction in the occupied circuit area and in the loop filter resistor noise with a factor of 1 / 4 in the power spectral density (PSD) comparison); and ii) the charge pump current is increased by a factor of four without affecting other parameters (as a result, there is a reduction in the charge pump noise with a factor of 1 / 4 in the PSD comparison, a reduction in the loop filter resistor noise with a factor of 1 / 16 in the PSD comparison, and an improvement in the charge pump linearity, which is very important with respect to the operation of fractional-N PLLs).

[0047] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, based on the study of the drawings, the disclosure, and the appended claims.

Claims

1. An oscillator circuit, comprising: a first voltage-to-current converter circuit configured to convert a first voltage to a first current; a second voltage-to-current converter circuit configured to convert a second voltage to a second current; a third voltage-to-current converter circuit configured to convert a third voltage to a third current; a ring oscillator circuit configured to generate an output signal, the output signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; a first amplifier circuit configured to generate a voltage applied as both the first voltage and the third voltage in response to a difference between a first feedback voltage and the voltage amplitude; and a first resistor across which the third current is applied to generate the first feedback voltage, wherein the first resistor has a resistance substantially equal to an effective resistance of the ring oscillator circuit, wherein when the voltage applied as both the first voltage and the third voltage is fixed by the first amplifier circuit, a change in the second voltage results in a corresponding change in the frequency of the output signal.

2. The circuit of claim 1, further comprising: a low pass filter configured to filter the first voltage.

3. An oscillator circuit, comprising: a first voltage-to-current converter circuit configured to convert a first voltage to a first current; a second voltage-to-current converter circuit configured to convert a second voltage to a second current; a third voltage-to-current converter circuit configured to convert a third voltage to a third current; a ring oscillator circuit configured to generate an output signal, the output signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; a first amplifier circuit configured to generate a voltage applied as both the first voltage and the third voltage in response to a difference between a first feedback voltage and the voltage amplitude; a first resistor across which the third current is applied to generate the first feedback voltage, wherein the first resistor has a resistance substantially equal to an effective resistance of the ring oscillator circuit; and a calibration circuit configured to determine the effective resistance of the ring oscillator circuit; and wherein the first resistor is a variable resistor, and wherein the resistance of the first resistor is set by the calibration circuit in response to the determined effective resistance of the ring oscillator circuit.

4. The circuit of claim 3, wherein the calibration circuit comprises: a fourth voltage-to-current converter circuit configured to convert a fourth voltage to a fourth current, wherein the fourth voltage is a voltage applied as both the first voltage and the second voltage to cause the ring oscillator circuit to generate the output signal having a desired frequency; a second amplifier circuit configured to generate a difference voltage in response to a difference between a second feedback voltage and the voltage amplitude; and a second resistor across which the fourth current is applied to generate the second feedback voltage, wherein the second resistor has a resistance substantially equal to the effective resistance of the ring oscillator circuit. a second resistor, the fourth current being applied across the second resistor to generate the second feedback voltage, wherein the second resistor has a variable resistance modulated by an output of the second amplifier circuit to drive the difference voltage towards zero.

5. The circuit of claim 4, wherein the modulated variable resistance is substantially equal to the effective resistance of the ring oscillator circuit.

6. The circuit of claim 5, wherein the calibration circuit further comprises a circuit configured to set the resistance of the first resistor equal to the modulated variable resistance of the second resistor.

7. The circuit of claim 4, wherein the calibration circuit further comprises a circuit configured to determine the voltage applied as both the first voltage and the second voltage that causes the ring oscillator circuit to generate the output signal having the desired frequency.

8. The circuit of claim 4, wherein the desired frequency is a phase-locked loop (PLL) frequency.

9. An oscillator circuit, comprising: a first voltage-to-current converter circuit having a first input configured to receive a first voltage and a first output configured to generate a first current; a second voltage-to-current converter circuit having a second input configured to receive a second voltage and a second output configured to generate a second current; a ring oscillator circuit configured to generate an output signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; a switch configured to selectively connect the first input to the second input; and a calibration circuit configured to actuate the switch to connect the first input and the second input and to determine a voltage applied to the first input and the second input as both the first voltage and the second voltage that causes a frequency of the output signal from the ring oscillator circuit to have a desired frequency.

10. The circuit of claim 9, wherein the calibration circuit comprises: a third voltage-to-current converter circuit having a third input configured to receive a third voltage and a third output configured to generate a third current; a first amplifier circuit configured to generate the voltage in response to a difference between a first feedback voltage and a reference voltage; and a first resistor, the third current being applied across the first resistor to generate the first feedback voltage, wherein the first resistor has a variable resistance modulated in response to a frequency difference between the frequency of the output signal and the desired frequency to drive the frequency difference towards zero.

11. The circuit of claim 10, wherein the calibration circuit further comprises a circuit configured to compare the frequency of the output signal to the desired frequency and to generate a resistance control signal in response to the comparison, the resistance control signal controlling a setting of the variable resistance of the first resistor. ​ ​ 12. The circuit of claim 10, wherein the calibration circuit further comprises: a fourth voltage-to-current converter circuit configured to convert a fourth voltage to a fourth current, wherein the fourth voltage is the voltage applied as both the first voltage and the second voltage to cause the ring oscillator circuit to generate the output signal having the desired frequency; a second amplifier circuit configured to generate a difference voltage in response to a difference between a second feedback voltage and the voltage amplitude; and a second resistor across which the fourth current is applied to generate the second feedback voltage, wherein the second resistor has a variable resistance modulated by an output of the second amplifier circuit to drive the difference voltage towards zero.

13. The circuit of claim 12, wherein the modulated variable resistance substantially equals an effective resistance of the ring oscillator circuit.

14. The circuit of claim 13, wherein the calibration circuit further comprises a circuit configured to set the resistance of the first resistor to equal the modulated variable resistance of the second resistor.

15. A phase-locked loop circuit, comprising: a controlled oscillator having an input configured to receive an oscillation control voltage and configured to generate an oscillation signal at a frequency set by the oscillation control voltage; and a loop circuit having a first input to receive the oscillation signal, a second input to receive a reference signal, and an output to generate the oscillation control voltage from a difference between the oscillation signal and the reference signal; wherein the controlled oscillator comprises: a first voltage-to-current converter circuit configured to convert a current control voltage to a first current; a second voltage-to-current converter circuit configured to convert the oscillation control voltage to a second current; a third voltage-to-current converter circuit configured to convert the current control voltage to a third current; a ring oscillator circuit configured to generate the oscillation signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; a first amplifier circuit configured to generate the current control voltage in response to a difference between a first feedback voltage and the voltage amplitude; and a first resistor across which the third current is applied to generate the first feedback voltage, wherein the first resistor has a resistance substantially equal to an effective resistance of the ring oscillator circuit, wherein when the current control voltage is pinned by the first amplifier circuit, a change in the oscillation control voltage results in a corresponding change in the frequency of the oscillation signal.

16. A phase-locked loop circuit, comprising: a controlled oscillator having an input configured to receive an oscillation control voltage and configured to generate an oscillation signal at a frequency set by the oscillation control voltage; and a loop circuit having a first input to receive the oscillation signal, a second input to receive a reference signal, and an output to generate the oscillation control voltage from a difference between the oscillation signal and the reference signal; wherein the controlled oscillator comprises: a first voltage-to-current converter circuit configured to convert a current control voltage into a first current; a second voltage-to-current converter circuit configured to convert an oscillation control voltage into a second current; a third voltage-to-current converter circuit configured to convert the current control voltage into a third current; a ring oscillator circuit configured to generate the oscillation signal having a voltage amplitude and having a frequency controlled by a sum of the first current and the second current; a first amplifier circuit configured to generate the current control voltage in response to a difference between a first feedback voltage and the voltage amplitude; a first resistor across which the third current is applied to generate the first feedback voltage, wherein the first resistor has a resistance substantially equal to an effective resistance of the ring oscillator circuit; and a calibration circuit configured to determine the effective resistance of the ring oscillator circuit; and wherein the first resistor is a variable resistor, and wherein the resistance of the first resistor is set by the calibration circuit in response to the determined effective resistance of the ring oscillator circuit.

17. The phase-locked loop circuit of claim 16, wherein the calibration circuit comprises: a switch circuit configured to apply the current control voltage also as the oscillation control voltage, wherein the current control voltage is at a level that causes the frequency of the oscillation signal output by the ring oscillator circuit to be substantially equal to a desired frequency of the phase-locked loop circuit; a fourth voltage-to-current converter circuit configured to convert the current control voltage into a fourth current; a second amplifier circuit configured to generate a difference voltage in response to a difference between a second feedback voltage and the voltage amplitude; and a second resistor across which the fourth current is applied to generate the second feedback voltage, wherein the second resistor has a variable resistance modulated by an output of the second amplifier circuit to drive the difference voltage towards zero.

18. The phase-locked loop circuit of claim 17, wherein the modulated variable resistance is substantially equal to the effective resistance of the ring oscillator circuit.

19. The phase-locked loop circuit of claim 18, wherein the calibration circuit further comprises a circuit configured to set the resistance of the first resistor to be equal to the modulated variable resistance of the second resistor.

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