Information recording method and system

Abstract

The present invention provides an information recording method and system, which includes the following steps: S1: obtaining an error code and storing the error code in a first register; S2: arranging the error codes in the first register in the order of reading and storing them in a FIFO memory; S3: judging whether the second register has data; if not, executing step S4; otherwise, executing step S5; S4: storing at least one error code in the FIFO memory in the order of sequence in the second register for the host computer to read the error code; S5: starting timing, when the timing reaches the set time, clearing the second register, and returning to execute step S3. Through the present invention, the problem that the host computer cannot completely record the error code due to the inconsistent scanning cycle between the host computer and the lower computer is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an information recording method and system. Background Art

[0002] At present, "host computer + slave computer" is a commonly used control architecture for semiconductor equipment. The host computer is usually a PC (personal computer), which is responsible for the interaction between the device and other controllers, the editing / scheduling of control instructions, the human-machine interface, and the recording of device status. The slave computer is usually a PLC (Programmable Logic Controller), which is usually responsible for the direct control and status acquisition of the actuators in the device. This control architecture of "host computer + slave computer" effectively improves the reliability and control efficiency of the control system. The error code of the actuator, as an important information of the device status, plays a very important role in the status monitoring and data analysis of the device. It is usually collected by the slave computer and recorded by the host computer.

[0003] The existing lower computer stores error codes in the following way: the lower computer stores the error code in a specified register, and sends an alarm message to the upper computer when the value of the register is not zero; the upper computer reads the register regularly and displays the alarm message on the display interface. In the process of reading the error code, the upper computer refreshes the register at a cycle of seconds, while the lower computer records the error code at a cycle of milliseconds. If the error code recorded by the lower computer changes during a read refresh cycle of the upper computer, the upper computer can only record the error code at the refresh time, but cannot completely record all the error codes. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes an information recording method and system to solve the problem that all error codes cannot be completely recorded.

[0005] To achieve the purpose of the present invention, a method for recording information is provided, the method comprising the following steps:

[0006] S1: Obtain an error code and store the error code in a first register;

[0007] S2: Arrange the error codes in the first register in the order of reading and store them in the FIFO memory;

[0008] S3: Determine whether the second register has data; if not, execute step S4; otherwise, execute step S5;

[0009] S4: storing at least one error code in the FIFO memory in a sequential order into a second register, so that the host computer can read the error code;

[0010] S5: Start timing, and when the timing reaches the set time, clear the second register and return to step S3.

[0011] Preferably, before step S1, the method further includes the following steps:

[0012] S0: Set the FIFO memory data length according to the scanning cycle of the upper computer and the lower computer.

[0013] Preferably, the FIFO memory data length is:

[0014] [(scan cycle of the upper computer / scan cycle of the lower computer)+1]×n, where n is the data length of the error code.

[0015] Preferably, the set time is greater than the scanning period of the host computer.

[0016] Preferably, the step S5 further includes:

[0017] After the timing starts, an alarm message is sent to the host computer, and after the timing reaches a set time, the sending of the alarm message is stopped.

[0018] An information recording system comprises: a host computer, a slave computer and an execution mechanism;

[0019] The lower computer includes: a first register, a second register, a FIFO memory and a processor;

[0020] The processor is used to obtain an error code from the execution mechanism and store the error code in the first register;

[0021] The processor is also used to arrange the error codes in the first register in the order of reading and store them in the FIFO memory; determine whether the second register has data; if not, store at least one error code in the order of reading in the FIFO memory into the second register for the host computer to read the error code; otherwise, start timing, and when the timing reaches a set time, clear the second register, and continue to return to determine whether the second register has data.

[0022] Preferably, before acquiring the error code from the execution mechanism, the processor is further used to set the data length of the FIFO memory according to the scanning cycle of the upper computer and the lower computer.

[0023] Preferably, the FIFO memory data length is:

[0024] [(scan cycle of the upper computer / scan cycle of the lower computer)+1]×n, where n is the data length of the error code.

[0025] Preferably, the set time is greater than the scanning period of the host computer.

[0026] Preferably, it also includes: an alarm unit;

[0027] The alarm unit sends alarm information to the host computer after the processor starts timing, and stops sending alarm information to the host computer after the timing reaches a set time.

[0028] The present invention has the following beneficial effects:

[0029] The information recording method and system provided by the present invention arranges the error codes in the first register in the order of reading and stores them in the FIFO memory, then determines whether the second register has data, and when there is no data in the second register, stores at least one error code in the order of reading in the FIFO memory into the second register, so that the host computer can read the error code; when there is data in the second register, the timing starts, and when the timing reaches the set time, the second register is cleared, and the second register is returned to continue to determine whether there is data. The present invention can store the error code in the FIFO in a timely and complete manner, thereby effectively solving the problem that the host computer cannot completely record the error code due to the inconsistency of the scanning cycle between the host computer and the slave computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A first flow chart of an information recording method provided by an embodiment of the present invention;

[0031] Figure 2 A second flow chart of the information recording method provided by an embodiment of the present invention;

[0032] Figure 3 A third flow chart of the information recording method provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the structure of an information recording system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solution of the present invention, the information recording method and system provided by the present invention are described in detail below with reference to the accompanying drawings.

[0035] Embodiment 1

[0036] Figure 1FIG. 1 is a flow chart of a first information recording method provided by an embodiment of the present invention. The information recording method in this embodiment includes the following steps:

[0037] Step S1: Obtain an error code and store the error code in a first register.

[0038] Specifically, in this embodiment, after the lower computer reads the error code from the actuator, it is temporarily stored in the first register. The first register can store a single-bit error code or a multi-bit misalignment code. Further, the actuator can be an execution unit of a semiconductor device, and the execution unit can record the error code of the semiconductor device in real time. Further, the actuator and the lower computer have an interactive interface, and the lower computer communicates with the upper computer through a conventional communication method.

[0039] In the embodiment of the present invention, the lower computer can be a PLC (Programmable Logic Controller), which uses a type of programmable memory for internally storing programs, executing user-oriented instructions such as logical operations, sequential control, timing, counting and arithmetic operations, and controlling various types of machinery or production processes through digital or analog input / output. The lower computer adopts PLC, and can achieve complete recording of error codes under existing hardware conditions, only by optimizing the program, which is convenient for analyzing machine failures. When the lower computer adopts PLC, it can achieve complete recording of error codes under existing hardware conditions, only by optimizing the program, which is convenient for analyzing machine failures.

[0040] Step S2: Arrange the error codes in the first register in the order of reading and store them in the FIFO memory.

[0041] Specifically, a FIFO (First Input First Output) memory is a first-in, first-out dual-port buffer, that is, the first data entering it is the first to be removed, one of the ports of the memory is the input port, and the other port is the output port of the memory.

[0042] Step S3: Determine whether the second register has data; if not, execute step S4; if yes, execute step S5.

[0043] Specifically, the host computer periodically reads the error code from the second register. The second register can store a single-bit error code or multiple-bit error codes.

[0044] Step S4: storing at least one error code in the FIFO memory in a sequential order into a second register, so that the host computer can read the error code.

[0045] Step S5: Start timing. When the timing reaches the set time, clear the second register and return to step S3.

[0046] Specifically, the set time is greater than the scanning cycle of the host computer, for example, the set time = the scanning cycle of the host computer + the first time period. Further, the first time period can be determined according to the hardware conditions of the upper and lower computers, for example, the first time period is 0.2s. For example, if the scanning cycle of the host computer is 500ms, then the set time is set to 700ms, thereby ensuring that the host computer can read the error code. Further, in the embodiment of the present invention, the scanning cycle of the host computer is the cycle of the host computer online scanning the second register.

[0047] The information recording method provided by the embodiment of the present invention arranges the error codes in the first register in the order of reading and stores them in the FIFO memory, then determines whether the second register has data, and when there is no data in the second register, stores at least one error code in the order of reading in the FIFO memory into the second register, so that the host computer can read the error code; when there is data in the second register, start timing, and when the timing reaches the set time, clear the second register, and return to continue to determine whether there is data in the second register. In the present invention, the error code can be stored in the FIFO in a timely and complete manner, thereby effectively solving the problem that the host computer cannot completely record the error code due to the inconsistency of the scanning cycle between the host computer and the lower computer.

[0048] Embodiment 2

[0049] Figure 2 FIG. 2 is a flow chart of a second method for recording information provided by an embodiment of the present invention. In this embodiment, the method for recording information includes the following steps:

[0050] Step S0: Setting the FIFO memory data length according to the scanning cycles of the upper computer and the lower computer.

[0051] Specifically, the data length of the FIFO memory is: [(scan cycle of the upper computer / scan cycle of the lower computer)+1]×n, where n is the data length of the error code.

[0052] Specifically, n is the data length of an error code. For example, if the scanning cycle of the host computer is 500 milliseconds, the scanning cycle of the PLC is 5 milliseconds, and the data length of an error code is 1 word, the required length of the FIFO queue is [(500 / 5)+1]*1=101 words.

[0053] Step S1: Obtain an error code and store the error code in a first register.

[0054] Step S2: Arrange the error codes in the first register in the order of reading and store them in the FIFO memory.

[0055] Step S3: Determine whether the second register has data; if not, execute step S4; if yes, execute step S5.

[0056] Step S4: storing at least one error code in the FIFO memory in a sequential order into a second register, so that the host computer can read the error code.

[0057] Step S5: Start timing. When the timing reaches the set time, clear the second register and return to step S3.

[0058] The information recording method provided by the embodiment of the present invention sets the data length of the FIFO memory according to the scanning cycle of the upper computer and the lower computer, thereby achieving complete preservation of error codes between the upper computer and the lower computer while ensuring that all error codes uploaded by the lower computer can be read by the upper computer.

[0059] Embodiment 3

[0060] Figure 3 FIG. 4 is a third flow chart of the information recording method provided by an embodiment of the present invention. The information recording method in this embodiment includes the following steps:

[0061] Step 100: Set the FIFO memory data length according to the scanning cycles of the upper computer and the lower computer.

[0062] Step 101: Obtain an error code and store the error code in a first register.

[0063] Step 102: Arrange the error codes in the first register in the order of reading, and store them in the FIFO memory.

[0064] Step 103: Determine whether the second register has data; if not, execute step S4; if yes, execute step S5.

[0065] Step 104: Store at least one error code in the FIFO memory in a sequential order into a second register, so that the host computer can read the error code.

[0066] Step 105: Start timing and send alarm information to the upper computer. When the timing reaches the set time, clear the second register and stop sending alarm information, and return to step S3.

[0067] The information recording method provided by the embodiment of the present invention sends an alarm message to the upper computer after starting the timing; when the alarm is generated and the delay setting time is exceeded, the data in the first register is overwritten. In this way, on the one hand, setting the timing setting time can ensure that the upper computer refreshes and records the error code, and on the other hand, by clearing the second register, it can be ensured that the upper computer can continue to extract the error code from the second register to avoid queue data overflow.

[0068] Embodiment 4

[0069] In view of the above information recording method, the present invention also provides an information recording system. Figure 4 The figure shows a structural diagram of an information recording system provided by an embodiment of the present invention. In this embodiment, the information recording system includes: a host computer, a slave computer and an execution mechanism.

[0070] The lower computer includes: a first register D0, a second register D1, a FIFO memory and a processor (not shown in the figure); the processor is used to obtain an error code from the actuator and store the error code in the first register D0; the processor is also used to arrange the error codes in the first register D0 in the order of reading, and store them in the FIFO memory, and judge whether there is data in the second register; if not, store at least one error code in the order of the FIFO memory in the second register for the upper computer to read the error code; otherwise, start timing, and when the timing reaches the set time, clear the second register, and continue to return to judge whether there is data in the second register.

[0071] In the information recording system provided by the embodiment of the present invention, after the processor arranges the error codes in the first register in the order of reading and stores them in the FIFO memory, it determines whether the second register has data. When there is no data in the second register, at least one error code in the order of reading in the FIFO memory is stored in the second register for the host computer to read the error code; when there is data in the second register, the timing is started, and when the timing reaches the set time, the second register is cleared, and the second register is returned to continue to determine whether there is data. The present invention can store the error code in the FIFO in a timely and complete manner, thereby effectively solving the problem that the host computer cannot completely record the error code due to the inconsistency of the scanning cycle between the host computer and the lower computer.

[0072] Specifically, in this embodiment, after the lower computer reads the error code from the actuator, it is temporarily stored in the first register. The upper computer periodically reads the error code from the second register. The first register and the second register can store a single-bit error code or a multi-bit misalignment code. Further, the actuator can be an execution unit of a semiconductor device, which can record the error code of the semiconductor device in real time. Further, the actuator and the lower computer have an interactive interface, and the lower computer and the upper computer communicate through a conventional communication method.

[0073] In the embodiment of the present invention, the lower computer can be a PLC (Programmable Logic Controller), which uses a type of programmable memory to store programs internally, execute user-oriented instructions such as logical operations, sequential control, timing, counting and arithmetic operations, and control various types of machinery or production processes through digital or analog input / output.

[0074] Specifically, the FIFO (First Input First Output) memory is a first-in, first-out dual-port buffer, that is, the first data to enter it is the first to be removed, one port of the memory is the input port, and the other port is the output port of the memory. The FIFO memory can store a single-bit error code or a multi-bit error code, such as Figure 4 As shown, the FIFO memory stores a 1 a 2 . . . a t error codes, where t is greater than 2. The error code at stored in the first register D0 is written into the FIFO memory and becomes the last error code of the FIFO memory. Each time, the front-end error code in the FIFO memory, such as a1, is stored in the second register D1 and becomes the error code a of the second register D1.

[0075] In this embodiment, when the lower computer adopts PLC, complete recording of error codes can be achieved by simply optimizing the program without changing the hardware conditions, which facilitates the analysis of machine failures.

[0076] Furthermore, in another embodiment of the present invention, before the processor obtains the error code from the actuator, it is also used to set the FIFO memory data length according to the scanning cycle of the upper computer and the lower computer.

[0077] Specifically, the data length of the FIFO memory is: [(scan cycle of the host computer / scan cycle of the slave computer)+1]×n, where n is the data length of the error code. Specifically, n is the data length of an error code. For example: the scan cycle of the host computer is 500 milliseconds, the scan cycle of the PLC is 5 milliseconds, and the data length of an error code is 1 word. The required length of the FIFO queue is [(500 / 5)+1]*1=101 words.

[0078] Specifically, the setting time is greater than the scanning cycle of the host computer, for example, the setting time = the scanning cycle of the host computer + the first time period. The first time period can be determined according to the hardware conditions of the upper and lower computers, for example, the first time period is 0.2s. For example, if the scanning cycle of the host computer is 500ms, then the setting time is set to 700ms, so as to ensure that the host computer can read the error code. Further, in the embodiment of the present invention, the scanning cycle of the host computer is the cycle of the host computer online scanning the second register.

[0079] In order to better prompt the host computer to read the error code, further, in another embodiment of the present invention, the information recording system also includes: an alarm unit; the alarm unit is used to send alarm information to the host computer after the processor starts timing, and stop sending alarm information to the host computer after the timing reaches a set time.

[0080] In summary, the information recording method and system provided by the present invention have the following characteristics:

[0081] 1. The error code is recorded in the queue in a timely and complete manner through the FIFO memory, which effectively solves the problem that the upper and lower computer scanning cycles are inconsistent, resulting in the upper computer being unable to completely record the error code (or other status information).

[0082] 2. The length N of the FIFO memory is determined by the host computer scanning cycle and the slave computer scanning cycle:

[0083] N=[(T 上 / T 下 )+1]×n, where T 上 is the scanning period of the host computer (i.e. the period of scanning the second register), T 下 is the scanning cycle of the lower computer, and n is the length of an error code data.

[0084] 3. Error code extraction mechanism in FIFO memory

[0085] When the alarm is generated, the delay setting time (slightly longer than the host computer scanning cycle, for example, can be set to T 上+0.2s), the data in the first register is overwritten. In this way, on the one hand, setting the timing setting time can ensure that the host computer refreshes and records the error code, and on the other hand, it can ensure that the error code continues to be extracted from the FIFO memory to avoid queue data overflow.

[0086] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An information recording method, characterized in that: The method comprises the following steps: S0: Set the FIFO memory data length according to the scanning cycle of the upper computer and the lower computer; the FIFO memory data length is: [(scan cycle of the host computer / scan cycle of the slave computer)+1]×n, where n is the data length of the error code; S1: Obtain an error code and store the error code in a first register; S2: Arrange the error codes in the first register in the order of reading and store them in the FIFO memory; S3: Determine whether the second register has data; if not, execute step S4; otherwise, execute step S5; S4: storing at least one error code in the FIFO memory in a sequential order into a second register, so that the host computer can read the error code; S5: Start timing, and when the timing reaches a set time, clear the second register and return to step S3; the set time is greater than the scanning cycle of the host computer.

2. The information recording method according to claim 1, characterized in that: The step S5 further includes: After the timing starts, an alarm message is sent to the host computer, and after the timing reaches a set time, the sending of the alarm message is stopped.

3. An information recording system, characterized in that: include: Host computer, slave computer and actuator; The lower computer includes: a first register, a second register, a FIFO memory and a processor; The processor is used to set the data length of the FIFO memory according to the scanning cycle of the host computer and the slave computer; the data length of the FIFO memory is: [(scan cycle of the host computer / scan cycle of the slave computer)+1]×n, where n is the data length of the error code; The processor is further configured to obtain an error code from the execution mechanism and store the error code into the first register; The processor is also used to arrange the error codes in the first register in the order of reading and store them in the FIFO memory; determine whether the second register has data; if not, store at least one error code in the FIFO memory in the order of reading into the second register for the host computer to read the error code; otherwise, start timing, and when the timing reaches a set time, clear the second register, and continue to return to determine whether the second register has data; the set time is greater than the scanning cycle of the host computer.

4. The information recording system according to claim 3, characterized in that: Also includes: Alarm unit; The alarm unit is used to send alarm information to the host computer after the processor starts timing, and stop sending alarm information to the host computer after the timing reaches a set time.

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