Semiconductor equipment

Abstract

A semiconductor device is provided herein. The semiconductor device includes: a scan input circuit configured to receive a scan input signal, a first data signal, and a scan enable signal, and in response to the scan enable signal to select either the first data signal or the scan input signal to output a first selection signal; a master latch configured to latch the first selection signal to output a first output signal; a slave latch configured to latch the first output signal to output a second output signal; a first inverter configured to invert the second output signal; and a scan output circuit configured to receive a signal output from the slave latch and an external signal to output a first scan output signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0069723, filed on June 13, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. Background Technology

[0004] With the growth of the mobile device market, such as smartphones and tablet PCs, the demand for low-power chips is increasing. Low-power chips are characterized by their ability to enable mobile devices, including those with low-power chips, to operate for extended periods using limited energy (such as the charge in a battery) with appropriate performance. It can be difficult to satisfy both appropriate performance and low power consumption.

[0005] Low-power chips capable of processing digital signals include flip-flops and latches. Flip-flops and latches serve as data storage elements. Data storage elements can be used to store states. Flip-flops and latches are electronic circuits that can store and hold one bit of information and are fundamental components of sequential logic circuits. Latches are level-sensitive data storage elements, while flip-flops are edge-sensitive data storage elements.

[0006] As the power consumption of the flip-flops and latches included in the chip increases, the power consumption of the mobile device that includes the chip may also increase. Furthermore, the operating speed of the flip-flops and latches included in the chip may affect the operating speed of the mobile device that includes the chip. Summary of the Invention

[0007] This disclosure provides a semiconductor device including a master-slave flip-flop that consumes low power and is implemented in a small area.

[0008] The technical aspects of this disclosure are not limited to those described above, and those skilled in the art should clearly understand from the following description other technical aspects of this disclosure not mentioned above.

[0009] According to one aspect of the present invention, a semiconductor device is provided, comprising: a scan input circuit configured to receive a scan input signal, a first data signal, and a scan enable signal, and to select either the first data signal or the scan input signal in response to the scan enable signal to output a first selection signal; a master latch configured to latch the first selection signal to output a first output signal; a slave latch configured to latch the first output signal to output a second output signal; a first inverter configured to invert the second output signal to output a final output signal; and a scan output circuit configured to receive a signal output from the slave latch and an external signal to output a first scan output signal.

[0010] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first scan input circuit configured to receive a scan input signal, a first data signal, and a scan enable signal, and in response to the scan enable signal to select either the first data signal or the scan input signal to output a first selection signal; a first master latch configured to latch the first selection signal to output a first output signal; a first slave latch configured to latch the first output signal to output a second output signal, wherein the first slave latch includes a first inverter that inverts the second output signal to output a third output signal; a second scan input circuit configured to receive the third output signal, the second data signal, and the scan enable signal, and in response to the scan enable signal to select either the second data signal or the third output signal to output a second selection signal; a second master latch configured to latch the second selection signal to output a fourth output signal; a second slave latch configured to latch the fourth selection signal to output a fifth output signal; and a scan output circuit configured to receive a signal output from the second slave latch and an external signal to output the first scan output signal.

[0011] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first scan input NAND gate configured to perform a NAND operation on a first scan input signal and a first scan enable signal to output a first output signal; a second scan input NAND gate configured to perform a NAND operation on an inverted first scan enable signal and a first data signal to output a second output signal; a first scan input circuit including a third scan input NAND gate configured to perform a NAND operation on the first output signal and the second output signal to output a third output signal; a first master latch configured to latch the third output signal to output a fourth output signal; a first slave latch configured to latch the fourth output signal to output a fifth output signal; a first inverter configured to invert the fifth output signal to output a first final output signal; and a first scan output circuit. The system comprises: a first scan output signal, a second scan input NAND gate, configured to receive a signal output from a first slave latch and a first external signal to output a first scan output signal; a fourth scan input NAND gate, configured to perform a NAND operation on an inverted second scan enable signal and a second data signal to output a sixth output signal; a second scan input circuit, including a fifth scan input NAND gate configured to perform a NAND operation on the first scan output signal and the sixth output signal to output a seventh output signal; a second master latch configured to latch the seventh output signal to output an eighth output signal; a second slave latch configured to latch the eighth output signal to output a ninth output signal; a second inverter configured to invert the ninth output signal to output a second final output signal; and a second scan output circuit configured to receive a signal output from a second slave latch and a second external signal to output a second scan output signal. Attached Figure Description

[0012] Exemplary embodiments of the present invention will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0014] Figure 2 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0015] Figures 3A to 3D Is included Figure 2 A circuit diagram of a tri-state inverter in a semiconductor device including a master-slave flip-flop, according to some embodiments;

[0016] Figures 4A to 4C Is included Figure 2 A circuit diagram of an inverter in a semiconductor device including a master-slave flip-flop, according to some embodiments;

[0017] Figure 5 It shows that it includes Figure 2 A circuit diagram of multiple scan output inverters in a semiconductor device including master-slave flip-flops according to some embodiments;

[0018] Figure 6 Is included Figure 2 A circuit diagram of a scan output NAND gate in a semiconductor device including a master-slave flip-flop, according to some embodiments;

[0019] Figure 7 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0020] Figure 8 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0021] Figure 9 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0022] Figure 10 Is included Figure 9 A circuit diagram of an inverter in a semiconductor device including a master-slave flip-flop, according to some embodiments;

[0023] Figure 11 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0024] Figure 12 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0025] Figure 13 Is included Figure 12 A circuit diagram of a scan-output NOR gate in a semiconductor device including a master-slave flip-flop, according to some embodiments;

[0026] Figure 14 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0027] Figure 15 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0028] Figure 16 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure;

[0029] Figure 17 This is a circuit diagram of a semiconductor device including a multi-bit master-slave flip-flop according to some embodiments of the present disclosure;

[0030] Figure 18 This is a circuit diagram of a semiconductor device including a multi-bit master-slave flip-flop according to some embodiments of the present disclosure;

[0031] Figure 19 This is a circuit diagram of a semiconductor device including a multi-bit master-slave flip-flop according to some embodiments of the present disclosure;

[0032] Figure 20 This is a circuit diagram of a semiconductor device including two master-slave flip-flops connected in series, according to some embodiments of the present disclosure;

[0033] Figure 21 This is a circuit diagram of a semiconductor device including a plurality of master-slave flip-flops connected in series, according to some embodiments of the present disclosure;

[0034] Figure 22 and Figure 23 It is a circuit diagram of a semiconductor device that includes multi-bit master-slave flip-flops connected in series;

[0035] Figure 24 This is an exemplary block diagram of an electronic system including a semiconductor device comprising a master-slave trigger, according to some embodiments of the present disclosure. Detailed Implementation

[0036] Figure 1 This is a block diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure. Figure 2 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0037] Reference Figure 1 and Figure 2 According to some embodiments, a semiconductor device including a master-slave flip-flop may include a master latch 100, a slave latch 200, a scan input circuit 300, and a scan output circuit 400.

[0038] The scan input circuit 300 may include a first inverter 312, a first scan tri-state inverter 311, and a second scan tri-state inverter 313. The scan input circuit 300 may receive a data signal D, a scan enable signal SE, and a scan input signal SI, and output the data signal D or the scan input signal SI to the first node MA in response to the scan enable signal SE via a control signal.

[0039] Specifically, when the scan enable signal SE is logic high (H), the scan input circuit 300 can output the scan input signal SI to the first node MA. That is, the first scan tri-state inverter 311, which is enabled in response to the logic high scan enable signal SE, can output the scan input signal SI to the first node MA.

[0040] Conversely, when the scan enable signal SE is logic low (L), the scan input circuit 300 can output the data signal D to the first node MA. For example, the second scan tri-state inverter 313, which is enabled in response to the logic low scan enable signal SE, can output the data signal D to the first node MA.

[0041] The scan input signal SI or data signal D output from the scan input circuit 300 to the first node MA can be the first selection signal.

[0042] Figure 2 The configuration of the scan input circuit 300 shown is illustrative, and this disclosure is not limited thereto. For example, as Figure 20 As shown, the scan input circuit 300 can be implemented using multiple transmission gates, multiplexers, or logic gates, which will be described below.

[0043] The main latch 100 may include a first input tri-state inverter 11, a first main latch tri-state inverter 12, and a second inverter 13.

[0044] The master latch 100 can store the data signal D input through the first node MA and output the data signal D to the second node SA. Specifically, the master latch 100 can output the data signal D input according to the first clock signal CK and the second clock signal CKN which is the inverse of the first clock signal CK to the second node SA.

[0045] The signal output to the second node SA can be the first output signal.

[0046] Specifically, the first input tri-state inverter 11 can receive the data signal D from the first node MA. When the first clock signal CK is logic low (L) and the second clock signal CKN is logic high (H), the first input tri-state inverter 11 can invert the data signal D to output the inverted data signal D to the second node SA. Conversely, when the first clock signal CK is logic high (H) and the second clock signal CKN is logic low (L), the first input tri-state inverter 11 can block the first master latch tri-state inverter 12 from the first node MA.

[0047] The output terminal of the first master latch tri-state inverter 12 can be connected to the output terminal of the first input tri-state inverter 11. The first master latch tri-state inverter 12 can invert the output signal provided from the second inverter 13 to output the inverted output signal to the second node SA.

[0048] Specifically, when the first clock signal CK is logic high (H) and the second clock signal CKN is logic low (L), the first master latch tri-state inverter 12 can invert the signal output from the second inverter 13 to the third node MB, so as to output the inverted signal to the second node SA. Conversely, when the first clock signal CK is logic low (L) and the second clock signal CKN is logic high (H), the first master latch tri-state inverter 12 can block the first input tri-state inverter 11 from the second node SA.

[0049] Slave latch 200 may include a second input tri-state inverter 21, a second master latch tri-state inverter 22, a third inverter 23, and a fourth inverter 32. Slave latch 200 may operate similarly to the master latch 100 described above.

[0050] Specifically, latch 200 can store the data signal D input through the second node SA and output the data signal D to the fifth node SC. Specifically, latch 200 can output the data signal D input to the second node SA in response to the first clock signal CK and the second clock signal CKN.

[0051] Specifically, the second-input tri-state inverter 21 can receive the data signal D from the second node SA. When the first clock signal CK is logic high (H) and the second clock signal CKN is logic low (L), the second-input tri-state inverter 21 can invert the data signal D to output the inverted data signal D to the fifth node SC. Conversely, when the first clock signal CK is logic low (L) and the second clock signal CKN is logic high (H), the second-input tri-state inverter 21 can block the data signal D input from the second node SA.

[0052] The second master latch tri-state inverter 22 can be connected to the output terminal of the second input tri-state inverter 21. The second master latch tri-state inverter 22 can invert the output signal provided from the third inverter 23 to output the inverted output signal to the fifth node SC.

[0053] Specifically, when the first clock signal CK is logic low (L) and the second clock signal CKN is logic high (H), the second master latch tri-state inverter 22 can invert the signal output from the third inverter 23 to output the inverted signal to the fifth node SC. Conversely, when the first clock signal CK is logic high (H) and the second clock signal CKN is logic low (L), the second master latch tri-state inverter 22 can block the second input tri-state inverter 21 from the second node SA.

[0054] A semiconductor device including a master-slave flip-flop, according to some embodiments, can receive a first clock signal CK and a second clock signal CKN. For example... Figure 2As shown, the first clock signal CK and the second clock signal CKN can be provided to a semiconductor device including a master-slave flip-flop via the fifth inverter 31. That is, for example, the first clock signal CK can be provided directly from the clock terminal without passing through a buffer circuit including multiple inverters, and the second clock signal CKN can be input as a clock signal inverted by the fifth inverter 31. The second clock signal CKN is inverted by the fourth inverter 32 in the latch 200, so that the first clock signal CK can be output.

[0055] The latch 200 can output the output signal to the fifth node SC, and the fifth inverter 41 can invert the output signal to output the final output signal Q.

[0056] A semiconductor device including a master-slave trigger according to some embodiments includes a scan output circuit 400 connected to a fifth node SC.

[0057] The scan output circuit 400 may include a first scan output inverter 51, a second scan output inverter 52, and a logic gate that performs logical operations on the input values. In a semiconductor device including master-slave flip-flops according to some embodiments, the logic gate may include a scan output NAND gate 61 that performs logical NAND operations on the input values.

[0058] The scan output circuit 400 can receive the output signal of the fifth node SC and external signals. As described above, the output signal is the signal output from the latch 200 to the fifth node SC, and the external signal may include the scan enable signal SE.

[0059] When the semiconductor device, including a master-slave flip-flop, according to some embodiments is not in scan test mode, the scan enable signal SE is logic low (L). Therefore, the inverted scan enable signal SEN is logic high (H).

[0060] The scan enable signal SE input to the scan output circuit 400 can be input to the scan output NAND gate 61 in the scan output circuit 400. Furthermore, the output signal input to the scan output circuit 400 can be input to the first scan output inverter 51, so that the inverted first output signal can be output to the sixth node SD. The first output signal can be input to the second scan output inverter 52, so that the inverted second output signal can be output to the final output node SZ.

[0061] The scan output NAND gate 61 receives the scan enable signal SE (logic low L) and the second output signal of the final output node SZ, and performs a logic NAND operation on the scan enable signal SE and the second output signal to output the scan output signal SO.

[0062] When not in scan test mode, the scan output signal SO can be fixed as logic high H due to logical NAND operations.

[0063] That is, when the scan output signal SO is fixed at logic high H without being in scan test mode, it can be determined that the semiconductor device, including the master-slave flip-flop, is operating normally.

[0064] When a semiconductor device including a master-slave flip-flop, according to some embodiments, is in scan test mode, the scan enable signal SE is logic high (H). Therefore, the inverting scan enable signal SEN is logic low (L).

[0065] In this case, the scan output NAND gate 61 receives the scan enable signal SE with logic high H and the second output signal of the final output node SZ, and performs a logic NAND operation on the scan enable signal SE and the second output to output the scan output signal SO.

[0066] In scan test mode, due to logical NAND operations, the scan output signal SO is equal to the final output signal Q.

[0067] In a semiconductor device including a master-slave flip-flop according to some embodiments, an inverted scan enable signal SEN can be input to the ground terminal of the first scan output inverter 51 and the second scan output inverter 52 of the scan output circuit 400.

[0068] When not in scan test mode, the inverting scan enable signal SEN is logic high (H), causing the first scan output inverter 51 and the second scan output inverter 52 to not operate. That is, when not in scan test mode, the number of unnecessary operations of the components in the scan output circuit 400 is reduced, thereby reducing unnecessary power consumption by semiconductor devices including master-slave flip-flops.

[0069] In scan test mode, the inverted scan enable signal SEN is logic low L, allowing the first scan output inverter 51 and the second scan output inverter 52 to operate as general inverters. That is, the output signal from latch 200 to the fifth node SC can be directly sent to the scan output NAND gate 61, and the scan output signal SO output from the scan output NAND gate 61 can be equal to the final output signal Q.

[0070] When not in scan test mode, a semiconductor device including a master-slave flip-flop, according to some embodiments, can prevent operation of the first scan output inverter 51 and the second scan output inverter 52. Furthermore, because the inverted scan enable signal SEN is input to the ground terminals of the first scan output inverter 51 and the second scan output inverter 52, the path of leakage current that may occur in the semiconductor device including the master-slave flip-flop is lengthened, thereby reducing the power consumed by the semiconductor device including the master-slave flip-flop.

[0071] In scan test mode, the first scan output inverter 51 and the second scan output inverter 52 of a semiconductor device including master-slave flip-flops according to some embodiments can operate as general inverters and have a delay as extended as that of the first scan output inverter 51 and the second scan output inverter 52. In scan test mode, a longer delay is preferred, which may require multiple buffers (or inverters). When buffers (or inverters) for delay are added outside the master-slave flip-flops, the proportion of the buffers (or inverters) occupied in the semiconductor device may increase, and unnecessary power consumption may increase. Therefore, as in the semiconductor device including master-slave flip-flops according to some embodiments, the first scan output inverter 51 and the second scan output inverter 52, serving as multiple buffers (or inverters) for delay, are embedded within the master-slave flip-flops, thereby reducing the area occupied for delay in the semiconductor device and reducing unnecessary power consumption.

[0072] Figures 3A to 3D Is included Figure 2 A circuit diagram of a tri-state inverter in a semiconductor device including a master-slave flip-flop, according to some embodiments.

[0073] First refer to Figure 3A The first input tri-state inverter 11 may include a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a second PMOS transistor MP2. The first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1, and the second PMOS transistor MP2 may be connected in series between the power supply voltage VDD and the ground voltage VSS.

[0074] The detailed operation of the first input tri-state inverter 11 has been described above, and its description will be omitted below. That is, due to the first PMOS transistor MP1 and the first NMOS transistor MN1 being selected in response to the first clock signal CK and the second clock signal CKN, the data signal D input to the first node MA can be controlled to be output to the second node SA.

[0075] Reference Figure 3BThe first main latch tri-state inverter 12 may include a third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, and a fourth PMOS transistor MP4. The third NMOS transistor MN3, the fourth NMOS transistor MN4, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 may be connected in series between the power supply voltage VDD and the ground voltage VSS.

[0076] The detailed operation of the first master latch tri-state inverter 12 has already been described above, and its description will be omitted below. That is, due to the third NMOS transistor MN3 and the third PMOS transistor MP3 being selected in response to the first clock signal CK and the second clock signal CKN, the data signal D input to the first node MA can be controlled to be output to the third node MB.

[0077] Reference Figure 3C The second input tri-state inverter 21 may include a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6 connected in series between the power supply voltage VDD and the ground voltage VSS.

[0078] In the second input tri-state inverter 21, the data signal D input to the second node SA can be controlled to be output to the fifth node SC due to the fifth NMOS transistor MN5 and the fifth PMOS transistor MP5 being selected in response to the first clock signal CK and the second clock signal CKN.

[0079] Reference Figure 3D The second main latch tri-state inverter 22 may include a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP8 connected in series between the power supply voltage VDD and the ground voltage VSS.

[0080] In the second master latch tri-state inverter 22, the data signal D input to the fourth node SB can be controlled to be output to the fifth node SC because the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are selected in response to the first clock signal CK or the second clock signal CKN.

[0081] Figures 4A to 4C Is included Figure 2 Circuit diagram of an inverter in a semiconductor device including a master-slave flip-flop, according to some embodiments.

[0082] Reference Figure 4AThe second inverter 13 can be implemented by connecting the ninth PMOS transistor MP9 to the ninth NMOS transistor MN9. The ninth PMOS transistor MP9 is selected in response to the voltage level of the second node SA to provide the power supply voltage VDD to the third node MB, and the ninth NMOS transistor MN9 is selected in response to the voltage level of the second node SA to provide the ground voltage VSS to the third node MB.

[0083] Reference Figure 4B The third inverter 23 can be implemented by connecting the tenth PMOS transistor MP10 to the tenth NMOS transistor MN10. The tenth PMOS transistor MP10 is selected in response to the voltage level of the fifth node SC to provide the power supply voltage VDD to the fourth node SB, and the tenth NMOS transistor MN10 is selected in response to the voltage level of the fifth node SC to provide the ground voltage VSS to the fourth node SB.

[0084] Reference Figure 4C The fourth inverter 32 can be implemented by connecting the eleventh PMOS transistor MP11 to the eleventh NMOS transistor MN11. The eleventh PMOS transistor MP11 is selected in response to the voltage level of the second clock signal CKN to provide the power supply voltage VDD as the first clock signal CK, and the eleventh NMOS transistor MN11 is selected in response to the voltage level of the second clock signal CKN to provide the ground voltage VSS as the first clock signal CK.

[0085] Figure 5 It shows that it includes Figure 2 The circuit diagram below illustrates a plurality of scan-output inverters in a semiconductor device including master-slave flip-flops, according to some embodiments. For reference, the basic operation and configuration of the inverters, which are repeated in the detailed description above, will be omitted in the following description.

[0086] Reference Figure 5 The first scan output inverter 51 may include a twelfth PMOS transistor MP12 and a twelfth NMOS transistor MN12. The first scan output inverter 51 can be selected in response to the voltage level of the fifth node SC, and inverts the voltage level of the fifth node SC to output the inverted voltage level to the sixth node SD. The second scan output inverter 52 may include a thirteenth PMOS transistor MP13 and a thirteenth NMOS transistor MN13. The second scan output inverter 52 can be selected in response to the voltage level of the sixth node SD, and inverts the voltage level of the sixth node SD to output the inverted voltage level to the final output node SZ.

[0087] Figure 6 Is included Figure 2A circuit diagram of a scan output NAND gate in a semiconductor device including a master-slave flip-flop, according to some embodiments.

[0088] Reference Figure 6 The source terminals of the fourteenth PMOS transistor MP14 and the fifteenth PMOS transistor MP15 are connected to the power supply voltage VDD, their drain terminals are connected to each other, and the drain terminals are connected to the drain terminal of the fourteenth NMOS transistor MN14, so that the scan output signal SO can be output. The fourteenth PMOS transistor MP14 can be turned on in response to the voltage level of the final output node SZ, and the fifteenth PMOS transistor MP15 can be turned on in response to the scan enable signal SE. The drain terminal of the fifteenth NMOS transistor MN15 is connected in series to the source terminal of the fourteenth NMOS transistor MN14. The fifteenth NMOS transistor MN15 can be turned on in response to the voltage level of the final output node SZ, and the fourteenth NMOS transistor MN14 can be turned on in response to the scan enable signal SE.

[0089] The logic operation of the NAND gate 61 when it is in scan test mode and when it is not in scan test mode is the same as the logic operation described above, so its description will be omitted below.

[0090] Figure 7 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0091] Reference Figure 7 ,and Figure 2 Unlike other latches, in the main latch 100, the output terminal of the reset NOR gate 12-1, which receives the reset signal R, can be connected to the first input tri-state inverter 11. Furthermore, the reset NOR gate 12-1 can receive a signal from the third node MB as an input. Other operations of the main latch 100 are similar to... Figure 2 Those are the same. Furthermore, with... Figure 2 Unlike latch 200, the output terminal of reset NOR gate 23-1, which receives the reset signal R, can be connected to the fourth node SB, and reset NOR gate 23-1 can receive a signal as input from the fifth node SC. Other operations of latch 200 are similar. Figure 2 The same applies to those. That is, when the reset signal R is "1", the final output signal Q can be fixed to "0".

[0092] Figure 8 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0093] Reference Figure 8 ,and Figure 2Unlike the scan output circuit 400, the scan output circuit 400 also includes a third scan output inverter 53 and a fourth scan output inverter 54. Therefore, in scan test mode, the delay time can be longer while maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q.

[0094] While maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q, the number of scan output inverters in the scan output circuit 400 is not limited to the above configuration. The scan output circuit 400 may also include 2n scan output inverters (where n is a natural number other than zero).

[0095] Other operations and configurations Figure 2 The same ones are repeated, so repeated descriptions will be omitted below.

[0096] Figure 9 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0097] Reference Figure 9 ,and Figure 2 Unlike other methods, the scan output circuit 400 receives the output signal from the fourth node SB. Specifically, according to some embodiments, the scan output circuit 400 may include a fifth scan output inverter 55. The fifth scan output inverter 55 may receive the signal output from the fourth node SB in the latch 200 and send the inverted output signal to the final output node SZ. Furthermore, the scan output NAND gate 61 may perform a logical NAND operation on the scan enable signal SE and the signal of the final output node SZ to output the scan output signal SO.

[0098] Detailed operation and Figure 2 The operation is similar, so its description will be omitted below.

[0099] Figure 10 Is included Figure 9 Circuit diagram of an inverter in a semiconductor device including a master-slave flip-flop, according to some embodiments.

[0100] Reference Figure 10 The fifth scan output inverter 55 may include a sixteenth PMOS transistor MP16 and a sixteenth NMOS transistor MN16 connected in series. The fifth scan output inverter 55 can be selected in response to the voltage level of the fourth node SB, and can invert the voltage level of the fourth node SB to output the inverted voltage level to the final output node SZ. Detailed operation is as follows... Figure 4A The operation is the same, so its description will be omitted below.

[0101] Figure 11This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0102] Reference Figure 11 ,and Figure 9 Unlike other circuits, the scan output circuit 400 may also include a sixth scan output inverter 56 and a seventh scan output inverter 57. Therefore, in scan test mode, the delay time can be longer while maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q.

[0103] While maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q, the number of scan output inverters in the scan output circuit 400 is not limited to the above configuration. The scan output circuit 400 may also include 2n+1 scan output inverters (where n is a natural number other than zero).

[0104] Other operations and configurations Figure 2 The same ones are repeated, so repeated descriptions will be omitted below.

[0105] Figure 12 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0106] Reference Figure 12 ,and Figure 2 Unlike other circuits, the logic gates of the scan output circuit 400 may include a scan output NOR gate 71 that performs a logical NOR operation on the input value.

[0107] In addition, with Figure 2 Unlike other signals, the external signal input to the scan output circuit 400 is an inverted scan enable signal SEN.

[0108] The scan output circuit 400 can receive signals output from the fifth node SC and external signals. As described above, the output signal is the signal output from the latch 200 to the fifth node SC, and the external signal may include an inverted scan enable signal SEN.

[0109] When the semiconductor device, including a master-slave flip-flop, according to some embodiments is not in scan test mode, the scan enable signal SE is logic low (L). Therefore, the inverted scan enable signal SEN is logic high (H).

[0110] The inverted scan enable signal SEN input to the scan output circuit 400 can be input to the scan output NOR gate 71 in the scan output circuit 400. Furthermore, the output signal input to the scan output circuit 400 can be input to the first scan output inverter 51, so that the inverted first output signal can be output to the sixth node SD. The first output signal can be input to the second scan output inverter 52, so that the inverted second output signal can be output to the final output node SZ.

[0111] The scan output NOR gate 71 receives the inverted scan enable signal SEN (logic high H) and the second output signal of the final output node SZ, and performs a logic NOR operation on the inverted scan enable signal SEN and the second output signal to output the scan output signal SO.

[0112] When not in scan test mode, the scan output signal SO can be fixed to logic low L due to the logic NOR operation.

[0113] That is, when the scan output signal SO is fixed at logic low L without being in scan test mode, it can be determined that the semiconductor device, including the master-slave flip-flop, is operating normally.

[0114] When a semiconductor device including a master-slave flip-flop, according to some embodiments, is in scan test mode, the scan enable signal SE is logic high (H). Therefore, the inverting scan enable signal SEN is logic low (L).

[0115] In this case, the scan output NOR gate 71 receives the inverted scan enable signal SEN (logic low L) and the second output signal of the final output node SZ, and performs a logic NOR operation on the inverted scan enable signal SEN and the second output signal to output the scan output signal SO.

[0116] In scan test mode, due to the logical NOR operation, the scan output signal SO is equal to the final output signal Q.

[0117] In a semiconductor device including a master-slave flip-flop according to some embodiments, an inverted scan enable signal SEN can be input to the ground terminal of the first scan output inverter 51 and the second scan output inverter 52 of the scan output circuit 400.

[0118] When not in scan test mode, the inverted scan enable signal SEN is logic high (H), causing the first scan output inverter 51 and the second scan output inverter 52 to not operate. That is, when not in scan test mode, the number of unnecessary operations of the components in the scan output circuit 400 is reduced, thereby reducing unnecessary power consumption by semiconductor devices including master-slave flip-flops.

[0119] In scan test mode, the inverted scan enable signal SEN is logic low L, allowing the first scan output inverter 51 and the second scan output inverter 52 to operate as general inverters. That is, the output signal from latch 200 to the third node MB can be directly sent to the scan output NOR gate 71, and the scan output signal SO output from the scan output NOR gate 71 can be equal to the final output signal Q.

[0120] When not in scan test mode, a semiconductor device including a master-slave flip-flop, according to some embodiments, can prevent operation of the first scan output inverter 51 and the second scan output inverter 52. Furthermore, because the inverted scan enable signal SEN is input to the ground terminals of the first scan output inverter 51 and the second scan output inverter 52, the path of leakage current that may occur in the semiconductor device including the master-slave flip-flop is lengthened, thereby reducing the power consumed by the semiconductor device including the master-slave flip-flop.

[0121] In scan test mode, the first scan output inverter 51 and the second scan output inverter 52 of the semiconductor device including master-slave flip-flops according to some embodiments can operate as general inverters and have a delay as extended as that of the first scan output inverter 51 and the second scan output inverter 52. In scan test mode, a longer delay is preferred, for which multiple buffers (or inverters) may be required. When buffers (or inverters) for delay are added outside the master-slave flip-flops, the proportion of the buffers (or inverters) occupied in the semiconductor device may increase, and unnecessary power consumption may increase. Therefore, as in the semiconductor device including master-slave flip-flops according to some embodiments, the first scan output inverter 51 and the second scan output inverter 52, serving as multiple buffers (or inverters) for delay, are embedded within the master-slave flip-flops, thereby reducing the area occupied for delay in the semiconductor device and reducing unnecessary power consumption.

[0122] Figure 13 Is included Figure 12 A circuit diagram of a scan-output NOR gate in a semiconductor device including a master-slave flip-flop, according to some embodiments.

[0123] Reference Figure 13 The scan output NOR gate 71 may include a seventeenth PMOS transistor MP17 and an eighteenth PMOS transistor MP18 connected in series from the power supply voltage VDD, and a seventeenth NMOS transistor MN17 and an eighteenth NMOS transistor MN18 connected in the source and drain terminals.

[0124] The drain terminal of the eighteenth PMOS transistor MP18 can be connected to the drain terminals of the seventeenth NMOS transistor MN17 and the eighteenth NMOS transistor MN18. The seventeenth PMOS transistor MP17 and the seventeenth NMOS transistor MN17 can be selected in response to the voltage level of the final output node SZ. The eighteenth PMOS transistor MP18 and the eighteenth NMOS transistor MN18 can be selected in response to the inverted scan enable signal SEN.

[0125] The drain terminal of the eighteenth PMOS transistor MP18 can output a scan output signal SO through the node connected to the drain terminals of the seventeenth NMOS transistor MN17 and the eighteenth NMOS transistor MN18.

[0126] Scan output NOR gate 71 operation and Figure 12 The above operations are the same, so their description will be omitted below.

[0127] Figure 14 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0128] Reference Figure 14 ,and Figure 12 Unlike the scan output circuit 400, the scan output circuit 400 also includes a third scan output inverter 53 and a fourth scan output inverter 54. Therefore, in scan test mode, the delay time can be longer while maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q.

[0129] While maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q, the number of scan output inverters in the scan output circuit 400 is not limited to the above configuration. The scan output circuit 400 may also include 2n scan output inverters (where n is a natural number other than zero).

[0130] Other operations and configurations Figure 12 The same ones are repeated, so repeated descriptions will be omitted below.

[0131] Figure 15 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0132] Reference Figure 15 ,and Figure 12 and Figure 14Unlike other methods, the scan output circuit 400 receives the output signal from the fourth node SB. Specifically, according to some embodiments, the scan output circuit 400 may include a fifth scan output inverter 55. The fifth scan output inverter 55 can receive the signal output from the fourth node SB in the latch 200 and send the inverted output signal to the final output node SZ. The scan output NOR gate 71 can perform a logical NOR operation on the scan enable signal SE and the signal of the final output node SZ to output the scan output signal SO.

[0133] Detailed operation and Figure 12 The operation is similar, so its description will be omitted below.

[0134] Figure 16 This is a circuit diagram of a semiconductor device including a master-slave flip-flop according to some embodiments of the present disclosure.

[0135] Reference Figure 16 ,and Figure 15 Unlike other circuits, the scan output circuit 400 may also include a sixth scan output inverter 56 and a seventh scan output inverter 57. Therefore, in scan test mode, the delay time can be longer while maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q.

[0136] While maintaining the pin polarity of the scan output signal SO equal to the pin polarity of the final output signal Q, the number of scan output inverters in the scan output circuit 400 is not limited to the above configuration. The scan output circuit 400 may also include 2n+1 scan output inverters (where n is a natural number other than zero).

[0137] Other operations and configurations Figure 15 The same ones are repeated, so repeated descriptions will be omitted below.

[0138] Figure 17 This is a circuit diagram of a semiconductor device including a multi-bit master-slave flip-flop according to some embodiments of the present disclosure.

[0139] Reference Figure 17 In some embodiments, a semiconductor device including a multi-bit master-slave flip-flop can store multiple data signals D0 and D1 and output signals Q0 and Q1 by responding to a scan enable signal SE with a control signal.

[0140] A semiconductor device including a multi-bit master-slave flip-flop may include a multi-bit scan input circuit 1300, a first master latch 700, a first slave latch 800, a second master latch 1300, a second slave latch 1400, and a scan output circuit 400.

[0141] The multi-bit scan input circuit 1300 may include a first scan tri-state inverter 1311, a second scan tri-state inverter 1313, a third scan tri-state inverter 1314, and a fourth scan tri-state inverter 1315. The multi-bit scan input circuit 1300 can receive a first data signal D0, a second data signal D1, a first scan input signal SI, a signal from the preceding fourth node SB, and a scan enable signal SE. In response to a control signal, the multi-bit scan input circuit 1300 can output either the first data signal D0 or the first scan input signal SI to the preceding first node MA. In response to a control signal, the multi-bit scan input circuit 1300 can output either the second data signal D1 or the signal from the preceding fourth node SB to the subsequent fourth node SB1.

[0142] In addition to processing two bits simultaneously, the multi-bit scan input circuit 1300 can be compared with the above reference. Figure 2 The described scan input circuit 300 operates similarly. That is, the multi-bit scan input circuit 1300 can selectively output the first data signal D0 and the first scan input signal SI to the preceding first node MA according to the voltage level of the scan enable signal SE, and selectively output the second data signal D1 and the signal of the preceding fourth node SB to the subsequent first node MA.

[0143] Figure 17 The configuration of the multi-bit scan input circuit 1300 shown is illustrative only, and this disclosure is not limited thereto. For example, as Figure 20 As shown, the multi-bit scan input circuit 1300 can be implemented using multiple transmission gates, multiplexers, or logic NAND gates, which will be described below.

[0144] The first master latch 700 and the first slave latch 800 can store the first data signal D0 and output the first final output signal Q0 in response to a control signal. The second master latch 1300 and the second slave latch 1400 can store the second data signal D1 and output the second final output signal Q1 in response to a control signal. The first master latch 700, the first slave latch 800, the second master latch 1300 and the second slave latch 1400 can share the first clock signal CK and the second clock signal CKN.

[0145] The configuration and operation of the first master latch 700 and the first slave latch 800, as well as the configuration and operation of the second master latch 1300 and the second slave latch 1400, are described with reference to... Figure 2 The master latch 100 and slave latch 200 are configured and operate identically, so their detailed descriptions will be omitted below.

[0146] The second master latch 1300 may include a third input tri-state inverter 14, a third master latch tri-state inverter 15, and a seventh inverter 16.

[0147] Except for outputting the second data signal D1 instead of the first data signal D0 to the subsequent second node SA in response to the first clock signal CK and the second clock signal CKN, the configuration and operation of the second master latch 1300 are similar to those of the first master latch 700, and therefore its description will be replaced by the description of the configuration and operation of the first master latch 700.

[0148] The second slave latch 1400 may include a fourth input tri-state inverter 24, a fourth slave latch tri-state inverter 25, and an eighth inverter 26.

[0149] Furthermore, except that the second data signal D1 instead of the first data signal D0 is output to the subsequent fifth node SC1 in response to the first clock signal CK and the second clock signal CKN, the configuration and operation of the second slave latch 1400 are similar to those of the first slave latch 800, and therefore its description will be replaced by the description of the configuration and operation of the first slave latch 800.

[0150] According to some embodiments, the scan output circuit 400 of a semiconductor device including a multi-bit master-slave flip-flop receives external signals and signals from the subsequent fifth node SC1.

[0151] Except that the output signal of the scan output circuit 400, which is input to the semiconductor device including a multi-bit master-slave flip-flop, is the signal of the fifth node SC1 of the subsequent stage, the configuration and operation of the scan output circuit 400 are similar to those in... Figure 2 , Figure 8 , Figure 12 and Figure 14 The operation of the scan output circuit 400 according to some embodiments described herein will be omitted below.

[0152] Figure 18 This is a circuit diagram of a semiconductor device including a multi-bit master-slave flip-flop according to some embodiments of this disclosure. For reference, the following will omit references to... Figure 7 and Figure 17 The description of the configuration of operations and configurations that overlap.

[0153] Figure 19 This is a circuit diagram of a semiconductor device including a multi-bit master-slave flip-flop according to some embodiments of this disclosure. For reference, the following will omit references to... Figure 17 Descriptions of overlapping operations and configurations.

[0154] Reference Figure 19According to some embodiments, the scan output circuit 400 of a semiconductor device including a multi-bit master-slave flip-flop receives external signals and signals from the subsequent fourth node SB1.

[0155] Except that the output signal of the scan output circuit 400, which is input to the semiconductor device including a multi-bit master-slave flip-flop, is the signal of the fourth node SB1 of the subsequent stage, the configuration and operation of the scan output circuit 400 are similar to those in Figure 9 , Figure 11 , Figure 15 and Figure 16 The configuration and operation of the scan output circuit 400 according to some embodiments described herein will be omitted below.

[0156] Figure 20 This is a circuit diagram of a semiconductor device comprising two master-slave flip-flops connected in series, according to some embodiments of the present disclosure.

[0157] Reference Figure 20 Each of the pre-stage scan input circuit 300-1 and the post-stage scan input circuit 300-2 may include multiple scan input NAND gates. That is, the pre-stage scan input circuit 300-1 may include: a first scan input NAND gate 321, which performs a NAND operation on a first scan input signal SI1 and a first scan enable signal SE1 to output a first output signal N1; a second scan input NAND gate 322, which performs a NAND operation on a first inverted scan enable signal SEN1 and a first data signal D1 to output a second output signal N2; and a second scan input NAND gate 323, which performs a NAND operation on the first output signal N1 and the second output signal N2 to output a third output signal N3.

[0158] The third output signal N3 can be output to the fifth node SC1 of the pre-stage stage via the first pre-stage master latch 100-1 and the first pre-stage slave latch 200-1. The output signal of the fifth stage SC1 can be output as the first final output signal Q1 via the first pre-stage inverter 41-1. The output signal of the fifth node SC1 can be input to the first pre-stage scan input circuit 400-1. The operation of the first pre-stage scan input circuit 400-1 is similar to... Figure 2 The operation of the scanning input circuit 300 is the same, so its description will be omitted below.

[0159] The number of master-slave triggers connected is not limited to the above configuration, and three or more master-slave triggers can be connected.

[0160] A semiconductor device including a pre-stage master-slave flip-flop can be connected in series to a semiconductor device including a post-stage master-slave flip-flop. The pre-stage master-slave flip-flop may include a pre-stage scan input circuit 300-1, a first pre-stage master latch 100-1, a first pre-stage slave latch 200-1, a first pre-stage inverter 41-1, and a first pre-stage scan input circuit 400-1.

[0161] The master-slave flip-flop includes a master-slave scan input circuit 300-2, a second master-slave latch 100, a slave latch 200-2, an inverter 41-2, and a scan output circuit 400-2.

[0162] In a semiconductor device comprising two master-slave flip-flops connected in series according to some embodiments, when the first pre-stage scan input circuit 400-1 is connected to the post-stage scan input circuit 300-2, the scan input NAND gate is omitted.

[0163] Because the output signal of the first pre-stage slave latch 200-1 is input to the first pre-stage scan input circuit 400-1, the pre-stage scan output NAND gate 61-1 acts as the scan input NAND gate in the subsequent scan input circuit 300-2. Therefore, the scan input NAND gate can be omitted from the series connection between two or more master-slave flip-flops.

[0164] By omitting the scan input NAND gate, precise scan test operations can be implemented across multiple cascaded master-slave flip-flops. Furthermore, robust scan hold time characteristics can be improved through robust scan test design. This increases the potential for improved performance not only in mobile devices, servers, or computers, but also in electronic components.

[0165] The second post-stage scan input circuit 300-2 may include a fourth scan input NAND gate 332. The fourth scan input NAND gate 332 can receive the second data signal D2 and the second scan enable signal SEN2, and perform a NAND operation on the second data signal D2 and the second scan enable signal SEN2 to output a fourth output signal N4. The fifth scan input NAND gate 333 receives the fourth output signal N4 and the first scan output signal SO1, and performs a NAND operation on the fourth output signal N4 and the first scan output signal SO1 to output a fifth signal N5. The fifth signal N5 is output from the second post-stage main latch 100-2 and the second post-stage latch 200-2 to the fifth post-stage output node SC2. The second post-stage inverter 41-2 can invert the output signal of the fifth post-stage output node SC2 to output a second final output signal Q2. The second post-stage scan output circuit 400-2 can receive the output signal of the fifth post-stage output node SC2 and an external signal (in this figure, the second scan enable signal SE2) to output a second scan output signal SO2. The operation of the second-stage scanning output circuit 400-2 and Figure 2 The operation of the scanning output circuit 400 is the same, so its description will be omitted below.

[0166] Figure 21 This is a circuit diagram of a semiconductor device comprising a plurality of master-slave flip-flops connected in series, according to some embodiments of the present disclosure.

[0167] Reference Figure 21 Besides with Figure 20 The different first pre-stage scan input circuit 400-1, except for the first scan output NAND gate 61b-1, can operate with... Figure 20 The operation is the same as that of the first pre-stage scanning input circuit 400-1.

[0168] Figure 22 and Figure 23 It is a circuit diagram of a semiconductor device that includes multi-bit master-slave flip-flops connected in series.

[0169] Reference Figure 22 and Figure 23 Semiconductor devices, including multi-bit master-slave flip-flops connected in series, can be connected for two bits, but the number of bits for the connection is not limited to this. Configuration and operation are similar to... Figure 19 , Figure 20 and Figure 21 The configuration and operation are described below, so repeated descriptions will be omitted. When connecting multi-bit master-slave flip-flops, the NAND gate can be omitted to reduce overhead. Furthermore, when not in scan test mode, the conversion of the first scan output node SO1 can be completely prevented, thus reducing switching power.

[0170] Figure 24 This is an exemplary block diagram of an electronic system including a semiconductor device comprising a master-slave trigger, according to some embodiments of the present disclosure.

[0171] Reference Figure 24 Electronic system 10000 may include a main processor 11010, working memory 12000, storage device 13000, communication block 14000, user interface 15000, and bus 16000. For example, electronic system 10000 may be one of electronic devices such as desktop computers, laptop computers, tablet computers, smartphones, wearable devices, video game consoles, workstations, servers, infotainment devices for vehicles, advanced driver assistance systems (ADAS) devices, etc.

[0172] The main processor 11010 can control the overall operation of the electronic system 10000. The main processor 11010 can handle various types of arithmetic and / or logical operations. For this purpose, the main processor 11010 may include dedicated circuitry (e.g., a field-programmable gate array (FPGA)), application-specific integrated circuits (ASICs), etc. For example, the main processor 11010 may include one or more processor cores and may be implemented using a general-purpose processor, a dedicated processor, or an application processor. The main processor 11010 may include a semiconductor device comprising master-slave flip-flops, a semiconductor device comprising multi-bit master-slave flip-flops, and / or a semiconductor device comprising multiple serially connected master-slave flip-flops according to some embodiments of this disclosure.

[0173] The working memory 12000 can store data used for the operation of the electronic system 10000. For example, the working memory 12000 can temporarily store data processed by or to be processed by the main processor 11010. For example, the working memory 12000 may include volatile memory such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), and / or non-volatile memory such as phase change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc.

[0174] Storage device 13000 may include at least one memory device and a controller. The memory device of storage device 13000 can store data independently of a power supply. For example, storage device 13000 may include non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc. Storage device 13000 may also include storage media such as solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash memory (UFS), etc. Storage device 13000 may include a sensor for measuring internal temperature. Storage device 13000 can process commands received from main processor 11010 and then record information related to the internal temperature measured by the sensor in a command response returned to main processor 11010.

[0175] For example, storage device 13000 can receive a read command from main processor 11010 and return a command response indicating the processing result of the read command to main processor 11010. The command response may additionally include information about the internal temperature of storage device 13000. In this case, information about whether the read command was successfully executed, information about whether the temperature of storage device 13000 is below a lower reference temperature, and information about whether the temperature of storage device 13000 is above an upper reference temperature can be recorded in the command response relative to the read command. Main processor 11010 can perform thermal throttling operations to adjust the temperature of storage device 13000 based on the temperature-related information received from storage device 13000.

[0176] Communication block 14000 can communicate with external devices / systems of electronic system 10000. For example, communication block 14000 can support at least one of various wireless communication protocols such as LTE, WiMAX, GSM, CDMA, Bluetooth, NFC, Wi-Fi, RFID, etc., and / or at least one of various wired communication protocols such as TCP / IP, USB, FireWire, etc.

[0177] User interface 15000 can arbitrate communication between the user and electronic system 10000. For example, user interface 15000 may include input interfaces such as a keyboard, mouse, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, etc. For example, user interface 15000 may include output interfaces such as liquid crystal display (LCD) devices, light-emitting diode (LED) display devices, organic LED (OLED) display devices, active-matrix OLED (AMOLED) display devices, speakers, motors, etc.

[0178] Bus 16000 can provide a communication path between components of electronic system 10000. Components of electronic system 10000 can exchange data with each other based on the bus format of bus 16000. For example, the bus format may include one or more of various interface protocols such as USB, Small Computer System Interface (SCSI), High-Speed ​​Peripheral Component Interconnect (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), High-Speed ​​Non-Volatile Memory (NVMe), UFS, etc.

Claims

1. A semiconductor device, comprising: The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal, and in response to the scan enable signal, select either the first data signal or the scan input signal to output a first selection signal; The master latch is configured to latch the first selection signal to output the first output signal; The latch is configured to latch the first output signal to output the second output signal; The first inverter is configured to invert the second output signal to output the final output signal; as well as The scan output circuit is configured to receive signals from the slave latch and external signals to output a first scan output signal. The scan output circuit includes a first scan output inverter, which is configured to invert the second output signal to output a third output signal. The ground terminal of the first scan output inverter receives the inverted scan enable signal.

2. The semiconductor device according to claim 1, wherein: The scan output circuit also includes: The second scan output inverter is configured to invert the third output signal to output the fourth output signal.

3. The semiconductor device according to claim 2, wherein, The scan output circuit includes a scan logic gate configured to receive an external signal and a fourth output signal, and to perform logic operations on the external signal and the fourth output signal to output a scan output signal.

4. The semiconductor device according to claim 3, wherein: Scan logic gates include scan output NAND gates; and External signals include scan enable signals.

5. The semiconductor device according to claim 3, wherein: Scan logic gates include scan-output NOR gates; and External signals include an inverted scan enable signal.

6. The semiconductor device according to claim 1, wherein: The scan output circuit also includes: The second scan output inverter is configured to invert the third output signal to output the fourth output signal. The ground terminal of the second scan output inverter receives the inverted scan enable signal.

7. The semiconductor device according to claim 6, wherein, The scan output circuit includes: A scan output NAND gate is configured to receive an external signal and a fourth output signal, and perform logical operations on the external signal and the fourth output signal to output a scan output signal; and External signals include scan enable signals.

8. The semiconductor device according to claim 6, wherein: The scan output circuit includes a scan output NOR gate configured to receive an external signal and a fourth output signal, and to perform logical operations on the external signal and the fourth output signal to output a scan output signal; and External signals include the inverted scan enable signal.

9. The semiconductor device according to claim 1, wherein: The latch includes a second inverter; The second inverter inverts the second output signal; The signal output from the latch is the output of the second inverter; as well as The external signal is the scan enable signal.

10. The semiconductor device according to claim 9, wherein, The scan output circuit also includes: The second scan output inverter is configured to invert the third output signal to output the fourth output signal; The ground terminal of the second scan output inverter receives the scan enable signal.

11. A semiconductor device, comprising: The first scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal, and in response to the scan enable signal, select either the first data signal or the scan input signal to output a first selection signal. The first master latch is configured to latch the first selection signal to output the first output signal; A first slave latch is configured to latch a first output signal to output a second output signal, wherein the first slave latch includes a first inverter, and the first inverter inverts the second output signal to output a third output signal; The second scan input circuit is configured to receive a third output signal, a second data signal, and a scan enable signal, and in response to the scan enable signal, select either the second data signal or the third output signal to output a second selection signal; The second master latch is configured to latch the second selection signal to output the fourth output signal; The second latch is configured to latch the fourth selection signal to output the fifth output signal; and The scan output circuit is configured to receive signals from the second slave latch and external signals to output a first scan output signal.

12. The semiconductor device according to claim 11, wherein: The scan output circuit includes: The first scan output inverter is configured to invert the fifth output signal to output the sixth output signal; and The second scan output inverter is configured to invert the sixth output signal to output the seventh output signal; The ground terminal of the first scan output inverter and the ground terminal of the second scan output inverter receive the inverted scan enable signal.

13. The semiconductor device according to claim 12, wherein: The scan output circuit includes a scan output NAND gate configured to receive an external signal and a seventh output signal, and to perform logical operations on the external signal and the seventh output signal to output a scan output signal; and External signals include scan enable signals.

14. The semiconductor device according to claim 12, wherein: The scan output circuit includes a scan output NOR gate configured to receive an external signal and a seventh output signal, and to perform logical operations on the external signal and the seventh output signal to output a scan output signal; and External signals include an inverted scan enable signal.

15. A semiconductor device, comprising: The first scan input NAND gate is configured to perform a NAND operation on the first scan input signal and the first scan enable signal to output a first output signal; The second scan input NAND gate is configured to perform a NAND operation on the inverted first scan enable signal and the first data signal to output a second output signal; The first scan input circuit includes a third scan input NAND gate, which is configured to perform a NAND operation on the first output signal and the second output signal to output a third output signal. The first master latch is configured to latch the third output signal to output the fourth output signal; The first slave latch is configured to latch the fourth output signal to output the fifth output signal; The first inverter is configured to invert the fifth output signal to output the first final output signal; The first scan output circuit is configured to receive a signal output from a first latch and a first external signal to output a first scan output signal. The fourth scan input NAND gate is configured to perform a NAND operation on the inverted second scan enable signal and the second data signal to output the sixth output signal; The second scan input circuit includes a fifth scan input NAND gate, which is configured to perform a NAND operation on the first scan output signal and the sixth output signal to output a seventh output signal. The second master latch is configured to latch the seventh output signal to output the eighth output signal; The second latch is configured to latch the eighth output signal to output the ninth output signal; The second inverter is configured to invert the ninth output signal to output the second final output signal; as well as The second scan output circuit is configured to receive a signal output from a second latch and a second external signal to output a second scan output signal.

16. The semiconductor device according to claim 15, wherein: The signals output from the first latch include the fifth output signal; as well as The first scan output circuit includes: The first scan output inverter is configured to invert the fifth output signal to output the tenth output signal; and The second scan output inverter is configured to invert the tenth output signal to output the eleventh output signal; The ground terminal of the first scan output inverter and the ground terminal of the second scan output inverter receive the inverted first scan enable signal.

17. The semiconductor device according to claim 16, wherein: The first scan output circuit includes a scan output NAND gate configured to receive an external signal and an eleventh output signal and perform logical operations on the external signal and the eleventh output signal; and External signals include the first scan enable signal.

18. The semiconductor device according to claim 16, wherein: The first scan output circuit includes a scan output NOR gate, which is configured to receive an external signal and an eleventh output signal and perform logical operations on the external signal and the eleventh output signal; and External signals include an inverted first scan enable signal.

19. The semiconductor device according to claim 15, wherein: The first slave latch includes a third inverter; The third inverter inverts the fourth output signal to output the tenth output signal; and External signals include an inverted first scan enable signal.

20. The semiconductor device according to claim 19, wherein, The first scan output circuit includes: The first scan output inverter is configured to invert the tenth output signal to output the eleventh output signal; and The second scan output inverter is configured to invert the eleventh output signal to output the twelfth output signal; The ground terminal of the first scan output inverter and the ground terminal of the second scan output inverter receive the inverted first scan enable signal.

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