A Bit Block Stream Error Detection Method and Device

Abstract

A method and device for detecting bit errors in a bit block stream, which solve the problems of high implementation difficulty and low carrying efficiency of the bit error detection method in the scenario of M / N Bit block exchange. The method includes: sending a first boundary bit block, where the first boundary bit block is used to distinguish the subsequent N bit blocks; sequentially sending the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to N; determining a first parity check result and a second parity check result, where the check object of the first parity check result includes consecutive m bits of each of the N bit blocks, and the check object of the second parity check result includes consecutive n bits of each of the N bit blocks, and at least one of m and n is greater than or equal to 2; sending a second boundary bit block, the first parity check result, and the second parity check result, where the second boundary bit block is used to distinguish the already sent N bit blocks.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a method and device for detecting bit error in a bit block stream. Background Art

[0002] In the prior art, various methods for detecting bit errors based on packets (PACKET) have been proposed. For example, cyclic redundancy check (CRC) detection is performed based on PACKET. Each Ethernet packet determines an error packet according to its frame check sequence (FCS) field (CRC-32). By statistically analyzing the error packet rate within a certain period of time, the quality of the user channel can be evaluated. However, the above method cannot accurately measure the bit error ratio (BER). When there is no user service packet, the BER cannot be statistically analyzed. Or when there are very few user service packets, it takes a long time to detect the BER.

[0003] For example, if one FCS check error in an Ethernet packet is regarded as one bit error, to evaluate a BER of 1*e-5, at least 100,000 Ethernet packets need to be continuously transmitted, received, and detected. Assuming the user service bandwidth is 10 Mbps and full traffic is sent, and the Ethernet packet length is 256 B, the detection time is at least 22.08 seconds. If the user service bandwidth is only 100 Kbps and the Ethernet packet length is 256 B, the detection time is at least 36.8 minutes (2208 seconds).

[0004] As shown in Table 1, the FCS occupies 4 bytes. Therefore, the above method also has the problem of occupying more fixed frame bytes, resulting in low carrying efficiency. Introducing CRC-32 check, when the minimum packet is 64 B, the carrying efficiency is reduced by 6.25%; when the maximum packet is 1518 B, the carrying efficiency is reduced by 0.263%.

[0005] Table 1

[0006] Preamble SFD Destination Source Length / Type Data and Pad FCS 7 1 6 6 2 46～1500 4

[0007] In addition, the prior art also proposes a bit error detection method based on bit interleaving parity (BIP) for each frame. For example, overhead bytes for BIP check are set in the frame structure of synchronous digital hierarchy (SDH) / optical transport network (OTN). Therefore, the carrying efficiency of this method is rigid and cannot dynamically define the check algorithm according to user requirements, such as downgrading BIP-8 to BIP-4 or upgrading to BIP-16.

[0008] At present, the fifth-generation communication technology (i.e., 5G) has been widely studied in the industry. Deterministic low latency, reliability, and security isolation technologies have become important issues that need to be overcome urgently in 5G. X-Ethernet (abbreviated as X-E) is a Bit Block switching technology based on the Ethernet physical layer, such as 64 / 66 Bit Block, and has the technical characteristics of deterministic ultra-low latency. X-Ethernet is based on M / N Bit block switching and can borrow the above error detection method to perform error detection. For example, it can include the following two methods:

[0009] Method 1: Borrow the method of performing CRC detection based on PACKET. X-E arranges several Bits for CRC check block by block. For example, for a 66Bit Block, 4 or 8 Bits can be set to perform CRC check on the other 60 or 56 Bits.

[0010] Method 2: Borrow the SDH / OTN method and arrange one byte or several Bits for BIP check block by block. For example, for a 66Bit Block, 2 - 8 Bits can be set to perform BIP check on the other 62 - 56 Bits.

[0011] Although the above two methods can be implemented, no matter which method is used, the processing unit in the device needs to operate block by block, so the implementation difficulty is relatively large. Moreover, the carrying efficiency of the above two methods is relatively low. For example, when performing BIP-4 / CRC-4 check on each block, the carrying efficiency will decrease by 6.25%, and when performing BIP-8 / CRC-8 on each block, the carrying efficiency will decrease by 12.5%. Summary of the Invention

[0012] The embodiments of the present application provide a method and device for error detection of bit block streams to solve the problems of relatively large implementation difficulty and low carrying efficiency of the error detection method in the scenario of M / N Bitblock switching.

[0013] In a first aspect, a method for error detection of bit block streams includes: sending a first boundary bit block, where the first boundary bit block is used to distinguish the subsequent N bit blocks, and N is a positive integer; sequentially sending the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to N; determining a first parity check result and a second parity check result, where the check object of the first parity check result includes consecutive m bits of each of the N bit blocks, and the check object of the second parity check result includes consecutive n bits of each of the N bit blocks, and at least one of m and n is greater than or equal to 2; sending a second boundary bit block, the first parity check result, and the second parity check result, where the second boundary bit block is used to distinguish the N bit blocks that have been sent.

[0014] Therefore, the method provided by the embodiments of the present application can completely implement the error or bit error detection of the M / N Bit Block network path without affecting the user service, with a 100% bearing efficiency. It can tolerate the bit blocks inserted or deleted due to synchronization problems during the transmission process, and the detection period (i.e., the number of bit blocks between two boundary bit blocks) and the detection accuracy (i.e., the preset algorithm) can be dynamically configured according to demand. In addition, the detection method can be used not only for the end-to-end path of the bit stream to be verified, but also for the non-end-to-end path of the bit stream to be verified. Therefore, the method provided by the embodiments of the present application can solve the problems of high implementation difficulty and low bearing efficiency of the bit error detection method in the M / N Bit block switching scenario.

[0015] It should be understood that when the path of the bit stream to be verified is from the bit block sending end to the bit block receiving end, or when the path of the bit stream to be verified is to any intermediate device before the bit block receiving end from the bit block sending end, the execution subject of the above method can be the bit block sending end. When the path of the bit stream to be verified is from the bit block sending end to the bit block receiving end, the path of the bit stream to be verified is an end-to-end path. When the path of the bit stream to be verified is to any intermediate device before the bit block receiving end from the bit block sending end, the path of the bit stream to be verified is a path with one end hanging. In the present application, it is collectively referred to as the sending device. Therefore, the embodiments of the present application can not only be used for bit error detection of the end-to-end path, but also for bit error detection of the non-end-to-end path. For example, the planned reserved path, the protection path of the 1:1 connection protection group or the path with other special purposes. When the path of the bit stream to be verified is from the first intermediate device after the bit block sending end to the second intermediate device before the bit block receiving end, the execution subject of the above method can be the first intermediate device. The path of the bit stream to be verified is a path with both ends hanging.

[0016] In a possible design, the type of each bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2 - M1 represents the number of header synchronization header bits in each bit block, M1 and M2 are positive integers, and M2 > M1.

[0017] In a possible design, sending the first boundary bit block includes: sending the first boundary bit block to a first device; sequentially sending the I-th bit block includes: sequentially sending the I-th bit block to the first device; sending the second boundary bit block, the first parity check result, and the second parity check result may include two cases: (1) sending the second boundary bit block, the first parity check result, and the second parity check result to the first device; thus, in the above implementation, the first parity check result and the second parity check result are sent to the first device together with two boundary bit blocks and N bit blocks between the two boundary bit blocks. When the path of the bit block stream to be checked is from the bit block sender to the bit block receiver, the first device here may be the bit block receiver. When the path of the bit block stream to be checked is to any intermediate device before reaching the bit block receiver from the bit block sender, or when the path of the bit block stream to be checked is from the first intermediate device after the bit block sender to the second intermediate device before the bit block receiver, the first device here may also refer to the intermediate device. (2) sending the second boundary bit block to the first device and sending the first parity check result and the second parity check result to a second device. It should be noted that the second device here may be an SDN controller or any device with the function of judging bit stream transmission error codes. In addition, both of these two methods can also be used simultaneously, that is, the first parity check result and the second parity check result are sent to both the first device and the second device. Therefore, the embodiments of the present application provide two optional methods to implement error code detection, which are more flexible and efficient and easy to implement.

[0018] In a possible design, for sending the second boundary bit block, the first parity check result, and the second parity check result, there are the following possible implementation methods: sending the second boundary bit block at a first moment and sending the first parity check result and the second parity check result at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

[0019] In a possible design, the first parity check result and the second parity check result are stored in the second boundary bit block.

[0020] Therefore, assuming that every N bit blocks in the bit block stream are grouped into one group, the i-th boundary bit block stores the first parity check result and the second parity check result corresponding to the i-th group of N bit blocks, and the (i + 1)-th boundary bit block stores the first parity check result and the second parity check result corresponding to the (i + 1)-th group of N bit blocks, where the (i + 1)-th group of N bit blocks are the bit blocks between the i-th boundary bit block and the (i + 1)-th boundary bit block, and i is a positive integer.

[0021] It should be understood that the boundary bit blocks mentioned in this application can be newly inserted bit blocks. When a boundary bit block is newly inserted, a first bit block can be deleted to reduce the impact on the user bandwidth. Herein, the first bit block refers to a bit block that may be inserted into or deleted from N bit blocks during the transmission of N bit blocks. For example, for a 64 / 66 bit block stream, the first bit block can refer to an idle block.

[0022] In a possible design, the first parity check result and the second parity check result are calculated according to a preset check algorithm. The preset check algorithm is used to keep the first parity check result and the second parity check result unchanged when a first bit block is added to or deleted from N bit blocks. The first bit block refers to a bit block that may be inserted into or deleted from N bit blocks during the transmission of N bit blocks. Therefore, adopting the preset check algorithm provided by the embodiments of this application can ensure that the first parity check result and the second parity check result can tolerate the insertion or deletion of one or more first bit blocks (such as IDLE Block) during the transmission process, and can also be detected when an error occurs in the first bit block.

[0023] In a possible design, the preset check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the pattern definition of the first bit block, y refers to the number of monitoring sections, x and y are positive integers, and y≥2. For example, the 8BIP-8 algorithm and the 16BIP-4 algorithm. The specific method for determining the first parity check result and the second parity check result using the xBIP–y algorithm is as follows: Starting from the first payload bit in N bit blocks, each consecutive x bits of each bit block are sequentially recorded into the first monitoring section to the yth monitoring section; for each monitoring section, an odd parity check or an even parity check is used to determine 1-bit monitoring codes, and y-bit monitoring codes are obtained. The y-bit monitoring codes include the first parity check result and the second parity check result. Therefore, adopting the xBIP–y algorithm provided by the embodiments of this application can tolerate the insertion or deletion of one or more first bit blocks during the transmission process, and the method is simple.

[0024] In a possible design, the preset check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of continuously bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of continuously bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A3... Az-1, Az, A1, A2, A3... Az-1, Az, respectively, and z is a positive integer, z≥2. The specific method for determining the first parity check result and the second parity check result using the flexBIP–z algorithm is as follows: Starting from the first payload bit in the N bit blocks, record A1 consecutive bits in each bit block to the first monitoring section, record A2 consecutive bits after the A1 consecutive bits to the second monitoring section, record A3 consecutive bits after the A2 consecutive bits to the third monitoring section, until recording Az consecutive bits after the Az-1 consecutive bits to the zth monitoring section; For each monitoring section, use odd parity check or even parity check to determine 1-bit monitoring code, and obtain z-bit monitoring code. The z-bit monitoring code includes the first parity check result and the second parity check result. Therefore, using the flexBIP–z algorithm provided by the embodiments of the present application can determine the first parity check result and the second parity check result more flexibly and simply, and tolerate the insertion or deletion of one or more first bit blocks during the transmission process.

[0025] In a possible design, determining the first parity check result and the second parity check result includes: determining a first check result set, where the first check result set includes y-bit monitoring code, or the first check result set includes z-bit monitoring code; Sending the first parity check result and the second parity check result includes: sending the first check result set. Therefore, using the method provided by the embodiments of the present application can completely implement the error or error code detection of the M / N Bit Block network path.

[0026] Second aspect, a method for detecting bit error in a bit block stream, comprising: receiving a first boundary bit block, which is used to distinguish the subsequent T bit blocks to be received, where T is a positive integer; sequentially receiving the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to T; receiving a second boundary bit block, which is used to distinguish the T bit blocks that have been received; determining a third parity check result and a fourth parity check result, the check object of the third parity check result includes consecutive m bits of each of the T bit blocks, the check object of the second parity check result includes consecutive n bits of each of the T bit blocks, and at least one of m and n is greater than or equal to 2; when receiving the first parity check result and the second parity check result, determining whether there is a bit error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, where the check object of the first parity check result includes consecutive m bits of each of the N bit blocks, the check object of the second parity check result includes consecutive n bits of each of the N bit blocks, and N is the number of bit blocks between the first boundary bit block and the second boundary bit block when determining the first parity check result and the second parity check result. Therefore, the method provided by the embodiments of the present application can completely implement the error or bit error detection of the M / N Bit Block network path, without affecting the user service, with a carrying efficiency of 100%, can tolerate the bit blocks inserted or deleted due to synchronization problems during the transmission process, and the detection period (i.e., the number of bit blocks between two boundary bit blocks) and the detection accuracy (i.e., the preset algorithm) can be dynamically configured according to demand. In addition, the detection method can be used not only for the end-to-end path of the bit block stream to be checked, but also for the non-end-to-end path of the bit block stream to be checked. Therefore, the method provided by the embodiments of the present application can solve the problems of high implementation difficulty and low carrying efficiency of the bit error detection method in the M / N Bit block switching scenario.

[0027] It should be understood that when the path of the bit block stream to be checked is from the bit block sending end to the bit block receiving end, Figure 13 the execution subject of each step can be the bit block receiving end. When the path of the bit block stream to be checked is any intermediate device before the bit block sending end to the bit block receiving end, or when the path of the bit block stream to be checked is from the bit block sending end to the bit block receiving end, the execution subject of the above method can be the intermediate device. In the present application, it is collectively referred to as the receiving device.

[0028] Note that the N bit blocks here are the bit blocks between the first boundary bit block and the second boundary bit block when the transmitting device determines the first parity check result and the second parity check result. As an optional embodiment, after the transmitting device sends the first boundary bit block, it sequentially sends the N bit blocks, then calculates the first parity check result and the second parity check result based on these N bit blocks, stores these two results in the second boundary bit block, and sends the second boundary bit block. However, considering that the first bit block may be inserted or deleted in the N bit blocks due to passing through asynchronous nodes in the path from the transmitting device to the receiving device, after receiving the first boundary bit block, the receiving device sequentially receives T bit blocks. At this time, there may be three situations: N = T, or N > T (i.e., the first bit block is inserted in the N bit blocks), or N < T (i.e., the first bit block is deleted in the N bit blocks).

[0029] In a possible design, it further includes: when the first parity check result and the second parity check result are not received, sending the third parity check result and the fourth parity check result to the second device, where the second device stores the first parity check result and the second parity check result. Note that the second device here can be an SDN controller, or any device with the function of judging bit stream transmission error codes. In addition, when the first parity check result and the second parity check result are received, the third parity check result and the fourth parity check result can also be sent to the second device. Therefore, the second device can receive the first parity check result and the second parity check result sent by the transmitting device, and the third parity check result and the fourth parity check result sent by the receiving device. The second device determines whether there is an error code in the transmission process of the bit block stream according to the two sets of results. Therefore, the embodiment of the present application provides error code detection through a third-party device, such as an SDN controller, or any device with the function of judging bit stream transmission error codes, which is more flexible and efficient and easy to implement.

[0030] In a possible design, the type of each bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2 - M1 represents the number of header synchronization header bits in each bit block, M1 and M2 are positive integers, and M2 > M1.

[0031] In a possible design, receiving the second boundary bit block includes: receiving the second boundary bit block at the first moment;

[0032] Receiving the first parity check result and the second parity check result includes: receiving the first parity check result and the second parity check result at the second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

[0033] In a possible design, the first parity check result and the second parity check result are stored in the second boundary bit block.

[0034] In a possible design, the third parity check result and the fourth parity check result are calculated according to a preset check algorithm, which is used to keep the third parity check result and the fourth parity check result unchanged when the first bit block is added to or deleted from T bit blocks. The first bit block refers to the bit block that may be inserted into or deleted from T bit blocks during the transmission of T bit blocks. Therefore, the preset check algorithm provided by the embodiments of the present application can ensure that the first parity check result and the second parity check result can tolerate the insertion or deletion of one or more first bit blocks (such as IDLE Block) during the transmission process, and can also be detected when the first bit block has an error code.

[0035] In addition, it should be understood that the preset algorithm used by the receiving device to determine the third parity check result and the fourth parity check result is the same as the preset algorithm used by the sending device to determine the first parity check result and the second parity check result, and the repeated parts will not be elaborated here.

[0036] In a possible design, the preset check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, and y≥2;

[0037] Determining the third parity check result and the fourth parity check result includes: starting from the first payload bit in T bit blocks, recording every x consecutive bits of each bit block to the first monitoring section to the yth monitoring section in sequence; using odd parity check or even parity check for each monitoring section to determine 1-bit monitoring codes, and obtaining y-bit monitoring codes, where the y-bit monitoring codes include the third parity check result and the fourth parity check result. Therefore, the xBIP–y algorithm provided by the embodiments of the present application can tolerate the insertion or deletion of one or more first bit blocks during the transmission process, and the method is simple.

[0038] In a possible design, the preset check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of continuously bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of continuously bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A 3……Az-1, Az, and A1, A2, A 3……Az-1, Az, and z are positive integers, and z≥2;

[0039] Determine the third parity check result and the fourth parity check result, including: starting from the first payload bit in the T bit blocks, record A1 consecutive bits of each bit block into the first monitoring section, record A2 consecutive bits after the A1 consecutive bits into the second monitoring section, record A3 consecutive bits after the A2 consecutive bits into the third monitoring section, until recording Az consecutive bits after the Az-1 consecutive bits into the zth monitoring section; use odd parity check or even parity check for each monitoring section to determine 1-bit monitoring codes, and obtain z-bit monitoring codes, where the z-bit monitoring codes include the third parity check result and the fourth parity check result. Therefore, the flexBIP–z algorithm provided by the embodiments of the present application can more flexibly and concisely determine the first parity check result and the second parity check result, and tolerate the insertion or deletion of one or more first bit blocks during the transmission process.

[0040] In a possible design, determine whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, including: if it is determined that the first parity check result and the third parity check result are the same, and the second parity check result and the fourth parity check result are the same, then determine that there is no error in the T bit blocks; if it is determined that the first parity check result and the third parity check result are different, and / or the second parity check result and the fourth parity check result are different, then determine that there is an error in the T bit blocks.

[0041] In a possible design, receive the first parity check result and the second parity check result, including: receive the first set of check results, the first set of check results is calculated according to the xBIP–y algorithm, and the y-bit monitoring codes included in the first set of check results include the first parity check result and the second parity check result; determine the third parity check result and the fourth parity check result, including: determine the second set of check results, the second parity check result is calculated according to the xBIP–y algorithm, and the y-bit monitoring codes included in the second set of check results include the third parity check result and the third parity check result;

[0042] When receiving the first parity check result and the second parity check result, determine whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, including: determine whether there is an error in the T bit blocks according to the first set of check results and the second set of check results. Therefore, the method provided by the embodiments of the present application can completely implement the error or error code detection of the M / N Bit Block network path.

[0043] In a possible design, receiving the first parity check result and the second parity check result includes: receiving a first set of check results, where the first set of check results is calculated according to the flexBIP–z algorithm, and the z-bit monitoring codes included in the first set of check results include the first parity check result and the second parity check result; determining the third parity check result and the fourth parity check result includes: determining a second set of check results, where the second set of check results is calculated according to the flexBIP–z algorithm, and the z-bit monitoring codes included in the second set of check results include the third parity check result and the fourth parity check result; when receiving the first parity check result and the second parity check result, determining whether there are error codes in T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result includes: determining whether there are error codes in T bit blocks according to the first set of check results and the second set of check results. Therefore, the method provided in the embodiments of the present application can completely implement the error or error code detection of the M / N Bit Block network path.

[0044] In a possible design, determining whether there are error codes in T bit blocks according to the first set of check results and the second set of check results includes: if it is determined that the first set of check results and the second set of check results are the same, determining that there are no error codes in T bit blocks; if it is determined that the first set of check results and the second set of check results are different, determining that there are error codes in T bit blocks.

[0045] In a third aspect, a method for detecting bit block stream error codes includes: a first device determining a detected section according to a start byte in a start block and an end byte in an end block corresponding to the start block in a bit block stream; the first device calculating a first check result according to the detected section. The first device sends the first check result and the bit block stream. For example, the algorithm used by the first device when calculating the first check result can be CRC-x or BIP-x, and the first check result is denoted as result B, and B can be one or more bytes. Therefore, the method provided in the embodiments of the present application can completely implement the error or error code detection of the M / N Bit Block network path, has little impact on user services, is close to SDH / OTN, is superior to the error code detection methods provided in the prior art, and has a simple implementation process and is easy to implement.

[0046] In a possible design, the bit block stream includes at least one M1 / M2 bit block; where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2–M1 represents the number of header synchronization header bits in each bit block, M1 and M2 are positive integers, and M2 > M1.

[0047] In a possible design, the first device sends the first verification result and the bit block stream, including: the first device sends the first verification result and the bit block stream to the second device; or, the first device sends the first verification result to the third device and sends the bit block stream to the second device. Therefore, the embodiments of the present application provide error code detection through a third-party device, such as an SDN controller or any device with the function of judging bit stream transmission error codes, which is more flexible and efficient and easy to implement.

[0048] In a possible design, before the first device sends the first verification result and the bit block stream to the second device, it further includes: the first device stores the first verification result in the end block to obtain an updated end block; or, the first device stores the first verification result in the verification result storage block and deletes any first bit block in the bit block stream, where the verification result storage block is a new block located before the end block, and the first bit block is a bit block that may be inserted into or deleted from the bit block stream during the transmission of the bit block stream. Therefore, the embodiments of the present application provide two methods for storing the first verification result, and the storage method is more flexible and easy to implement.

[0049] In a possible design, when the first device stores the first verification result in the end block to obtain an updated end block, it includes: when the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, the first device stores the first verification result before the end byte in the end block, moves the end byte to a new block after the end block according to the number of bytes occupied by the first verification result, deletes any first bit block in the bit block stream, and uses the new block where the end byte is located after moving as the updated end block; when the number of bytes occupied by the first verification result is less than the target number of bytes, the first device stores the first verification result before the end byte in the end block, moves the end byte backward by the number of bytes occupied by the first verification result, and uses the bit block where the end byte is located after moving as the updated end block; where the target number of bytes is the number of bytes after the end byte in the end block plus 1. Therefore, the method provided by the embodiments of the present application is easy to implement.

[0050] Fourthly, a method for detecting bit block stream error codes includes: the second device determines the detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream; the second device calculates the second verification result according to the detected section. When the second device receives the first verification result, the second device determines whether there is an error code in the detected section according to the first verification result and the second verification result. Therefore, the method provided by the embodiments of the present application can completely implement the error or error code detection of the M / N Bit Block network path, has little impact on user services, is close to SDH / OTN, is superior to the error code detection methods provided in the prior art, and has a simple implementation process and is easy to implement.

[0051] The algorithm adopted by the second device when calculating the second verification result is the same as the algorithm adopted by the first device when calculating the first verification result.

[0052] In a possible design, the bit block stream includes at least one M1 / M2 bit block; where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2–M1 represents the number of header synchronization bits in each bit block, and M1 and M2 are positive integers, and M2 > M1.

[0053] In a possible design, the second device determines the detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream, including three possible cases: (1) When the second device receives the first verification result and the first verification result is stored in the end block, the second device deletes the second verification result from the end block to obtain an updated end block, and takes the bytes between the start byte in the start block and the end byte in the updated end block as the detected section; (2) When the second device receives the first verification result and the first verification result is stored in the verification result storage block, the second device deletes the verification result storage block from the bit block stream to obtain an updated bit block stream, and takes the bytes between the start byte in the start block and the end byte in the end block in the updated bit block stream as the detected section, where the verification result storage block is located before the end block. In the above two cases, the first verification result is included in the bytes between the start byte in the start block and the end byte in the end block. Therefore, it is necessary to first delete the first verification result and take the remaining part as the detected section. In addition, when the second device receives the first verification result and the first verification result is stored in the verification result storage block, the second device deletes the verification result storage block from the bit block stream to obtain an updated bit block stream, where the verification result storage block is located before the end block. At the same time, in order to reduce the impact on the user bandwidth, it is necessary to add a first bit block after the end block. (3) When the second device does not receive the first verification result, the second device takes the bytes between the start byte in the start block and the end byte in the end block in the bit block stream as the detected section. At this time, the bytes between the start byte in the start block and the end byte in the end block do not include the first verification result and can be directly used as the detected section.

[0054] In a possible design, it further includes: when the second device does not receive the first verification result, the second device sends the second verification result to a third device that stores the first verification result. Therefore, the embodiments of the present application provide two methods for storing the first verification result, and the storage method is more flexible and easy to implement.

[0055] In a possible design, the second device determines whether there is an error code in the detected section according to the first verification result and the second verification result, including: if the second device determines that the first verification result is the same as the second verification result, it determines that there is no error code in the detected section; if it determines that the first verification result is different from the second verification result, it determines that there is an error code in the detected section.

[0056] In a possible design, the second device deletes the first verification result from the end block to obtain an updated end block, including: when the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, the second device moves the end byte to a bit block before the end block according to the number of bytes occupied by the first verification result, adds a first bit block to the bit block stream, and uses the bit block where the end byte is located after moving as the updated end block; when the number of bytes occupied by the first verification result is less than the target number of bytes, the second device moves the end byte forward by the number of bytes occupied by the first verification result according to the number of bytes occupied by the first verification result, and uses the bit block where the end byte is located after moving as the updated end block; where the target number of bytes is the number of bytes before the end byte in the end block plus 1. Therefore, the method provided by the embodiments of the present application is simple to implement.

[0057] In a fifth aspect, a bit block stream error code detection device includes a processor and a transceiver. The transceiver is used to send bit stream blocks, and the processor is used to complete the method in the first aspect or any possible implementation manner of the first aspect according to the bit stream blocks sent by the transceiver.

[0058] In a sixth aspect, a bit block stream error code detection device includes a processor and a transceiver. The transceiver is used to receive bit stream blocks, and the processor is used to complete the method in the second aspect or any possible implementation manner of the second aspect according to the bit stream blocks received by the transceiver.

[0059] In a seventh aspect, a bit block stream error code detection device includes a processor and a transceiver. The transceiver is used to send bit stream blocks, and the processor is used to complete the method in the first aspect or any possible implementation manner of the first aspect according to the bit stream blocks sent by the transceiver.

[0060] In an eighth aspect, a bit block stream error code detection device includes a processor and a transceiver. The transceiver is used to receive bit stream blocks, and the processor is used to complete the method in the second aspect or any possible implementation manner of the second aspect according to the bit stream blocks received by the transceiver.

[0061] An embodiment of the present application proposes a new device for transmitting the M1 / M2 bit block stream. A new error detection unit, also known as the Bit Error Ratio (BER) unit, is added to this device, abbreviated as BER. This unit is used to calculate the verification result and perform error detection. Among them, the PE device includes uAdpt, L1.5 Switch, nAdpt, and BER. One end of it is connected to the user device, and the interface is UNI. The other end is connected to the network device, and the interface is NNI. The P device includes uAdpt, L1.5 Switch, nAdpt, and BER, and both ends are connected to the network device, and the interface is NNI, as shown in Figures 23(a) and 23(b).

[0062] An embodiment of the present application also proposes a packet bearing product, such as an IPRAN or PTN device planned to load the X-E feature. Refer to Figure 24 As shown, for a packet bearing product provided by the present application, the interface board here can be the interface chip of the interface card of the box-type device or the line card of the frame-type device.

[0063] Alternatively, an embodiment of the present application also proposes a packet bearing product. Refer to Figure 25 As shown, the present application provides a new type of chip, such as SDxxxx, with BER built into the chip; or between an existing interface chip, such as SDyyyy and the main control switching board, add a Field-Programmable Gate Array (FPGA) or a Network Processor (NP), and implement the function of BER through the FPGA or NP.

[0064] In a ninth aspect, the present application provides a computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When it runs on a computer, it causes the computer to execute the method described in the first aspect or any possible design of the first aspect.

[0065] In a tenth aspect, the present application also provides a computer program product containing instructions. When it runs on a computer, it causes the computer to execute the method described in the first aspect or any possible design of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 It is a schematic diagram of the code pattern definition of 64 / 66Bit encoding in an embodiment of the present application;

[0067] Figure 2 It is a schematic diagram of the code pattern definition of the idle block in an embodiment of the present application;

[0068] Figure 3(a) is one of the schematic diagrams of the structure of the PE device in an embodiment of the present application;

[0069] Figure 3(b) is one of the schematic structural diagrams of device P in the embodiment of the present application;

[0070] Figure 4 It is a schematic diagram of forming a network and forwarding by using X-E technology in the embodiment of the present application;

[0071] Figure 5 It is a schematic diagram of the basic idea of BIP-8 in the embodiment of the present application;

[0072] Figure 6 It is one of the bit block stream error code detection methods in the embodiment of the present application;

[0073] Figure 7 It is a schematic diagram of the position and code pattern definition of the second boundary bit block in the embodiment of the present application;

[0074] Figure 8 It is a schematic diagram of inserting the first bit block in the embodiment of the present application;

[0075] Figure 9 It is a schematic diagram of the basic idea of 8BIP-8 in the embodiment of the present application;

[0076] Figure 10 It is a schematic diagram of the basic idea of 16BIP-4 in the embodiment of the present application;

[0077] Figure 11(a) is a schematic diagram of the basic idea of flexBIP-8 in the embodiment of the present application;

[0078] Figure 11(b) is a schematic diagram of the basic idea of flexBIP-9 in the embodiment of the present application;

[0079] Figure 12 It is the second bit block stream error code detection method in the embodiment of the present application;

[0080] Figure 13 It is the third bit block stream error code detection method in the embodiment of the present application;

[0081] Figure 14 It is a schematic diagram of the 64 / 66 bit stream in the embodiment of the present application;

[0082] Figure 15 It is a schematic diagram of the code pattern definition of the pure data block D in the embodiment of the present application;

[0083] Figure 16 It is a schematic diagram of the code pattern definition of the start block in the embodiment of the present application;

[0084] Figure 17 It is a schematic diagram of the code pattern definition of the end block in the embodiment of the present application;

[0085] Figure 18Schematic diagram of the first device storing the first verification result in the end block in the embodiment of this application;

[0086] Figure 19 Schematic diagram of the first device calculating the first verification result B using CRC-8 or BIP-8 and inserting it into the end block in the embodiment of this application;

[0087] Figure 20 Schematic diagram of the additional bit block before the first device inserts the first verification result B into the end block in the embodiment of this application;

[0088] Figure 21 The fourth method for bit block stream error detection in the embodiment of this application;

[0089] Figure 22 Schematic diagram of the second device deleting the first verification result B in the end block in the embodiment of this application;

[0090] Figure 23(a) is the second schematic diagram of the structure of the PE device in the embodiment of this application;

[0091] Figure 23(b) is the second schematic diagram of the structure of the P device in the embodiment of this application;

[0092] Figure 24 The first schematic diagram of the structure of the packet bearing product in the embodiment of this application;

[0093] Figure 25 The second schematic diagram of the structure of the packet bearing product in the embodiment of this application;

[0094] Figure 26 Schematic diagram of error checking where the path of the bit block stream to be verified is an end-to-end path in the embodiment of this application;

[0095] Figure 27(a) is the first schematic diagram of error checking where the path of the bit block stream to be verified is a non-end-to-end path in the embodiment of this application;

[0096] Figure 27(b) is the second schematic diagram of error checking where the path of the bit block stream to be verified is a non-end-to-end path in the embodiment of this application;

[0097] Figure 28 The first schematic diagram of the structure of the bit block stream error detection device in the embodiment of this application;

[0098] Figure 29 The second schematic diagram of the structure of the bit block stream error detection device in the embodiment of this application;

[0099] Figure 30 The third schematic diagram of the structure of the bit block stream error detection device in the embodiment of this application;

[0100] Figure 31This is the fourth schematic structural diagram of the bit block stream error detection device in the embodiments of the present application. Detailed implementation manners

[0101] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0102] The bit block mentioned in the embodiments of the present application is an M1 / M2 bit block. M1 / M2 bit represents a coding method. Among them, M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2 - M1 represents the number of header synchronization header bits in each bit block, M1 and M2 are positive integers, and M2 > M1.

[0103] It is this M1 / M2 bit block stream that is transmitted on the Ethernet physical layer link. For example, 1G Ethernet uses 8 / 10Bit coding, and the 1GE physical layer link transmits an 8 / 10Bit Block stream; 10GE / 40GE / 100GE uses 64 / 66Bit coding, and the 10GE / 40GE / 100GE physical layer link transmits a 64 / 66Bit Block stream. In the future, with the development of Ethernet technology, other coding methods may also appear, such as 128 / 130Bit coding, 256 / 258Bit coding, etc. For the convenience of description, the M1 / M2 bit block stream is uniformly used in the embodiments of the present application.

[0104] For the M1 / M2 bit block stream of L1.5 layer switching, there are different types of Bit Blocks and they are clearly specified in the standard. The following takes the code type definition of 64 / 66Bit coding as an example for illustration, as Figure 1 shown, where the 2 Bits "10" or "01" at the head are the 64 / 66Bit Block synchronization header bits, and the subsequent 64Bits are used to carry payload data or protocols. Figure 1 includes 16 code type definitions. Each line represents the code type definition of a bit block. Among them, D0 - D7 represent data bytes, C0 - C7 represent control bytes, S0 represents the start byte, T0 - T7 represent the end bytes. The second line corresponds to the code type definition of the idle block (IDLE Block), and the idle block can be represented by / I / . Specifically, as Figure 2 shown. The seventh line corresponds to the code type definition of the start block, and the start block can be represented by / s / . The ninth to sixteenth lines respectively correspond to the code type definitions of 8 end blocks, and the 8 end blocks can be uniformly represented by / T / .

[0105] Furthermore, in the X-E technology system, the M1 / M2 bit block stream is transmitted by using the devices shown in FIGS. 3(a) and 3(b). Specifically, as shown in FIGS. 3(a) and 3(b), it includes a PE device and a P device. Among them, the PE device represents an edge device, one end of which is connected to a user device, and the interface is the user-side interface (User network interface, UNI), and the other end is connected to a network device, and the interface is NNI. The P device represents a network device, and both ends are connected to network devices, and the interface is the interface between networks or between devices within a network (Network to Network interface, NNI).

[0106] Taking FIG. 3(a) as an example, the customer signal adaptation unit (uAdpt) represents the user-side processing unit of the X-E technology system, which is used to access user service signals and perform functions such as line code conversion and rate adaptation. The network signal adaptation unit (nAdpt) represents the network-side processing unit of the X-E technology system, which is used to send the service signals in the device to the network side and complete the corresponding functional processing; or receive the network-side service signals and transfer them to other processing units in the device. The L1.5 switch or X-Ethernet switch, that is, X-Ethernet Relay (i.e., the forwarding of intermediate nodes), is embodied as a switching unit.

[0107] As Figure 4 shown, it is a schematic diagram of building and forwarding a network by using the X-E technology, Figure 4 and the path shown therein is the X-E end-to-end forwarding path.

[0108] In addition, two common verification algorithms used in the embodiments of the present application are briefly introduced.

[0109] (1) BIP-x: Based on the BIP algorithm, the basic idea of this algorithm is to divide the signal to be verified into X verification blocks. For example, SDH uses BIP-16, BIP-8, BIP-2, and OTN uses BIP-8.

[0110] For example, refer to Figure 5As shown in the figure, the process of generating the 8-bit monitoring code shown in BIP-8 can be briefly described as follows: all the parts of the bit stream to be verified are divided into a series of 8-bit code groups in groups of 8 bits. Taking the BIP-8 code as the first column and the first 8-bit sequence as the second column, they are arranged in turn to form a monitoring matrix. Then, the first bit of each 8-bit sequence code group and the first bit of the BIP-8 code form the first monitoring code group (the first row of the matrix), the second bit of each 8-bit sequence code group and the second bit of the BIP-8 code form the second monitoring code group (the second row of the matrix), and so on. Finally, the first bit of the BIP-8 code provides even parity for the first monitoring code group (that is, makes the number of "1"s in the monitoring code group even), the second bit of the BIP-8 code provides even parity for the second monitoring code group, and so on. It should be noted that odd parity can also be used here.

[0111] (2) CRC-x: Based on the CRC algorithm, where the standardized algorithms include CRC-4, CRC-8, CRC-16, CRC-32, etc., an X-bit cyclic check is performed on the signal to be verified. CRC-32 is used for the frame or packet of Ethernet, and the CRC-32 result is stored in the last FCS field (4 bytes) of the frame or packet.

[0112] Refer to Figure 6 As shown in the figure, an embodiment of the present application proposes a method for detecting bit errors in a bit block stream to solve the problems of high implementation difficulty and low carrying efficiency of the bit error detection method in the scenario of M / N Bitblock switching. This method includes:

[0113] Step 600: Send the first boundary bit block, which is used to distinguish the subsequent N bit blocks, and N is a positive integer.

[0114] Step 610: Send the I-th bit block in turn, where I is an integer greater than or equal to 1 and less than or equal to N.

[0115] Step 620: Determine the first parity check result and the second parity check result. The verification object of the first parity check result includes consecutive m bits of each bit block among the N bit blocks, and the verification object of the second parity check result includes consecutive n bits of each bit block among the N bit blocks, and at least one of m and n is greater than or equal to 2.

[0116] Step 630: Send the second boundary bit block, the first parity check result, and the second parity check result. The second boundary bit block is used to distinguish the N bit blocks that have been sent.

[0117] It should be understood that when the path of the bit block stream to be verified is from the bit block sending end to the bit block receiving end, or when the path of the bit block stream to be verified is to any intermediate device before the bit block sending end to the bit block receiving end,Figure 6 The execution entity of each step can be the bit block sender. When the path of the bit block stream to be verified is from the bit block sender to the bit block receiver, the path of the bit block stream to be verified is an end-to-end path. When the path of the bit block stream to be verified is from the bit block sender to any intermediate device before the bit block receiver, the path of the bit block stream to be verified is a path with one end hanging. In this application, they are collectively referred to as the sending device.

[0118] Therefore, the embodiments of this application can not only be used for error code detection of end-to-end paths, but also for error code detection of non-end-to-end paths. For example, planned reserved paths, protection paths of 1:1 connection protection groups, or paths for other special purposes.

[0119] When the path of the bit block stream to be verified is from the first intermediate device after the bit block sender to the second intermediate device before the bit block receiver, Figure 6 The execution entity of each step can be the first intermediate device. The path of the bit block stream to be verified is a path with both ends hanging.

[0120] For steps 600, 610, and 630, the embodiments of this application provide the following two possible implementation manners:

[0121] The first possible implementation manner:

[0122] Send the first boundary bit block to the first device;

[0123] Send the I-th bit block to the first device in sequence;

[0124] Send the second boundary bit block, the first parity check result, and the second parity check result to the first device;

[0125] Therefore, in the above implementation manner, the first parity check result and the second parity check result are sent to the first device together with the two boundary bit blocks and the N bit blocks between the two boundary bit blocks. When the path of the bit block stream to be verified is from the bit block sender to the bit block receiver, the first device here can be the bit block receiver. When the path of the bit block stream to be verified is from the bit block sender to any intermediate device before the bit block receiver, or when the path of the bit block stream to be verified is from the first intermediate device after the bit block sender to the second intermediate device before the bit block receiver, the first device here can also refer to the intermediate device.

[0126] The second possible implementation manner:

[0127] Send the first boundary bit block to the first device;

[0128] Send the I-th bit block to the first device in sequence;

[0129] Send a second boundary bit block to a first device, and send a first parity check result and a second parity check result to a second device.

[0130] It should be noted that the second device here can be an SDN controller or any device with the function of judging bit error in bit stream transmission.

[0131] In addition, the two methods here can also be used simultaneously, that is, the first parity check result and the second parity check result are sent to both the first device and the second device.

[0132] Furthermore, it should be understood that the second boundary bit block is sent at a first moment, and the first parity check result and the second parity check result are sent at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

[0133] The check object of the first parity check result can be consecutive m bits of each of the N bit blocks, and the check object of the second parity check result can be consecutive n bits of each of the N bit blocks. In a possible implementation, the check object of the first parity check result may include, in addition to consecutive m bits of each of the N bit blocks, consecutive m bits of the first boundary bit block, or may also include consecutive m bits of the second boundary bit block; similarly, the check object of the second parity check result may include, in addition to consecutive n bits of each of the N bit blocks, consecutive n bits of the first boundary bit block, or may also include consecutive n bits of the second boundary bit block.

[0134] In a possible implementation, the first parity check result and the second parity check result can be stored in the second boundary bit block. Therefore, assuming that every N bit blocks in the bit block stream are grouped into one group, the i-th boundary bit block stores the first parity check result and the second parity check result corresponding to the i-th group of N bit blocks, and the (i + 1)-th boundary bit block stores the first parity check result and the second parity check result corresponding to the (i + 1)-th group of N bit blocks, where the (i + 1)-th group of N bit blocks are the bit blocks between the i-th boundary bit block and the (i + 1)-th boundary bit block, and i is a positive integer.

[0135] It should be understood that the boundary bit block mentioned in this application can be a newly inserted bit block. When a boundary bit block is newly inserted, a first bit block can be deleted, where the first bit block refers to a bit block that may be inserted into or deleted from the N bit blocks during the transmission of the N bit blocks. For example, for a 64 / 66 bit block stream, the first bit block can refer to an idle block.

[0136] As an alternative embodiment, as Figure 7 shown, taking the 64 / 66-bit block stream as an example, after determining the first parity check result and the second parity check result, the second boundary bit block is Figure 1 the bit block pattern definition corresponding to the 8th row in Figure 1 , that is, the type of the bit block is 0x4B, the O code of the bit block is 0x06, the first parity check result and the second parity check result are stored in 3 Data fields of the bit block, and the unoccupied Data field Bits are filled with binary 0. Therefore, the second boundary bit block is inserted after N bit blocks, and at the same time, in order to reduce the impact on the user bandwidth, an idle block can be deleted.

[0137] When considering that the M1 / M2-bit block stream traverses an asynchronous node (that is, the receive clock is not necessarily completely synchronized with the node clock and the transmit clock) during transmission, generally, the first bit block is inserted or deleted to eliminate the frequency impact. For example, the 64 / 66-bit block stream is implemented by inserting or deleting an IDLE Block, as Figure 8 shown. Therefore, when determining the first parity check result and the second parity check result in step 620, if the existing BIP-x algorithm is used, the first parity check result and the second parity check result will be affected due to the insertion or deletion of the first bit block during transmission.

[0138] In the embodiment of the present application, the first parity check result and the second parity check result are calculated according to a preset check algorithm, and the preset check algorithm is used to ensure that the first parity check result and the second parity check result do not change when the first bit block is added or reduced in N bit blocks.

[0139] Specifically, to ensure that the first parity check result and the second parity check result can tolerate the insertion or deletion of one or more first bit blocks (such as an IDLE Block) during transmission, and can also be detected when the first bit block has an error, the present application has modified the existing BIP algorithm, which may include but is not limited to the following two algorithms:

[0140] Algorithm 1: The preset check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, y≥2.

[0141] Starting from the first payload bit in N bit blocks, each x consecutive bits of each bit block are sequentially recorded into the first monitoring section to the yth monitoring section; for each monitoring section, an odd parity check or an even parity check is used to determine 1-bit monitoring code, and y-bit monitoring code is obtained, and the y-bit monitoring code includes the first parity check result and the second parity check result.

[0142] It should be understood that when calculating the first parity check result and the second parity check result, the synchronization bit headers in each bit block are not included.

[0143] As an alternative embodiment, for example Figure 9 As shown, the existing BIP-x algorithm can be regarded as a special case of the xBIP-y algorithm (i.e., the scenario where x = 1). Figure 8 It is a schematic diagram of the 64 / 66Bit Block using the 8BIP-8 algorithm. Among them, B0 to B7 are 8 monitoring codes (also called parity check codes) included in the 8BIP-8 algorithm. Each monitoring code corresponds to a monitoring section, providing odd or even parity check for the bits included in the corresponding monitoring section. Each monitoring section corresponds to 8 consecutive bits of each bit block. For example, the first monitoring section corresponds to the first payload bit to the eighth payload bit of each bit block, the second monitoring section corresponds to the ninth payload bit to the sixteenth payload bit of each bit block, ……, the eighth monitoring section corresponds to the fifty-seventh payload bit to the sixty-fourth payload bit of each bit block. Specifically, for the inserted IDLE Block, the first byte is 0x1e and the others are 0. The first byte of the IDLE Block enters the first monitoring section of the 8BIP-8, and the other bytes enter the second to eighth monitoring sections. 0x1e has 4 binary 1s, and the other fields are 0 with 0 binary 1s. Therefore, no matter how many IDLE Blocks are inserted or deleted during the transmission process, the parity check results of B0 to B7 are not affected.

[0144] As an alternative embodiment, for example Figure 10 As shown Figure 10 It is a schematic diagram of the 64 / 66Bit Block using the 16BIP-4 algorithm. Among them, B0 to B3 are 4 monitoring codes (also called parity check codes) included in the 16BIP-4 algorithm. Each monitoring code corresponds to a monitoring section, providing odd or even parity check for the bits included in the corresponding monitoring section. Each monitoring section corresponds to 16 consecutive bits of each bit block. For example, the first monitoring section corresponds to the first payload bit to the sixteenth payload bit of each bit block, the second monitoring section corresponds to the seventeenth payload bit to the thirty-second payload bit of each bit block, the third monitoring section corresponds to the thirty-third payload bit to the forty-eighth payload bit of each bit block, and the fourth monitoring section corresponds to the forty-ninth payload bit to the sixty-fourth payload bit of each bit block.

[0145] Algorithm 2: The preset check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of continuously bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of continuously bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A3 …… Az-1, Az, A1, A2, A3 …… Az-1, Az, and z is a positive integer, z≥2.

[0146] Starting from the first payload bit in the N bit blocks, record A1 consecutive bits in each bit block to the first monitoring section, record A2 consecutive bits after the A1 consecutive bits to the second monitoring section, record A3 consecutive bits after the A2 consecutive bits to the third monitoring section, until recording Az consecutive bits after the Az-1 consecutive bits to the zth monitoring section; for each monitoring section, use odd parity or even parity to determine 1-bit monitoring code, and obtain z-bit monitoring code, where the z-bit monitoring code includes the first parity check result and the second parity check result.

[0147] As an optional implementation example, as shown in Fig. 11(a), Fig. 11(a) is a schematic diagram of the 64 / 66 Bit Block using the flexBIP-8 algorithm. Among them, B0 to B7 are 8 monitoring codes included in the flexBIP-8 algorithm. Each monitoring code corresponds to a monitoring section and provides odd parity or even parity for the bits included in the corresponding monitoring section. The first monitoring section corresponds to the first payload bit to the eighth payload bit of each bit block, the second monitoring section corresponds to the ninth payload bit to the eighteenth payload bit of each bit block, the third monitoring section corresponds to the nineteenth payload bit to the twenty-fourth payload bit of each bit block, the fourth monitoring section corresponds to the twenty-fifth payload bit to the thirty-third payload bit of each bit block, the fifth monitoring section corresponds to the thirty-fourth payload bit to the fortieth payload bit of each bit block, the sixth monitoring section corresponds to the forty-first payload bit to the forty-eighth payload bit of each bit block, the seventh monitoring section corresponds to the forty-ninth payload bit to the fifty-eighth payload bit of each bit block, and the eighth monitoring section corresponds to the fifty-ninth payload bit to the sixty-fourth payload bit of each bit block.

[0148] As an alternative embodiment, as shown in FIG. 11(b), FIG. 11(b) is a schematic diagram of the 64 / 66Bit Block using the flexBIP-9 algorithm. Among them, B0 to B8 are 9 monitoring codes included in the flexBIP-9 algorithm. Each monitoring code corresponds to a monitoring section, and provides odd parity or even parity for the bits included in the corresponding monitoring section. The first monitoring section corresponds to the first payload bit to the eighth payload bit of each bit block. The second monitoring section corresponds to 7 bits from the 9th payload bit to the 15th payload bit of each bit block. The third monitoring section corresponds to 7 bits from the 16th payload bit to the 22nd payload bit of each bit block. The fourth monitoring section corresponds to 7 bits from the 23rd payload bit to the 29th payload bit of each bit block. The fifth monitoring section corresponds to 7 bits from the 30th payload bit to the 36th payload bit of each bit block. The sixth monitoring section corresponds to 7 bits from the 37th payload bit to the 43rd payload bit of each bit block. The seventh monitoring section corresponds to 7 bits from the 44th payload bit to the 50th payload bit of each bit block. The eighth monitoring section corresponds to 7 bits from the 51st payload bit to the 57th payload bit of each bit block. The ninth monitoring section corresponds to 7 bits from the 58th payload bit to the 64th payload bit of each bit block.

[0149] When determining the first parity check result and the second parity check result in step 620, the check object of the first parity check result includes N bit blocks and the bit blocks in the first boundary described in step 600. Any one of the continuous 9 groups of bits of each bit block enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the first parity check result. The check object of the second parity check result includes N bit blocks and the bit blocks in the first boundary described in step 600. Any one of the other 8 groups of the continuous 9 groups of bits of each bit block except the group selected by the first parity check result enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the second parity check result.

[0150] When determining the first parity check result and the second parity check result in step 620, the check object of the first parity check result includes N bit blocks and the bit blocks in the second boundary described in step 630. Any one of the continuous 9 groups of bits of each bit block enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the first parity check result. The check object of the second parity check result includes N bit blocks and the bit blocks in the second boundary described in step 630. Any one of the other 8 groups of the continuous 9 groups of bits of each bit block except the group selected by the first parity check result enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the second parity check result.

[0151] When determining the third parity check result and the fourth parity check result in step 1230 below, the objects of the third parity check result include T bit blocks and the bit blocks in the first boundary described in step 1200. Any one of the consecutive 9 groups of bits in each bit block enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the third parity check result. The objects of the fourth parity check result include T bit blocks and the bit blocks in the first boundary described in step 600. Any one of the other 8 groups of the consecutive 9 groups of bits in each bit block except the group selected by the third parity check result enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the fourth parity check result.

[0152] When determining the third parity check result and the fourth parity check result in step 1230, the objects of the third parity check result include T bit blocks and the bit blocks in the second boundary described in step 1220. Any one of the consecutive 9 groups of bits in each bit block enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the third parity check result. The objects of the fourth parity check result include T bit blocks and the bit blocks in the second boundary described in step 1220. Any one of the other 8 groups of the consecutive 9 groups of bits in each bit block except the group selected by the third parity check result enters the corresponding check area of the flexBIP-9 algorithm, and finally forms the fourth parity check result.

[0153] Specifically, the inserted bit block is an idle block (IDLE Block), the first byte is 0x1e, and the others are 0. The first byte of the IDLEBlock enters the first monitoring section of flexBIP-9, and the others are grouped by 7 consecutive bits and enter the 2nd to 9th monitoring sections. 0x1e has 4 binary 1s, and the other fields are 0, with 0 binary 1s. Therefore, no matter how many IDLE Blocks are inserted or deleted during the transmission process, the check results of B0 to B8 are not affected.

[0154] Specifically, when the inserted bit block is a low-power idle block (LPI Block), the first byte is 0x1e, and the others are grouped into 8 groups by 7 bits, and each group is 0x6. The first byte of the LPI enters the first monitoring section of flexBIP-9, and the others are grouped by 7 consecutive bits and enter the 2nd to 9th monitoring sections. 0x1e has 4 binary 1s, and the other 7-bit fields are 0x6, with 2 binary 1s. Therefore, no matter how many LPI Blocks are inserted or deleted during the transmission process, the check results of B0 to B8 are not affected.

[0155] Specifically, when the inserted bit block is an error block, the first byte is 0x1e, and the others are divided into 8 groups according to 7 bits, with each group being 0x1e. The first byte of the LPI enters the first monitoring section of flexBIP-9, and the others are grouped according to consecutive 7 bits and enter the 2nd to 9th monitoring sections. Since 0x1e has 4 binary 1s, the verification results of B0 to B8 are not affected regardless of how many ERROR Blocks are inserted or deleted during the transmission process.

[0156] Therefore, as can be seen from the two preset algorithms provided above, the y-bit monitoring code obtained through Algorithm 1 can be used as the first set of verification results, or the z-bit monitoring code obtained through Algorithm 2 can be used as the first set of verification results. When sending the first parity verification result and the second parity verification result, all the obtained verification results, that is, the first set of verification results, can be sent simultaneously.

[0157] Refer to Figure 12 As shown, an embodiment of the present application proposes a method for detecting bit error in a bit block stream to solve the problems of high implementation difficulty and low carrying efficiency of the bit error detection method in the scenario of M / N Bitblock exchange. The method includes:

[0158] Step 1200: Receive the first boundary bit block, which is used to distinguish the subsequent T bit blocks received, where T is a positive integer.

[0159] Step 1210: Sequentially receive the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to T.

[0160] Step 1220: Receive the second boundary bit block, which is used to distinguish the T bit blocks that have been received.

[0161] Step 1230: Determine the third parity verification result and the fourth parity verification result. The verification object of the third parity verification result includes consecutive m bits of each bit block in the T bit blocks, and the verification object of the fourth parity verification result includes consecutive n bits of each bit block in the T bit blocks, where at least one of m and n is greater than or equal to 2.

[0162] Step 1240: When the first parity check result and the second parity check result are received, determine whether there are error bits in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result. The objects of verification of the first parity check result include consecutive m bits of each of the N bit blocks, and the objects of verification of the second parity check result include consecutive n bits of each of the N bit blocks. N is the number of bit blocks between the first boundary bit block and the second boundary bit block when determining the first parity check result and the second parity check result.

[0163] It should be understood that when the path of the bit block stream to be verified is from the bit block sending end to the bit block receiving end, Figure 12 the execution entity of each step in can be the bit block receiving end. When the path of the bit block stream to be verified is any intermediate device before the bit block sending end to the bit block receiving end, or when the path of the bit block stream to be verified is from the bit block sending end to the bit block receiving end, Figure 12 the execution entity of each step in can be the intermediate device. In this application, they are collectively referred to as the receiving device.

[0164] It should be noted that the N bit blocks here are the bit blocks between the first boundary bit block and the second boundary bit block when the sending device determines the first parity check result and the second parity check result.

[0165] As an optional embodiment, after the sending device sends the first boundary bit block, it sequentially sends N bit blocks, then calculates the first parity check result and the second parity check result according to these N bit blocks, stores these two results in the second boundary bit block, and sends the second boundary bit block. However, considering that the first bit block may be inserted or deleted in the N bit blocks due to passing through asynchronous nodes in the path from the sending device to the receiving device, after the receiving device receives the first boundary bit block, it sequentially receives T bit blocks. At this time, there may be three situations: N = T, or N > T (that is, the first bit block is inserted in the N bit blocks), or N < T (that is, the first bit block is deleted in the N bit blocks).

[0166] In a possible implementation, when the first parity check result and the second parity check result are not received, the third parity check result and the fourth parity check result are sent to the second device, where the second device stores the first parity check result and the second parity check result. It should be noted that the second device here can be an SDN controller or any device with the function of judging bit stream transmission error codes. In addition, when the first parity check result and the second parity check result are received, the third parity check result and the fourth parity check result can also be sent to the second device. Therefore, the second device can receive the first parity check result and the second parity check result sent by the sending device, as well as the third parity check result and the fourth parity check result sent by the receiving device, and the second device determines whether there is an error code in the transmission process of the bit block stream according to the two sets of results.

[0167] In a possible implementation, the second boundary bit block is received at the first moment, and the first parity check result and the second parity check result are received at the second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

[0168] The check object of the third parity check result can be m consecutive bits of each of the T bit blocks, the check object of the fourth parity check result can be n consecutive bits of each of the T bit blocks, the check object of the first parity check result can be m consecutive bits of each of the N bit blocks, and the check object of the second parity check result can be n consecutive bits of each of the N bit blocks. In a possible implementation, the check object of the third parity check result can include, in addition to m consecutive bits of each of the T bit blocks, m consecutive bits of the first boundary bit block, or m consecutive bits of the second boundary bit block; similarly, the check object of the fourth parity check result can include, in addition to n consecutive bits of each of the T bit blocks, n consecutive bits of the first boundary bit block, or n consecutive bits of the second boundary bit block. The check object of the first parity check result can include, in addition to m consecutive bits of each of the N bit blocks, m consecutive bits of the first boundary bit block, or m consecutive bits of the second boundary bit block; similarly, the check object of the second parity check result can include, in addition to n consecutive bits of each of the N bit blocks, n consecutive bits of the first boundary bit block, or n consecutive bits of the second boundary bit block.

[0169] When the check object of the first parity check result includes m consecutive bits of the first boundary bit block, the check object of the third parity check result also needs to include m consecutive bits of the first boundary bit block; when the check object of the first parity check result includes m consecutive bits of the second boundary bit block, the check object of the third parity check result also needs to include m consecutive bits of the second boundary bit block; when the check object of the second parity check result includes n consecutive bits of the first boundary bit block, the check object of the fourth parity check result also needs to include n consecutive bits of the first boundary bit block; when the check object of the second parity check result includes n consecutive bits of the second boundary bit block, the check object of the fourth parity check result also needs to include n consecutive bits of the second boundary bit block.

[0170] In a possible implementation manner, the first parity check result and the second parity check result are stored in the second boundary bit block.

[0171] In a possible implementation manner, the specific method for the receiving device to determine whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result is as follows: if it is determined that the first parity check result is the same as the third parity check result, and the second parity check result is the same as the fourth parity check result, it is determined that there is no error in the T bit blocks; if it is determined that the first parity check result is different from the third parity check result, and / or the second parity check result is different from the fourth parity check result, it is determined that there is an error in the T bit blocks.

[0172] In addition, it should be understood that the preset algorithm used by the receiving device to determine the third parity check result and the fourth parity check result is the same as the preset algorithm used by the sending device to determine the first parity check result and the second parity check result, and the repeated parts will not be elaborated here.

[0173] In a possible implementation manner, if the receiving device receives a first check result set, the first check result set is calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the first check result set includes the first parity check result and the second parity check result. Then the receiving device needs to determine a second check result set, the second parity check result is calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the second check result set includes the third parity check result and the fourth parity check result. Further, the receiving device determines whether there is an error in the T bit blocks according to the first check result set and the second check result set.

[0174] In a possible implementation, if the receiving device receives a first set of verification results, where the first set of verification results is calculated according to the flexBIP–z algorithm and the z-bit monitoring codes included in the first set of verification results include a first parity check result and a second parity check result. Then the receiving device needs to determine a second set of verification results, where the second set of verification results is calculated according to the flexBIP–z algorithm and the z-bit monitoring codes included in the second set of verification results include a third parity check result and a fourth parity check result. Further, the receiving device determines whether there are error codes in the T bit blocks according to the first set of verification results and the second set of verification results.

[0175] Specifically, the receiving device determines whether there are error codes in the T bit blocks according to the first set of verification results and the second set of verification results, including the following two possible cases:

[0176] (1) If it is determined that the first set of verification results is the same as the second set of verification results, it is determined that there are no error codes in the T bit blocks;

[0177] (2) If it is determined that the first set of verification results is different from the second set of verification results, it is determined that there are error codes in the T bit blocks.

[0178] By using the method provided in the embodiments of the present application, the error or error code detection of the M / N Bit Block network path can be fully implemented without affecting the user service, with a bearing efficiency of 100%. It can tolerate the bit blocks inserted or deleted due to synchronization problems during the transmission process, and the detection period (i.e., the number of bit blocks between two boundary bit blocks) and the detection accuracy (i.e., the preset algorithm) can be dynamically configured according to demand. In addition, this detection method can be used not only for the path of the bit block stream to be verified as an end-to-end path, but also for the path of the bit block stream to be verified as a non-end-to-end path.

[0179] Refer to Figure 13 As shown, the embodiments of the present application propose a method for detecting bit block stream error codes to solve the problems of high implementation difficulty and low bearing efficiency of the error code detection method in the scenario of M / N Bitblock switching. The method includes:

[0180] Step 1300: The first device determines the detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream.

[0181] As Figure 14 shown, for a 64 / 66-bit stream, the user service starts with the start block / S / marker and ends with the end block / T / marker, and the middle D is a pure data block, specifically as Figure 15 shown. As Figure 1 shown in, the 7th row corresponds to the pattern definition of the start block, and S0 represents the start byte, specifically asFigure 16 As shown, lines 9 to 16 respectively correspond to the code pattern definitions of 8 end blocks. T0 to T7 represent end bytes. Specifically, as Figure 17 shown, taking the end block including T0 as an example, the detected section is the bytes between S0 and T0.

[0182] Step 1310: The first device calculates a first verification result according to the detected section.

[0183] The algorithm used by the first device when calculating the first verification result can be CRC-x or BIP-x. The result of the first verification result is denoted as B, and B can be one or more bytes.

[0184] Step 1320: The first device sends the first verification result and the bit block stream.

[0185] Regarding step 1320, the first device sending the first verification result and the bit block stream may specifically include the following two possible implementation manners:

[0186] The first possible implementation manner: The first device sends the first verification result and the bit block stream to the second device.

[0187] The second possible implementation manner: The first device sends the first verification result to the third device and sends the bit block stream to the second device.

[0188] It should be noted that the first device here is the bit block sending end, the second device is the bit block receiving end, and the third device is the SDN controller, or any device with the function of judging bit stream transmission error codes.

[0189] In a possible implementation manner, before the first device sends the first verification result and the bit block stream to the second device, the first device needs to store the calculated first verification result, including the following two possible storage manners:

[0190] The first storage manner: The first device stores the first verification result in the end block to obtain an updated end block.

[0191] As Figure 18 shown, the first device storing the first verification result in the end block specifically includes the following two scenarios:

[0192] Scenario 1: When the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, the first device stores the first verification result before the end byte in the end block, and moves the end byte to a new block after the end block according to the number of bytes occupied by the first verification result, deletes any first bit block in the bit block stream, and takes the new block where the end byte is located after moving as the updated end block. The target number of bytes is the number of bytes after the end byte in the end block plus 1.

[0193] Scenario 2: When the number of bytes occupied by the first verification result is less than the target number of bytes, the first device stores the first verification result before the end byte in the end block, and moves the end byte backward by the number of bytes occupied by the first verification result according to the number of bytes occupied by the first verification result, and uses the bit block where the end byte is located after being moved as the updated end block. Wherein, the target number of bytes is the number of bytes after the end byte in the end block plus 1.

[0194] As an optional embodiment, as Figure 19 shown, when the first device calculates the first verification result B using CRC-8 or BIP-8, B only occupies 1 BYTE.

[0195] When B is not inserted into the end block, if the end block is D0 D1 D2 D3 D4 D5 D6 T7, the target number of bytes is 1. After inserting B, it is updated to D0 D1 D2 D3 D4 D5 D6 B, and then an additional Block is added, and the updated end block is T0 C1 C2 C3 C4 C5 C6 C7.

[0196] When B is not inserted into the end block, if the end block is T0 C1 C2 C3 C4 C5 C6 C7, the target number of bytes is 8. After inserting B, the updated end block is B T1 C1 C2 C3 C4 C5 C6. Similarly, when B is not inserted into the end block, if the end bytes included in the end block are T1 to T6 respectively, after inserting B, they are correspondingly updated to T2 to T7.

[0197] The second storage method: The first device stores the first verification result in the verification result storage block and deletes any first bit block in the bit block stream. The verification result storage block refers to a newly added block before the end block, and the first bit block refers to a bit block that may be inserted into the bit block stream or deleted from the bit block stream during the transmission of the bit block stream.

[0198] For example, before the end block, next to the end block, a data block is separately allocated for storing the first verification result B calculated using CRC-x or BIP-x, with the type D0 D1 D2 D3 D4 D5 D6 D7, corresponding to Figure 1 the code pattern definition corresponding to the first line in. D0 to D7 are used to store the calculation result B. When inserting B, in order to reduce the impact on the user bandwidth, one IDLE Block (the block marked with / I / ) after / T / Block is deleted. As Figure 20 shown, B occupies a separate Block, and 1 IDLE Block after / T / is deleted.

[0199] Refer to Figure 21As shown in the figure, an error code detection method for bit block streams is proposed in an embodiment of the present application to solve the problems of high implementation difficulty and low carrying efficiency of the error code detection method in the scenario of M / N Bitblock exchange. The method includes:

[0200] Step 2100: The second device determines the detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream.

[0201] Regarding step 2100, the second device determines the detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream, including the following three specific situations:

[0202] Situation 1: When the second device receives the first verification result and the first verification result is stored in the end block, the second device deletes the second verification result from the end block to obtain the updated end block, and takes the bytes between the start byte in the start block and the end byte in the updated end block as the detected section.

[0203] Situation 2: When the second device receives the first verification result and the first verification result is stored in the verification result storage block, the second device deletes the verification result storage block from the bit block stream to obtain the updated bit block stream, and takes the bytes between the start byte in the start block and the end byte in the end block in the updated bit block stream as the detected section, where the verification result storage block is located before the end block.

[0204] In the above two situations, the bytes between the start byte in the start block and the end byte in the end block include the first verification result. Therefore, it is necessary to first delete the first verification result and take the remaining part as the detected section.

[0205] Situation 3: When the second device does not receive the first verification result, the second device takes the bytes between the start byte in the start block and the end byte in the end block in the bit block stream as the detected section.

[0206] At this time, the bytes between the start byte in the start block and the end byte in the end block do not include the first verification result and can be directly used as the detected section.

[0207] Specifically, in a possible implementation manner, when the second device does not receive the first verification result, the second device sends the second verification result to the third device, and the third device stores the first verification result. The third device is an SDN controller or any device with the function of judging bit stream transmission error codes.

[0208] Step 2110: The second device calculates the second verification result according to the detected section.

[0209] Similarly, the algorithm used by the second device to calculate the second verification result is the same as the algorithm used by the first device to calculate the first verification result.

[0210] Step 2120: When the second device receives the first verification result, the second device determines whether there is an error code in the detected section according to the first verification result and the second verification result.

[0211] Specifically, if the second device determines that the first verification result is the same as the second verification result, it determines that there is no error code in the detected section. If it determines that the first verification result is different from the second verification result, it determines that there is an error code in the detected section.

[0212] Further, the second device deletes the first verification result from the end block to obtain an updated end block, which specifically includes the following two scenarios:

[0213] Scenario 1: When the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, the second device moves the end byte to a bit block before the end block according to the number of bytes occupied by the first verification result, adds a first bit block to the bit block stream, and uses the bit block where the end byte is located after moving as the updated end block. The target number of bytes is the number of bytes before the end byte in the end block plus 1.

[0214] Scenario 2: When the number of bytes occupied by the first verification result is less than the target number of bytes, the first device moves the end byte forward by the number of bytes occupied by the first verification result, and uses the bit block where the end byte is located after moving as the updated end block. The target number of bytes is the number of bytes before the end byte in the end block plus 1.

[0215] As Figure 22 shown, when the first device calculates the first verification result B using CRC-8 or BIP-8, B only occupies 1 BYTE.

[0216] When the end block is B T1 C1 C2 C3 C4 C5 C6, the target number of bytes is 2. After deleting B, the updated end block is T0 C1 C2 C3 C4 C5 C6 C7. Similarly, if the end bytes included in the end block are T2 to T7 respectively, after deleting B, they are correspondingly updated to T1 to T6.

[0217] When the end block is T0 C1 C2 C3 C4 C5 C6 C7, the data block immediately before the end block is D0 D1 D2D3 D4 D5 D6 B, and the target number of bytes is 1. After deleting B, the updated end block is D0 D1 D2 D3 D4 D5 D6T7.

[0218] In addition, when the second device receives the first verification result and the first verification result is stored in the verification result storage block, the second device deletes the verification result storage block from the bit block stream to obtain an updated bit block stream, where the verification result storage block is located before the end block. At the same time, in order to reduce the impact on the user's bandwidth, a first bit block needs to be added after the end block.

[0219] The method provided by the embodiments of the present application can completely implement the error or error code detection of the M / N Bit Block network path, has little impact on user services, is close to SDH / OTN, is superior to the existing packet detection methods, and has a simple and easy-to-implement implementation process.

[0220] The embodiments of the present application propose a new device for transmitting the M1 / M2 bit block stream. A new error code detection unit, also known as a Bit Error Ratio (BER) unit, is added to the device, abbreviated as BER. This unit is used to calculate the verification result and perform error code detection.

[0221] The PE device includes uAdpt, L1.5 Switch, nAdpt, and BER. One end of it is connected to the user device, and the interface is UNI. The other end is connected to the network device, and the interface is NNI. The P device includes uAdpt, L1.5 Switch, nAdpt, and BER, and both ends are connected to the network device, and the interface is NNI, as shown in Figures 23(a) and 23(b).

[0222] The embodiments of the present application also propose a packet bearing product, such as an IPRAN or PTN device planned to load the X-E feature. Refer to Figure 24 As shown, for a packet bearing product provided by the present application, the interface board here can be the interface card of a box-type device or the interface chip of a line card of a frame-type device.

[0223] Alternatively, the embodiments of the present application also propose a packet bearing product. Refer to Figure 25 As shown, the present application provides a new type of chip, such as SDxxxx, with BER built into the chip; or between an existing interface chip, such as SDyyyy and the main control switching board, a Field-Programmable Gate Array (FPGA) or a Network Processor (NP) is added to implement the function of BER through the FPGA or NP.

[0224] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0225] As an optional embodiment, refer to Figure 26 As shown, the path of the bit block stream to be verified is an end-to-end path.

[0226] Embodiment 1: Taking the user-side interface (UNI) as 1GE, the network-side interface (NNI) as 100GE, three-terminal X-E devices XE1, XE2, XE3, the switching granularity of the L1.5Switch and the network-side signal flow as 64 / 66Bit Block flow, and inserting an 8BIP-8 check result every 1024 Blocks on the user side of XE1 as an example to illustrate Figure 26 the embodiments shown.

[0227] STEP 1: The 1GE user signal enters the XE1 device from the UNI side. The uAdpt transcodes the 8 / 10BitBlock into 64 / 66Bit Block, that is, 8 1GE user signals without 2Bit synchronization headers are assembled into 1 64Bit string in sequence, and then 2Bit synchronization headers are added to form 1 64 / 66Bit block. In this way, a 64 / 66Bit Block flow is finally formed. The BER counts the Blocks in the bit block flow from the uAdpt side, inserts a first boundary bit block before the first bit block, and calculates the first check result set using the 8BIP-8 algorithm. When the number of Blocks reaches 1024, as the first group of Blocks, the first check result set is stored in a bit block identified by 4B and 06 and inserted after the 1024th bit block as the second boundary bit block. At the same time, an IDLE Block in the bit block flow is deleted. The bit block flow after BER processing enters the L1.5 Switch and then enters the nAdpt and is sent to the network side.

[0228] It should be noted that the BER continues to count the Blocks and calculates the first check result set of the second group of Blocks using the 8BIP-8 algorithm, which is the same as the processing method of the first group of Blocks. Then, the first check result set of the second group of Blocks is stored in a bit block identified by 4B and 06 and inserted after the 2048th bit block as the third boundary bit block. The BER repeats the above process until the bit block flow ends.

[0229] STEP 2: The bit block flow sent by X1 is transmitted to the nAdpt of XE2. The receiving clock frequency is slower than the system clock of XE1. The nAdpt of X2 needs to insert one or more IDLE Blocks when sending to the L1.5 Switch to tolerate the transmission speed problem caused by the clock frequency asynchronization, and then transmits it to the direction of the network-side XE3.

[0230] STEP 3: The bit block stream sent by X2 is transmitted to XE3. After passing through nAdpt and L1.5 Switch, it reaches the BER unit on the UNI side. When the BER receives the first boundary bit block, it starts to perform 8BIP-8 parity check calculation on the subsequent received bit block stream. When it receives the second boundary bit block inserted by XE1, the BER stops the calculation and takes the bit blocks between the first boundary bit block and the second boundary bit block as the first group of Blocks. The BER compares the second check result set obtained from the current calculation with the first check result set stored in the second boundary bit block. If they are consistent, there is no error; if they are inconsistent, it counts and stores the number of error bits. At the same time, it deletes the second boundary bit block from the bit block stream and inserts an IDLE Block. After the bit block stream is processed by the BER and reaches uAdpt, it removes 2 synchronization header Bits, divides 64 Bits into 8 groups of 8 Bits, adds 2 Bits of synchronization header to each group, and sends them to the UNI link in sequence.

[0231] It should be noted that the BER continues to count the Blocks and uses the 8BIP-8 algorithm to calculate the second check result set of the second group of Blocks. The second group of Blocks is the bit blocks between the second boundary bit block and the third boundary bit block. When it receives the third boundary bit block inserted by XE1, the BER stops the calculation. The processing method is the same as that of the first group of Blocks. The BER compares the second check result set of the current calculated second group of Blocks with the first check result set of the second group of Blocks stored in the third boundary bit block. If they are consistent, there is no error; if they are inconsistent, it counts and stores the number of error bits. The BER repeats the above process until the bit block stream ends.

[0232] Therefore, the user signal enters XE1, is transmitted through XE2, and flows out of the network from XE3. The xBIP-y error detection is completely implemented on the entire end-to-end path, and the implementation method is simple. The Blocks carrying the xBIP-y results are compensated by adding and deleting IDLE Blocks, which has no impact on the user service, and the carrying efficiency is 100%. During the transmission process, there are cases of IDLE Block insertion or deletion when passing through asynchronous nodes. The xBIP-y algorithm tolerates this scenario and ensures the accuracy and effectiveness of the check results.

[0233] In addition, the above-mentioned 8BIP-8 algorithm can be calculated and replaced with the flexBIP-z algorithm.

[0234] The xBIP-y algorithm and the flexBIP-y algorithm are significantly superior to the static rigid methods of ETHERNET, SDH, and OTN that occupy fixed bytes. With the compensation of the first bit block, there is no impact on user signals. However, the error code or error detection of the existing ETHERNET, SDH, and OTN occupies fixed bytes and consumes user bandwidth. As an optional embodiment, referring to FIGS. 27(a) and 27(b), the path of the bit block stream to be verified is a non-end-to-end path.

[0235] It should be noted that the unit that calculates the first set of verification results and inserts the second boundary bit block at the start end of the path shown in FIG. 27(a) is the BER on the nAdpt unit side, and the unit that calculates the second set of verification results and deletes the second boundary bit block at the end of this path segment is the BER on the nAdpt unit side;

[0236] In addition, there is no insertion and extraction of user signals in the path shown in FIG. 27(a), that is, there is no need for the uAdpt at both ends to perform related operations.

[0237] The unit that calculates the first set of verification results and inserts the second boundary bit block at the start end of the path shown in FIG. 27(b) is the BER on the uAdpt unit side, and the unit that calculates the second set of verification results and deletes the second boundary bit block at the end of this path segment is the BER on the nAdpt unit side;

[0238] In addition, the bit block stream in the path shown in FIG. 27(b) does not flow to the L1.5 Switch element and the uAdpt unit at the end.

[0239] Embodiment 2: Taking the user-side interface (UNI) as 1GE, the network-side interface (NNI) as 100GE, three-terminal X-E devices XE1, XE2, XE3, the switching granularity of the L1.5Switch, and the network-side signal flow as 64 / 66Bit Block stream, and taking the insertion of a BIP-8 result B1 into the end block on the user side of XE1 as an example to illustrate Figure 26 the embodiment shown.

[0240] STEP 1: One GE user signal enters the XE1 device from the UNI side. The uAdpt transcodes the 8 / 10 Bit Block into a 64 / 66 Bit Block, that is, it assembles 8 1GE user signals without 2-bit synchronization headers into a 64-bit string in sequence, and then adds 2-bit synchronization headers to form a 64 / 66 Bit block. In this way, a 64 / 66 Bit Block stream is finally formed. The BER identifies the bit block stream coming from the uAdpt side, starts BIP-8 calculation from the block marked with the start block / S / , stops the calculation when it receives the block marked with the end block / T / , inserts the result B1 before / T / , and modifies the pattern of / T / at the same time. The bit block stream after being processed by the BER enters the L1.5 Switch and then enters the nAdpt and is sent to the network side.

[0241] It should be noted that the BER continues to identify the bit block stream coming from the uAdpt side and repeats the above process until the bit block stream ends.

[0242] STEP 2: The bit block stream sent by X1 is transmitted to the nAdpt of XE2. The receiving clock frequency is lower than the system clock of XE1. When the nAdpt of X2 sends it to the L1.5 Switch, one or several IDLE Blocks need to be deleted to tolerate the transmission speed problem caused by the asynchronous clock frequency, and then it is transmitted to the direction of XE3 on the network side.

[0243] STEP 3: The bit block stream sent by X2 is transmitted to XE3, passes through the nAdpt and L1.5 Switch, and reaches the BER unit on the UNI side; the BER identifies the bit block stream, starts BIP-8 calculation from the block marked with the start block / S / , stops the calculation before the result B1 in the end block when it receives the block marked with the end block / T / , deletes the result B1, and modifies the pattern of / T / at the same time. The BER compares the currently calculated result B2 with the result B1. If they are the same, there is no error code; if they are different, it counts the number of error codes and stores them. After the bit block stream is processed by the BER and reaches the uAdpt, 2 synchronization header bits are removed, the 64 bits are divided into 8 8-bit groups, 2-bit synchronization headers are added to each group, and they are sent to the UNI link in sequence.

[0244] In addition, the above-mentioned BIP-8 algorithm can be calculated and replaced with the CRC-8 algorithm.

[0245] Therefore, the user signal enters XE1, is transmitted through XE2, and flows out of the network from XE3. The CRC or BIP error detection is fully implemented on the entire end-to-end path, and the implementation method is simple; the bearing efficiency is improved compared with the existing Ethernet, and is close to SDH and OTN, but compared with Figure 26There is a certain gap from Embodiment 1 shown;

[0246] In addition, if in STEP 1, BER inserts the result B1 into an independent block before / T / Block, and at the same time, by deleting the IDLE Block after / T / Block, and in STEP 3, deleting this independent block and adding an IDLE Block after / T / Block for compensation, it has no impact on user services and the bearer efficiency is 100%.

[0247] The bit block stream error code detection method provided by the embodiments of this application is a detection method for the transmission path of the bit block stream, which is not limited to wired telecommunications bearers and can be fully applied to wireless communication, industrial or industrial communication networks.

[0248] Based on the same concept, this application also provides a bit block stream error code detection device, which can be used to execute the corresponding Figure 6 method embodiments described above. Therefore, the implementation manners of the bit block stream error code detection device provided by the embodiments of this application can refer to the implementation manners of this method, and the repeated parts will not be described again.

[0249] Refer to Figure 28 As shown, the embodiments of this application provide a bit block stream error code detection device 2800, including: a transceiver 2801 and a processor 2802;

[0250] The transceiver 2801 is used to send a first boundary bit block, and the first boundary bit block is used to distinguish N subsequent bit blocks to be sent, where N is a positive integer; and sequentially send the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to N;

[0251] The processor 2802 is used to determine a first parity check result and a second parity check result. The check object of the first parity check result includes m consecutive bits of each bit block among the N bit blocks, and the check object of the second parity check result includes n consecutive bits of each bit block among the N bit blocks. At least one of m and n is greater than or equal to 2;

[0252] The transceiver 2801 is further used to send a second boundary bit block, the first parity check result, and the second parity check result, and the second boundary bit block is used to distinguish the N bit blocks that have been sent.

[0253] In a possible design, the type of each bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2–M1 represents the number of header synchronization header bits in each bit block, M1 and M2 are positive integers, and M2>M1.

[0254] In a possible design, the transceiver 2801 is configured to:

[0255] Send a first boundary bit block to a first device;

[0256] Sequentially send the I-th bit block to the first device;

[0257] Send a second boundary bit block, the first parity check result, and the second parity check result to the first device;

[0258] Alternatively, send a second boundary bit block to the first device, and send the first parity check result and the second parity check result to a second device.

[0259] In a possible design, the transceiver 2801 is configured to:

[0260] Send the second boundary bit block at a first moment, and send the first parity check result and the second parity check result at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

[0261] In a possible design, the first parity check result and the second parity check result are stored in the second boundary bit block.

[0262] In a possible design, the first parity check result and the second parity check result are calculated according to a preset check algorithm, which is used to not change the first parity check result and the second parity check result when a first bit block is added to or deleted from the N bit blocks. The first bit block refers to a bit block that may be inserted into or deleted from the N bit blocks during the transmission of the N bit blocks.

[0263] In a possible design, the preset check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, and y≥2;

[0264] The processor 2802 is configured to start from the first payload bit in the N bit blocks, and sequentially record every x consecutive bits of each bit block to the first monitoring section to the y-th monitoring section;

[0265] Determine a 1-bit monitoring code for each monitoring section using odd parity or even parity to obtain a y-bit monitoring code, where the y-bit monitoring code includes the first parity check result and the second parity check result.

[0266] In a possible design, the preset check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of continuously bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of continuously bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A3... Az-1, Az, A1, A2, A3... Az-1, Az, respectively, and z is a positive integer, z≥2;

[0267] The processor 2802 is configured to start from the first payload bit in the N bit blocks, record A1 consecutive bits in each bit block into the first monitoring section, record A2 consecutive bits after the A1 consecutive bits into the second monitoring section, record A3 consecutive bits after the A2 consecutive bits into the third monitoring section, until Az consecutive bits after the Az-1 consecutive bits are recorded into the zth monitoring section;

[0268] For each monitoring section, an odd parity check or an even parity check is used to determine 1-bit monitoring codes, and z-bit monitoring codes are obtained. The z-bit monitoring codes include the first parity check result and the second parity check result.

[0269] In a possible design, the processor 2802 is configured to:

[0270] Determine a first check result set, where the first check result set includes the y-bit monitoring codes, or the first check result set includes the z-bit monitoring codes;

[0271] The transceiver 2801 is configured to:

[0272] Transmit the first check result set.

[0273] Based on the same concept, the present application further provides a bit block stream error code detection device, which can be used to execute the corresponding method embodiments described above Figure 12 Therefore, the implementation manners of the bit block stream error code detection device provided in the embodiments of the present application can refer to the implementation manners of the method. The repeated parts will not be described again.

[0274] Refer to Figure 29 As shown, the embodiments of the present application provide a bit block stream error code detection device 2900, including: a transceiver 2901 and a processor 2902;

[0275] The transceiver 2901 is configured to receive a first boundary bit block, where the first boundary bit block is used to distinguish the subsequent T bit blocks received, and T is a positive integer; sequentially receive the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to T; receive a second boundary bit block, where the second boundary bit block is used to distinguish the T bit blocks that have been received;

[0276] A processor 2902, configured to determine a third parity check result and a fourth parity check result, where the objects of the third parity check result include consecutive m bits of each of the T bit blocks, and the objects of the fourth parity check result include consecutive n bits of each of the T bit blocks, and at least one of m and n is greater than or equal to 2; when receiving the first parity check result and the second parity check result through the transceiver, determine whether there are bit errors in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, where the objects of the first parity check result include consecutive m bits of each of the N bit blocks, the objects of the second parity check result include consecutive n bits of each of the N bit blocks, and N is the number of bit blocks between the first boundary bit block and the second boundary bit block when determining the first parity check result and the second parity check result.

[0277] In a possible design, the transceiver 2901 is further configured to:

[0278] When not receiving the first parity check result and the second parity check result, send the third parity check result and the fourth parity check result to a second device, where the first parity check result and the second parity check result are stored in the second device.

[0279] In a possible design, the type of each bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2 - M1 represents the number of header synchronization bits in each bit block, and M1 and M2 are positive integers, and M2 > M1.

[0280] In a possible design, the transceiver 2901 is configured to:

[0281] Receive a second boundary bit block at a first moment;

[0282] Receive the first parity check result and the second parity check result at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

[0283] In a possible design, the first parity check result and the second parity check result are stored in the second boundary bit block.

[0284] In a possible design, the third parity check result and the fourth parity check result are calculated according to a preset check algorithm, which is used to keep the third parity check result and the fourth parity check result unchanged when a first bit block is added to or removed from the T bit blocks. The first bit block refers to a bit block that may be inserted into or deleted from the T bit blocks during the transmission of the T bit blocks.

[0285] In a possible design, the preset check algorithm is the xBIP–y algorithm, where x refers to the number of consecutively bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, with y≥2;

[0286] The processor 2902 is configured to start from the first payload bit in the T bit blocks and record every x consecutive bits of each bit block to the first monitoring section to the yth monitoring section in sequence;

[0287] For each monitoring section, odd parity check or even parity check is used to determine a 1-bit monitoring code, and a y-bit monitoring code is obtained. The y-bit monitoring code includes the third parity check result and the fourth parity check result.

[0288] In a possible design, the preset check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of consecutively bit-interleaved bits corresponding to each monitoring section is not all the same. The number of consecutively bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A 3……Az-1, Az respectively, and A1, A2, A 3……Az-1, Az, z are positive integers, with z≥2;

[0289] The processor 2902 is configured to start from the first payload bit in the T bit blocks, record A1 consecutive bits of each bit block to the first monitoring section, record A2 consecutive bits after the A1 consecutive bits to the second monitoring section, record A3 consecutive bits after the A2 consecutive bits to the third monitoring section, until recording Az consecutive bits after the Az-1 consecutive bits to the zth monitoring section;

[0290] For each monitoring section, odd parity check or even parity check is used to determine a 1-bit monitoring code, and a z-bit monitoring code is obtained. The z-bit monitoring code includes the third parity check result and the fourth parity check result.

[0291] In a possible design, the processor 2902 is configured to:

[0292] If it is determined that the first parity check result is the same as the third parity check result, and the second parity check result is the same as the fourth parity check result, it is determined that there is no error in the T bit blocks;

[0293] If it is determined that the first parity check result is different from the third parity check result, and / or the second parity check result is different from the fourth parity check result, it is determined that there is an error in the T bit blocks.

[0294] In a possible design, the transceiver 2901 is configured to:

[0295] Receive a first set of check results, which is calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the first set of check results includes the first parity check result and the second parity check result;

[0296] The processor 2902 is configured to: determine a second set of check results, where the second parity check result is calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the second set of check results includes the third parity check result and the fourth parity check result; determine whether there is an error in the T bit blocks according to the first set of check results and the second set of check results.

[0297] In a possible design, the transceiver 2901 is configured to:

[0298] Receive a first set of check results, which is calculated according to the flexBIP–z algorithm, and the z-bit monitoring code included in the first set of check results includes the first parity check result and the second parity check result;

[0299] The processor 2902 is configured to: determine a second set of check results, which is calculated according to the flexBIP–z algorithm, and the z-bit monitoring code included in the second set of check results includes the third parity check result and the fourth parity check result; determine whether there is an error in the T bit blocks according to the first set of check results and the second set of check results.

[0300] In a possible design, the processor 2902 is configured to:

[0301] If it is determined that the first set of check results is the same as the second set of check results, it is determined that there is no error in the T bit blocks;

[0302] If it is determined that the first set of check results is different from the second set of check results, it is determined that there is an error in the T bit blocks.

[0303] Based on the same concept, this application also provides a bit block stream error detection device, which can be used to execute the corresponding method embodiments described above. Figure 13 Therefore, the implementation manner of the bit block stream error detection device provided in the embodiments of this application can refer to the implementation manner of this method, and repeated parts will not be described again.

[0304] Referring to Figure 30 As shown, the embodiments of this application provide a bit block stream error detection device 3000, including: a transceiver 3001 and a processor 3002;

[0305] The processor 3002 is configured to determine a detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream; calculate a first check result according to the detected section;

[0306] The transceiver 3001 is configured to send the first check result and the bit block stream;

[0307] In a possible design, the bit block stream includes at least one M1 / M2 bit block; where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2–M1 represents the number of header sync header bits in each bit block, M1 and M2 are positive integers, and M2>M1.

[0308] In a possible design, the transceiver 3001 is configured to:

[0309] Send the first check result and the bit block stream to a second device;

[0310] Or, send the first check result to a third device and send the bit block stream to the second device;

[0311] In a possible design, the processor 3002 is further configured to:

[0312] Before the transceiver sends the first check result and the bit block stream to the second device, store the first check result in the end block to obtain an updated end block; or store the first check result in a check result storage block and delete any first bit block in the bit block stream, where the check result storage block refers to a newly added block located before the end block, and the first bit block refers to a bit block that may be inserted into or deleted from the bit block stream during the transmission of the bit block stream.

[0313] In a possible design, the processor 3002 is configured to:

[0314] When the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, store the first verification result before the end byte in the end block, move the end byte to a new block after the end block according to the number of bytes occupied by the first verification result, delete any first bit block in the bit block stream, and use the new block where the end byte is located after moving as the updated end block;

[0315] When the number of bytes occupied by the first verification result is less than the target number of bytes, store the first verification result before the end byte in the end block, move the end byte backward by the number of bytes occupied by the first verification result, and use the bit block where the end byte is located after moving as the updated end block;

[0316] Wherein, the target number of bytes is the number of bytes after the end byte in the end block plus 1.

[0317] Based on the same concept, this application also provides a bit block stream error code detection device, which can be used to execute the above Figure 21 corresponding method embodiments in, so the implementation manners of the bit block stream error code detection device provided by the embodiments of this application can refer to the implementation manners of this method, and repeated parts will not be described again.

[0318] Refer to Figure 31 As shown, the embodiments of this application provide a bit block stream error code detection device 3100, including: a transceiver 3101 and a processor 3102;

[0319] The processor 3102 is configured to determine a detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream; calculate a second verification result according to the detected section;

[0320] When receiving the first verification result through the transceiver 3101, determine whether there is an error code in the detected section according to the first verification result and the second verification result.

[0321] In a possible design, the bit block stream includes at least one M1 / M2 bit block; wherein, M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2 - M1 represents the number of header synchronization bits in each bit block, M1 and M2 are positive integers, and M2 > M1.

[0322] In a possible design, the processor 3102 is configured to

[0323] When the first verification result is received through the transceiver and the first verification result is stored in the end block, the second verification result is deleted from the end block to obtain an updated end block, and the bytes between the start byte in the start block and the end byte in the updated end block are used as the detected section;

[0324] When the first verification result is received through the transceiver and the first verification result is stored in the verification result storage block, the verification result storage block is deleted from the bit block stream to obtain an updated bit block stream, and the bytes between the start byte in the start block and the end byte in the end block in the updated bit block stream are used as the detected section, where the verification result storage block is located before the end block;

[0325] When the first verification result is not received, the bytes between the start byte in the start block and the end byte in the end block in the bit block stream are used as the detected section;

[0326] In a possible design, the transceiver 3101 is further configured to:

[0327] When the first verification result is not received, the second verification result is sent to a third device that stores the first verification result.

[0328] In a possible design, the processor 3102 is configured to:

[0329] If it is determined that the first verification result is the same as the second verification result, it is determined that there is no error code in the detected section;

[0330] If it is determined that the first verification result is different from the second verification result, it is determined that there is an error code in the detected section.

[0331] In a possible design, the processor 3102 is configured to:

[0332] When the number of bytes occupied by the first verification result is greater than or equal to the target number of bytes, the end byte is moved to a bit block before the end block according to the number of bytes occupied by the first verification result, and a first bit block is newly added in the bit block stream, and the bit block where the end byte is located after being moved is used as the updated end block;

[0333] When the number of bytes occupied by the first verification result is less than the target number of bytes, the end byte is moved forward by the number of bytes occupied by the first verification result, and the bit block where the end byte is located after being moved is used as the updated end block;

[0334] Wherein, the target number of bytes is the number of bytes before the end byte in the end block plus 1.

[0335] In summary, the embodiment of the present application provides a method for detecting bit error in a bit block stream. The method includes: a sending device sends a first boundary bit block, which is used to distinguish N subsequent bit blocks to be sent, where N is a positive integer; the I-th bit block is sent in sequence, where I is an integer greater than or equal to 1 and less than or equal to N; a first parity check result and a second parity check result are determined. The check object of the first parity check result includes m consecutive bits of each of the N bit blocks, and the check object of the second parity check result includes n consecutive bits of each of the N bit blocks, and at least one of m and n is greater than or equal to 2; a second boundary bit block, the first parity check result and the second parity check result are sent, and the second boundary bit block is used to distinguish the N bit blocks that have been sent. At the same time, a receiving device receives the first boundary bit block, which is used to distinguish T subsequent bit blocks to be received, where T is a positive integer; the I-th bit block is received in sequence, where I is an integer greater than or equal to 1 and less than or equal to T; the second boundary bit block is received, and the second boundary bit block is used to distinguish the T bit blocks that have been received; a third parity check result and a fourth parity check result are determined. The check object of the third parity check result includes m consecutive bits of each of the T bit blocks, and the check object of the second parity check result includes n consecutive bits of each of the T bit blocks, and at least one of m and n is greater than or equal to 2; when the first parity check result and the second parity check result are received, it is determined whether there is a bit error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result. Wherein, the check object of the first parity check result includes m consecutive bits of each of the N bit blocks, and the check object of the second parity check result includes n consecutive bits of each of the N bit blocks, and N is the number of bit blocks between the first boundary bit block and the second boundary bit block when the first parity check result and the second parity check result are determined. Therefore, by using the method provided by the embodiment of the present application, the error or bit error detection of the M / N Bit Block network path can be completely implemented without affecting the user service, the bearing efficiency is 100%, the bit blocks inserted or deleted due to synchronization problems during the transmission process can be tolerated, and the detection period (that is, the number of bit blocks between two boundary bit blocks) and the detection accuracy (that is, the preset algorithm) can be dynamically configured according to demand. In addition, the path of the bit block stream to be verified by this detection method can be an end-to-end path, and can also be used for the path of the bit block stream to be verified that is not an end-to-end path. Therefore, by using the method provided by the embodiment of the present application, the problem that it is difficult to implement the bit error detection method and the bearing efficiency is low in the scenario of M / N Bit block exchange can be solved.

[0336] The embodiments of the present application also provide a method for detecting bit block stream error codes. The method includes: a first device determines a detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream; the first device calculates a first verification result according to the detected section. The first device sends the first verification result and the bit block stream. For example, the algorithm adopted by the first device when calculating the first verification result can be CRC-x or BIP-x, and the result of the first verification result is denoted as B, and B can be one or more bytes. A second device determines a detected section according to the start byte in the start block and the end byte in the end block corresponding to the start block in the bit block stream; the second device calculates a second verification result according to the detected section. When the second device receives the first verification result, the second device determines whether there is an error code in the detected section according to the first verification result and the second verification result. Therefore, the method provided by the embodiments of the present application can completely implement the error or error code detection of the M / N BitBlock network path, has little impact on user services, is close to SDH / OTN, is superior to the error code detection methods provided in the prior art, and has a simple and easy-to-implement implementation process.

[0337] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the embodiments of the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0338] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for implementing in the process Figure 1 one process or multiple processes and / or blocks Figure 1 a device for the functions specified in one block or multiple blocks.

[0339] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements in the process Figure 1one or more processes and / or blocks Figure 1 the functions specified in one or more blocks.

[0340] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus, causing a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one Figure 1 one or more processes and / or blocks Figure 1 or more processes and / or blocks.

[0341] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A method for sending a bit block stream, characterized in that, Including: Sending a first boundary bit block, which is used to distinguish N subsequent bit blocks, where N is a positive integer; Sequentially sending the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to N; Determining a first parity check result and a second parity check result, where the check object of the first parity check result includes consecutive m bits of at least one bit block among the N bit blocks, and the check object of the second parity check result includes consecutive n bits of at least one bit block among the N bit blocks, and at least one of m and n is greater than or equal to 2. Herein, the first parity check result and the second parity check result are calculated according to a preset parity check algorithm, and the preset parity check algorithm is used to keep the first parity check result and the second parity check result unchanged when a first bit block is added to or deleted from the N bit blocks. The first bit block refers to a bit block inserted into or deleted from the N bit blocks during the transmission of the N bit blocks, and the first bit block includes an idle block; Sending a second boundary bit block, the first parity check result, and the second parity check result, where the second boundary bit block is used to distinguish the completed N bit blocks.

2. The method according to claim 1, characterized in that, The consecutive m bits of the at least one bit block and the consecutive n bits of the at least one bit block are different bits.

3. The method according to claim 1, characterized in that The type of the bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in at least one bit block, M2 represents the total number of bits in at least one bit block, M2 - M1 represents the number of header synchronization bits in at least one bit block, and M1 and M2 are positive integers, and M2 > M1.

4. The method according to any one of claims 1-3, characterized in that, Sending the first boundary bit block includes: Sending the first boundary bit block to a first device; Sequentially sending the I-th bit block includes: Sequentially sending the I-th bit block to the first device; Sending the second boundary bit block, the first parity check result, and the second parity check result includes: Sending the second boundary bit block, the first parity check result, and the second parity check result to the first device; Or, sending the second boundary bit block to the first device and sending the first parity check result and the second parity check result to a second device.

5. The method according to claim 1, characterized in that, The check object of the first parity check result further includes consecutive m bits of the first boundary bit block, and the check object of the second parity check result further includes consecutive n bits of the first boundary bit block.

6. The method according to any one of claims 1-3 or 5, characterized in that, The check object of the first parity check result further includes consecutive m bits of the second boundary bit block, and the check object of the second parity check result further includes consecutive n bits of the second boundary bit block.

7. The method according to any one of claims 1 to 3 or 5, characterized in that Sending the second boundary bit block, the first parity check result, and the second parity check result includes: Sending the second boundary bit block at a first moment and sending the first parity check result and the second parity check result at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

8. The method according to any one of claims 1 to 3 or 5, characterized in that, The first parity check result and the second parity check result are stored in the second boundary bit block.

9. The method according to claim 1, wherein The preset check algorithm is the xBIP–y algorithm, where x refers to the number of consecutively bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, with y≥2; Determining the first parity check result and the second parity check result includes: Starting from the first payload bit in the N bit blocks, every x consecutive bits of at least one bit block are sequentially recorded into the first monitoring section to the yth monitoring section; For each monitoring section, an odd parity check or an even parity check is used to determine a 1-bit monitoring code, obtaining a y-bit monitoring code, where the y-bit monitoring code includes the first parity check result and the second parity check result.

10. The method according to claim 1, wherein The preset check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of consecutively bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of consecutively bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A3 …… Az-1, Az, where A1, A2, A3 …… Az-1, Az, and z are positive integers, with z≥2; Determining the first parity check result and the second parity check result includes: Starting from the first payload bit in the N bit blocks, A1 consecutive bits in at least one bit block are recorded into the first monitoring section, A2 consecutive bits after the A1 consecutive bits are recorded into the second monitoring section, A3 consecutive bits after the A2 consecutive bits are recorded into the third monitoring section, until Az consecutive bits after the Az-1 consecutive bits are recorded into the zth monitoring section; For each monitoring section, an odd parity check or an even parity check is used to determine a 1-bit monitoring code, obtaining a z-bit monitoring code, where the z-bit monitoring code includes the first parity check result and the second parity check result.

11. The method according to claim 9, wherein Determining the first parity check result and the second parity check result includes: Determining a first check result set, where the first check result set includes the y-bit monitoring code; Sending the first parity check result and the second parity check result includes: Sending the first check result set.

12. A method for receiving a bit block stream, characterized in that, including: Receiving a first boundary bit block, where the first boundary bit block is used to distinguish the subsequent T bit blocks received, and T is a positive integer; Sequentially receiving the Ith bit block, where I is an integer greater than or equal to 1 and less than or equal to T; Receiving a second boundary bit block, where the second boundary bit block is used to distinguish the T bit blocks that have been received completely; Determine a third parity check result and a fourth parity check result. The objects to be checked for the third parity check result include consecutive m bits of at least one bit block among the T bit blocks, and the objects to be checked for the fourth parity check result include consecutive n bits of at least one bit block among the T bit blocks. At least one of m and n is greater than or equal to 2. Wherein, the third parity check result and the fourth parity check result are calculated according to a preset parity check algorithm, and the preset parity check algorithm is used to not change the third parity check result and the fourth parity check result when the first bit block is added to or removed from the T bit blocks. The first bit block refers to the bit block inserted into or deleted from the T bit blocks during the transmission of the T bit blocks, and the first bit block includes idle blocks; When the first parity check result and the second parity check result are received, determine whether there is an error code in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result. Wherein, the objects to be checked for the first parity check result include consecutive m bits of at least one bit block among the N bit blocks, and the objects to be checked for the second parity check result include consecutive n bits of at least one bit block among the N bit blocks. N is the number of bit blocks between the first boundary bit block and the second boundary bit block when the first parity check result and the second parity check result are determined.

13. The method according to claim 12, characterized in that, The consecutive m bits of the at least one bit block and the consecutive n bits of the at least one bit block are different bits.

14. The method according to claim 12, characterized in that, Further include: When the first parity check result and the second parity check result are not received, send the third parity check result and the fourth parity check result to a second device, and the first parity check result and the second parity check result are stored in the second device.

15. The method according to claim 12, wherein The objects to be checked for the third parity check result further include consecutive m bits of the first boundary bit block, and the objects to be checked for the fourth parity check result further include n bits of the first boundary bit block; the objects to be checked for the first parity check result further include consecutive m bits of the first boundary bit block, and the objects to be checked for the second parity check result further include consecutive n bits of the first boundary bit block.

16. The method according to any one of claims 12-15, characterized in that, The objects to be checked for the third parity check result further include consecutive m bits of the second boundary bit block, and the objects to be checked for the fourth parity check result further include n bits of the second boundary bit block; the objects to be checked for the first parity check result further include consecutive m bits of the second boundary bit block, and the objects to be checked for the second parity check result further include consecutive n bits of the second boundary bit block.

17. The method according to claim 12, wherein The type of the bit block is an M1 / M2 bit block. Here, M1 represents the number of payload bits in at least one bit block, M2 represents the total number of bits in at least one bit block, M2 - M1 represents the number of header synchronization header bits in at least one bit block, M1 and M2 are positive integers, and M2 > M1.

18. The method according to any one of claims 12-15 or 17, characterized in that, Receiving a second boundary bit block, including: Receiving the second boundary bit block at a first moment; Receiving a first parity check result and a second parity check result, including: Receiving the first parity check result and the second parity check result at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

19. The method according to any one of claims 12 - 15 or 17, characterized in that The first parity check result and the second parity check result are stored in the second boundary bit block.

20. The method according to claim 12, characterized in that, The preset parity check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, and y ≥ 2; Determining a third parity check result and a fourth parity check result, including: Starting from the first payload bit in the T bit blocks, recording every x consecutive bits of at least one bit block to the first monitoring section to the yth monitoring section in sequence; Determining 1-bit monitoring codes for each monitoring section using odd parity check or even parity check to obtain y-bit monitoring codes, where the y-bit monitoring codes include the third parity check result and the fourth parity check result.

21. The method according to claim 12, wherein The preset parity check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of continuously bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of continuously bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A3... Az-1, Az respectively, where A1, A2, A3... Az-1, Az and z are positive integers, and z ≥ 2; Determining a third parity check result and a fourth parity check result, including: Starting from the first payload bit in the T bit blocks, recording A1 consecutive bits of at least one bit block to the first monitoring section, recording A2 consecutive bits after the A1 consecutive bits to the second monitoring section, recording A3 consecutive bits after the A2 consecutive bits to the third monitoring section, until recording Az consecutive bits after the Az-1 consecutive bits to the zth monitoring section; Determining 1-bit monitoring codes for each monitoring section using odd parity check or even parity check to obtain z-bit monitoring codes, where the z-bit monitoring codes include the third parity check result and the fourth parity check result.

22. The method according to any one of claims 12 - 15, 17 or 20, characterized in that, Determining whether there are bit errors in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, including: If it is determined that the first parity check result is the same as the third parity check result, and the second parity check result is the same as the fourth parity check result, then it is determined that there are no bit errors in the T bit blocks; If it is determined that the first parity check result and the third parity check result are different, and / or the second parity check result and the fourth parity check result are different, it is determined that there is an error in the T bit blocks.

23. The method according to claim 12, wherein Receiving the first parity check result and the second parity check result includes: Receiving a first set of check results, where the first set of check results is calculated according to the xBIP–y algorithm, and the y-bit monitoring codes included in the first set of check results include the first parity check result and the second parity check result; Determining the third parity check result and the fourth parity check result includes: Determining a second set of check results, where the second parity check result is calculated according to the xBIP–y algorithm, and the y-bit monitoring codes included in the second set of check results include the third parity check result and the third parity check result; When the first parity check result and the second parity check result are received, determining whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result includes: Determining whether there is an error in the T bit blocks according to the first set of check results and the second set of check results.

24. The method according to claim 20, wherein Receiving the first parity check result and the second parity check result includes: Receiving a first set of check results, where the first set of check results is calculated according to the flexBIP–z algorithm, and the z-bit monitoring codes included in the first set of check results include the first parity check result and the second parity check result; Determining the third parity check result and the fourth parity check result includes: Determining a second set of check results, where the second set of check results is calculated according to the flexBIP–z algorithm, and the z-bit monitoring codes included in the second set of check results include the third parity check result and the fourth parity check result; When the first parity check result and the second parity check result are received, determining whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result includes: Determining whether there is an error in the T bit blocks according to the first set of check results and the second set of check results.

25. The method according to claim 23 or 24, characterized in that Determining whether there is an error in the T bit blocks according to the first set of check results and the second set of check results includes: If it is determined that the first set of check results and the second set of check results are the same, it is determined that there is no error in the T bit blocks; If it is determined that the first set of check results and the second set of check results are different, it is determined that there is an error in the T bit blocks.

26. A bit block stream transmitting device, characterized in that Includes: A transceiver for sending a first boundary bit block, where the first boundary bit block is used to distinguish the subsequent N bit blocks to be sent, and N is a positive integer; Sequentially sending the I-th bit block, where I is an integer greater than or equal to 1 and less than or equal to N; A processor for determining a first parity check result and a second parity check result, wherein the check object of the first parity check result includes consecutive m bits of at least one bit block among the N bit blocks, and the check object of the second parity check result includes consecutive n bits of at least one bit block among the N bit blocks, at least one of m and n being greater than or equal to 2. Herein, the first parity check result and the second parity check result are calculated according to a preset check algorithm, which is used to keep the first parity check result and the second parity check result unchanged when a first bit block is added to or removed from the N bit blocks. The first bit block refers to a bit block inserted into or deleted from the N bit blocks during the transmission of the N bit blocks, and the first bit block includes idle blocks. The transceiver is further configured to send a second boundary bit block, the first parity check result, and the second parity check result, where the second boundary bit block is used to distinguish the N bit blocks that have been completely sent.

27. The device according to claim 26, characterized in that, The consecutive m bits of the at least one bit block and the consecutive n bits of the at least one bit block are different bits.

28. The device according to claim 26, wherein The check object of the first parity check result further includes consecutive m bits of the first boundary bit block, and the check object of the second parity check result further includes consecutive n bits of the first boundary bit block.

29. The device according to any one of claims 26-28, characterized in that, The check object of the first parity check result further includes consecutive m bits of the second boundary bit block, and the check object of the second parity check result further includes consecutive n bits of the second boundary bit block.

30. The device according to claim 26, characterized in that, The type of the bit block is M1 / M2 bit block, where M1 represents the number of payload bits in at least one bit block, M2 represents the total number of bits in at least one bit block, M2 - M1 represents the number of header synchronization bits in at least one bit block, and M1 and M2 are positive integers with M2 > M1.

31. The device according to any one of claims 26 - 28 or 30, characterized in that, The transceiver is configured to: Send a first boundary bit block to a first device; Sequentially send the I-th bit block to the first device; Send a second boundary bit block, the first parity check result, and the second parity check result to the first device; Alternatively, send a second boundary bit block to the first device and send the first parity check result and the second parity check result to a second device.

32. The device according to any one of claims 26-28 or 30, characterized in that, The transceiver is configured to: Send the second boundary bit block at a first time and send the first parity check result and the second parity check result at a second time, where the first time is earlier than the second time, or the first time is later than the second time, or the first time is equal to the second time.

33. The device according to any one of claims 26-28 or 30, characterized in that The first parity check result and the second parity check result are stored in the second boundary bit block.

34. The device according to claim 26, characterized in that, The preset check algorithm is the xBIP - y algorithm, where x refers to the number of bits of consecutive bit interleaving, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers with y ≥ 2; The processor is configured to sequentially record every x consecutive bits of at least one bit block from the first payload bit in the N bit blocks to the first monitoring section to the yth monitoring section; Determine a 1-bit monitoring code for each monitoring section using odd parity or even parity to obtain a y-bit monitoring code, where the y-bit monitoring code includes the first parity check result and the second parity check result.

35. The device according to claim 26, characterized in that, The preset parity check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of consecutive bits interleaved for each monitoring section is not all the same. The number of consecutive bits interleaved for the z monitoring sections are A1, A2, A3... Az−1, Az respectively, where A1, A2, A3... Az−1, Az and z are positive integers, and z≥2; The processor is configured to record A1 consecutive bits in the at least one bit block to the first monitoring section starting from the first payload bit in the N bit blocks, record A2 consecutive bits after the A1 consecutive bits to the second monitoring section, record A3 consecutive bits after the A2 consecutive bits to the third monitoring section, until Az consecutive bits after the Az−1 consecutive bits are recorded to the zth monitoring section; Determine a 1-bit monitoring code for each monitoring section using odd parity or even parity to obtain a z-bit monitoring code, where the z-bit monitoring code includes the first parity check result and the second parity check result.

36. The device according to claim 34, characterized in that, The processor is configured to: Determine a first set of check results, where the first set of check results includes the y-bit monitoring code; The transceiver is configured to: Transmit the first set of check results.

37. A bit block stream receiving device, characterized in that, Comprising: A transceiver, configured to receive a first boundary bit block, where the first boundary bit block is used to distinguish the subsequent T bit blocks received, and T is a positive integer; Sequentially receive the Ith bit block, where I is an integer greater than or equal to 1 and less than or equal to T; receive a second boundary bit block, where the second boundary bit block is used to distinguish the T bit blocks that have been received; A processor, configured to determine a third parity check result and a fourth parity check result. The objects of the third parity check result include consecutive m bits of at least one bit block among the T bit blocks. The objects of the fourth parity check result include consecutive n bits of at least one bit block among the T bit blocks. At least one of m and n is greater than or equal to 2. The third parity check result and the fourth parity check result are calculated according to a preset parity check algorithm. The preset parity check algorithm is used to keep the third parity check result and the fourth parity check result unchanged when a first bit block is added to or removed from the T bit blocks. The first bit block refers to a bit block inserted into or deleted from the T bit blocks during the transmission of the T bit blocks, and the first bit block includes idle blocks. When the first parity check result and the second parity check result are received by the transceiver, it is determined whether there are bit errors in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result. Wherein, the objects of the first parity check result include consecutive m bits of at least one bit block among the N bit blocks, the objects of the second parity check result include consecutive n bits of at least one bit block among the N bit blocks, and N is the number of bit blocks between the first boundary bit block and the second boundary bit block when the first parity check result and the second parity check result are determined.

38. The device according to claim 37, characterized in that, The consecutive m bits of the at least one bit block and the consecutive n bits of the at least one bit block are different bits.

39. The apparatus according to claim 37, wherein The transceiver is further configured to: When the first parity check result and the second parity check result are not received, send the third parity check result and the fourth parity check result to a second device, where the second device stores the first parity check result and the second parity check result.

40. The device according to claim 37, characterized in that The objects of the third parity check result further include consecutive m bits of the first boundary bit block, and the objects of the fourth parity check result further include n bits of the first boundary bit block; the objects of the first parity check result further include consecutive m bits of the first boundary bit block, and the objects of the second parity check result further include consecutive n bits of the first boundary bit block.

41. The device according to any one of claims 37 to 40, characterized in that, The objects of the third parity check result further include consecutive m bits of the second boundary bit block, and the objects of the fourth parity check result further include n bits of the second boundary bit block; the objects of the first parity check result further include consecutive m bits of the second boundary bit block, and the objects of the second parity check result further include consecutive n bits of the second boundary bit block.

42. The device according to claim 37, wherein The type of the bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in at least one bit block, M2 represents the total number of bits in at least one bit block, M2–M1 represents the number of header synchronization header bits in at least one bit block, and M1 and M2 are positive integers with M2 > M1.

43. The device according to any one of claims 37 - 40 or 42, characterized in that, The transceiver is used for: Receiving a second boundary bit block at a first moment; Receiving a first parity check result and a second parity check result at a second moment, where the first moment is earlier than the second moment, or the first moment is later than the second moment, or the first moment is equal to the second moment.

44. The device according to any one of claims 37 - 40 or 42, characterized in that, The first parity check result and the second parity check result are stored in the second boundary bit block.

45. The device according to claim 37, characterized in that, The preset parity check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers with y≥2; The processor is used for starting from the first payload bit in the T bit blocks, and sequentially recording every x consecutive bits of at least one bit block into the first monitoring section to the yth monitoring section; Determining a 1-bit monitoring code for each monitoring section by using odd parity check or even parity check to obtain a y-bit monitoring code, where the y-bit monitoring code includes the third parity check result and the fourth parity check result.

46. The device according to claim 37, wherein, The preset parity check algorithm is the flexBIP–z algorithm, where z refers to the number of monitoring sections, and the number of continuously bit-interleaved bits corresponding to each monitoring section is not all the same. The numbers of continuously bit-interleaved bits corresponding to the z monitoring sections are A1, A2, A3 …… Az-1, Az respectively, where A1, A2, A3 …… Az-1, Az and z are positive integers with z≥2; The processor is used for starting from the first payload bit in the T bit blocks, recording A1 consecutive bits of at least one bit block into the first monitoring section, recording A2 consecutive bits after the A1 consecutive bits into the second monitoring section, recording A3 consecutive bits after the A2 consecutive bits into the third monitoring section, until recording Az consecutive bits after the Az-1 consecutive bits into the zth monitoring section; Determining a 1-bit monitoring code for each monitoring section by using odd parity check or even parity check to obtain a z-bit monitoring code, where the z-bit monitoring code includes the third parity check result and the fourth parity check result.

47. The device according to any one of claims 37-40, 42, or 45-46, characterized in that, The processor is used for: If it is determined that the first parity check result is the same as the third parity check result, and the second parity check result is the same as the fourth parity check result, then determining that there is no error code in the T bit blocks; If it is determined that the first parity check result is different from the third parity check result, and / or the second parity check result is different from the fourth parity check result, then determining that there is an error code in the T bit blocks.

48. The device according to claim 45, characterized in that, The transceiver is used for: Receive a first set of verification results, where the first set of verification results is calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the first set of verification results includes the first parity check result and the second parity check result; The processor is configured to: determine a second set of verification results, where the second parity check result is calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the second set of verification results includes the third parity check result and the third parity check result; determine whether there is an error code in the T bit blocks according to the first set of verification results and the second set of verification results.

49. The device according to claim 46, wherein The transceiver is configured to: Receive a first set of verification results, where the first set of verification results is calculated according to the flexBIP–z algorithm, and the z-bit monitoring code included in the first set of verification results includes the first parity check result and the second parity check result; The processor is configured to: determine a second set of verification results, where the second set of verification results is calculated according to the flexBIP–z algorithm, and the z-bit monitoring code included in the second set of verification results includes the third parity check result and the fourth parity check result; determine whether there is an error code in the T bit blocks according to the first set of verification results and the second set of verification results.

50. The device according to claim 48 or 49, characterized in that, The processor is configured to: If it is determined that the first set of verification results is the same as the second set of verification results, determine that there is no error code in the T bit blocks; If it is determined that the first set of verification results is different from the second set of verification results, determine that there is an error code in the T bit blocks.

51. A method for sending a bit block stream, characterized in that, It includes: Obtain at least one bit block; Determine a first parity check result and a second parity check result, where the verification object of the first parity check result is consecutive m bits of each bit block in the at least one bit block, and the verification object of the second parity check result includes consecutive n bits of each bit block in the at least one bit block, and at least one of m and n is greater than or equal to 2. Among them, the first parity check result and the second parity check result are calculated according to a preset verification algorithm, and the preset verification algorithm is used to not change the first parity check result and the second parity check result when a first bit block is added to or deleted from the N bit blocks. The first bit block refers to a bit block that can be inserted into or deleted from the N bit blocks during the transmission of the N bit blocks; Send the first parity check result and the second parity check result.

52. The method according to claim 51, wherein The consecutive m bits of the at least one bit block and the consecutive n bits of the at least one bit block are different bits.

53. The method according to claim 51, characterized in that, The type of each bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2–M1 represents the number of header synchronization header bits in each bit block, and M1 and M2 are positive integers, and M2>M1.

54. The method according to claim 51, wherein The preset check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, with y≥2; Determining a first parity check result and a second parity check result includes: Starting from the first payload bit in the N bit blocks, recording every x consecutive bits of at least one bit block to the first monitoring section to the yth monitoring section in sequence; Determining a 1-bit monitoring code for each monitoring section using odd parity or even parity to obtain a y-bit monitoring code, where the y-bit monitoring code includes the first parity check result and the second parity check result.

55. The method according to claim 54, wherein, Determining a first parity check result and a second parity check result includes: Determining a first set of check results, where the first set of check results includes the y-bit monitoring code; Sending the first parity check result and the second parity check result includes: Sending the first set of check results.

56. A method for receiving a bit block stream, characterized in that, Includes: Obtaining at least one bit block; Determining a third parity check result and a fourth parity check result, where the check object of the third parity check result includes m consecutive bits of each bit block in the at least one bit block, and the check object of the fourth parity check result includes n consecutive bits of each bit block in the at least one bit block, and at least one of m and n is greater than or equal to 2. Here, the third parity check result and the fourth parity check result are calculated according to a preset check algorithm, and the preset check algorithm is used to not change the third parity check result and the fourth parity check result when the first bit block is added to or deleted from the T bit blocks. The first bit block refers to the bit block inserted into or deleted from the T bit blocks during the transmission of the T bit blocks; When receiving the first parity check result and the second parity check result, determining whether there is an error code in the at least one bit block according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result.

57. The method according to claim 56, wherein The m consecutive bits of the at least one bit block and the n consecutive bits of the at least one bit block are different bits.

58. The method according to claim 56, wherein, The type of each bit block is an M1 / M2 bit block, where M1 represents the number of payload bits in each bit block, M2 represents the total number of bits in each bit block, M2–M1 represents the number of header synchronization header bits in each bit block, and M1 and M2 are positive integers, with M2>M1.

59. The method according to claim 56, wherein The preset check algorithm is the xBIP–y algorithm, where x refers to the number of continuously bit-interleaved bits, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, with y≥2; Determining a third parity check result and a fourth parity check result includes: Starting from the first payload bit in the T bit blocks, recording every x consecutive bits of at least one bit block to the first monitoring section to the yth monitoring section in sequence; For each monitored section, an odd parity check or an even parity check is used to determine a 1-bit monitoring code, and a y-bit monitoring code is obtained. The y-bit monitoring code includes the third parity check result and the fourth parity check result.

60. The method according to any one of claims 56-59, characterized in that, Determine whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, including: If it is determined that the first parity check result is the same as the third parity check result, and the second parity check result is the same as the fourth parity check result, it is determined that there is no error in the T bit blocks; If it is determined that the first parity check result is different from the third parity check result, and / or the second parity check result is different from the fourth parity check result, it is determined that there is an error in the T bit blocks.

61. The method according to any one of claims 56-59, characterized in that, Receive the first parity check result and the second parity check result, including: Receive a first set of check results, which is calculated according to the xBIP–y algorithm. The y-bit monitoring code included in the first set of check results includes the first parity check result and the second parity check result; Determine the third parity check result and the fourth parity check result, including: Determine a second set of check results. The second parity check result is calculated according to the xBIP–y algorithm. The y-bit monitoring code included in the second set of check results includes the third parity check result and the fourth parity check result; When the first parity check result and the second parity check result are received, determine whether there is an error in the T bit blocks according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result, including: Determine whether there is an error in the T bit blocks according to the first set of check results and the second set of check results.

62. The method according to claim 61, characterized in that, Determine whether there is an error in the T bit blocks according to the first set of check results and the second set of check results, including: If it is determined that the first set of check results is the same as the second set of check results, it is determined that there is no error in the T bit blocks; If it is determined that the first set of check results is different from the second set of check results, it is determined that there is an error in the T bit blocks.

63. A bit block stream sending device, characterized in that, Include: A transceiver for obtaining at least one bit block; A processor for determining a first parity check result and a second parity check result, wherein the object of the first parity check result is m consecutive bits of each bit block in the at least one bit block, and the object of the second parity check result includes n consecutive bits of each bit block in the at least one bit block, and at least one of m and n is greater than or equal to 2. The first parity check result and the second parity check result are calculated according to a preset check algorithm, which is used to keep the first parity check result and the second parity check result unchanged when a first bit block is added or removed from N bit blocks. The first bit block refers to the bit block inserted into or deleted from the N bit blocks during the transmission of the N bit blocks; The transceiver is further configured to receive the first parity check result and the second parity check result.

64. The device according to claim 63, wherein, The m consecutive bits of the at least one bit block and the n consecutive bits of the at least one bit block are different bits.

65. The device according to claim 63, characterized in that, The type of the bit block is M1 / M2 bit block, where M1 represents the number of payload bits in at least one bit block, M2 represents the total number of bits in at least one bit block, M2 - M1 represents the number of header synchronization header bits in at least one bit block, and M1 and M2 are positive integers, and M2 > M1.

66. The apparatus according to claim 63, wherein, The preset check algorithm is the xBIP - y algorithm, where x refers to the number of bits of continuous bit interleaving, x is determined according to the code pattern definition of the first bit block, y refers to the number of monitoring sections, and x and y are positive integers, and y ≥ 2; The processor is configured to record every x consecutive bits of at least one bit block to the first monitoring section to the yth monitoring section in sequence starting from the first payload bit in the N bit blocks; For each monitoring section, an odd parity check or an even parity check is used to determine a 1-bit monitoring code, and a y-bit monitoring code is obtained, and the y-bit monitoring code includes the first parity check result and the second parity check result.

67. The device according to claim 66, characterized in that, The processor is configured to: Determine a first set of check results, where the first set of check results includes the y-bit monitoring code; The transceiver is configured to: Transmit the first set of check results.

68. A bit block stream receiving device, characterized in that, Including: A transceiver for obtaining at least one bit block; A processor is configured to determine a third parity check result and a fourth parity check result. The objects of the third parity check result include m consecutive bits of each bit block in the at least one bit block, and the objects of the fourth parity check result include n consecutive bits of each bit block in the at least one bit block. At least one of m and n is greater than or equal to 2. Wherein, the third parity check result and the fourth parity check result are calculated according to a preset check algorithm, and the preset check algorithm is used to not change the third parity check result and the fourth parity check result when a first bit block is added to or removed from T bit blocks. The first bit block refers to a bit block inserted into or deleted from the T bit blocks during the transmission of the T bit blocks; when receiving a first parity check result and a second parity check result, determine whether there is an error code in the at least one bit block according to the first parity check result and the third parity check result, and the second parity check result and the fourth parity check result.

69. The device according to claim 68, characterized in that, The m consecutive bits of the at least one bit block and the n consecutive bits of the at least one bit block are different bits.

70. The device according to claim 68, characterized in that, The type of the bit block is M1 / M2 bit block, where M1 represents the number of payload bits in the at least one bit block, M2 represents the total number of bits in the at least one bit block, M2–M1 represents the number of header synchronization header bits in the at least one bit block, and M1 and M2 are positive integers, and M2>M1.

71. The device according to claim 68, wherein The preset check algorithm is the xBIP–y algorithm, where x refers to the number of bits of continuous bit interleaving, x is determined according to the code pattern definition of the first bit block, and y refers to the number of monitoring sections. x and y are positive integers, and y≥2; The processor is configured to start from the first payload bit of the T bit blocks, and sequentially record every x consecutive bits of at least one bit block to the first monitoring section to the yth monitoring section; For each monitoring section, an odd parity check or an even parity check is used to determine a 1-bit monitoring code, and a y-bit monitoring code is obtained. The y-bit monitoring code includes the third parity check result and the fourth parity check result.

72. The device according to any one of claims 68-71, characterized in that, The processor is configured to: If it is determined that the first parity check result is the same as the third parity check result, and the second parity check result is the same as the fourth parity check result, it is determined that there is no error code in the T bit blocks; If it is determined that the first parity check result is different from the third parity check result, and / or the second parity check result is different from the fourth parity check result, it is determined that there is an error code in the T bit blocks.

73. The device according to any one of claims 68 - 71, characterized in that, The transceiver is configured to: Receive a first set of check results, which is calculated according to the xBIP–y algorithm. The y-bit monitoring code included in the first set of check results includes the first parity check result and the second parity check result; The processor is configured to: determine a second set of verification results, where the second parity verification results are calculated according to the xBIP–y algorithm, and the y-bit monitoring code included in the second set of verification results includes the third parity verification result and the third parity verification result; determine whether there is an error in the T bit blocks according to the first set of verification results and the second set of verification results.

74. The device according to claim 73, characterized in that, The processor is configured to: If it is determined that the first set of verification results is the same as the second set of verification results, determine that there is no error in the T bit blocks; If it is determined that the first set of verification results is different from the second set of verification results, determine that there is an error in the T bit blocks.

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