Display device

Abstract

The display device may include a base substrate, an active pattern, a first electrode, a second electrode, a control electrode, and a display element. The active pattern may be disposed on the base substrate. The first electrode may be disposed between the base substrate and the active pattern and connected to one end of the active pattern. The second electrode may be disposed on the upper portion of the active pattern and connected to the other end of the active pattern. The control electrode may overlap with the active pattern and be insulated from the active pattern. The display element may be disposed on the upper portion of the second electrode and connected to the second electrode.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device capable of achieving high resolution. Background Art

[0002] The demand for high-resolution display devices is increasing. In order to exceed the limits of viewing angles and to display three-dimensional images, high-resolution display devices are necessary. In addition, high-resolution display devices are currently also required in head-mounted displays where users view the display device at a relatively close distance, and the necessity for high-resolution display devices is also increasing in smartphones, televisions, laptops, monitors, etc.

[0003] However, due to the limitations of process equipment used to manufacture high-resolution display devices, there is a limit to reducing the size of thin-film transistors that drive pixels. Even if the size is reduced, there is still a problem that the performance of the thin-film transistors cannot meet the target benchmark value. Summary of the invention

[0004] An object of the present invention is to provide a high-resolution display device.

[0005] In addition, an object of the present invention is to minimize the vertical crosstalk phenomenon in a display device, improve the response speed and / or brightness of a display element, and reduce the contact resistance between an active pattern and a second electrode.

[0006] The display device involved in the embodiment of the present invention may include a base substrate, an active pattern, a first electrode, a second electrode, a control electrode and a display element. The active pattern may be arranged on the base substrate. The first electrode may be arranged between the base substrate and the active pattern and connected to one end of the active pattern. The second electrode may be arranged on the upper part of the active pattern and connected to the other end of the active pattern. The control electrode may overlap with the active pattern and be insulated from the active pattern. The display element may be arranged on the upper part of the second electrode and connected to the second electrode.

[0007] The display device may further include at least two insulating layers disposed between the second electrode and the first electrode.

[0008] The display device may include first to fourth insulating layers. The first insulating layer may be disposed between the first electrode and the active pattern. The second insulating layer may be disposed between the active pattern and the control electrode. The third insulating layer may be disposed between the control electrode and the second electrode. The fourth insulating layer may be disposed between the second electrode and the display element.

[0009] The first electrode may contact the active pattern through a first contact hole provided in the first insulating layer, and the second electrode may contact the active pattern through a second contact hole provided in the second insulating layer and the third insulating layer.

[0010] The thickness of the first insulating layer may be thicker than the thickness of the first electrode.

[0011] The control electrode may be disposed on an upper portion of the active pattern.

[0012] The display device may further include a first data line and a second data line adjacent to each other in a first direction and extending in a second direction intersecting the first direction. The active pattern may overlap the first data line and not overlap the second data line, and extend between the first data line and the second data line.

[0013] The display device may further include a gate line insulated from and crossing the first data line and the second data line. The gate line may be arranged on both sides of the second electrode in the first direction, and the gate line may be arranged on one side of the second electrode in the second direction and not on the other side.

[0014] The second electrode may be disposed between the first data line and the second data line.

[0015] The display element may include a pixel electrode, a reference electrode, and a liquid crystal layer. The pixel electrode may be connected to the second electrode. The reference electrode may be insulated from and overlap the pixel electrode, and may receive a predetermined voltage. The liquid crystal layer may change the arrangement state of liquid crystal molecules according to the voltage applied to the pixel electrode and the reference electrode.

[0016] The display device may further include an interlayer insulating film disposed between the pixel electrode and the reference electrode. The pixel electrode may be disposed on the interlayer insulating film. The liquid crystal layer may be disposed on the pixel electrode.

[0017] The display device may further include a color filter disposed between the second electrode and the display element and overlapping the display element.

[0018] The display device may further include a cover layer disposed between the color filter and the display element and covering the color filter.

[0019] The display device may further include at least three insulating layers arranged between the second electrode and the first electrode.

[0020] The display device involved in the embodiment of the present invention may include a base substrate, an active pattern, a first electrode, a second electrode, a control electrode, a plurality of insulating layers and a display element. The active pattern may be arranged on the base substrate. The first electrode may be arranged on a layer different from the active pattern and may be connected to one end of the active pattern. The second electrode may be arranged on a layer different from the active pattern and the first electrode and may be connected to the other end of the active pattern. The control electrode may overlap with the active pattern and may be insulated from the active pattern. A plurality of insulating layers may be arranged between the second electrode and the first electrode and may be at least two or more. The display element may be arranged on the upper part of the second electrode and may be connected to the second electrode.

[0021] The second electrode may be disposed on an upper portion of the active pattern.

[0022] The first electrode may be disposed at a lower portion of the active pattern.

[0023] The number of the plurality of insulating layers disposed between the second electrode and the first electrode may be three or more.

[0024] A display device according to an embodiment of the present invention may include a base substrate, an active pattern, a first electrode, a second electrode, a control electrode, a display element, and first to fourth insulating layers.

[0025] The active pattern may be arranged on the base substrate. The first electrode may be arranged on a layer different from the active pattern and may be connected to one end of the active pattern. The second electrode may be arranged on a layer different from the active pattern and the first electrode and may be connected to the other end of the active pattern. The control electrode may overlap with the active pattern and may be insulated from the active pattern. The display element may be arranged on the upper part of the second electrode and may be connected to the second electrode.

[0026] The first insulating layer may be disposed between the first electrode and the active pattern. The second insulating layer may be disposed between the active pattern and the control electrode. The third insulating layer may be disposed between the control electrode and the second electrode. The fourth insulating layer may be disposed between the second electrode and the display element.

[0027] The control electrode may be disposed on an upper portion of the active pattern.

[0028] (Effects of the Invention)

[0029] According to the embodiment of the present invention, the structure of the layer provided with the first electrode and the layer provided with the second electrode can be made different, so that a high-resolution display device can be realized.

[0030] In the embodiment of the present invention, a plurality of insulating layers are arranged between the second electrode and the first electrode, so that the electrostatic capacitance of the parasitic capacitor can be controlled to be relatively small, and the vertical crosstalk phenomenon can be minimized.

[0031] In an embodiment of the present invention, a plurality of insulating layers are arranged between the control electrode and the first electrode, so that the RC delay value of the voltage signal applied to the pixel electrode of the display element can be relatively reduced, and the response speed and / or brightness can be improved.

[0032] In the display panel according to the embodiment of the present invention, the contact area between the active pattern and the second electrode is increased, so the contact resistance can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a perspective view showing a display device according to an embodiment of the present invention.

[0034] Figure 2 yes Figure 1 An exploded perspective view of a display device.

[0035] Figure 3 Yes means Figure 2 A block diagram of a portion of a display device.

[0036] Figure 4 This is a plan view showing an enlarged portion of a display panel according to an embodiment of the present invention.

[0037] Figure 5 It is along Figure 4 A cross-sectional view taken along line II′.

[0038] Figure 6 It is along Figure 4 A cross-sectional view taken along line II-II′.

[0039] Figure 7 is a schematic diagram showing a display panel in which vertical crosstalk occurs.

[0040] Figures 8a to 8c It means that the display panel according to the comparative example is formed with Figure 5 The AA region corresponds to a cross-sectional view of a portion of the structure process region.

[0041] Fig. 9 In the display panel according to other embodiments of the present invention, Figure 4 A cross-sectional view taken along line II′.

[0042] Fig.10 In the display panel according to other embodiments of the present invention, Figure 4 A cross-sectional view taken along line II-II′.

[0043] Fig.11 is a cross-sectional view showing a portion of a display panel according to another embodiment of the present invention.

[0044] Fig.12 In other embodiments of the present invention, Figure 4 A cross-sectional view taken along line II′.

[0045] Fig.13 It is along Figure 5 A cross-sectional view taken along line II-II′.

[0046] Fig.14 This is a plan view showing an enlarged portion of a display panel according to another embodiment of the present invention.

[0047] Fig.15 It is along Fig.14 A cross-sectional view taken along line II′.

[0048] Fig.16 It is along Fig.14 A cross-sectional view taken along line II-II′.

[0049] (Explanation of symbols)

[0050] DP: display panel; TR: thin film transistor; ACT: active pattern; IE: first electrode; OE: second electrode; CE: control electrode; EL1: pixel electrode; EL2: reference electrode. DETAILED DESCRIPTION

[0051] In this specification, when a certain component (or region, layer, part, etc.) is mentioned as being located on, connected to or combined with other components, it means that it is directly configured / connected / combined on the other components, or a third component may be configured in between.

[0052] The same reference numerals denote the same components. In addition, in each figure, the thickness, ratio, and size of each component are exaggerated for effective description of the technical content.

[0053] "And / or" includes more than one combination of all possible defined related components.

[0054] The terms first, second, etc. may be used to describe various constituent elements, and the constituent elements should not be limited to the terms. The terms are used only for the purpose of distinguishing one constituent element from another constituent element. For example, without exceeding the scope of the present invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. The expression of the singular includes multiple expressions when there is no clear opposite meaning in the text.

[0055] In addition, the terms such as “below”, “on the lower side”, “above”, and “on the upper side” are used to explain the connection relationship between the components shown in the drawings. Each of the above terms is a relative concept and is explained based on the directions shown in the drawings.

[0056] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those generally understood by those skilled in the art. In addition, such terms as defined in commonly used dictionaries should be interpreted as having a consistent meaning in the context of the relevant technology, and are clearly defined herein unless they are interpreted as ideal or overly formal.

[0057] Terms such as "including" or "having" should be understood as referring to the existence of features, numbers, steps, actions, constituent elements, parts or combinations thereof recorded in the specification, and do not exclude in advance the existence or additional possibility of one or more other features, numbers, steps, actions, constituent elements, parts or combinations thereof.

[0058] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0059] Figure 1 is a perspective view showing a display device according to an embodiment of the present invention, Figure 2 yes Figure 1 An exploded perspective view of a display device.

[0060] Reference Figure 1 as well as Figure 2 The display device EA may be a device activated according to an electrical signal. The display device EA may include various embodiments. For example, the display device EA may include a desktop, a laptop, a computer, a smart TV, a smart phone, etc.

[0061] The display apparatus EA may display an image IM on a front surface. The front surface may be defined in parallel with a plane defined by the first direction DR1 and the second direction DR2.

[0062] The front surface of the display device EA includes a transmission area TA and a frame area BZA adjacent to the transmission area TA. The display device EA displays an image IM in the transmission area TA. The transmission area TA may have a quadrilateral shape parallel to the first direction DR1 and the second direction DR2. However, this is an example, and the transmission area TA may have various shapes and is not limited to any one embodiment.

[0063] The frame area BZA is adjacent to the transmission area TA. The frame area BZA may surround the transmission area TA. However, this is an example, and the frame area BZA may be configured to be adjacent to only one side of the transmission area TA, or may be omitted. A display device according to an embodiment of the present invention may include various embodiments, and is not limited to any one embodiment.

[0064] The normal direction of the front surface may correspond to the thickness direction DR3 (hereinafter referred to as the third direction) of the display device EA. In this embodiment, the front surface (or upper surface) and the back surface (or lower surface) of each component are defined based on the direction of displaying the image IM. The front surface and the back surface are opposite to each other in the third direction DR3.

[0065] On the other hand, the directions indicated by the first direction DR1 to the third direction DR3 are relative concepts and can be changed to other directions. Hereinafter, the first direction to the third direction are the directions indicated by the first direction DR1 to the third direction DR3, respectively, and the same reference numerals are used.

[0066] The display device EA may include a window member WM, a display panel DP, and a receiving member HS.

[0067] The window member WM provides the front surface of the display device EA. The window member WM may be disposed on the front surface of the display panel DP to protect the display panel DP. For example, the window member WM may include a glass substrate, a sapphire substrate, or a plastic film. The window member WM may have a multi-layer or single-layer structure. For example, the window member WM may have a laminated structure of a plurality of plastic films bonded by an adhesive, or a laminated structure of a glass substrate and a plastic film bonded by an adhesive.

[0068] The window member WM may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area through which incident light is transmitted. The transmission area TA may have a shape corresponding to the active area AA. For example, the transmission area TA may overlap the entire surface or at least a portion of the active area AA. The image IM displayed in the active area AA of the display panel DP may be recognized externally through the transmission area TA.

[0069] The frame area BZA may be an area with a relatively low light transmittance compared to the transmission area TA. The frame area BZA defines the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA.

[0070] The frame area BZA may have a predetermined color. The frame area BZA may cover the peripheral area NAA of the display panel DP to block the peripheral area NAA from being recognized from the outside. On the other hand, this is an example, and in the window member WM according to an embodiment of the present invention, the frame area BZA may also be omitted.

[0071] The receiving part HS may be combined with the window part WM. The receiving part HS provides a back surface of the display device EA. The receiving part HS is combined with the window part WM to define an inner space.

[0072] The storage component HS may include a relatively rigid material. For example, the storage component HS may include a plurality of housings and / or plates made of glass, plastic, or metal. The storage component HS may stably protect the various components of the display device EA stored in the internal space from external impacts. The internal space provided by the storage component HS may store the display panel DP and various components, such as a main board, a communication module, and a battery.

[0073] The display panel DP may be disposed at a lower portion of the window member WM and housed in the housing member HS.

[0074] The display panel DP may be an organic light emitting display panel, a liquid crystal display panel, a plasma display panel, an electrophoretic display panel, a MEMS display panel (microelectromechanical system display panel), an electrowetting display panel, or the like.

[0075] The display panel DP may include an active area AA and a peripheral area NAA divided on a plane. The active area AA may be an area that displays an image IM according to an electrical signal. The peripheral area NAA may be an area covered by a border area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA. A driving circuit or driving wiring, etc. for driving the active area AA may be configured in the peripheral area NAA.

[0076] Figure 3 Yes means Figure 2 A block diagram of a portion of a display device.

[0077] In the embodiment of the present invention, the case where the display panel DP is a liquid crystal display panel is taken as an example for description.

[0078] The display device EA may further include a timing controller 200 , a gate driver 300 , and a data driver 400 in addition to the display panel DP.

[0079] The display panel DP may include a plurality of gate lines G1 ˜Gm, a plurality of data lines D1 ˜Dn, a thin film transistor TR, and a display element PX.

[0080] The gate lines G1 to Gm are spaced apart from each other and extend. The data lines D1 to Dn are spaced apart from each other and extend to cross the gate lines G1 to Gm. The display element PX is connected to the gate lines G1 to Gm and the data lines D1 to Dn through the thin film transistor TR, thereby displaying an image IM.

[0081] The timing controller 200 receives image data RGB and control signals from an external graphics control unit (not shown). The control signals may include: a vertical synchronization signal (hereinafter referred to as "Vsync signal"), which is a frame distinction signal; a horizontal synchronization signal (hereinafter referred to as "Hsync signal"), which is a line distinction signal; a data selection signal (hereinafter referred to as "DE signal"), which has a specific signal level during the period of outputting data in order to display the area with data input; and a main clock signal MCLK.

[0082] The timing controller 200 converts the image data RGB into a specification that meets the data driver 400, and outputs the converted image data DATA to the data driver 400. The timing controller 200 generates a gate control signal GS1 and a data control signal DS1. The timing controller 200 outputs the gate control signal GS1 to the gate driver 300, and outputs the data control signal DS1 to the data driver 400.

[0083] The gate control signal GS1 is a signal for driving the gate driver 300 , and the data control signal DS1 is a signal for driving the data driver 400 .

[0084] The gate driver 300 generates a gate signal based on the gate control signal GS1 and outputs the gate signal to the gate lines G1 to Gm. The gate control signal GS1 may include: a scan start signal indicating the start of scanning; at least one clock signal controlling the output period of the gate-on voltage; and an output enable signal defining the duration of the gate-on voltage.

[0085] The data driver 400 generates grayscale voltages based on the image data DATA based on the data control signal DS1 and outputs the grayscale voltages to the data lines D1 to Dn as data voltages.

[0086] The timing controller 200, the gate driver 300 and the data driver 400 can be directly mounted on the display panel DP in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit board and attached to the display panel DP in the form of a TCP (tape carrier package), or mounted on other printed circuit boards. Differently, at least one of the gate driver 300 and the data driver 400 can be integrated on the display panel DP together with the gate lines G1 to Gm, the data lines D1 to Dn and the thin film transistor TR. In addition, the timing controller 200, the gate driver 300 and the data driver 400 can be integrated into a single chip.

[0087] Figure 4 is a plan view showing an enlarged portion of a display panel according to an embodiment of the present invention, Figure 5 It is along Figure 4 The cross-sectional view taken along line II′ of Figure 6 It is along Figure 4 A cross-sectional view taken along line II-II′.

[0088] Figure 4 Shows the configuration with Figure 3 An area of ​​a display element PX.

[0089] The display panel DP may include a base substrate SUB1, a driving element layer DRL, and a display element layer DPL.

[0090] The base substrate SUB1 may be an insulating substrate and may be made of various materials such as glass and plastic, and is not limited to any one embodiment.

[0091] The driving element layer DRL is disposed on the base substrate SUB1. The driving element layer DRL may include a reference Figure 3 The gate lines G1 to Gm, the data lines D1 to Dn, and the thin film transistor TR are described.

[0092] exist Figure 4 , two data lines DLa and DLb adjacent to each other, one gate line GLa, and a thin film transistor TR are illustrated.

[0093] The adjacent data lines DLa and DLb extend along the second direction DR2. The display panel DP described in this embodiment is a high-resolution display panel, and the distance between the adjacent data lines DLa and DLb in the first direction DR1 may be less than 5 μm.

[0094] The gate line GLa may extend substantially in the first direction DR1, but may have a partially bent portion in a region overlapping with the data lines DLa and DLb. The gate line GLa may be disposed on a layer different from that of the data lines DLa and DLb.

[0095] The thin film transistor TR may be connected to a data line DLa and a gate line GLa, and the display element PX of the display element layer DPL may be driven through the data line DLa and the gate line GLa.

[0096] The thin film transistor TR may include a first electrode IE, a second electrode OE, an active pattern ACT, and a control electrode CE. In addition, the driving element layer DRL may include an insulating layer disposed between the first electrode IE, the second electrode OE, the active pattern ACT, and the control electrode CE, and in an embodiment of the present invention, includes first to fourth insulating layers IL1 to IL4.

[0097] The first electrode IE may be disposed on the base substrate SUB1. The first electrode IE may be connected to one end of the active pattern ACT. The first electrode IE may be defined as a portion of the data line DLa. However, this is not limited thereto, and the first electrode IE may have a shape protruding from the data line DLa. The first electrode IE may have a multilayer structure, for example, a structure in which Ti / Al / Ti are stacked in sequence.

[0098] The first insulating layer IL1 may be disposed on the first electrode IE. The first insulating layer IL1 may include silicon oxide or silicon nitride. The first insulating layer IL1 may have a thickness thicker than the first electrode IE. As described later, when the thickness of the first insulating layer IL1 is thicker than the thickness of the first electrode IE, it is easy to control the electrostatic capacitance of the parasitic capacitance CPa and CPb between the second electrode OE and the first electrode IE to be relatively small.

[0099] The active pattern ACT may extend from the first electrode IE in the first direction DR1, and be bent to extend in the second direction DR2 between adjacent data lines DLa and DLb. The active pattern ACT may overlap one of the adjacent data lines DLa and DLb (for example, DLa) and not overlap the other data line (for example, DLb).

[0100] The active pattern ACT may be disposed on the first insulating layer IL1. The active pattern ACT may include any one of amorphous silicon, polysilicon, and an oxide semiconductor. One end of the active pattern ACT may contact the first electrode IE through a first contact hole CH1 provided in the first insulating layer IL1.

[0101] The second insulating layer IL2 may be disposed on the active pattern ACT. The second insulating layer IL2 may insulate the active pattern ACT from the control electrode CE. The second insulating layer IL2 may include silicon oxide or silicon nitride.

[0102] The control electrode CE may be disposed on the second insulating layer IL2. The control electrode CE may be defined as a portion of the gate line GLa. However, it is not limited thereto, and the control electrode CE may have a shape protruding from the gate line GLa. The control electrode CE may overlap the active pattern ACT.

[0103] In the present embodiment, the case where the control electrode CE is arranged on the upper portion of the active pattern ACT is exemplified, but the present invention is not limited thereto and the control electrode CE may be arranged on the lower portion of the active pattern ACT.

[0104] The third insulating layer IL3 may be disposed on the control electrode CE. The third insulating layer IL3 may include silicon oxide or silicon nitride.

[0105] The second electrode OE may be disposed between adjacent data lines DLa and DLb. The gate line GLa may surround the second electrode OE in an open form. That is, the gate line GLa may be disposed on both sides of the second electrode OE in the first direction DR1, and the gate line GLa may be disposed on one side of the second electrode OE in the second direction DR2, but not on the other side.

[0106] The second electrode OE may be disposed on the third insulating layer IL3. The second electrode OE may be disposed on a layer different from the first electrode IE, the active pattern ACT, and the control electrode CE. The second electrode OE may contact the other end of the active pattern ACT through a second contact hole CH2 provided in the second insulating layer IL2 and the third insulating layer IL3.

[0107] The fourth insulating layer IL4 may be disposed on the second electrode OE. The fourth insulating layer IL4 may include silicon oxide or silicon nitride.

[0108] As high-resolution display devices are realized, the distance between adjacent data lines DLa and DLb will become relatively narrow. If the second electrode OE is configured on the same layer as the first electrode IE, the second electrode OE needs to be spaced apart from the first electrode IE. When the margin in the process is considered, the space for configuring the second electrode OE will become narrower. In an embodiment of the present invention, the layer configured with the first electrode IE and the layer configured with the second electrode OE have different structures, so that a driving element layer DRL for realizing a high-resolution display device can be formed.

[0109] Figure 7 is a schematic diagram showing a display panel in which vertical crosstalk occurs.

[0110] To configure in Figure 7 The following description will take as an example a case where display elements in the first area AR1 of the display panel 1 output data corresponding to a white image, and display elements arranged in the remaining area except the first area AR1 output data corresponding to a black image.

[0111] When the data line of the display panel 1 extends along the second direction DR2, the display elements arranged in the second area AR2 and the third area AR3 adjacent to the first area AR1 in the second direction DR2 share the data line with the display elements arranged in the first area AR1. Due to the white data applied to the display elements arranged in the first area AR1, the potential of the pixel electrodes of the display elements arranged in the second area AR2 and the third area AR3 may become higher, and thus, the second area AR2 and the third area AR3 may display a gray image between white and black. At this time, the fourth area AR4 that does not share the data line with the display elements arranged in the first area AR1 can display a black image. This phenomenon can be defined as vertical crosstalk.

[0112] If, unlike the embodiments of the present invention, the first electrode and the second electrode are located on the same layer, or an insulating layer is arranged between the first electrode and the second electrode, the distance between the first electrode and the second electrode becomes relatively close, the electrostatic capacitance of the parasitic capacitance formed between the first electrode and the second electrode will further increase, and the vertical crosstalk phenomenon may increase.

[0113] Refer again Figures 4 to 6 In the embodiment of the present invention, parasitic capacitors CPa and CPb may be formed between the second electrode OE and the adjacent data lines DLa and DLb. A first insulating layer IL1 to a third insulating layer IL3 may be disposed between the second electrode OE and the data lines DLa and DLb. In the embodiment of the present invention, unlike the comparative example, a plurality of insulating layers are disposed between the second electrode OE and the first electrode IE, so that the electrostatic capacitance of the parasitic capacitors CPa and CPb may be controlled to be relatively small, and the vertical crosstalk phenomenon may be minimized.

[0114] Generally, in a thin film transistor, as the electrostatic capacitance of the capacitor formed between the control electrode and the first electrode increases, the RC delay value of a signal applied through the thin film transistor increases.

[0115] If an insulating layer is disposed between the control electrode and the first electrode in a manner different from the embodiment of the present invention, the distance between the control electrode and the first electrode is relatively reduced, and the electrostatic capacitance of the capacitor formed between the control electrode and the first electrode is relatively increased. Therefore, the RC delay value of the signal applied to the pixel electrode of the display element through the thin film transistor is increased, and the response speed or brightness may be insufficient compared to the target value.

[0116] In the embodiment of the present invention, a first insulating layer IL1 and a second insulating layer IL2 may be disposed between the control electrode CE and the first electrode IE. In the embodiment of the present invention, unlike the comparative example, a plurality of insulating layers are disposed between the control electrode CE and the first electrode IE, so the RC delay value of the voltage signal applied to the pixel electrode EL1 of the display element PX is relatively reduced, and the response speed and / or brightness may be improved.

[0117] The display element layer DPL is disposed on the driving element layer DRL.

[0118] The display element layer DPL may include a plurality of display elements PX. In an embodiment of the present invention, the display element PX may be a liquid crystal display element. However, it is not limited thereto, and in other embodiments of the present invention, the display element PX may be an organic light emitting display element.

[0119] The display element PX may include a pixel electrode EL1 , a reference electrode EL2 , and a liquid crystal layer LC.

[0120] The pixel electrode EL1 may be connected to the second electrode OE through a third contact hole CH3 provided in the fourth insulating layer IL4. The pixel electrode EL1 and the reference electrode EL2 may face each other and be insulated. The pixel electrode EL1 and the reference electrode EL2 may include a transparent conductive material. The pixel electrode EL1 may receive a voltage applied by the thin film transistor TR, and the reference electrode EL2 may receive a certain common voltage.

[0121] The liquid crystal layer LC includes liquid crystal molecules. The arrangement state of the liquid crystal molecules can be changed according to the voltage applied to the pixel electrode EL1 and the reference electrode EL2, so that light incident from the lower part of the display element layer DPL can be transmitted or blocked. In the embodiment of the present invention, the case where the liquid crystal layer LC is configured between the pixel electrode EL1 and the reference electrode EL2 is illustrated.

[0122] The display element layer DPL may further include an upper layer UPL. The upper layer UPL may protect the display element PX, or may be a component of the display element PX, such as a base substrate of the reference electrode EL2. The upper layer UPL may be made of an insulating material and may be provided in various forms and materials.

[0123] Figures 8a to 8c In the display panel according to the comparative example, Figure 5 The AA region corresponds to a cross-sectional view of a portion of the structure process. Figures 8a to 8c The manufacturing process of the comparative example illustrates the effect of the display device involved in the embodiment of the present invention.

[0124] for Figures 8a to 8c The symbols of the components of the display panel 2 involved in the comparative example are the same as those in the reference Figures 4 to 6 The symbols of the corresponding components in the display panel DP described are indicated by adding “-1”.

[0125] exist Figures 8a to 8c In the display panel 2, a control electrode CE-1 may be disposed on the upper portion of the active pattern ACT-1, and a second electrode OE-1 may be disposed on the upper portion of the control electrode CE-1. The second electrode OE-1 is connected to the active pattern ACT-1 through a contact hole CHk. Although not shown, the first electrode is disposed between the control electrode CE-1 and the second electrode OE-1, that is, between the second insulating layer IL2-1 and the third insulating layer IL3-1.

[0126] Reference Figure 8a After forming the second electrode OE-1, an insulating layer ILD is formed on the entire surface of the second electrode OE-1. Then, in order to pattern the insulating layer ILD, a photosensitive film is coated on the insulating layer ILD. Then, the photosensitive film configured in the contact area PA for contact with the pixel electrode EL1-1 described later is exposed and removed to form a photosensitive pattern PRT. At this time, a valley is formed in the second electrode OE-1 and the insulating layer ILD covering the contact hole CHk. Since the exposure amount in the valley of the insulating layer ILD is insufficient and the photosensitive film is not removed, a residual photosensitive pattern PRP remains.

[0127] Then, refer to Figure 8b , the photosensitive pattern PRT and the residual photosensitive pattern PRP are etched through the insulating layer ILD using a mask to form a fourth insulating layer IL4 - 1 and a residual insulating layer ILP.

[0128] Then, refer to Figure 8c, a pixel electrode EL1-1 is formed on the second electrode OE-1, the fourth insulating layer IL4-1 and the residual insulating layer ILP. The pixel electrode EL1-1 contacts a portion 11 of the upper surface of the second electrode OE-1 exposed through the residual insulating layer ILP and the fourth insulating layer IL4-1. Due to the residual insulating layer ILP, the contact area between the second electrode OE-1 and the pixel electrode EL1-1 is reduced, and the contact resistance between the second electrode OE-1 and the pixel electrode EL1-1 increases.

[0129] Refer again Figure 5 as well as Figure 6 In the display panel DP according to the embodiment of the present invention, the depth of the second contact hole CH2 where the active pattern ACT contacts the second electrode OE is less than the reference Figures 8a to 8c The depth of the contact hole CHk is described, and therefore, compared with the comparative example, the contact area between the active pattern ACT and the second electrode OE is increased, and the contact resistance can be reduced.

[0130] Fig. 9 In the display panel according to other embodiments of the present invention, Figure 4 The cross-sectional view taken along line II′ of Fig.10 In the display panel according to other embodiments of the present invention, Figure 4 A cross-sectional view taken along line II-II′.

[0131] For reference Fig. 9 as well as Fig.10 The display panel DP1 described in the reference Figure 5 as well as Figure 6 The description will be mainly based on the differences of the display panel DP, and components not described are given the same reference numerals and their detailed description will be omitted.

[0132] The driving element layer DRL1 of the display panel DP1 may further include a light shielding layer BML and a buffer layer BF.

[0133] The light shielding layer BML may be disposed between the base substrate SUB1 and the first electrode IE. The light shielding layer BML may be disposed to overlap with the thin film transistor TR but not to overlap with the display element PX1.

[0134] The light shielding layer BML may block light incident from a lower portion of the base substrate SUB 1. The light shielding layer BML may include a substance that reflects or blocks the incident light.

[0135] The buffer layer BF may be disposed on the light shielding layer BML and disposed below the first electrode IE. The buffer layer BF may improve the bonding force between the base substrate SUB1 and each layer disposed on the upper portion of the base substrate SUB1.

[0136] The display panel DP1 may further include a color filter CF.

[0137] The color filter CF may be disposed between the driving element layer DRL1 and the display element layer DPL1 .

[0138] The color filter CF may be arranged to overlap the pixel electrode EL11 and the reference electrode EL22. The color filter CF includes an organic substance having a color such as red, green, or blue, and plays a role in transmitting light corresponding to a specific wavelength band among the light incident on the display element PX1.

[0139] The display element layer DPL1 may further include a cover layer CP and an interlayer insulating layer ITL.

[0140] A cover layer CP may be disposed on the fourth insulating layer IL4 and the color filter CF. The cover layer CP may be disposed at a lower portion of the display element PX1.

[0141] The cover layer CP covers the color filter CF. The cover layer CP may include an insulating substance.

[0142] The display element PX1 may include a pixel electrode EL11 , a reference electrode EL22 , and a liquid crystal layer LC.

[0143] The reference electrode EL22 may be disposed on the cover layer CP.

[0144] The interlayer insulating layer ITL may be disposed between the pixel electrode EL11 and the reference electrode EL22. The interlayer insulating layer ITL may include silicon oxide or silicon nitride.

[0145] The pixel electrode EL11 may be disposed on the interlayer insulating layer ITL and the reference electrode EL22. The pixel electrode EL11 may be connected to the second electrode OE through a fourth contact hole CH4 provided in the fourth insulating layer IL4, the cover layer CP, and the interlayer insulating layer ITL.

[0146] The liquid crystal layer LC may be disposed on the pixel electrode EL11 and disposed at a lower portion of the upper layer UPL.

[0147] Fig.11 is a cross-sectional view showing a portion of a display panel according to another embodiment of the present invention.

[0148] Reference Fig.11 The display panel DP2 described in the reference Figures 4 to 6 Compared with the display panel DP described above, the difference is that the display panel DP2 is an organic light emitting display panel, and the rest is substantially the same.

[0149] The plurality of display elements PX2 included in the display element layer DPL2 may be organic light emitting display elements.

[0150] The display element PX2 may include a pixel electrode EL1 , a hole control layer HCL, a light emitting layer EML, an electron control layer ECL, and a reference electrode EL2 .

[0151] The pixel electrode EL1 may be connected to the second electrode OE through a third contact hole CH3 provided in the fourth insulating layer IL4 .

[0152] The display element layer DPL2 further includes a pixel definition film PDL. An opening is defined in the pixel definition film PDL to expose at least a portion of the pixel electrode EL1.

[0153] The hole control layer HCL is disposed on the pixel electrode EL1 and may be formed on the entire surface of the base substrate SUB1.

[0154] The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be configured to overlap with the pixel electrode EL1. The light emitting layer EML may include an organic substance and / or an inorganic substance. The light emitting layer EML may generate red, green, blue, or white light, but is not limited to the color of the generated light. The light emitting layer EML may have a multilayer structure.

[0155] The electron control layer ECL is disposed on the light emitting layer EML and may be formed on the entire surface of the base substrate SUB1.

[0156] The reference electrode EL2 is disposed on the electron control layer ECL. The pixel electrode EL1 may be an anode, and the reference electrode EL2 may be a cathode.

[0157] The display element layer DPL2 may include a sealing layer TFE disposed on the reference electrode EL2. The sealing layer TFE directly covers the reference electrode EL2.

[0158] The encapsulation layer TFE may include at least one encapsulation inorganic film and at least one encapsulation organic film. The encapsulation inorganic films and the encapsulation organic films may be alternately stacked.

[0159] Fig.12 In other embodiments of the present invention, Figure 4 The cross-sectional view taken along line II′ of Fig.13 It is along Figure 5 A cross-sectional view taken along line II-II′.

[0160] For reference Fig.12 as well as Fig.13 The display panel DP3 described in the reference Figures 4 to 6 The following description will focus on the differences between the display panel DP described above, and the components not described here are different from those described above. Figures 4 to 6 Same description as .

[0161] The thin film transistor TR1 may include a first electrode IE1, a second electrode OE1, an active pattern ACT1, and a control electrode CE1.

[0162] In addition, the driving element layer DRL1 may include various insulating layers disposed between the first electrode IE1, the second electrode OE1, the active pattern ACT1, and the control electrode CE1, and in an embodiment of the present invention, may include first to fourth insulating layers IL11 to IL41 and an active insulating layer AIL.

[0163] The active insulating layer AIL may be disposed on the base substrate SUB1. The active insulating layer AIL may have a first thickness T1.

[0164] The active pattern ACT1 may be disposed on the active insulating layer AIL. The planar shape of the active pattern ACT1 is similar to that of the reference Figure 4 The active pattern ACT described is similar, so the detailed description is omitted.

[0165] The first insulating layer IL11 may be disposed on the active pattern ACT1. The first insulating layer IL11 may include silicon oxide or silicon nitride.

[0166] The first electrode IE1 may be disposed on the first insulating layer IL11. The first electrode IE1 may be connected to one end of the active pattern ACT1 through a contact hole provided in the first insulating layer IL11. The first electrode IE1 may have a multilayer structure, for example, a structure in which Ti / Al / Ti are stacked in sequence. The first electrode IE1 may have a second thickness T2. The second thickness T2 may be less than the first thickness T1. In the case where the thickness T1 of the active insulating layer AIL is relatively greater than the thickness T2 of the first electrode IE1, it is easy to control the electrostatic capacitance of the parasitic capacitances CPa1 and CPb1 between the second electrode OE1 and the first electrode IE1 to be relatively small.

[0167] The second insulating layer IL21 may be disposed on the first electrode IE1. The second insulating layer IL21 may include silicon oxide or silicon nitride.

[0168] The control electrode CE1 may be disposed on the second insulating layer IL21. The control electrode CE1 may overlap the active pattern ACT1.

[0169] The third insulating layer IL31 may be disposed on the control electrode CE1. The third insulating layer IL31 may include silicon oxide or silicon nitride.

[0170] The second electrode OE1 may be disposed on the third insulating layer IL31 . The second electrode OE1 may pass through a contact hole provided in the first insulating layer IL11 and the second insulating layer IL21 to contact the other end of the active pattern ACT1 .

[0171] The fourth insulating layer IL41 may be disposed on the second electrode OE1. The fourth insulating layer IL41 may include silicon oxide or silicon nitride.

[0172] According to the display panel DP3 involved in the embodiment of the present invention, an active insulating layer AIL is configured under the active pattern ACT1 to increase the relative height of the active pattern ACT1 and the second electrode OE1, thereby increasing the distance between the first electrode IE1 and the second electrode OE1, and reducing the electrostatic capacitance of the parasitic capacitors CPa1 and CPb1.

[0173] Fig.14 is a plan view showing an enlarged portion of a display panel according to another embodiment of the present invention, Fig.15 It is along Fig.14 The cross-sectional view taken along line II′ of Fig.16 It is along Fig.14 A cross-sectional view taken along line II-II′.

[0174] For reference Figures 14 to 16 The display panel DP4 described in the reference Figures 4 to 6 The following description will focus on the differences between the display panel DP described above, and the components not described here are different from those described above. Figures 4 to 6 Same description as .

[0175] The thin film transistor TR2 may include a first electrode IE2, a second electrode OE2, an active pattern ACT2, and a control electrode CE2.

[0176] In addition, the driving element layer DRL2 may include various insulating layers disposed between the first electrode IE2, the second electrode OE2, the active pattern ACT2, and the control electrode CE2, and in an embodiment of the present invention, may include first to fourth insulating layers IL12 to IL42.

[0177] The first electrode IE2 may include a first sub-electrode IES1 and a second sub-electrode IES2.

[0178] The first sub-electrode IES1 may be disposed on the base substrate SUB1. The first sub-electrode IES1 may be disposed on the same layer as the data lines DLa and DLb.

[0179] The second sub-electrode IES2 may be configured on the first sub-electrode IES1 .

[0180] The first insulating layer IL12 may be disposed on the first sub-electrode IES1 .

[0181] The active pattern ACT2 may be disposed on the first insulating layer IL12. The planar shape of the active pattern ACT2 is similar to the reference Figure 4The active patterns ACT described are similar, so the detailed description is omitted.

[0182] The second insulating layer IL22 may be disposed on the active pattern ACT2 .

[0183] The control electrode CE2 may be disposed on the second insulating layer IL22. The control electrode CE2 may overlap the active pattern ACT2.

[0184] The third insulating layer IL32 may be disposed on the control electrode CE2 .

[0185] The second electrode OE2 and the second sub-electrode IES2 may be disposed on the third insulating layer IL32 .

[0186] The second sub-electrode IES2 may pass through the contact hole CH11 provided in the second insulating layer IL22 and the third insulating layer IL32 and be connected to one end of the active pattern ACT2. The contact hole CH11 may expose a portion of the upper surface of the first sub-electrode IES1 and a portion of the edge of the upper surface of the active pattern ACT2. Due to the shape of the contact hole CH11, the second sub-electrode IES2 may be electrically connected to the first sub-electrode IES1 and the active pattern ACT2.

[0187] The second electrode OE2 may pass through a contact hole CH21 provided in the second insulating layer IL22 and the third insulating layer IL32 to be connected to the other end of the active pattern ACT2 .

[0188] The fourth insulating layer IL42 may be disposed on the second sub-electrode IES2 and the second electrode OE2.

[0189] According to the display panel DP4 involved in an embodiment of the present invention, the first electrode IE1 is divided into a first sub-electrode IES1 and a second sub-electrode IES2, and the contact hole CH11 is designed to have a shape that exposes a portion of the upper surface of the active pattern ACT2, so that the electrical connection between the active pattern ACT2 and the first sub-electrode IES1 can be more stable.

[0190] In summary, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined only by the claims.

Claims

1. A display device, comprising: base substrate; an active pattern, disposed on the base substrate; A data line, disposed on the base substrate; a first electrode, disposed between the base substrate and the active pattern and connected to one end of the active pattern, wherein the first electrode and the data line are disposed on the same layer; a second electrode, arranged on an upper portion of the active pattern and connected to the other end of the active pattern, wherein the second electrode is arranged on a layer different from that of the first electrode; a control electrode overlapping the active pattern and insulated from the active pattern; as well as A display element is arranged on the upper part of the second electrode and includes a pixel electrode connected to the second electrode, The data lines include a first data line and a second data line, the first data line and the second data line are adjacent to each other in a first direction and extend in a second direction intersecting the first direction. The pixel electrode is connected to the second electrode between the first data line and the second data line. The pixel electrode overlaps the first data line and the second data line, The active pattern overlaps the first data line and does not overlap the second data line.

2. The display device according to claim 1, further comprising: At least two insulating layers are disposed between the second electrode and the first electrode.

3. The display device according to claim 1, further comprising: a first insulating layer, disposed between the first electrode and the active pattern; a second insulating layer, disposed between the active pattern and the control electrode; a third insulating layer, disposed between the control electrode and the second electrode; as well as The fourth insulating layer is disposed between the second electrode and the display element.

4. The display device according to claim 3, wherein: The first electrode contacts the active pattern through a first contact hole provided in the first insulating layer. The second electrode contacts the active pattern through a second contact hole provided in the second insulating layer and the third insulating layer.

5. The display device according to claim 3, wherein: The thickness of the first insulating layer is thicker than the thickness of the first electrode.

6. The display device according to claim 1, wherein: The control electrode is disposed on an upper portion of the active pattern.

7. The display device according to claim 1, further comprising: a gate line, insulated from and crossing the first data line and the second data line, The gate line surrounds the second electrode.

8. The display device according to claim 1, further comprising: The second electrode is disposed between the first data line and the second data line.

9. The display device according to claim 1, wherein: The display element comprises: a pixel electrode connected to the second electrode; a reference electrode, insulated from and overlapping the pixel electrode, and receiving a predetermined voltage; and The liquid crystal layer changes the arrangement state of liquid crystal molecules according to the voltage applied to the pixel electrode and the reference electrode.

Images