Semiconductor package and semiconductor device

Abstract

Semiconductor packages and semiconductor devices are provided. The semiconductor package includes a semiconductor chip; and a polydimethylsiloxane (PDMS) layer disposed on the semiconductor chip, an upper surface of the PDMS layer being exposed to the outside. Since the semiconductor package can include the PDMS layer, heat dissipation performance of the semiconductor package in a vacuum state can be improved.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0071776, filed with the Korean Intellectual Property Office on June 17, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor packages and semiconductor devices, and more specifically, to semiconductor packages and semiconductor devices having high thermal radiation performance in a vacuum state. Background Technology

[0004] High storage capacity of semiconductor chips and thin, lightweight semiconductor devices incorporating such chips are desirable. Since semiconductor chips generate a significant amount of heat, the ability to dissipate heat to the outside of the semiconductor device is crucial for ensuring operational stability and product reliability.

[0005] Furthermore, semiconductor devices have recently been widely used in devices that operate in a vacuum, such as spacecraft, space stations, and satellites. Therefore, improved heat dissipation performance of semiconductor devices in a vacuum is desirable. Summary of the Invention

[0006] The present invention provides semiconductor packages and semiconductor devices that have high heat dissipation performance in a vacuum state.

[0007] The present invention provides semiconductor packages and semiconductor devices with high electrical insulation and durability.

[0008] According to one aspect of the present invention, this disclosure relates to a semiconductor package comprising: a semiconductor chip; and a polydimethylsiloxane (PDMS) layer disposed on the semiconductor chip, wherein the upper surface of the PDMS layer is exposed to the outside of the semiconductor package.

[0009] According to one aspect of the present invention, this disclosure relates to a semiconductor package comprising: a semiconductor chip; a heat sink located on the semiconductor chip; and a polydimethylsiloxane (PDMS) layer disposed on the heat sink, wherein the upper surface of the PDMS layer is exposed to the outside of the semiconductor package.

[0010] According to an aspect of the present inventive concept, the disclosure relates to a semiconductor device including a substrate, a semiconductor chip mounted on the substrate, a controller mounted on the substrate and configured to control the semiconductor chip, a housing configured to enclose the semiconductor chip and the controller, and an internal polydimethylsiloxane (PDMS) layer on an inner wall of the housing.

[0011] The semiconductor package and semiconductor device according to the present inventive concept include a polydimethylsiloxane (PDMS) layer and can have high heat dissipation performance in a vacuum state.

[0012] In addition, the semiconductor package and semiconductor device according to the present inventive concept include a polydimethylsiloxane (PDMS) layer and can have high electrical insulation and durability. BRIEF DESCRIPTION OF DRAWINGS

[0013] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a cross-sectional view of a semiconductor package according to a comparative example;

[0015] Figures 2 to 14 is a cross-sectional view of a semiconductor package according to an example embodiment of the present inventive concept;

[0016] Figure 15 is a cross-sectional view illustrating a method of forming a polydimethylsiloxane (PDMS) layer according to an example embodiment of the present inventive concept;

[0017] Figure 16 is a graph illustrating a thickness of a PDMS layer formed according to a number of revolutions per minute (RPM) of a rotating plate of a spin chuck;

[0018] Figures 17 to 21 is a view illustrating a method of forming a PDMS layer according to an example embodiment of the present inventive concept. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals will be used throughout the different drawings and similar soaking elements will be indicated with the same or similar reference numeral.

[0020] Figure 1 is a cross-sectional view of a semiconductor package 100 according to a comparative example. The semiconductor package 100 can include a semiconductor chip 10 and a heat spreader 11.

[0021] Referring to Figure 1A heat spreader 11 can be disposed on the semiconductor chip 10. The heat spreader 11 is configured to dissipate heat generated by the semiconductor chip 10 to the outside of the semiconductor package 100. In addition, the heat spreader 11 can include a metal material having high thermal conductivity. For example, the heat spreader 11 can include at least one of metal materials having high thermal conductivity, such as aluminum (Al), nickel (Ni), copper (Cu), magnesium (Mg), and silver (Ag).

[0022] When the heat spreader 11 includes a metal material, the heat spreader 11 can generally have a value of about 0.2 to about 0.7 in thermal emissivity in an infrared (IR) segment. The thermal emissivity can be defined by a ratio of radiated heat of an object to radiated heat on a black body surface. The thermal emissivity can be an index indicating an efficiency of heat energy dissipation caused by radiation on a surface of an object. For example, when the thermal emissivity of an object is high, the object can dissipate a greater amount of heat energy to the outside of the semiconductor package 100 through radiation. In an embodiment, when the heat spreader 11 of the semiconductor package 100 includes Ni, the heat spreader 11 can have a value of about 0.2 to about 0.4 in thermal emissivity in the IR segment.

[0023] When the semiconductor package 100 in the comparative example includes the heat spreader 11 formed of a metal material, the semiconductor package 100 can have weak heat dissipation performance in a vacuum state. The vacuum state can include a state in which air does not exist or a low pressure state in which a pressure of air does not exceed 1 / 1,000 mmHg. When the semiconductor chip 10 of the semiconductor package 100 operates in the vacuum state, a convection heat transfer phenomenon caused by air can be very weak. Accordingly, the heat dissipation performance of the semiconductor package 100 including the heat spreader 11 formed of a metal material can be weak in the vacuum state.

[0024] Figure 2 is a cross-sectional view of a semiconductor package 200 according to an example embodiment of the inventive concept. The semiconductor package 200 according to the inventive concept can include a semiconductor chip 20 and a polydimethylsiloxane (PDMS) layer 21.

[0025] In an embodiment, the semiconductor chip 20 according to the inventive concept can include a plurality of individual devices of various types. The plurality of individual devices of various types can include various microelectronic devices, for example, a metal oxide semiconductor field effect transistor (MOSFET) such as a complementary metal-insulator-semiconductor (CMOS) transistor, an image sensor such as a system large scale integration (LSI) or a CMOS image sensor (CIS), a micro electro mechanical system (MEMS), an active device, and a passive device.

[0026] In an embodiment, the semiconductor chip 20 can include a memory semiconductor chip. The memory semiconductor chip can include a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) or a non-volatile memory semiconductor chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0027] In addition, the semiconductor chip 20 can include a logic chip. For example, the semiconductor chip 20 can include a central processing unit (CPU), a micro processing unit (MPU), a graphic processing unit (GPU), or an application processor (AP).

[0028] In an embodiment, the semiconductor package 200 is illustrated as including one semiconductor chip 20. However, the semiconductor package 200 can include two or more semiconductor chips. The two or more semiconductor chips included in the semiconductor package 200 can be semiconductor chips of the same type or semiconductor chips of different types. For example, the semiconductor package 200 can be a system in package (SIP) in which semiconductor chips of different types are electrically connected and operate as one system.

[0029] In an embodiment, the semiconductor chip 20 can include an upper surface 20a and a lower surface 20b. Chip pads (not shown) can be formed on the lower surface 20b of the semiconductor chip 20. The chip pads can be electrically connected to a plurality of individual devices of various types formed on the semiconductor chip 20. In addition, although not illustrated in FIG. 1, the semiconductor package 200 can further include a passivation layer covering the lower surface 20b of the semiconductor chip 20. Figure 2 In an embodiment, the semiconductor chip 20 can include an upper surface 20a and a lower surface 20b. Chip pads (not shown) can be formed on the lower surface 20b of the semiconductor chip 20. The chip pads can be electrically connected to a plurality of individual devices of various types formed on the semiconductor chip 20. In addition, although not illustrated in FIG. 1, the semiconductor package 200 can further include a passivation layer covering the lower surface 20b of the semiconductor chip 20.

[0030] In an embodiment, when the semiconductor chip 20 of the semiconductor package 200 operates, the semiconductor chip 20 can be heated, and the heated semiconductor chip 20 can radiate electromagnetic waves. For example, when the semiconductor chip 20 operates, the semiconductor chip 20 can be heated to about 70 degrees Celsius until about 130 degrees Celsius, and the semiconductor chip 20 can radiate electromagnetic waves in an IR band. In addition, the semiconductor chip 20 can heat the PDMS layer 21 on the upper surface 20a through thermal conduction.

[0031] In an embodiment, the PDMS layer 21 according to the inventive concept can be disposed on the semiconductor chip 20, and an upper portion of the PDMS layer 21 can be exposed to the outside of the semiconductor package 200. For example, a lower surface of the PDMS layer 21 can be in contact with an upper surface of the semiconductor chip 20, and an upper surface of the PDMS layer 21 can be exposed to the outside of the semiconductor package 200. In addition, the PDMS layer 21 can be an inorganic polymer layer including a chemical structure [C2H6OSi] n .

[0032] In an embodiment, the PDMS layer 21 can be attached to the upper surface 20a of the semiconductor chip 20. As shown, a side surface of the PDMS layer 21 can be exposed to the outside of the semiconductor package 200, or can be self-aligned with a side surface of the semiconductor chip 20. The inventive concept is not limited thereto. In some embodiments, the side surface of the PDMS layer 21 can be disposed inwardly compared to the side surface of the semiconductor chip 20, and an area occupied by the upper surface of the PDMS layer 21 can be smaller than an area occupied by the upper surface of the semiconductor chip 20. For example, when viewed from above, the side surface of the PDMS layer 21 can be located within a perimeter formed by the side surface of the semiconductor chip 20, and an area of the PDMS layer 21 can be smaller than an area of the semiconductor chip 20. Figure 2

[0033] In an embodiment, the PDMS layer 21 can be formed to have a thickness v1 in which a value of a thermal emissivity in an IR band is about 0.6 to about 1. In more detail, when the semiconductor chip 20 of the semiconductor package 200 is operated in a vacuum state, the thickness v1 of the PDMS layer 21 can be determined such that the value of the thermal emissivity of the PDMS layer 21 in the IR band is about 0.6 to about 1.

[0034] In addition, when the semiconductor chip 20 of the semiconductor package 200 is operated in a vacuum state, the thickness v1 of the PDMS layer 21 can be determined such that a value of a thermal emissivity in an IR band is greater than a value of a thermal emissivity in other bands (e.g., a visible light band or an ultraviolet (UV) band).

[0035] ​In an embodiment, the PDMS layer 21 can be formed with a thickness v1 of approximately 1 micrometer to approximately 300 micrometers. More specifically, the PDMS layer 21 can be formed with a thickness v1 of approximately 1 micrometer to approximately 200 micrometers. When the PDMS layer 21 is formed with the above thickness v1 and the semiconductor chip 20 of the semiconductor package 200 operates under vacuum, the PDMS layer 21 can have a thermal emissivity of approximately 0.6 to approximately 1 in the IR band. For example, when the PDMS layer 21 is formed with a thickness v1 of approximately 1 micrometer to approximately 300 micrometers and the semiconductor chip 20 of the semiconductor package 200 operates under vacuum, the PDMS layer 21 can have a thermal emissivity of approximately 0.6 to approximately 1 in the band of electromagnetic waves with wavelengths of approximately 5 micrometers to approximately 15 micrometers.

[0036] In this embodiment, when the PDMS layer 21 is formed to a thickness v1, the heat dissipation performance of the semiconductor package 200 including the PDMS layer 21 under vacuum conditions can be improved. (Referring to...) Figure 1 When the semiconductor chip 10 of the comparative example semiconductor package 100 is operated in a vacuum state, the thermal emissivity of the Ni-containing heat sink 11 in the IR segment can be approximately 0.2 to approximately 0.4. However, when the semiconductor package 200 according to the present invention is operated in a vacuum state, the thermal emissivity of the PDMS layer 21 in the IR segment can have a value of approximately 0.6 to approximately 1. Therefore, the thermal radiation performance of the semiconductor package 200 according to the present invention in a vacuum state can be used as a reference. Figure 1 The thermal radiation performance of the semiconductor package 100 in the comparative example is approximately two to five times greater. For example, the amount of heat radiated to the outside of the semiconductor package 200 through the PDMS layer 21 of the semiconductor package 200 according to the present invention can be greater than the amount of heat radiated to the outside of the semiconductor package 200 through the heat sink 11 of the semiconductor package 200 in the comparative example. Therefore, since the semiconductor package 200 according to the present invention can efficiently dissipate the heat generated by the semiconductor chip 20 in a vacuum state, the operational stability of the semiconductor chip 20 and the product reliability can be ensured.

[0037] In an embodiment, since the viscosity of the PDMS layer 21 according to the inventive concept can be greater than that of ordinary silicone rubber, the PDMS layer 21 can be stably attached to the upper portion of the semiconductor chip 20. Since the coefficient of elasticity of the PDMS layer 21 can be greater than that of ordinary silicone rubber, the semiconductor package 200 including the PDMS layer 21 can be less damaged by external impact. For example, the semiconductor package 200 including the PDMS layer 21 can have greater resistance against damage caused by external impact. Since the reactivity of the PDMS layer 21 to other chemicals (e.g., chemical gas and chemical solution) can be lower than that of ordinary silicone rubber, and the electrical insulation of the PDMS layer 21 can be higher than that of ordinary silicone rubber, the durability of the semiconductor package 200 can be improved.

[0038] Figure 3 is a cross-sectional view of a semiconductor package 300 according to an example embodiment of the inventive concept.

[0039] In an embodiment, the semiconductor package 300 can include a semiconductor chip 30 and a PDMS layer 31. Since the semiconductor chip 30 and the PDMS layer 31 can include the technical features described with reference to the semiconductor chip 20 and the PDMS layer 21 of FIGS. 1 to 4, a detailed description thereof is omitted. Figure 2

[0040] In an embodiment, the PDMS layer 31 can have a concave-convex structure. For example, the PDMS layer 31 can have a structure in which concave and convex are repeated. As shown in FIG. 6, the PDMS layer 31 can include a base 31a and a protrusion 31b protruding from the base 31a. The PDMS layer 31 can have an increased surface area by the concave-convex structure. For example, the surface area of the upper surface of the PDMS layer 31 can be greater than that of the lower surface of the PDMS layer 31. Figure 3

[0041] In an example embodiment, the PDMS layer 31 can have a concave-convex structure by a cutting process. For example, the concave-convex PDMS layer 31 can be formed by etching a portion of a cuboid PDMS layer 31 by means of a mechanical cutting process. The inventive concept is not limited thereto. The concave-convex PDMS layer 31 can be formed by etching a portion of a cuboid PDMS layer 31 by means of a chemical etching process or a photolithography process.

[0042] ​​In an embodiment, the protrusions 31b of the PDMS layer 31 can protrude from the base 31a as a cuboid, and the upper portions of the protrusions 31b can include flat surfaces. In some embodiments, the flat surfaces of the protrusions 31b can be coplanar with each other. The inventive concept is not limited thereto. The upper portions of the protrusions 31b of the PDMS layer 31 can include convex surfaces. In some embodiments, the uppermost surfaces of the convex surfaces can be at the same vertical height. As used herein, terms such as "same", "identical", "planar", or "coplanar" do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other measurement, but are intended to include almost the same orientation, layout, position, shape, size, amount, or other measurement within an acceptable deviation that can occur due to a manufacturing process, for example.

[0043] In an embodiment, the PDMS layer 31 can be formed to a thickness v2 of about 1 micrometer to about 300 micrometers. For example, the sum of the thicknesses of the base 31a and the protrusions 31b of the PDMS layer 31 can be about 1 micrometer to about 300 micrometers. In more detail, the PDMS layer 31 can be formed to a thickness v2 of about 1 micrometer to about 200 micrometers. For example, the sum of the thicknesses of the base 31a and the protrusions 31b of the PDMS layer 31 can be about 1 micrometer to about 200 micrometers.

[0044] In an embodiment, Figure 3 The emissivity of the bumpy PDMS layer 31 can have a value greater than Figure 2 the emissivity of the PDMS layer 21. Accordingly, Figure 3 The heat dissipation performance of the semiconductor package 300 in a vacuum state can be higher than the heat dissipation performance of the semiconductor package 200 described with reference to Figure 2 in a vacuum state.

[0045] Figure 4 is a cross-sectional view of a semiconductor package 400 according to an example embodiment of the inventive concept.

[0046] Referring to Figure 4 , the semiconductor package 400 can include a semiconductor chip 40, a primer 41, an adhesive 42, and a PDMS layer 43. Since the technical features of the semiconductor chip 40 and the PDMS layer 43 can respectively include the technical features described with reference to Figure 2 the semiconductor chip 20 and the PDMS layer 21, detailed descriptions thereof are omitted.

[0047] In an embodiment, a primer 41 can be disposed on the upper surface 40a of the semiconductor chip 40. The primer 41 can be coated on the upper surface 40a of the semiconductor chip 40 and can make the surface of the upper surface 40a of the semiconductor chip 40 flat. For example, the primer 41 can fill any recesses in the upper surface 40a of the semiconductor chip 40. In some embodiments, the upper surface of the primer 41 can be flat. In addition, when the primer 41 is coated on the upper surface 40a of the semiconductor chip 40, the primer 41 can remove impurities on the upper surface 40a of the semiconductor chip 40. The PDMS layer 43 can be stably attached to the upper surface 40a of the semiconductor chip 40 through the primer 41.

[0048] In an embodiment, an adhesive 42 can be disposed on the upper surface of the primer 41 and can attach the PDMS layer 43 to the primer 41. The adhesive 42 can be buried in the PDMS layer 43. Accordingly, the adhesive 42 can not be exposed to the outside of the semiconductor package 400. The adhesive 42 can include a silicon adhesive. For example, the adhesive 42 can include a thermosetting silicon adhesive that is hardened when heat is applied.

[0049] In an embodiment, the PDMS layer 43 can be disposed on the primer 41. In addition, the PDMS layer 43 can cover the adhesive 42 and can be firmly attached to the primer 41 through the adhesive 42. For example, the PDMS layer 43 can surround the upper surface and the side surface of the adhesive 42, and the lower surface of the adhesive 42 can contact the upper surface of the primer 41.

[0050] Figure 5 A semiconductor package 500 according to an example embodiment of the inventive concept. The semiconductor package 500 can include a semiconductor chip 50, a molding material 51, a primer 52, an adhesive 53, a PDMS layer 54, a redistribution layer 55, and an external connection terminal 56. Since the technical features of the semiconductor chip 50, the primer 52, the adhesive 53, and the PDMS layer 54 can respectively include the technical features described with reference to the semiconductor chip 40, the primer 41, the adhesive 42, and the PDMS layer 43 of FIGS. 1 to 6, the detailed description thereof is omitted. Figure 4

[0051] In an embodiment, the molding material 51 can surround the side surface 50c of the semiconductor chip 50. In some embodiments, the molding material can contact the side surface 50c of the semiconductor chip 50. In addition, the molding material 51 can protect the semiconductor chip 50 against external impact. The molding material 51 can include a silicon-based material, a thermosetting material, a thermoplastic material, or a UV-treated material, for example, an epoxy molding compound.

[0052] In an embodiment, as Figure 5 ​As illustrated, the molding material 51 can cover the side surface 50c of the semiconductor chip 50 and can not cover the upper surface 50a of the semiconductor chip 50. For example, an upper surface of the molding material 51 can be coplanar with the upper surface 50a of the semiconductor chip 50. The inventive concept is not limited thereto. The molding material 51 can cover the side surface 50c and the upper surface 50a of the semiconductor chip 50. In some embodiments, the molding material can contact the side surface 50c and the upper surface 50a of the semiconductor chip 50.

[0053] In an embodiment, a redistribution layer 55 can be formed on the lower surface 50b of the semiconductor chip 50. The redistribution layer 55 can electrically connect the chip pads of the semiconductor chip 50 to external connection terminals 56.

[0054] In an embodiment, the redistribution layer 55 can include a redistribution pattern 55a and an insulating layer 55b. The redistribution pattern 55a can be electrically connected to chip pads (not shown) formed on the lower surface 50b of the semiconductor chip 50. In addition, the redistribution pattern 55a can provide an electrical connection path for electrically connecting the chip pads to an external device. The insulating layer 55b can protect the redistribution pattern 55a electrically connected to the chip pads from external impact. For example, the insulating layer 55b can include at least one of a silicon oxide layer, a silicon nitride layer, and an insulating polymer.

[0055] In an embodiment, the external connection terminals 56 can be disposed under the redistribution layer 55 and can be electrically connected to the redistribution pattern 55a of the redistribution layer 55. The external connection terminals 56 can provide a path through which the semiconductor package 500 can be electrically connected to an external device. For example, the semiconductor package 500 can be electrically connected to an external device such as a system substrate and a motherboard through the external connection terminals 56. The external connection terminals 56 can include solder balls. The solder balls can include a metallic material such as tin (Sn), silver (Ag), copper (Cu), or aluminum (Al). The external connection terminals 56 can be spherical. However, the inventive concept is not limited thereto. The external connection terminals 56 can be cylindrical, polyhedral, or polygonal.

[0056] In an embodiment, the PDMS layer 54 can be formed to have a thickness v3 in which a value of a thermal emissivity in an IR segment is about 0.6 to about 1. In more detail, when the semiconductor chip 50 of the semiconductor package 500 is operated in a vacuum state, the thickness v3 of the PDMS layer 54 can be determined such that the value of the thermal emissivity of the PDMS layer 54 in the IR segment is about 0.6 to about 1. For example, the thickness v3 of the PDMS layer 54 can be determined such that the value of the thermal emissivity of the PDMS layer 54 in a segment in which a wavelength of an electromagnetic wave is about 5 micrometers to about 15 micrometers is about 0.6 to about 1.

[0057] In an embodiment, when the PDMS layer 54 is formed to have a thickness v3 of about 1 μm to about 300 μm, the PDMS layer 54 has a thermal emissivity of about 0.6 to about 1 in a segment in which the wavelength of an electromagnetic wave is about 5 μm to about 15 μm. In more detail, the PDMS layer 54 can have a thickness v3 of about 1 μm to about 200 μm.

[0058] In an embodiment, the area of the lower surface of the PDMS layer 54 can be greater than the area of the upper surface 50a of the semiconductor chip 50. For example, the area of the lower surface of the PDMS layer 54 can be substantially equal to the sum of the area of the upper surface 50a of the semiconductor chip 50 and the area of the upper surface of the molding material 51. For example, the area of the PDMS layer 54 can be the same as the combined area of the upper surface 50a of the semiconductor chip 50 and the upper surface of the molding material 51 when viewed from above to below. In addition, the side surface of the PDMS layer 54 can be self-aligned with the side surface of the semiconductor package 500.

[0059] Since the semiconductor package 500 includes the PDMS layer 54, the semiconductor package 500 can have high heat dissipation performance, electrical insulation, and durability in a vacuum state.

[0060] Figure 6 is a cross-sectional view of a semiconductor package 600 according to an example embodiment of the inventive concept. The semiconductor package 600 can include a semiconductor chip 60, a heat spreader 61, and a PDMS layer 62. Since the technical features of the semiconductor chip 60 are the same as those described with reference to the semiconductor chip 10, Figure 1 a detailed description thereof is omitted.

[0061] In an embodiment, the heat spreader 61 can be disposed on the semiconductor chip 60. For example, the heat spreader 61 can be attached to the upper surface 60a of the semiconductor chip 60 through an adhesive film (not shown). Heat generated by the semiconductor chip 60 can be transferred to the heat spreader 61 through a heat conduction phenomenon.

[0062] In an embodiment, the heat spreader 61 can include a metal material. For example, the heat spreader 61 can include at least one metal material among Al, Mg, Cu, Ni, and Ag. The inventive concept is not limited thereto. The heat spreader 61 can include at least one material among a ceramic material, a carbon material, and a polymer material having high thermal conductivity.

[0063] As described above, the PDMS layer 54 can be formed to have a thickness v3 of about 1 μm to about 300 μm. In this case, the PDMS layer 54 can have a thermal emissivity of about 0.6 to about 1 in a segment in which the wavelength of an electromagnetic wave is about 5 μm to about 15 μm. In more detail, the PDMS layer 54 can have a thickness v3 of about 1 μm to about 200 μm. Figure 6As shown, the side surface of the heat spreader 61 can be self-aligned with the side surface of the semiconductor chip 60. Also, the area of the lower surface of the heat spreader 61 can be substantially equal to the area of the upper surface of the semiconductor chip 60. The present inventive concept is not limited thereto. The side surface of the heat spreader 61 can be located inwardly compared to the side surface of the semiconductor chip 60. For example, the side surface of the heat spreader 61 can be located within a perimeter formed by the side surface of the semiconductor chip 60, and the area occupied by the lower surface of the heat spreader 61 can be smaller than the area of the upper surface of the semiconductor chip 60.

[0064] In an embodiment, the PDMS layer 62 can be disposed on the heat spreader 61, and an upper portion of the PDMS layer 62 can be exposed to the outside of the semiconductor package 600. For example, the upper surface of the PDMS layer 62 can be exposed to the outside of the semiconductor package 600. The side surface of the PDMS layer 62 can be self-aligned with the side surface of the heat spreader 61. Also, the area of the lower surface of the PDMS layer 62 can be equal to the area of the upper surface of the heat spreader 61.

[0065] In an embodiment, the PDMS layer 62 can be formed to have a thickness v4 at which the value of the thermal emissivity in the IR band is about 0.7 to about 1. In more detail, when the semiconductor chip 60 of the semiconductor package 600 is operated in a vacuum state, the thickness v4 of the PDMS layer 62 can be determined such that the PDMS layer 62 has a thermal emissivity having a value of about 0.7 to about 1 in the IR band.

[0066] In an embodiment, when the PDMS layer 62 is disposed on the heat spreader 61 to have a thickness v4 of about 1 μm to about 300 μm and the semiconductor package 600 is operated in a vacuum state, the PDMS layer 62 can have a thermal emissivity having a value of about 0.7 to about 1 in a band in which the wavelength of electromagnetic waves is about 5 μm to about 15 μm. In more detail, the PDMS layer 62 can have a thickness v4 of about 1 μm to about 200 μm.

[0067] In an embodiment, since the semiconductor package 600 can include the heat spreader 61 disposed between the semiconductor chip 60 and the PDMS layer 62, the PDMS layer 62 can have a thermal emissivity having a value of about 0.7 to about 1 in a band in which the wavelength of electromagnetic waves is about 5 μm to about 15 μm when the semiconductor chip 60 of the semiconductor package 600 is operated.

[0068] Figure 6 The value of the thermal emissivity of the PDMS layer 62 of the semiconductor package 600 can be greater than the value of the thermal emissivity of the PDMS layer 21 of the semiconductor package 200. Accordingly, Figure 6 The heat dissipation performance of the semiconductor package 600 in a vacuum state can be higher than that of the semiconductor package 200. Figure 2the semiconductor package 200 in a vacuum state. The heat dissipation performance of the semiconductor package 200 and 600 in a vacuum state will be described in more detail later with reference to Figure 10 the graphs of FIGS. 10 and 11.

[0069] In an embodiment, the semiconductor package 600 includes the PDMS layer 62 and can have high heat dissipation performance in a vacuum state as described above. In addition, when the semiconductor chip 60 of the semiconductor package 600 is operated at an atmospheric pressure, heat generated by the semiconductor chip 60 can be dissipated to the outside of the semiconductor package 600 due to a convection heat transfer phenomenon of the heat spreader 61. Accordingly, the semiconductor package 600 can also have high heat dissipation performance at an atmospheric pressure. In addition, the semiconductor package 600 includes the PDMS layer 62 and can have high electrical insulation and durability.

[0070] Figure 7 is a cross-sectional view of a semiconductor package 700 according to an example embodiment of the inventive concept. The semiconductor package 700 can include a semiconductor chip 70, a heat spreader 71, and a PDMS layer 72. Since technical features of the semiconductor chip 70 and the PDMS layer 72 are the same as those of the semiconductor chip 60 and the PDMS layer 62, respectively, described with reference to Figure 1 , a detailed description thereof will be omitted.

[0071] In an embodiment, the PDMS layer 72 can have a concave-convex structure. For example, the PDMS layer 72 can have a structure in which concaves and convexes are repeatedly formed. As Figure 7 indicated, the PDMS layer 72 can include a base 72a and protrusions 72b protruding from the base 72a. Since technical features of the PDMS layer 72 having the concave-convex structure can be the same as those of the PDMS layer 31 having the concave-convex structure described with reference to Figure 3 , a detailed description thereof will be omitted.

[0072] In an embodiment, a thermal emissivity of the PDMS layer 72 having the concave-convex structure of Figure 7 may be higher than a thermal emissivity of the PDMS layer 62 of Figure 6 . Accordingly, a heat dissipation performance of the semiconductor package 700 in a vacuum state of Figure 7 may be higher than the heat dissipation performance in a vacuum state of the semiconductor package 600 described with reference to Figure 6 .

[0073] Figure 8 is a cross-sectional view of a semiconductor package 800 according to an embodiment of the inventive concept. The semiconductor package 800 can include a semiconductor chip 80, a heat spreader 81, a primer 82, an adhesive 83, and a PDMS layer 84.

[0074] In an embodiment, a heat spreader 81 can be disposed on the upper surface 80a of the semiconductor chip 80, and a primer 82 can be disposed on the upper surface of the heat spreader 81. The primer 82 is coated on the upper surface of the heat spreader 81, and can make the surface of the upper surface of the heat spreader 81 flat. For example, the primer 82 can fill any recesses in the upper surface of the heat spreader 81. In addition, when the primer 82 is coated on the upper surface of the heat spreader 81, the primer 82 can remove impurities on the upper surface of the heat spreader 81.

[0075] Since the technical features of the semiconductor chip 80, the primer 82, the adhesive 83, and the PDMS layer 84 of the semiconductor package 800 can be respectively the same as the technical features described with reference to the semiconductor chip 40, the primer 41, the adhesive 42, and the PDMS layer 43 of the semiconductor package 400, Figure 4 a detailed description thereof is omitted.

[0076] Figure 9 is a cross-sectional view of a semiconductor package 900 according to an example embodiment of the inventive concept. The semiconductor package 900 can include a semiconductor chip 90, a molding material 91, a heat spreader 92, a primer 93, an adhesive 94, a PDMS layer 95, a redistribution layer 96, and external connection terminals 97.

[0077] In an embodiment, the area of the lower surface of the heat spreader 92 can be greater than the area of the upper surface 90a of the semiconductor chip 90. For example, the area of the lower surface of the heat spreader 92 can be virtually equal to the sum of the area of the upper surface 90a of the semiconductor chip 90 and the area of the upper surface of the molding material 91. The side surface of the heat spreader 92 can be self-aligned with the side surface of the semiconductor package 900.

[0078] In an embodiment, the area of the lower surface of the PDMS layer 95 can be greater than the area of the upper surface 90a of the semiconductor chip 90. In addition, the area of the lower surface of the PDMS layer 95 can be virtually equal to the area of the upper surface of the heat spreader 92. The side surface of the PDMS layer 95 can be self-aligned with the side surface of the semiconductor package 900.

[0079] Since the technical features of the semiconductor chip 90, the molding material 91, the primer 93, the adhesive 94, the PDMS layer 95, the redistribution layer 96, and the external connection terminals 97 of the semiconductor package 900 can be respectively the same as the technical features described with reference to the semiconductor chip 50, the molding material 51, the primer 52, the adhesive 53, the PDMS layer 54, the redistribution layer 55, and the external connection terminals 56 of the semiconductor package 500, Figure 5 a detailed description thereof is omitted.

[0080] Figure 10 is a graph showing the heat dissipation performance of a semiconductor package according to the inventive concept in a vacuum state. In more detail, Figure 10 the graph shows thatFigure 1 Semiconductor package 100, Figure 2 Semiconductor package 200 and Figure 6 The heat dissipation performance of the semiconductor package 600 under vacuum conditions. Line A of the graph shows the heat dissipation performance under vacuum conditions. Figure 1 The thermal emissivity of the semiconductor package 100 in the electromagnetic wave wavelength range of 5 micrometers to 15 micrometers. Line B of the graph shows the thermal emissivity in... Figure 2 The thermal emissivity of the semiconductor package 200 in the electromagnetic wave wavelength range of 5 micrometers to 15 micrometers. Line C of the graph shows the thermal emissivity in... Figure 6 The thermal emissivity of the electromagnetic waves in the semiconductor package 600 has a wavelength range of 5 micrometers to 15 micrometers.

[0081] Experiments were conducted to measure the heat dissipation performance of semiconductor packages 100, 200, and 600 under vacuum conditions. In the experiments, the semiconductor chips 10, 20, and 60, which comprised semiconductor packages 100, 200, and 600, were of the same performance and type. Furthermore, in the experiments… Figure 1 The material, shape, and thickness of the heat sink 11 of the semiconductor package 100 are the same as those of the heat sink 11. Figure 6 The heat sink 61 of the semiconductor package 600 has the same material, shape, and thickness. Furthermore, in the experiment, the PDMS layer 21 of the semiconductor package 200 has the same material and shape as the PDMS layer 62 of the semiconductor package 600. In the experiment, Figure 2 The PDMS layer 21 of the semiconductor package 200 and Figure 6 The PDMS layer 62 of the semiconductor package 600 is formed to have the same thickness in the range of about 1 micrometer to about 300 micrometers.

[0082] The heat dissipation performance of semiconductor packages 100, 200 and 600 under vacuum conditions is obtained by measuring the thermal emissivity of the heat sink 11 or PDMS layers 21 and 62 of semiconductor packages 100, 200 and 600 in the IR band using an IR polarizer after operating semiconductor packages 100, 200 and 600 under vacuum conditions.

[0083] Reference Figure 10 ,when Figure 1 When the semiconductor chip 10 of the semiconductor package 100 in the comparative example is operated in a vacuum state, the heat sink 11 can have a thermal emissivity of about 0.2 to about 0.4 in the range of electromagnetic wave wavelengths of about 5 micrometers to about 15 micrometers.

[0084] When the present invention is conceived Figure 2The thermal emissivity of the semiconductor chip 20 of the semiconductor package 200 according to the embodiments of the present inventive concept can be greater than the thermal emissivity of the semiconductor chip 20 of the semiconductor package 100 of the comparative example.

[0085] When the semiconductor chip 60 of the semiconductor package 600 according to the embodiments of the present inventive concept operates in a vacuum state, the PDMS layer 62 can have a thermal emissivity of about 0.7 to about 1 in a segment in which the wavelength of electromagnetic waves is about 5 micrometers to about 15 micrometers. Figure 6

[0086] The heat dissipation performance of the semiconductor packages 200 and 600 according to the embodiments of the present inventive concept in a vacuum state can be higher than the heat dissipation performance of the semiconductor package 100 of the comparative example in a vacuum state. In more detail, in a segment in which the wavelength of electromagnetic waves is about 5 micrometers to about 15 micrometers, the thermal emissivity of the semiconductor packages 200 and 600 according to the embodiments of the present inventive concept can be about 1.5 times to about 5 times higher than the thermal emissivity of the semiconductor package 100 of the comparative example.

[0087] In addition, since the semiconductor chip 60 of the semiconductor package 600 according to the embodiments of the present inventive concept is disposed on the PDMS layer 62, the thermal emissivity of the semiconductor chip 60 can be greater than the thermal emissivity of the semiconductor chip 20 of the semiconductor package 200 according to the embodiments of the present inventive concept. Figure 6 The semiconductor package 600 according to the embodiments of the present inventive concept can further include a heat spreader 61 disposed between the semiconductor chip 60 and the PDMS layer 62, and thus the thermal emissivity of the semiconductor chip 60 can be greater than the thermal emissivity of the semiconductor chip 20 of the semiconductor package 200 according to the embodiments of the present inventive concept. Figure 6 The value of the thermal emissivity of the semiconductor package 600 according to the embodiments of the present inventive concept can be greater than the value of the thermal emissivity of the semiconductor package 200 according to the embodiments of the present inventive concept. Figure 2 The value of the thermal emissivity of the semiconductor package 600 according to the embodiments of the present inventive concept can be greater than the value of the thermal emissivity of the semiconductor package 200 according to the embodiments of the present inventive concept.

[0088] Figure 11 FIG. 11 is a cross-sectional view of a semiconductor device 1100 according to an embodiment of the present inventive concept. The semiconductor device 1100 according to the embodiment of the present inventive concept can include a memory device. For example, the semiconductor device 1100 can include a main memory device such as a random access memory (RAM) and a read only memory (ROM). In addition, the semiconductor device 1100 can include a secondary memory device such as a hard disk drive (HDD) and a solid state drive (SSD).

[0089] In an embodiment, the semiconductor device 1100 can be mounted in a device that operates in a vacuum state. In more detail, the semiconductor device 1100 can be mounted in each device that operates in a vacuum state such as a spacecraft, a space station, and a satellite.

[0090] Referring to FIG. 11, Figure 11 , the semiconductor device 1100 can include a substrate 101, a semiconductor chip 102, a controller 103, a housing 104, and an internal PDMS layer 105.

[0091] ​In this embodiment, the semiconductor chip 102 and the controller 103 may be mounted on the upper surface 101a of the substrate 101 and may be electrically connected to the substrate 101. The substrate 101 may include a printed circuit board (PCB) comprising at least one material selected from silicon, phenolic resin, epoxy resin, and polyimide.

[0092] In this embodiment, the upper substrate pad 111 may be disposed on the upper surface 101a of the substrate 101. The upper substrate pad 111 may be electrically connected to the semiconductor chip 102 disposed on the substrate 101. For example, the upper substrate pad 111 may be electrically connected to the semiconductor chip 102 via an upper connection member (not shown) disposed between the semiconductor chip 102 and the upper substrate pad 111.

[0093] In an embodiment, the lower substrate pad 112 may be disposed on the lower surface 101b of the substrate 101. The lower substrate pad 112 may be electrically connected to an external device. For example, a lower connecting member (not shown) may be formed below the lower substrate pad 112, and the lower connecting member may electrically connect the lower substrate pad 112 to an external device.

[0094] In an embodiment, the semiconductor device 1100 may include a plurality of semiconductor chips 102. For example... Figure 11 As shown, the semiconductor device 1100 may include two or more semiconductor chips 102. Depending on the purpose of the semiconductor device 1100, the semiconductor device 1100 may include semiconductor chips 102 of the same type or different types. For example, the semiconductor device 1100 may include semiconductor chips 102 of different types, and the different types of semiconductor chips 102 may be electrically connected to each other.

[0095] In an embodiment, semiconductor device 1100 may include stacked semiconductor chips 102. For example, semiconductor device 1100 may include semiconductor chips 102 stacked in two layers. The inventive concept is not limited thereto. Semiconductor device 1100 may include semiconductor chips 102 stacked in three or more layers. Alternatively, semiconductor device 1100 may include a single-layer semiconductor chip 102.

[0096] In the embodiment, due to the technical features of the semiconductor chip 102 of the semiconductor device 1100 and the reference... Figure 2 The technical features described for semiconductor chip 20 are the same, so its detailed description is omitted.

[0097] In an embodiment, the controller 103 of the semiconductor device 1100 can be mounted on the upper surface 101a of the substrate 101 and can be electrically connected to the substrate 101. Also, the controller 103 can control the semiconductor chip 102. For example, when the semiconductor device 1100 is a memory device, the controller 103 can write data into the semiconductor chip 102 and can read data from the semiconductor chip 102.

[0098] In an embodiment, the semiconductor device 1100 can include a housing 104. The housing 104 can include an inner wall 104a and an outer wall 104b. The housing 104 can be combined with the substrate 101, and the inner wall 104a of the housing 104 can surround the semiconductor chip 102 and the controller 103. The inner wall 104a of the housing 104 can be spaced apart from the upper surface of the semiconductor chip 102. Also, the inner wall 104a of the housing 104 can be spaced apart from the upper surface of the controller 103.

[0099] In an embodiment, the housing 104 can include a metal material having high thermal conductivity. For example, the housing 104 can include at least one of metal materials (such as Al, Ni, Cu, Mg, and Ag) having high thermal conductivity.

[0100] In an embodiment, the inner PDMS layer 105 of the semiconductor device 1100 can be attached to the inner wall 104a of the housing 104. For example, the inner PDMS layer 105 can be formed along the inner wall 104a of the housing 104. For example, the inner PDMS layer 105 can be attached to the upper portion and the side portion of the inner wall 104a of the housing 104. The present inventive concept is not limited thereto. The inner PDMS layer 105 can be attached to one of the upper portion and the side portion of the inner wall 104a of the housing 104. In some embodiments, the inner PDMS layer 105 can be attached to the housing 104 through an adhesive film (not shown).

[0101] In an embodiment, when the semiconductor chip 102 of the semiconductor device 1100 operates in a vacuum state, the inner PDMS layer 105 can partially absorb thermal energy radiated by the semiconductor chip 102. Also, the inner PDMS layer 105 can dissipate the absorbed thermal energy to the outside through thermal radiation.

[0102] In an embodiment, the internal PDMS layer 105 may be formed with a thickness v5, wherein the thermal emissivity in the IR segment is approximately 0.6 to approximately 1. More specifically, when the semiconductor chip 102 of the semiconductor device 1100 operates in a vacuum state, the thickness v5 of the internal PDMS layer 105 may be determined such that the thermal emissivity of the internal PDMS layer 105 in the IR segment is approximately 0.6 to approximately 1. For example, the thickness v5 of the internal PDMS layer 105 may be determined such that the thermal emissivity of the internal PDMS layer 105 in the segment with electromagnetic wavelengths of approximately 5 micrometers to approximately 15 micrometers is approximately 0.6 to approximately 1.

[0103] In an embodiment, when the internal PDMS layer 105 of the semiconductor device 1100 is formed to a thickness v5 of approximately 1 micrometer to approximately 300 micrometers and the semiconductor chip 102 of the semiconductor device 1100 is operated in a vacuum state, the internal PDMS layer 105 may have a thermal emissivity of approximately 0.6 to approximately 1 in the segment of electromagnetic waves with wavelengths of approximately 5 micrometers to approximately 15 micrometers. More specifically, the internal PDMS layer 105 may have a thickness v5 of approximately 1 micrometer to approximately 200 micrometers.

[0104] The internal PDMS layer 105 of the semiconductor device 1100 can partially absorb the heat energy emitted by the substrate 101, the semiconductor chip 102, and the controller 103. Furthermore, the internal PDMS layer 105 can radiate the absorbed heat as electromagnetic waves in the IR region to the outside of the semiconductor device 1100. Therefore, the heat dissipation performance of the semiconductor device 1100 under vacuum conditions can be improved.

[0105] In the embodiment, with Figure 11 Unlike other materials, the internal PDMS layer 105 can be disposed between the side surface of the substrate 101 and the inner wall 104a of the housing 104. Due to the high viscosity of the internal PDMS layer 105, the substrate 101 and the housing 104 can be firmly bonded to each other. In addition, since the internal PDMS layer 105 is disposed between the side surface of the substrate 101 and the inner wall 104a of the housing 104, the heat dissipation performance of the semiconductor device 1100 under vacuum conditions can be improved.

[0106] Figure 12 This is a cross-sectional view of a semiconductor device 1200 according to an exemplary embodiment of the present invention. In the embodiment, the semiconductor device 1200 may include a substrate 101, a semiconductor chip 102, a controller 103, a housing 104, an inner PDMS layer 105, and an outer PDMS layer 121.

[0107] In an embodiment, the external PDMS layer 121 of the semiconductor device 1200 may be attached to the outer wall 104b of the housing 104. For example, the external PDMS layer 121 may be formed along the outer wall 104b of the housing 104. For example, the external PDMS layer 121 may be attached to the upper and side portions of the outer wall 104b of the housing 104. The inventive concept is not limited thereto. The external PDMS layer 121 may be attached to either the upper or side portion of the outer wall 104b of the housing 104. In some embodiments, the external PDMS layer 121 may be attached to the housing 104 by means of an adhesive film (not shown).

[0108] In this embodiment, when the semiconductor chip 102 of the semiconductor device 1200 is operating in a vacuum state, the outer PDMS layer 121 can receive thermal energy from the inner PDMS layer 105, which is heated by the radiative heat of the semiconductor chip 102. The outer PDMS layer 121 can dissipate the thermal energy to the outside of the semiconductor device 1200 through thermal radiation.

[0109] In an embodiment, when the semiconductor chip 102 of the semiconductor device 1200 is formed to a thickness v6 of approximately 1 micrometer to approximately 300 micrometers, the outer PDMS layer 121 may have a thermal emissivity of approximately 0.6 to approximately 1 in the range of electromagnetic wavelengths of approximately 5 micrometers to approximately 15 micrometers. More specifically, the outer PDMS layer 121 may have a thickness v6 of approximately 1 micrometer to approximately 200 micrometers.

[0110] The semiconductor device 1200 may include an external PDMS layer 121 and can have high heat dissipation performance in a vacuum state due to thermal radiation. In addition, the semiconductor device 1200, including the external PDMS layer 121, can have high electrical insulation and durability.

[0111] In the embodiment, with Figure 12 Unlike other materials, the outer PDMS layer 121 can have an uneven structure. For example, the outer PDMS layer 121 can have a structure with repeated concave and convex sections. In some embodiments, the outer PDMS layer 121 can be formed with an uneven structure on the upper and side portions of the outer wall 104b of the housing 104. Due to the technical features of the outer PDMS layer 121 with an uneven structure, it is similar to the reference material. Figure 3 The technical features described for the PDMS layer 31 with its uneven structure are the same, so its detailed description is omitted. Since the external PDMS layer 121 can have an uneven structure, the heat dissipation performance of the semiconductor device 1200 under vacuum conditions can be improved.

[0112] In the embodiments, although Figure 12The semiconductor device 1200 can further include an internal heat spreader disposed between the internal PDMS layer 105 and the case 104, although not shown. In addition, the semiconductor device 1200 can further include an external heat spreader disposed between the external PDMS layer 121 and the case 104. Since the technical features of the internal heat spreader and the external heat spreader are the same as those described with reference to the heat spreader 61 of FIG. 1, a detailed description thereof is omitted. Since the semiconductor device 1200 can further include the external heat spreader and the internal heat spreader, heat dissipation performance of the semiconductor device 1200 in a vacuum state can be improved. Figure 6

[0113] In an embodiment, although Figure 12 The semiconductor device 1200 can include a hole passing through the internal PDMS layer 105, the case 104, and the external PDMS layer 121, although not shown. When the semiconductor device 1200 operates at atmospheric pressure, heated air in the case 104 can be dissipated to the outside of the semiconductor device 1200 through the hole. Accordingly, heat dissipation performance of the semiconductor device 1200 at atmospheric pressure can be improved.

[0114] Figure 13 is a cross-sectional view of a semiconductor device 1300 according to an example embodiment of the inventive concept. The semiconductor device 1300 can include a substrate 101, a semiconductor chip 102, a controller 103, a case 104, an internal PDMS layer 105, an external PDMS layer 121, a first PDMS layer 131, a second PDMS layer 132, and a third PDMS layer 133.

[0115] In an embodiment, the first PDMS layer 131 can be disposed on the semiconductor chip 102 and can be covered by the case 104. For example, an upper surface of the first PDMS layer 131 can be covered by the case 104. In addition, the upper surface of the first PDMS layer 131 can face an upper portion of an inner wall of the case 104. In some embodiments, a lower surface of the first PDMS layer 131 can contact an upper surface of the semiconductor chip 102. Each first PDMS layer 131 can be formed to have a thickness of about 1 micrometer to about 300 micrometers. In more detail, each first PDMS layer 131 can have a thickness of about 1 micrometer to about 200 micrometers. When each first PDMS layer 131 is formed to have the above-described thickness, each first PDMS layer 131 can have a thermal emissivity of about 0.6 to about 1 in a segment in which a wavelength of an electromagnetic wave is about 5 micrometers to about 15 micrometers.

[0116] ​In an embodiment, the second PDMS layer 132 can be disposed on the controller 103, and can be covered by the case 104. For example, an upper surface of the second PDMS layer 132 can be covered by the case 104. Also, the upper surface of the second PDMS layer 132 can face an upper portion of an inner wall of the case 104. In some embodiments, the second PDMS layer 132 can contact an upper surface of the controller 103. The second PDMS layer 132 can be formed to have a thickness of about 1 μm to about 300 μm. In more detail, the second PDMS layer 132 can have a thickness of about 1 μm to about 200 μm. When the second PDMS layer 132 is formed to have the above-described thickness, the second PDMS layer 132 can have a thermal emissivity of about 0.6 to about 1 in a segment in which a wavelength of an electromagnetic wave is about 5 μm to about 15 μm.

[0117] In an embodiment, the third PDMS layer 133 can be attached to an upper surface of the substrate 101. In more detail, the third PDMS layer 133 can be formed in a portion of the upper surface of the substrate 101 in which the semiconductor chip 102 and the controller 103 are not formed. The third PDMS layer 133 can be covered by the case 104. For example, an upper surface of the third PDMS layer 133 can be covered by the case 104. Also, the upper surface of the third PDMS layer 133 can face an upper portion of an inner surface of the case 104. In some embodiments, a lower surface of the third PDMS layer 133 can contact the upper surface of the substrate 101. Each of the third PDMS layers 133 can be formed to have a thickness of about 1 μm to about 300 μm. In more detail, each of the third PDMS layers 133 can be formed to have a thickness of about 1 μm to about 200 μm. When each of the third PDMS layers 133 is formed to have the above-described thickness, each of the third PDMS layers 133 can have a thermal emissivity of about 0.6 to about 1 in a segment in which a wavelength of an electromagnetic wave is about 5 μm to about 15 μm.

[0118] Since the semiconductor device 1300 can include the first PDMS layer 131 to the third PDMS layer 133, heat dissipation performance of the semiconductor device 1300 in a vacuum state can be improved.

[0119] Figure 14 is a cross-sectional view of a semiconductor device 1400 according to an example embodiment of the inventive concept. In an embodiment, the semiconductor device 1400 can include the substrate 101, the semiconductor chip 102, the controller 103, the case 104, the internal PDMS layer 105, the external PDMS layer 121, the first PDMS layer 131, the second PDMS layer 132, the third PDMS layer 133, a first heat spreader 141, a second heat spreader 142, and a third heat spreader 143.

[0120] In an embodiment, the first heat spreader 141 can be disposed between the semiconductor chip 102 and the first PDMS layer 131. When the semiconductor device 1400 including the first heat spreader 141 is operated in a vacuum state, each of the first PDMS layers 131 can have a thermal emissivity of about 0.7 to about 1 in a segment in which a wavelength of an electromagnetic wave is about 5 μm to about 15 μm.

[0121] In an embodiment, the second heat spreader 142 can be disposed between the controller 103 and the second PDMS layer 132. When the semiconductor device 1400 including the second heat spreader 142 is operated in a vacuum state, the second PDMS layer 132 can have an emissivity of about 0.7 to about 1 in a segment in which a wavelength of an electromagnetic wave is about 5 μm to about 15 μm.

[0122] In an embodiment, the third heat spreader 143 can be disposed between the substrate 101 and the third PDMS layer 133. When the semiconductor device 1400 including the third heat spreader 143 is operated in a vacuum state, each of the third PDMS layers 133 can have a thermal emissivity of about 0.7 to about 1 in a segment in which a wavelength of an electromagnetic wave is about 5 μm to about 15 μm.

[0123] In an embodiment, since the semiconductor device 1400 can include the first to third PDMS layers 131 to 133 and the first to third heat spreaders 141 to 143, heat dissipation performance of the semiconductor device 1400 in a vacuum state can be improved. Accordingly, operation stability and product reliability of the semiconductor device 1400 can be improved. In addition, Figure 14 the semiconductor device 1400 in a vacuum state can be higher than Figure 13 the semiconductor device 1300 in a vacuum state.

[0124] Figure 15 is a view illustrating a method of forming a PDMS layer. In more detail, Figure 15 is a view illustrating a method of forming a PDMS layer 21 on a semiconductor chip 20 of a semiconductor package 200. Figure 2 is a view illustrating a method of forming a PDMS layer 21 on a semiconductor chip 20 of a semiconductor package 200.

[0125] In an embodiment, the method of forming the PDMS layer 21 in the semiconductor package 200 can include a process of attaching the semiconductor package 200 to a rotary chuck 150. The rotary chuck 150 can include a main body 151 and a rotary plate 152 rotatable about a central axis of the main body 151. The semiconductor package 200 can be attached to an upper surface of the rotary plate 152 by an adhesive member.

[0126] In an embodiment, the method of forming the PDMS layer 21 in the semiconductor package 200 can include a process of spraying a coating solution L on the semiconductor chip 20 of the semiconductor package 200. The coating solution L can be sprayed on the semiconductor chip 20 through the nozzle 153. The coating solution L can include PDMS and a thermal curing agent. For example, the coating solution L can include PDMS and a thermal curing agent in a weight ratio of 10:1.

[0127] In an embodiment, the method of forming the PDMS layer 21 in the semiconductor package 200 can include a process of rotating the rotating plate 152. The thickness of the PDMS layer 21 formed can vary according to the revolutions per minute (RPM) of the rotating plate 152. For example, when the rotating plate 152 is rotated at about 500 rpm, the PDMS layer 21 can be formed on the semiconductor chip 20 to a thickness of about 200 micrometers. Also, when the rotating plate 152 is rotated at about 3,000 rpm, the PDMS layer 21 can be formed on the semiconductor chip 20 to a thickness of about 20 micrometers.

[0128] In an embodiment, the method of forming the PDMS layer 21 in the semiconductor package 200 can include a process of thermally curing the semiconductor package 200 including the coating solution L. For example, the semiconductor package 200 can be heated at a temperature of about 50 degrees Celsius to about 70 degrees Celsius for about two hours to about four hours. The coating solution L is hardened by the thermal curing agent, and thus, the PDMS layer 21 can be formed on the semiconductor chip 20.

[0129] Figure 16 is a graph showing the thickness of the PDMS layer 21 according to the RPM of the rotating plate 152 of the spin chuck 150.

[0130] Referring to Figure 16 along with Figure 15 , the RPM of the rotating plate 152 can be inversely proportional to the thickness of the PDMS layer 21. In more detail, when the RPM of the rotating plate 152 is greater, the thickness of the PDMS layer 21 can be smaller. Also, when the RPM of the rotating plate 152 is smaller, the thickness of the PDMS layer 21 can be greater.

[0131] In an embodiment, using data related to the amount of the coating solution L sprayed on the semiconductor package 200 according to the RPM of the rotating plate and the thickness of the PDMS layer 21, a plurality of semiconductor packages 200 each including a PDMS layer 21 of a uniform thickness can be manufactured.

[0132] Figures 17 to 21 is a view showing a method of forming a PDMS layer according to an embodiment of the inventive concept. In more detail, Figures 17 to 21 is a view showing a method of forming a PDMS layer according to an embodiment of the inventive concept. In more detail, Figure 8FIG. 8 is a view of a method of forming a PDMS layer 84 on a heat spreader 81 of a semiconductor package 800 according to an embodiment of the present disclosure.

[0133] Referring to Figure 17 The method of forming the PDMS layer 84 on the heat spreader 81 of the semiconductor package 800 can include a process of forming a polymer layer 172 on the silicon substrate 171. The polymer layer 172 can be a water-soluble polymer layer that is dissolvable in water.

[0134] Referring to Figure 18 The method of forming the PDMS layer 84 in the semiconductor package 800 can include a process of forming the PDMS layer 84 on the polymer layer 172. Since technical features of the process of forming the PDMS layer 84 on the polymer layer 172 can be the same as those described with reference to the process of forming the PDMS layer 21 on the semiconductor chip 20 of FIG. 8, a detailed description thereof is omitted. Figure 15

[0135] Referring to Figure 19 The method of forming the PDMS layer 84 in the semiconductor package 800 can include a process of forming the heat spreader 81 on the semiconductor chip 80 and a process of forming the primer 82 on the heat spreader 81. The primer 82 can be coated on the upper surface 81a of the heat spreader 81. The primer 82 can make the surface of the upper surface 81a of the heat spreader 81 flat. In addition, when the primer 82 is coated on the upper surface 81a of the heat spreader 81, the primer 82 can remove impurities on the upper surface 81a of the heat spreader 81.

[0136] In an embodiment, the method of forming the PDMS layer 84 in the semiconductor package 800 can include a process of attaching the adhesive 83 on the primer 82. The adhesive 83 can include a silicon adhesive, such as a thermosetting silicon adhesive.

[0137] Referring to Figure 20 The method of forming the PDMS layer 84 in the semiconductor package 800 can include a process of attaching the PDMS layer 84 formed on the silicon substrate 171 to the primer 82 on the heat spreader 81. In more detail, the PDMS layer 84 formed on the silicon substrate 171 can be attached to the primer 82 on the heat spreader 81 through the adhesive 83. At this time, the adhesive 83 can be buried in the PDMS layer 84, and the adhesive 83 can not be exposed to the outside of the semiconductor package 800.

[0138] In an embodiment, the method of forming the PDMS layer 84 in the semiconductor package 800 can include a process of thermally curing the semiconductor package 800. Through the thermal curing process, the PDMS layer 84 can be firmly attached to the heat spreader 81.

[0139] Referring to Figure 21 ​The method of forming the PDMS layer 84 in the semiconductor package 800 can include a process of dissolving the polymer layer 172 into water. The polymer layer 172 is dissolved into water, and thus, the silicon substrate 171 can be easily detached from the semiconductor package 800.

[0140] While the present concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package comprising: a semiconductor chip; a polydimethylsiloxane layer disposed on an upper surface of the semiconductor chip; a primer on the semiconductor chip; and an adhesive on the primer, wherein a lower surface of the polydimethylsiloxane layer faces the upper surface of the semiconductor chip, and an upper surface of the polydimethylsiloxane layer is exposed to an outside of the semiconductor package, wherein the polydimethylsiloxane layer is disposed on the primer, and wherein the adhesive is buried in the polydimethylsiloxane layer, the polydimethylsiloxane layer surrounds an upper surface and side surfaces of the adhesive, and a lower surface of the adhesive contacts an upper surface of the primer. 2.The semiconductor package of claim 1, the polydimethylsiloxane layer has a thickness of 1 to 300 micrometers. wherein, 3.The semiconductor package of claim 2, a side surface of the polydimethylsiloxane layer is self-aligned with a side surface of the semiconductor chip, and wherein wherein the polydimethylsiloxane layer has a thickness of 1 to 200 micrometers. 4.The semiconductor package of claim 1, the polydimethylsiloxane layer has a concavo-convex structure. wherein 5.The semiconductor package of claim 1, further comprising: a molding material surrounding a side surface of the semiconductor chip; a redistribution layer formed on a lower surface of the semiconductor chip; and an external connection terminal electrically connected to the redistribution layer, wherein an area of the lower surface of the polydimethylsiloxane layer is greater than an area of the upper surface of the semiconductor chip. 6.A semiconductor package comprising: a semiconductor chip; a heat spreader on an upper surface of the semiconductor chip; a polydimethylsiloxane layer disposed on the heat spreader; a primer on the heat spreader; and an adhesive on the primer, wherein the heat spreader is interposed between the semiconductor chip and the polydimethylsiloxane layer, wherein an upper surface of the polydimethylsiloxane layer is exposed to an outside of the semiconductor package, wherein the polydimethylsiloxane layer is disposed on the primer, and wherein the adhesive is buried in the polydimethylsiloxane layer, the polydimethylsiloxane layer surrounds an upper surface and side surfaces of the adhesive, and a lower surface of the adhesive contacts an upper surface of the primer. 7.The semiconductor package of claim 6, the polydimethylsiloxane layer is formed to a thickness of 1 to 300 micrometers. 8.The semiconductor package of claim 7, a side surface of the heat spreader is disposed inwardly compared to a side surface of the semiconductor chip, wherein wherein a side surface of the polydimethylsiloxane layer is self-aligned with a side surface of the heat spreader, and wherein the polydimethylsiloxane layer is formed to a thickness of 1 to 200 micrometers. wherein the adhesive comprises a thermosetting silicone adhesive. ​ ​ 9. The semiconductor package of claim 6, wherein, ​ 10. The semiconductor package of claim 6, wherein a surface area of an upper surface of the polydimethylsiloxane layer is greater than a surface area of a lower surface of the polydimethylsiloxane layer.

11. The semiconductor package of claim 6, further comprising: a molding material surrounding a side surface of the semiconductor chip; a redistribution layer formed on a lower surface of the semiconductor chip; and an external connection terminal electrically connected to the redistribution layer, wherein a surface area of a lower surface of the polydimethylsiloxane layer is greater than a surface area of an upper surface of the semiconductor chip and equal to a surface area of an upper surface of the heat spreader.

12. A semiconductor device comprising: a substrate; a semiconductor chip mounted on an upper surface of the substrate; a controller mounted on the upper surface of the substrate and configured to control the semiconductor chip; a housing configured to enclose the semiconductor chip and the controller; an internal polydimethylsiloxane layer on an inner wall of the housing; a primer on the semiconductor chip; a first polydimethylsiloxane layer disposed on the primer; and an adhesive on the primer, a lower surface of the adhesive contacting an upper surface of the primer, wherein the adhesive is buried in the first polydimethylsiloxane layer and the first polydimethylsiloxane layer surrounds an upper surface and side surfaces of the adhesive.

13. The semiconductor device of claim 12, the internal polydimethylsiloxane layer is formed to a thickness of 1 to 300 micrometers, and wherein wherein the internal polydimethylsiloxane layer is disposed between a side surface of the substrate and the inner wall of the housing.

14. The semiconductor device of claim 12, further comprising: an external polydimethylsiloxane layer on an outer wall of the housing, wherein the external polydimethylsiloxane layer is formed to a thickness of 1 to 300 micrometers.

15. The semiconductor device of claim 12, an upper surface of the first polydimethylsiloxane layer is covered by the housing, and wherein wherein the first polydimethylsiloxane layer has a thickness of 1 to 300 micrometers.

16. The semiconductor device of claim 12, further comprising: a second polydimethylsiloxane layer disposed on the controller, wherein an upper surface of the second polydimethylsiloxane layer is covered by the housing, and wherein the second polydimethylsiloxane layer has a thickness of 1 to 300 micrometers.

17. The semiconductor device of claim 16, further comprising: a heat spreader disposed between the controller and the second polydimethylsiloxane layer.

18. The semiconductor device of claim 12, further comprising: ​ a second polydimethylsiloxane layer disposed on the substrate, wherein an upper surface of the second polydimethylsiloxane layer is covered by the case, and wherein the second polydimethylsiloxane layer has a thickness of 1 to 300 micrometers.

19. The semiconductor device according to claim 12, wherein, the semiconductor device is mounted in a device that operates in a vacuum state.

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