integrated circuit

Abstract

An integrated circuit includes a fin active region protruding from a substrate; a plurality of semiconductor patterns on an upper surface of the fin active region; a gate electrode surrounding the plurality of semiconductor patterns and including a main gate portion and sub gate portions, the main gate portion on an uppermost semiconductor pattern of the plurality of semiconductor patterns, the sub gate portions between the fin active region and a lowermost semiconductor pattern of the plurality of semiconductor patterns and between the plurality of semiconductor patterns, respectively; a spacer structure disposed on sidewalls of the main gate portion; and a source / drain region on a side of the gate electrode. The source / drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width that is less than the first width.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0071768, filed on June 17, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of this disclosure relate to integrated circuits and methods of manufacturing the same, and more specifically, to integrated circuits including multi-gate structure transistors and methods of manufacturing the same. Background Technology

[0004] Due to advancements in electronic technology, integrated circuits have become highly integrated and smaller in size. However, this miniaturization has led to a decrease in the reliability of integrated circuits due to short-channel effects. To mitigate these effects, multi-gate integrated circuits, such as nanosheet transistors, have been proposed. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, an integrated circuit may include: a substrate; a finned active region protruding from the substrate and extending in a first direction; a plurality of semiconductor patterns located on an upper surface of the finned active region; a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, the gate electrode including a main gate portion and a plurality of sub-gate portions, the main gate portion being disposed on the uppermost semiconductor pattern of the plurality of semiconductor patterns, the plurality of sub-gate portions being respectively located between the finned active region and the lowermost semiconductor pattern of the plurality of semiconductor patterns and between the plurality of semiconductor patterns; a spacer structure located on a sidewall of the main gate portion; and a source / drain region disposed on one side of the gate electrode and connected to the plurality of semiconductor patterns, the source / drain region contacting the bottom surface of the spacer structure. The top portion of the uppermost semiconductor pattern may have a first width in the first direction. The bottom portion of the uppermost semiconductor pattern may have a second width in the first direction that is less than the first width. The main gate portion may include a bottom portion having sloping sidewalls.

[0006] According to an exemplary embodiment of the present invention, an integrated circuit may include: a substrate; a finned active region protruding from the substrate and extending in a first direction; a plurality of semiconductor patterns located on an upper surface of the finned active region; a gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, the gate electrode including a main gate portion and a plurality of sub-gate portions, the main gate portion being disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns, the plurality of sub-gate portions being respectively disposed between the finned active region and the lowermost semiconductor pattern among the plurality of semiconductor patterns and between the plurality of semiconductor patterns; a spacer structure located on a sidewall of the main gate portion; and a source / drain region disposed on one side of the gate electrode and connected to the plurality of semiconductor patterns, the source / drain region contacting the bottom surface of the spacer structure. The top portion of the uppermost semiconductor pattern may have a first width in the first direction. The bottom portion of the uppermost semiconductor pattern may have a second width in the first direction that is less than the first width. The bottom portion of the main gate portion may have a third width in the first direction. The middle portion of the main gate portion may have a fourth width, which is different from the third width, in the first direction.

[0007] According to an exemplary embodiment of the present invention, an integrated circuit may include: a substrate; a finned active region protruding from the substrate; a plurality of semiconductor patterns located on an upper surface of the finned active region, each of the plurality of semiconductor patterns including a channel region; a gate electrode surrounding the plurality of semiconductor patterns and including a main gate portion and a plurality of sub-gate portions, the main gate portion being disposed on the uppermost semiconductor pattern of the plurality of semiconductor patterns, the plurality of sub-gate portions being disposed between the finned active region and the lowermost semiconductor pattern of the plurality of semiconductor patterns, and between the plurality of semiconductor patterns; a spacer structure located on a sidewall of the main gate portion; and a source / drain region located on one side of the gate electrode and connected to the plurality of semiconductor patterns, the source / drain region contacting the bottom surface of the spacer structure. The bottom portion of the uppermost semiconductor pattern may be narrower than the top portion of the uppermost semiconductor pattern. At least a portion of the sidewall of the main gate portion may be inclined. The sidewall of the main gate portion may overlap at least partially perpendicularly with the spacer structure. Attached Figure Description

[0008] Figure 1 This is a layout diagram illustrating an example embodiment of an integrated circuit according to a concept of the present invention.

[0009] Figure 2 It is along Figure 1 The cross-sectional view taken by line A1-A1'.

[0010] Figure 3 It is along Figure 1 The cross-sectional view taken from line B1-B1'.

[0011] Figure 4 yes Figure 2 A magnified view of part of the CX1.

[0012] Figure 5 This is a cross-sectional view illustrating an example embodiment of an integrated circuit according to a concept of the present invention.

[0013] Figure 6 This is a cross-sectional view illustrating an example embodiment of an integrated circuit according to a concept of the present invention.

[0014] Figure 7 This is a cross-sectional view illustrating an example embodiment of an integrated circuit according to a concept of the present invention.

[0015] Figure 8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11 , Figure 12 , Figure 13 , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. Figure 8 , Figure 9A , Figure 10A , Figure 11 , Figure 12 , Figure 13 , Figure 14A , Figure 15A , Figure 16A and Figure 17A It is along Figure 1 The cross-sectional view taken by line A1-A1'. Figure 9B , Figure 10B , Figure 16B , Figure 17B It is along Figure 1 The cross-sectional view taken from line B1-B1'. Figure 14B and Figure 15B They are in Figure 14A and Figure 15AA horizontal cross-sectional view at the first vertical height LV1.

[0016] Figure 8 , Figure 9A and Figure 9B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. Figure 10A and Figure 10B It is along Figure 11 The cross-sectional view taken from line A1-A1'. Figure 12 Is Figure 4 A horizontal cross-sectional view at the first vertical height LV1.

[0017] Figure 13 and Figure 13 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention.

[0018] Figure 14A , Figure 14B and Figure 4 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. Detailed Implementation

[0019] Various exemplary embodiments will now be described more fully below with reference to the accompanying drawings. Throughout this application, the same reference numerals may denote the same elements.

[0020] Figure 15A This is a layout diagram illustrating an example embodiment of an integrated circuit according to a concept of the present invention. Figure 15B It is along Figure 16A The cross-sectional view taken by line A1-A1'. Figure 16B It is along Figure 17A The cross-sectional view taken from line B1-B1'. Figure 17B yes Figure 2 A magnified view of part of the CX1.

[0021] Reference Figure 18 In an example embodiment of the integrated circuit 100 according to the present invention, the substrate 110 may include a finned active region FA in the device region DR. The finned active region FA can be used to form a transistor TR, such as an NMOS transistor or a PMOS transistor.

[0022] Substrate 110 may include semiconductor materials (such as Si or Ge) or compound semiconductor materials (such as SiGe, SiC, GaAs, InAs, or InP). In some embodiments, substrate 110 may include group III-V materials and / or group IV materials. Group III-V materials may be binary, ternary, or quaternary compounds comprising at least one group III material and at least one group V material. Group III-V materials may include compounds comprising at least one element selected from In, Ga, and Al as group III materials and at least one element selected from As, P, and Sb as group V materials. For example, group III-V materials may include InP, In... z Ga 1-z As (0≤z≤1) and Al z Ga 1-z At least one of As (0≤z≤1). Binary compounds can be, for example, one of InP, GaAs, InAs, InSb, and GaSb. Ternary compounds can be, for example, one of InGaP, InGaAs, AlInAs, InGaSb, GaAsSb, and GaAsP. Group IV materials can be Si or Ge. However, Group III-V and Group IV materials are not limited to those mentioned above.

[0023] In some examples, group III-V materials and group IV materials such as Ge can be used as channel materials for fabricating low-power and high-speed transistors. High-performance CMOS transistors can be formed by using semiconductor substrates comprising group III-V materials (e.g., GaAs) with higher electron mobility than silicon substrates, and semiconductor substrates comprising semiconductor materials such as Ge with higher hole mobility than silicon substrates. In some embodiments, when an NMOS transistor is formed on substrate 110, substrate 110 may include one of the aforementioned group III-V materials. In some embodiments, when a PMOS transistor is formed on substrate 110, at least a portion of substrate 110 may include Ge. In some embodiments, substrate 110 may have a silicon-on-insulator (SOI) structure. Substrate 110 may include conductive regions, such as doped wells or doped structures.

[0024] The finned active region FA can extend in a first direction X and can protrude from the upper surface 110M of the substrate 110 in a third direction Z. The first direction can be parallel to the upper surface 110M of the substrate 110. The third direction can be perpendicular to the upper surface 110M of the substrate 110. A device isolation trench 114T can be formed in the substrate 110 to define the finned active region FA. A device isolation layer 114 can be disposed in the device isolation trench 114T. In some embodiments, the device isolation layer 114 may include a device isolation liner conformally formed on the inner surface of the device isolation trench 114T and a gap-filling insulating layer disposed on the device isolation liner and filling the device isolation trench 114T. The upper surface of the device isolation layer 114 can be located at the same height as the upper surface of the finned active region FA. In some embodiments, the upper surface of the device isolation layer 114 can be located at a lower height than the upper surface of the finned active region FA, such that the lower sidewall of the finned active region FA can be covered by the device isolation layer 114. Device isolation pads and gap-filling insulating layers may include silicon oxide, silicon nitride, or combinations thereof.

[0025] Multiple semiconductor patterns NS can be disposed on the finned active region FA, perpendicularly spaced from the upper surface 110M of the substrate 110. The multiple semiconductor patterns NS can comprise the same material as the substrate 110. For example, the multiple semiconductor patterns NS can comprise semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe, SiC, GaAs, InAs, or InP. Each of the multiple semiconductor patterns NS can comprise a channel region.

[0026] Multiple semiconductor patterns NS may include a first semiconductor pattern NS1, a second semiconductor pattern NS2, and a third semiconductor pattern NS3 sequentially stacked on the upper surface 110M of the substrate 110. Each of the multiple semiconductor patterns NS may have a relatively large width in the second direction Y and a relatively small thickness in the third direction Z. For example, each of the multiple semiconductor patterns NS may have a nanosheet shape. The second direction Y may be parallel to the upper surface 110M of the substrate 110 and perpendicular to the first direction X. For example, the first semiconductor pattern NS1 may have a first thickness t11 of approximately 1 nm to 10 nm, the second semiconductor pattern NS2 may have a second thickness t12 of approximately 1 nm to 10 nm, and the third semiconductor pattern NS3 may have a third thickness t13 of approximately 1 nm to 20 nm. Figure 19A As shown, the third thickness t13 of the third semiconductor pattern NS3 can be greater than the first thickness t11 of the first semiconductor pattern NS1 and the second thickness t12 of the second semiconductor pattern NS2, but the present invention is not limited thereto. In some embodiments, the plurality of semiconductor patterns NS can each have a width of approximately 5 nm to 100 nm in the first direction X or the second direction Y, but the present invention is not limited thereto.

[0027] like Figure 19B As shown, multiple semiconductor patterns NS can be spaced apart from each other. However, the inventive concept is not limited to this. For example, the spacing between the multiple semiconductor patterns NS can be different from each other. The number of multiple semiconductor patterns NS is not limited to this. Figure 18 The quantity shown.

[0028] The gate electrode 120 may extend along the second direction Y in the fin active region FA. The gate electrode 120 may surround a plurality of semiconductor patterns NS and may extend on the fin active region FA and the device isolation layer 114.

[0029] The gate electrode 120 may include a main gate portion 120M and a plurality of sub-gate portions 120S. The main gate portion 120M may cover the uppermost semiconductor pattern NS (e.g., the upper surface of the third semiconductor pattern NS3). The plurality of sub-gate portions 120S may be respectively disposed between the finned active region FA and the lowermost semiconductor pattern NS, and between the plurality of semiconductor patterns NS. For example, the plurality of sub-gate portions 120S may be respectively disposed between the finned active region FA and the first semiconductor pattern NS1, between the first semiconductor pattern NS1 and the second semiconductor pattern NS2, and between the second semiconductor pattern NS2 and the third semiconductor pattern NS3. The main gate portion 120M may be disposed on the upper surface of the third semiconductor pattern NS3 and the device isolation layer 114, and may be connected to the plurality of sub-gate portions 120S.

[0030] The main gate portion 120M has a sloping sidewall 120SI at its bottom portion that is inclined along the third direction Z (or, not perpendicular to the upper surface 110M of the substrate 110). The sidewall 120SW of the main gate portion 120M may include the sloping sidewall 120SI extending from the bottom surface of the main gate portion 120M to a predetermined height. For example, the height of the sloping sidewall 120SI of the main gate portion 120M in the third direction Z may be approximately 1% to 20% of the height of the main gate portion 120M on the uppermost semiconductor pattern NS.

[0031] The gate electrode 120 may include a work function conductive layer and a buried conductive layer. The work function conductive layer may be disposed on the upper surface of a plurality of semiconductor patterns NS, and the buried conductive layer may be disposed on the work function conductive layer. In some embodiments, the work function conductive layer may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof, but the inventive concept is not limited thereto. The buried conductive layer may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof. However, the inventive concept is not limited thereto.

[0032] A gate insulating layer 128 may be disposed between the gate electrode 120 and each of the plurality of semiconductor patterns NS. The gate insulating layer 128 may be conformally disposed on the surface of the plurality of semiconductor patterns NS. The gate insulating layer 128 may be disposed on the upper surface of the finned active region FA and may extend onto the device isolation layer 114.

[0033] In some embodiments, the gate insulating layer 128 may have a stacked structure of an interface layer and a high-dielectric layer. The interface layer can be used to mitigate interface defects between the high-dielectric layer and the surfaces of the plurality of semiconductor patterns NS, and between the high-dielectric layer and the upper surface of the finned active region FA.

[0034] The interface layer may include a low-dielectric material having a dielectric constant of about 9 or less, such as silicon oxide, silicon oxynitride, germanium oxide, gallium oxide, or combinations thereof. In some embodiments, the interface layer may include silicates, a combination of silicates and silicon oxide, or a combination of silicates and silicon oxynitride. In some embodiments, the interface layer may be omitted.

[0035] The high-dielectric layer may include a material with a dielectric constant higher than that of silicon oxide. For example, the high-dielectric layer may have a dielectric constant of approximately 10 to 25. The high-dielectric layer may include, for example, hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof, but the inventive concept is not limited thereto. The high-dielectric layer can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The high-dielectric layer may have a dielectric constant of approximately... to The thickness is [not specified], but the concept of the present invention is not limited thereto.

[0036] The spacer structure 130 may be disposed on each of the opposing sidewalls of the main gate portion 120M. The gate insulating layer 128 may be disposed between the main gate portion 120M and the spacer structure 130. The spacer structure 130 may include a first spacer 132 and a second spacer 134 sequentially disposed on the sidewall 120SW of the main gate portion 120M.

[0037] like Figure 19A As shown, the first spacer 132 may be conformally disposed on the sidewall 120SW of the main gate portion 120M and on the third semiconductor pattern NS3 adjacent to the main gate portion 120M. The bottom portion of the first spacer 132 may extend in a horizontal direction (e.g., a first direction X) on the upper surface of the third semiconductor pattern NS3 and may be disposed between the second spacer 134 and the third semiconductor pattern NS3. The first spacer 132 and the second spacer 134 may include silicon nitride or silicon oxynitride, but are not limited thereto.

[0038] A recessed region RS1 can be formed in a finned active region FA on each of the multiple semiconductor patterns NS on opposite sides. A source / drain region 140 can fill the recessed region RS1. The source / drain region 140 can be connected to the end of one side of the multiple semiconductor patterns NS.

[0039] The source / drain region 140 may include a first semiconductor layer 142, a second semiconductor layer 144, a third semiconductor layer 146, and a fourth semiconductor layer 148 sequentially stacked on the inner surface of the recessed region RS1. The first to fourth semiconductor layers 142, 144, 146, and 148 may be grown from the fin active region FA and multiple semiconductor patterns NS using a selective epitaxial growth (SEG) process.

[0040] In some embodiments, a first semiconductor layer 142 may be formed to a predetermined thickness in the inner surface of the recessed region RS1 and may contact a plurality of semiconductor patterns NS. A second semiconductor layer 144 may be conformally formed to a relatively small thickness on the first semiconductor layer 142. A third semiconductor layer 146 may be formed to fill the lower portion of the recessed region RS1. A fourth semiconductor layer 148 may be formed on the third semiconductor layer 146 and the second semiconductor layer 144 to fill the upper portion of the recessed region RS1. A portion of the upper surface of the fourth semiconductor layer 148 may contact the bottom surface of the spacer structure 130. Another portion of the upper surface of the fourth semiconductor layer 148 may protrude to a height higher than the bottom surface of the spacer structure 130. Therefore, the fourth semiconductor layer 148 may fill the upper portion of the recessed region RS1, and the edge portion of the fourth semiconductor layer 148 may extend below the spacer structure 130 to overlap with the spacer structure 130.

[0041] The first to fourth semiconductor layers 142, 144, 146, and 148 may include at least one of an epitaxial Si layer, an epitaxial SiGe layer, and an epitaxial SiP layer. In some embodiments, all of the first to fourth semiconductor layers 142, 144, 146, and 148 may include a Si layer, and the impurity concentrations of the first to fourth semiconductor layers 142, 144, 146, and 148 may be different from each other. In some embodiments, all of the first to fourth semiconductor layers 142, 144, 146, and 148 may include a SiGe layer, and the Ge content of the first to fourth semiconductor layers 142, 144, 146, and 148 may be different from each other. In some embodiments, at least one of the first to fourth semiconductor layers 142, 144, 146, and 148 may include a Si layer, and at least another semiconductor layer of the first to fourth semiconductor layers 142, 144, 146, and 148 may include a SiGe layer. However, the inventive concept is not limited thereto. In some embodiments, at least one of the first to fourth semiconductor layers 142, 144, 146, and 148 may be omitted. In some embodiments, at least one additional semiconductor layer may be formed between adjacent layers of the first to fourth semiconductor layers 142, 144, 146, and 148.

[0042] like Figure 1 As shown, the width of the recessed region RS1 in the middle portion can be greater than the width of the recessed region RS1 in the upper portion. Therefore, the width of the source / drain region 140 in the middle portion of the recessed region RS1 can be greater than the width of the source / drain region 140 in the uppermost portion, such that at least a portion of the plurality of semiconductor patterns NS in contact with the source / drain region 140 has inclined sidewalls.

[0043] The source / drain region 140 may have sloping sidewalls; therefore, the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3) may have a pair of sloping sidewalls NSSW that conform to the contour of the sloping sidewalls of the source / drain region 140. For example, both of the sloping sidewalls NSSW may contact the first semiconductor layer 142 of the source / drain region 140. The top portion of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3) may have a first width W11 in the first direction X, and the bottom portion of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3) may have a second width W12 in the first direction X that is smaller than the first width.

[0044] The uppermost semiconductor pattern (or the third semiconductor pattern NS3) may include a tail portion NSTL adjacent to (or below) the spacer structure 130 at each of its opposite edge portions along the first direction X. The tail portion NSTL may indicate a portion of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3) that vertically overlaps with the spacer structure 130. The tail portion NSTL may project outward relative to the sidewall 120SW of the main gate portion 120M in the first direction X. For example, the edge of the tail portion NSTL may be spaced apart from the sidewall 120SW in the first direction X. Since a portion of the plurality of semiconductor patterns NS includes the tail portion NSTL, a portion of the plurality of semiconductor patterns NS may have an inverted trapezoidal shape. The tail portion NSTL may be disposed inward relative to the outer sidewall of the spacer structure 130 (e.g., a sidewall of the spacer structure 130 opposite to another sidewall of the spacer structure 130 that contacts the main gate portion 120M) and may be spaced apart from the outer sidewall of the spacer structure 130 in the first direction X.

[0045] The bottom portion of the main gate portion 120M may have a third width W21 in the first direction X, and the middle portion of the main gate portion 120M may have a fourth width W22 in the first direction that is greater than the third width W21. The first spacer 132 may fill the space defined by the inclined sidewall 120SI of the bottom portion of the main gate portion 120M and the upper surface of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3). For example, the first spacer 132 may include a protrusion 132P at its bottom portion, and the protrusion 132P may fill the space defined by the inclined sidewall 120SI of the bottom portion of the main gate portion 120M and the upper surface of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3). The gate insulating layer 128 may be disposed between the inclined sidewall 120SI of the main gate portion 120M and the protrusion 132P of the first spacer 132. The inclined sidewall 120SI of the main gate portion 120M may overlap perpendicularly with a portion of the spacer structure 130 (e.g., the protrusion 132P of the first spacer 132).

[0046] As described above, the uppermost semiconductor pattern NS (e.g., the third semiconductor pattern NS3) can have an inverted trapezoidal shape. The first width W11 of the top portion of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3) can be greater than the third width W21 of the bottom portion of the main gate portion 120M. Since the protrusion 132P of the first spacer 132 is disposed between the bottom portion of the main gate portion 120M and the source / drain region 140, the spacing between the source / drain region 140 and the main gate portion 120M can be relatively increased compared to a structure in which the main gate portion 120M has a vertical sidewall at its bottom portion. Therefore, leakage current between the source / drain region 140 and the main gate portion 120M can be prevented or reduced. Furthermore, in the process of forming the source / drain region 140 or removing the dummy gate structure (see...), Figure 19B In the process of forming the gate electrode 120 (DG), process defects such as undesirable connections between the dummy gate structure DG and the source / drain region 140 or between the gate electrode 120 and the source / drain region 140 can be prevented.

[0047] Gate insulating pad 152 and inter-gate insulating layer 154 may be sequentially disposed on the sidewall of spacer structure 130, source / drain region 140, and device isolation layer 114. Upper insulating layer 162 may be disposed on gate electrode 120 and inter-gate insulating layer 154. Contact plug 166 may be disposed in contact hole 166H that passes through upper insulating layer 162 and exposes the upper surface of source / drain region 140. Metal silicide layer 168 may be disposed between contact plug 166 and source / drain region 140. For example, metal silicide layer 168 may include titanium silicide or cobalt silicide, but is not limited thereto.

[0048] Although not shown in the accompanying drawings, vias and interconnect layers may be provided on the upper insulating layer 162 to connect the contact plug 166 and the gate electrode 120.

[0049] Generally, dummy gate structures can be formed on multiple semiconductor patterns NS (see Figure 19A The recessed region RS1 can be formed by removing portions of the semiconductor pattern NS on each side opposite to the dummy gate structure DG, and the source / drain region 140 can be formed in the recessed region RS1. However, since the spacing between the recessed region RS1 and the dummy gate structure DG is relatively small at the edge portions of the semiconductor pattern NS, process defects may occur, such as undesirable connections between the dummy gate structure DG and the source / drain region 140 or between the gate electrode 120 and the source / drain region 140. Therefore, leakage current will occur between the gate electrode 120 and the source / drain region 140.

[0050] According to an exemplary embodiment of the present invention, a portion of a plurality of semiconductor patterns NS may have an inverted trapezoidal shape, and the uppermost semiconductor pattern NS may have a tail portion NSTL at each of its opposite edges. Therefore, a relatively large spacing distance can be obtained between the source / drain region 140 and the dummy gate structure DG, or between the source / drain region 140 and the gate electrode 120, thereby preventing process defects such as undesired connections between the dummy gate structure DG and the source / drain region 140, or between the gate electrode 120 and the source / drain region 140. Therefore, leakage current between the source / drain region 140 and the main gate portion 120M can be prevented or reduced.

[0051] Figure 18 This is a cross-sectional view illustrating an example embodiment of an integrated circuit according to a concept proposed in this invention. Figure 19A In this context, the same labels are used to indicate... Figure 19B The same elements shown.

[0052] Reference Figure 19A In an example embodiment of the integrated circuit 100A according to the present invention, the spacer structure 130A may include a first spacer 132A and a second spacer 134A sequentially disposed on the sidewall of the main gate portion 120M. The bottom portions of the first spacer 132A and the second spacer 134A may extend horizontally along the upper surface of a plurality of semiconductor patterns NS. The second spacer 134A may include a lateral extension 134W extending outward from the sidewall of the first spacer 132A. The bottom portion of the first spacer 132A may be disposed between the lateral extension 134W and the uppermost semiconductor pattern NS (third semiconductor pattern NS3). The lateral extension 134W may perpendicularly overlap with the tail portion NSTL of the uppermost semiconductor pattern NS (or the third semiconductor pattern NS3).

[0053] Since the lateral extension 134W is disposed above the upper surface of the uppermost semiconductor pattern NS, the upper surface of the uppermost semiconductor pattern NS can be covered by the spacer structure 130A during the process of etching the semiconductor pattern NS to form the recessed region RS1A. Therefore, the uppermost semiconductor pattern NS can have inclined sidewalls NSSW with a relatively large angle. The spacing between the source / drain region 140A and the main gate portion 120M can be relatively large.

[0054] The first width W11A of the top portion of the uppermost semiconductor pattern NS in the first direction X can be greater than the second width W12A of the bottom portion of the uppermost semiconductor pattern NS in the first direction X. For example, the first width W11A of the top portion of the uppermost semiconductor pattern NS in the first direction X can be greater than a reference.Figure 15A to Figure 17B The first width W11 of the top portion of the uppermost semiconductor pattern NS is described, but the inventive concept is not limited thereto.

[0055] In the manufacturing process of an exemplary embodiment of the invention, the first spacer layer (see...) Figure 20 132L), second spacer layer (see ...). Figure 21 134L) and covering spacer layer (see ... Figure 16A The 136LA can be formed in a dummy gate structure (see...). Figure 16B On the DG), an anisotropic etching process can be performed on the first spacer layer 132L, the second spacer layer 134L, and the cover spacer layer 136LA to form the spacer structure 130A. When the cover spacer layer 136LA has a relatively large thickness, the second spacer layer 134L extends horizontally from the dummy gate structure (see DG) on multiple semiconductor patterns NS. Figure 20 The portion of the DG extension can be etched relatively less in the anisotropic etching process due to the covering spacer layer 136LA, thereby preserving the lateral extension 134W.

[0056] According to integrated circuit 100A, since the spacing between the source / drain region 140A and the main gate portion 120M is relatively large, leakage current between the source / drain region 140A and the main gate portion 120M can be prevented or reduced. Process defects, such as undesirable connections between the dummy gate structure DG and the source / drain region 140A or between the gate electrode 120 and the source / drain region 140A, can be prevented.

[0057] Figure 21 This is a cross-sectional view illustrating an example embodiment of an integrated circuit according to a concept proposed in this invention. Figure 6 In this context, the same labels are used to indicate... Figure 22 The same elements shown.

[0058] Reference Figure 23 In the integrated circuit 100B of an exemplary embodiment of the present invention, the bottom portion of the main gate portion 120MB may have a third width W21B, and the middle portion of the main gate portion 120MB may have a fourth width W22B smaller than the third width W21B. The bottom portion of the main gate portion 120MB may have a sloped sidewall 120SIB. The sloped sidewall 120SIB may have a positive slope (or may extend downward and outward). The portion of the main gate portion 120MB adjacent to the sloped sidewall 120SIB of the main gate portion 120MB may represent a protrusion 120MP. The protrusion 120MP of the main gate portion 120MB may protrude outward toward the spacer structure 130B at the bottom portion of the main gate portion 120MB.

[0059] The spacer structure 130B may include a first spacer 132B and a second spacer 134B. The portion of the first spacer 132B adjacent to the protrusion 120MP of the main gate portion 120MB may have a relatively thin thickness.

[0060] In the manufacturing process of an exemplary embodiment of the present invention, the dummy gate structure (see Figure 24 The dummy gate insulating layer below the DG (see DG) Figure 22 The sidewalls of the DGI (see DGI) Figure 23 The DGI_OS performs an etching process to create a dummy gate insulating layer (see DGI_OS). Figure 24 The DGI is formed to have recessed sidewalls (see Figure 15A to Figure 17B (DGI_IS). Afterwards, a dummy gate structure can be configured (see...). ​ Spacer structures are formed on the DG (see ​ (130). Furthermore, a recessed region RS1 can be formed on each side of the dummy gate structure DG, and a source / drain region 140B can be formed in the recessed region RS1. After performing the process of removing the dummy gate structure DG, a portion of the bottom portion of the first spacer 132B on the upper surface of the exposed semiconductor pattern NS can be removed. In this case, since the spacing between the dummy gate structure DG and the source / drain region 140 is relatively large, the source / drain region 140 can be prevented from being exposed to the etching environment during the removal process of the dummy gate structure DG.

[0061] The source / drain region 140B may include a first semiconductor layer 142B, a second semiconductor layer 144B, a third semiconductor layer 146B, and a fourth semiconductor layer 148B sequentially disposed in the recessed region RS1. The first semiconductor layer 142B may have a relatively large thickness. The upper surface of the first semiconductor layer 142B may contact the bottom surface of the spacer structure 130B.

[0062] In some embodiments, all of the first semiconductor layer 142B, the second semiconductor layer 144B, the third semiconductor layer 146B, and the fourth semiconductor layer 148B may comprise Si layers, and the impurity concentrations of the first to fourth semiconductor layers 142B, 144B, 146B, and 148B may differ from one another. In some embodiments, all of the first to fourth semiconductor layers 142B, 144B, 146B, and 148B may comprise SiGe layers, and the Ge content of the first to fourth semiconductor layers 142B, 144B, 146B, and 148B may differ from one another. For example, the first semiconductor layer 142B may have a relatively low impurity concentration or a relatively low Ge content, while the third semiconductor layer 146B and the fourth semiconductor layer 148B may have a relatively high impurity concentration or a relatively high Ge content. In this case, the spacing between the third semiconductor layer 146B and the main gate portion 120MB or the spacing between the fourth semiconductor layer 148B and the main gate portion 120MB can be relatively large, and leakage current between the source / drain region 140B (e.g., the third semiconductor layer 146B and the fourth semiconductor layer 148B of the source / drain region 140B) and the main gate portion 120MB can be prevented or reduced.

[0063] ​ This is a cross-sectional view illustrating an example embodiment of an integrated circuit according to a concept proposed in this invention. ​ In this context, the same labels are used to indicate... ​ The same elements shown.

[0064] Reference ​ In an exemplary embodiment of the integrated circuit 100C according to the present invention, an internal spacer 172 may be disposed between the source / drain region 140 and the gate electrode 120. The internal spacer 172 may be disposed between each of the plurality of sub-gate portions 120S and the source / drain region 140, and a gate insulating layer 128 may be disposed between each of the plurality of sub-gate portions 120S and the internal spacer 172. For example, the internal spacer 172 may comprise silicon nitride or silicon oxynitride.

[0065] In the integrated circuit 100C of the exemplary embodiment of the present invention, since the spacing between the source / drain region 140 and the main gate portion 120M is relatively large, leakage current between the source / drain region 140 and the main gate portion 120M can be prevented or reduced.

[0066] ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​, ​ , ​ , ​ , ​ , ​ , ​ , ​ and ​ This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ and ​ It is along ​ The cross-sectional view taken by line A1-A1'. ​ , ​ , ​ , ​ It is along ​ The cross-sectional view taken from line B1-B1'. ​ and ​ They are in ​ and ​ A horizontal cross-sectional view at the first vertical height LV1.

[0067] Reference ​ The sacrificial layer 210 and the channel semiconductor layer PNS can be repeatedly and alternately formed on the upper surface 110M of the substrate 110 to form a sacrificial stack 210S. The sacrificial layer 210 and the channel semiconductor layer PNS can be formed by epitaxial processes.

[0068] In some embodiments, the sacrificial layer 210 and the channel semiconductor layer PNS can be formed of materials with different etch selectivity. For example, the sacrificial layer 210 and the channel semiconductor layer PNS can be formed of a group IV semiconductor single crystal layer, a group IV-IV compound semiconductor single crystal layer, or a group III-V compound semiconductor single crystal layer. For example, the sacrificial layer 210 can be formed of a different material than the channel semiconductor layer PNS. In some embodiments, the sacrificial layer 210 can be formed of silicon germanium (SiGe), and the channel semiconductor layer PNS can be formed of crystalline silicon.

[0069] In some embodiments, the epitaxial process may include chemical vapor deposition (CVD) processes (such as vapor phase epitaxy (VPE) or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or combinations thereof. In the above epitaxial processes, liquid or vapor precursors may be used to form the sacrificial layer 210 and the channel semiconductor layer PNS.

[0070] Reference ​ and​ After forming a hard mask pattern extending along the first direction X to a predetermined length on the uppermost channel semiconductor layer PNS, the hard mask pattern can be used as an etching mask to etch the sacrificial layer 210, the channel semiconductor layer PNS and the substrate 110 to form the sacrificial pattern 210P and the device isolation trench 114T.

[0071] After filling the device isolation trench 114T with insulating material, the insulating material can be planarized to form a device isolation layer 114 that fills the device isolation trench 114T. The finned active region FA can be defined in the substrate 110 through the device isolation layer 114.

[0072] The hard mask pattern retained on the sacrificial pattern 210P can be removed, and then the device isolation layer 114 can be removed to a predetermined thickness using a recess process. In some embodiments, the recess process can be performed until the upper surface of the device isolation layer 114 is at the same height as the upper surface 110M of the substrate 110. In some embodiments, the recess process can be performed until the upper surface of the device isolation layer 114 is at a lower height than the upper surface 110M of the substrate 110, such that a portion of the sidewalls of the finned active region FA can be exposed.

[0073] Reference ​ and ​ A dummy gate structure DG can be formed on the sacrificial pattern 210P and the device isolation layer 114. The dummy gate structure DG may include a dummy gate insulating layer DGI, a dummy gate line DGL, and a dummy gate capping layer DGC.

[0074] For example, the dummy gate line DGL can be formed of polysilicon. The dummy gate capping layer DGC can be formed of silicon nitride. The dummy gate insulating layer DGI can be formed of a material with etch selectivity relative to the dummy gate line DGL, and can be formed of, for example, thermal oxide, silicon oxide, and silicon nitride.

[0075] The dummy gate insulating layer (DGI) can have a sidewall DGI_OS that protrudes outward from the sidewall of the dummy gate structure (DG). For example, when the height of the dummy gate structure (DG) is relatively high, a portion of the dummy gate insulating layer (DGI) can be retained without being removed in an etching environment, allowing the sidewall DGI_OS of the dummy gate insulating layer (DGI) to protrude outward from the sidewall of the dummy gate line (DGL).

[0076] Reference ​ An additional etching process can be performed to remove a portion of the sidewall DGI_OS of the dummy gate insulating layer DGI, allowing the dummy gate insulating layer DGI to have a recessed sidewall DGI_IS. The recessed sidewall DGI_IS of the dummy gate insulating layer DGI can be a portion recessed inward from the sidewall of the dummy gate line DGL.

[0077] Reference ​ A first spacer layer 132L, a second spacer layer 134L, and a cover spacer layer 136L can be sequentially formed on the dummy gate structure DG. For example, the first spacer layer 132L and the second spacer layer 134L can be formed of silicon nitride or silicon oxynitride, and the cover spacer layer 136L can be formed of silicon oxide. However, the inventive concept is not limited thereto.

[0078] A first spacer layer 132L can be conformally formed on the recessed sidewall DGI_OS of the dummy gate insulating layer DGI. Therefore, the portion of the first spacer layer 132L that contacts the recessed sidewall DGI_OS of the dummy gate insulating layer DGI can correspond to... ​ The protrusion 132P of the first spacer layer 132 shown.

[0079] Reference ​ An anisotropic etching process can be performed on the first spacer layer 132L, the second spacer layer 134L, and the cover spacer layer 136L to form a spacer structure 130 on each sidewall of the opposite sidewall of the dummy gate structure DG.

[0080] In the anisotropic etching process, the covering spacer layer 136L on the upper surface of the dummy gate structure DG and the upper surface of the sacrificial pattern 210P can also be removed. The spacer structure 130 may include a first spacer 132 and a second spacer 134 sequentially disposed on each sidewall of the dummy gate structure DG. The bottom surface of the second spacer 134 may be covered by the first spacer 132. ​ As shown, the spacer layer 136L can be completely removed, so the sidewalls of the second spacer 134 may not be covered by the spacer layer 136L. However, in some embodiments, a portion of the spacer layer 136L may remain on a portion of the sidewalls of the second spacer 134. In this case, an additional etching process may be performed to remove the spacer layer 136L. In some embodiments, the additional etching process for removing the spacer layer 136L may not be performed, and the remaining portion of the spacer layer 136L may be removed in a subsequent process for forming the recessed region RS1.

[0081] Reference ​ and ​The portions of the sacrificial pattern 210P and the substrate 110 on opposite sides of the dummy gate structure DG and the spacer structure 130 can be etched to form a recessed region RS1 on each side of the opposite side of the dummy gate structure DG. Because the recessed region RS1 is formed, the sacrificial pattern 210P can be divided into a plurality of semiconductor patterns NS. For example, the plurality of semiconductor patterns NS may include a first semiconductor pattern NS1, a second semiconductor pattern NS2, and a third semiconductor pattern NS3 spaced apart from each other by the sacrificial layer 210.

[0082] In some embodiments, during the process of forming the recessed region RS1, the uppermost semiconductor pattern NS overlapping the spacer structure 130 may not be removed (or a portion of the third semiconductor pattern NS3 may not be removed, but other semiconductor patterns NS overlapping the spacer structure 130 (e.g., the second semiconductor pattern NS2 or the first semiconductor pattern NS1) may be removed). The width of the middle portion of the recessed region RS1 may be greater than the width of the upper portion of the recessed region RS1. Multiple sacrificial layers 210 may include tail portions 210TL overlapping the spacer structure 130. Multiple semiconductor patterns NS may include tail portions overlapping the spacer structure 130 (see, for example...). ​ The NSTL is similar to the tail portion 210TL of multiple sacrificial layers 210.

[0083] As described above, since the surface of the second spacer layer 134L is covered by the spacer layer 136L during the formation process of the spacer structure 130, the spacer structure 130 retained after the anisotropic etching process can have a relatively large width d11 in the first direction X. For example, when the width d11 of the spacer structure 130 in the first direction X is relatively large, the portion of the sacrificial layer 210 adjacent to the spacer structure 130 can be less exposed to the etching environment during the formation process of the recessed region RS1, thus allowing the tail portion 210TL of each sacrificial layer 210 to be formed. Furthermore, since the first spacer 132 includes a protrusion 132P, the spacing distance between the recessed region RS1 and the dummy gate structure DG can be relatively increased.

[0084] Reference ​ and ​A first semiconductor layer 142, a second semiconductor layer 144, a third semiconductor layer 146, and a fourth semiconductor layer 148 can be sequentially formed to form a source / drain region 140. For example, the first to fourth semiconductor layers 142, 144, 146, and 148 can be formed by epitaxially growing semiconductor material from multiple semiconductor patterns NS, a sacrificial layer 210, and a substrate 110 exposed on the inner surface of the recessed region RS1. The first to fourth semiconductor layers 142, 144, 146, and 148 may include at least one of epitaxially grown Si layers, SiC layers, SiGe layers, and SiP layers.

[0085] Subsequently, a gate insulating pad 152 and an inter-gate insulating layer 154 can be sequentially formed on the sidewalls of the spacer structure 130, the source / drain region 140, and the device isolation layer 114. The upper portion of the dummy gate structure DG, the gate insulating pad 152, and the inter-gate insulating layer 154 can be planarized to remove the dummy gate capping layer DGC of the dummy gate structure DG, thereby exposing the upper surface of the dummy gate line DGL.

[0086] Reference ​ and ​ The dummy gate line DGL and dummy gate insulating layer DGI exposed through the inter-gate insulating layer 154 can be removed to form the gate space GS.

[0087] Subsequently, the multiple sacrificial layers 210 retained on the finned active region FA can be removed via the gate space GS to expose a portion of the upper surface of the multiple semiconductor patterns NS and the finned active region FA. Therefore, a sub-gate space GSS can be formed between the multiple semiconductor patterns NS and between the lowermost semiconductor pattern in the multiple semiconductor patterns NS and the finned active region FA. The removal process of the multiple sacrificial layers 210 can be performed using a wet etching process that utilizes the difference in etch selectivity between the multiple sacrificial layers 210 and the multiple semiconductor patterns NS.

[0088] As described above, because the width d11 of the spacer structure 130 in the first direction X is relatively large, and the first spacer 132 includes a protrusion 132P, the upper surface of the source / drain region 140 will not be exposed during the removal process of the dummy gate line DGL. For example, when the spacing between the source / drain region 140 and the dummy gate line DGL is relatively small, the edge portion of the source / drain region 140 may also be exposed to the etching environment during the removal process of the dummy gate line DGL. Therefore, process failures may occur, such as the source / drain region 140 being etched or the gate electrode material filling the removed area of ​​the source / drain region 140. However, because the width d11 of the spacer structure 130 in the first direction X is relatively large, and the first spacer 132 includes a protrusion 132P, no process defects will occur during the removal process of the dummy gate line DGL.

[0089] Reference ​ and ​ A gate insulating layer 128 can be formed on the inner surface of the gate space GS and the inner surface of the sub-gate space GSS. A gate electrode 120 can be formed on the gate insulating layer 128 to fill the gate space GS and the sub-gate space GSS. For example, after conformally forming a work function conductive layer on the inner surface of the gate space GS and the inner surface of the sub-gate space GSS, a buried conductive layer can be formed on the work function conductive layer to fill the gate space GS and the sub-gate space GSS. Thereafter, the upper portion of the buried conductive layer can be planarized until the upper surface of the inter-gate insulating layer 154 is exposed, thereby forming the gate electrode 120. In some embodiments, the work function conductive layer can be formed of Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof. The buried conductive layer can be formed from Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, TaSiN, or combinations thereof.

[0090] Refer again ​ After forming the upper insulating layer 162 and then forming the contact hole 166H that penetrates the upper insulating layer 162, the contact hole 166H can be filled with a conductive material to form a contact plug 166.

[0091] According to the above-described method for manufacturing the integrated circuit 100, since the second spacer layer 134L is covered by the cover spacer layer 136L during the formation process of the spacer structure 130, the width d11 of the spacer structure 130 in the first direction X can be relatively large. Furthermore, because an etching process for forming the recessed sidewall DGI_IS of the dummy gate insulating layer DGI is performed, the first spacer 132 can include a protrusion 132P. Therefore, since the spacing distance between the source / drain region 140 and the dummy gate structure DG is relatively increased, the upper surface of the source / drain region 140 is not exposed by the gate space GS. During the above-described removal process of the dummy gate line DGL, the exposure and removal of the source / drain region 140 do not occur.

[0092] ​ , ​ and ​ This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention. ​ and ​ It is along ​ The cross-sectional view taken from line A1-A1'. ​ Is ​ A horizontal cross-sectional view at the first vertical height LV1.

[0093] Reference ​ A first spacer layer 132L, a second spacer layer 134L, and a cover spacer layer 136LA can be sequentially formed on the upper surface and sidewalls of the dummy gate structure DG. The cover spacer layer 136LA can have a relatively large thickness.

[0094] Reference ​ and ​ An anisotropic etching process can be performed on the first spacer layer 132L, the second spacer layer 134L, and the covering spacer layer 136LA to form the spacer structure 130A. In the anisotropic etching process, the second spacer 134A can be formed to include a lateral extension 134W extending in the horizontal direction.

[0095] like ​ As shown, the cover spacer layer 136LA can be completely removed, leaving the sidewalls of the second spacer 134A uncovered. However, in some embodiments, a portion of the cover spacer layer 136LA may remain on at least a portion of the sidewalls of the second spacer 134A. In this case, an additional etching process may be performed to remove the cover spacer layer 136LA. In some embodiments, the additional etching process for removing the cover spacer layer 136LA may not be performed, and the remaining portion of the cover spacer layer 136LA may also be removed in a subsequent process for forming the recessed region RS1A.

[0096] Subsequently, portions of the sacrificial pattern 210P and the substrate 110 on opposite sides of the dummy gate structure DG and the isolation structure 130A can be etched to form a recessed region RS1A on each side of the opposite side of the dummy gate structure DG.

[0097] As described above, in the formation process of the spacer structure 130A, since the second spacer layer 134L is covered by a relatively thick covering spacer layer 136LA, the spacer structure 130A retained in the anisotropic etching process can have a relatively large width d12 in the first direction X. For example, when the width d12 of the spacer structure 130A in the first direction X is relatively large, in the formation process of the recessed region RS1A, the portion of the sacrificial layer 210 adjacent to the spacer structure 130A can be less exposed to the etching environment. Therefore, a tail portion 210TL of each sacrificial layer 210 can be formed.

[0098] After that, the reference can be executed. ​ The process described is used to form integrated circuit 100A.

[0099] ​ and ​ This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention.

[0100] First, you can execute the reference. ​ and ​ The described process involves removing the dummy gate line DGL and dummy gate insulating layer DGI exposed by the inter-gate insulating layer 154 to form a gate space GS, and removing the sacrificial layer 210 exposed through the gate space GS to form a sub-gate space GSS between multiple semiconductor patterns NS and between the bottommost semiconductor pattern NS and the finned active region FA. In this case, the first spacer 132 may include a protrusion 132P at its bottom portion, thus ensuring a relatively large spacing distance between the source / drain region 140 and the gate space GS during the removal process of the dummy gate line DGL.

[0101] Reference ​ A portion of the bottom portion of the first spacer 132B exposed in the gate space GS can be removed. Therefore, the width of the bottom portion of the gate space GS can be greater than the width of the middle portion of the gate space GS.

[0102] Reference ​ A gate insulating layer 128 and a gate electrode 120 can be formed on the inner surface of the gate space GS and the inner surface of the sub-gate space GSS. The main gate portion 120M can be formed as a protrusion including an edge that fills the bottom portion of the gate space GS (see [reference]). ​ (120MP).

[0103] According to the above method, in the removal process of the dummy gate structure DG, since a relatively large spacing distance is obtained between the dummy gate structure DG and the source / drain region 140, the source / drain region 140 will not be exposed to the etching environment in the removal process of the dummy gate structure DG.

[0104] ​ , ​ and ​ This is a cross-sectional view illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present invention.

[0105] Reference ​ In a structure with a recessed region RS1, the portion of the sacrificial layer 210 exposed in the recessed region RS1 can be removed by an isotropic etching process to form a recessed region RSE between multiple semiconductor patterns NS. In some embodiments, a wet etching process utilizing the difference in etch selectivity between the multiple sacrificial layers 210 and the multiple semiconductor patterns NS can be performed to form the recessed region RSE. For example, in a wet etching process, the sacrificial layer 210 including SiGe can be etched faster than multiple semiconductor patterns NS including Si to form the recessed region RSE.

[0106] Reference ​ An internal spacer layer 172L can be conformally formed on the upper surface of the dummy gate structure DG, the sidewall of the spacer structure 130, the inner surface of the recessed region RS1, and the inner surface of the recessed region RSE. The internal spacer layer 172L can be formed to a sufficient thickness to fill the recessed region RSE.

[0107] Reference ​ An anisotropic etching process can be performed on the internal spacer layer 172L so that the internal spacer 172 can be retained in the recessed region RSE. In the anisotropic etching process, the internal spacer layer 172L on the sidewalls of the dummy gate structure DG and the spacer structure 130, as well as in the recessed region RS1, can be removed.

[0108] After that, the reference can be executed. ​ The process described is used to form integrated circuit 100C.

[0109] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the exemplary embodiments without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. An integrated circuit, the integrated circuit comprising: Substrate; A fin-type active region, the fin-type active region protruding from the substrate and extending in a first direction; Multiple semiconductor patterns are disposed on the upper surface of the fin-type active region; A gate electrode, the gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, the gate electrode including a main gate portion and a plurality of sub-gate portions, the main gate portion being disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns, and the plurality of sub-gate portions being disposed respectively between the fin active region and the lowermost semiconductor pattern among the plurality of semiconductor patterns and between the plurality of semiconductor patterns; A spacer structure is disposed on the sidewall of the main gate portion; as well as Source / drain regions are disposed on the side of the gate electrode and connected to the plurality of semiconductor patterns, and the source / drain regions contact the bottom surface of the spacer structure. Wherein, the entire top surface of the uppermost semiconductor pattern has a first width in the first direction, and the entire bottom surface of the uppermost semiconductor pattern has a second width in the first direction that is smaller than the first width, such that the uppermost semiconductor pattern has an inverted trapezoidal cross-section, and The main gate portion includes a bottom portion with inclined sidewalls.

2. The integrated circuit according to claim 1, wherein, The bottom surface of the bottom portion of the main gate portion has a third width in the first direction. The middle portion of the main gate portion has a fourth width in the first direction that is different from the third width.

3. The integrated circuit according to claim 2, wherein, The third width is smaller than the first width.

4. The integrated circuit according to claim 1, wherein, The source / drain regions contact the bottom surface of the spacer structure, and The inclined sidewall of the main gate portion overlaps perpendicularly with at least a portion of the spacer structure, such that at least a portion of the bottom surface of the spacer structure is below the inclined sidewall of the main gate portion.

5. The integrated circuit according to claim 1, wherein, The spacer structure includes a first spacer and a second spacer sequentially disposed on the sidewall of the main gate portion. At least a portion of the first spacer has a triangular cross-section, and the at least a portion of the first spacer fills the space defined by the inclined sidewall of the main gate portion and the upper surface of the uppermost semiconductor pattern.

6. The integrated circuit according to claim 1, wherein, The uppermost semiconductor pattern has a pair of sloping sidewalls, and the source / drain region contacts at least one of the pair of sloping sidewalls. The uppermost semiconductor pattern includes a tail portion located below the spacer structure.

7. The integrated circuit according to claim 1, wherein, The source / drain region includes a first semiconductor layer, a second semiconductor layer disposed on a first portion of the first semiconductor layer, and a third semiconductor layer disposed on a second portion of the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the third semiconductor layer are in contact with the bottom surface of the spacer structure.

8. The integrated circuit according to claim 1, wherein, The bottom surface of the bottom portion of the main gate portion is above the top surface of the uppermost semiconductor pattern.

9. The integrated circuit according to claim 2, wherein, The fourth width in the first direction is smaller than the third width.

10. The integrated circuit according to claim 1, wherein, The spacer structure includes a first spacer and a second spacer sequentially disposed on the sidewall of the main gate portion. The second spacer includes a lateral extension extending outward from the sidewall of the first spacer.

11. The integrated circuit according to claim 10, wherein, The uppermost semiconductor pattern includes a tail portion that overlaps perpendicularly with the lateral extension.

12. The integrated circuit according to claim 1, further comprising: An internal spacer located between each of the plurality of sub-gate portions and the source / drain region.

13. An integrated circuit, the integrated circuit comprising: Substrate; A fin-type active region, the fin-type active region protruding from the substrate and extending in a first direction; Multiple semiconductor patterns are disposed on the upper surface of the fin-type active region; A gate electrode, the gate electrode surrounding the plurality of semiconductor patterns and extending in a second direction perpendicular to the first direction, the gate electrode including a main gate portion and a plurality of sub-gate portions, the main gate portion being disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns, and the plurality of sub-gate portions being disposed respectively between the fin active region and the lowermost semiconductor pattern among the plurality of semiconductor patterns and between the plurality of semiconductor patterns; A spacer structure is disposed on the sidewall of the main gate portion; as well as Source / drain regions are disposed on the side of the gate electrode and connected to the plurality of semiconductor patterns, and the source / drain regions contact the bottom surface of the spacer structure. Wherein, the entire top surface of the uppermost semiconductor pattern has a first width in the first direction, and the entire bottom surface of the uppermost semiconductor pattern has a second width in the first direction that is smaller than the first width, such that the uppermost semiconductor pattern has an inverted trapezoidal cross-section, and The bottom portion of the main gate portion has a third width in the first direction. The middle portion of the main gate portion has a fourth width in the first direction that is different from the third width.

14. The integrated circuit according to claim 13, wherein, The bottom portion of the main gate portion has sloping sidewalls. The uppermost semiconductor pattern has a pair of sloping sidewalls. The pair of inclined sidewalls of the uppermost semiconductor pattern both protrude outward relative to the inclined sidewall of the bottom portion of the main gate portion.

15. The integrated circuit according to claim 14, wherein, The uppermost semiconductor pattern includes a tail portion adjacent to the source / drain region at each of the opposite edge portions of the uppermost semiconductor pattern. The edge of the tail portion is spaced apart from the inclined sidewall of the main gate portion in the first direction.

16. An integrated circuit, the integrated circuit comprising: Substrate; A fin-type active region, the fin-type active region protruding from the substrate; Multiple semiconductor patterns are disposed on the upper surface of the fin-type active region, and each of the multiple semiconductor patterns includes a channel region. A gate electrode surrounds the plurality of semiconductor patterns and includes a main gate portion and a plurality of sub-gate portions. The main gate portion is disposed on the uppermost semiconductor pattern among the plurality of semiconductor patterns, and the plurality of sub-gate portions are respectively disposed between the fin active region and the lowermost semiconductor pattern among the plurality of semiconductor patterns, and between the plurality of semiconductor patterns. A gate insulating layer surrounding the main gate portion and each of the plurality of sub-gate portions; A spacer structure is disposed on the sidewall of the main gate portion, and the gate insulating layer is located between the sidewall of the main gate portion and the spacer structure; as well as Source / drain regions are disposed on the side of the gate electrode and connected to the plurality of semiconductor patterns, and the source / drain regions contact the bottom surface of the spacer structure. Wherein, the bottom portion of the uppermost semiconductor pattern is narrower than the top portion of the uppermost semiconductor pattern, and At least a portion of the sidewall of the main gate portion is inclined and overlaps perpendicularly with a portion of the spacer structure.

17. The integrated circuit according to claim 16, wherein, The spacer structure includes a first spacer and a second spacer sequentially disposed on the sidewall of the main gate portion. The bottom portion of the first spacer is disposed on the upper surface of the uppermost semiconductor pattern.

18. The integrated circuit according to claim 17, wherein, The middle portion of the main gate portion is wider than the bottom portion of the main gate portion. The first spacer includes a protrusion that fills the space defined by the sidewall of the main gate portion and the upper surface of the uppermost semiconductor pattern.

19. The integrated circuit according to claim 17, wherein, The second spacer includes a lateral extension that extends laterally from the sidewall of the first spacer. The uppermost semiconductor pattern includes a tail portion at each of the opposite edge portions of the uppermost semiconductor pattern. The lateral extension and the tail portion overlap at least partially perpendicularly.

20. The integrated circuit according to claim 17, wherein, The source / drain region includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and a third semiconductor layer disposed on the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the third semiconductor layer are in contact with the bottom surface of the spacer structure.

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