Charging control circuit and charging control method

Abstract

The present application provides a charging control circuit and a charging control method. The circuit includes: a power adapter; a chip for connecting the power adapter and a charging load; the chip includes a first timing circuit for connecting the power adapter and the charging load; when the charging load is disconnected from the first timing circuit, the first timing circuit starts its timing function and, when a first preset time is reached, transmits a first timing signal to the power adapter; the power adapter is used to receive the first timing signal and stop outputting an electrical signal to the charging load. The technical solution provided in the above embodiments of the present application can stop power supply when the charging load is unplugged, thereby avoiding electric leakage and improving safety.

Description

Technical Field

[0001] This application relates to the technical field of chargers, and particularly to a charging control circuit and a charging control method. Background Art

[0002] During the use of electronic devices such as mobile phones by users, in order to facilitate charging when needed, the user can directly insert the charging cable interface into the mobile phone to start charging. There is often a situation where the plug of the power adapter is plugged into the power supply for a long time. When a fast charging device (charger and charging cable) fast charges a mobile phone, the voltage and current provided to the mobile phone are relatively high. If the mobile phone is unplugged for a long time while the charger still outputs high voltage and high current, there will be a potential safety hazard of electric leakage and it will also damage the fast charging device. Summary of the Invention

[0003] An embodiment of this application provides a charging control circuit to improve the safety of the charger.

[0004] An embodiment of this application provides a charging control circuit, including:

[0005] A power adapter;

[0006] A chip for connecting the power adapter and a charging load;

[0007] The chip includes a first timing circuit for connecting the power adapter and the charging load;

[0008] When the charging load is disconnected from the first timing circuit, the first timing circuit starts its timing function and, when reaching a first preset time, transmits a first timing signal to the power adapter;

[0009] The power adapter is used to receive the first timing signal and stop outputting an electrical signal to the charging load.

[0010] In one embodiment, the chip further includes:

[0011] A second timing circuit connecting the first timing circuit and the power adapter;

[0012] The first timing circuit is further used to transmit the first timing signal to the second timing circuit;

[0013] The second timing circuit is used to start its timing function when receiving the first timing signal and, when reaching a second preset time, transmit a second timing signal to the power adapter;

[0014] The power adapter is further used to receive the second timing signal and enter a normal charging mode.

[0015] In one embodiment, the second timing circuit includes:

[0016] A capacitive power control module, connected to the power adapter, the first timing circuit, the second oscillator, and the second counter; the capacitive power control module is configured to receive a first timing signal, release a charging voltage, and provide an oscillation enable signal to the second oscillator.

[0017] A second oscillator, configured to receive the oscillation enable signal and generate a clock signal.

[0018] A second counter, connected to the first timing circuit, the second oscillator, the power adapter, and the capacitive power control module, configured to receive the first timing signal and the clock signal, start counting, and transmit a second timing signal to the power adapter when the count reaches a second preset value.

[0019] In one embodiment, the capacitive power control module includes:

[0020] An exclusive-NOR gate, the input terminals of the exclusive-NOR gate are connected to the first timing circuit and the second counter.

[0021] An N-type field effect transistor, connected to the output terminal of the exclusive-NOR gate, configured to control the charging and discharging of the capacitor.

[0022] A capacitor, connected to the power adapter and the N-type field effect transistor.

[0023] An enable signal generation circuit, connected to the power adapter, the capacitor, and the second oscillator, configured to output an oscillation enable signal to the second oscillator.

[0024] In one embodiment, the enable signal generation circuit includes:

[0025] A startup circuit, connected to the power adapter and the capacitor, configured to generate an enabling voltage.

[0026] A voltage conversion circuit, connected to the startup circuit and the power adapter, configured to convert the enabling voltage into a control signal.

[0027] A NOR gate, the input terminals of the NOR gate are connected to the output terminal of the voltage conversion circuit and the output terminal of the exclusive-NOR gate, and the output terminal of the NOR gate is connected to the second oscillator.

[0028] In one embodiment, the first timing circuit includes:

[0029] A first oscillator, configured to generate a clock signal.

[0030] A first counter, connected to the first oscillator, configured to receive the clock signal and perform counting, and transmit a first timing signal to the power adapter when the count reaches a first preset value.

[0031] The embodiments of the present application also provide a charging control method, including:

[0032] When the charging load is unplugged, trigger the first timing circuit to start the timing function;

[0033] When the first preset time is reached, the first timing circuit transmits a first timing signal to the power adapter;

[0034] The power adapter receives the first timing signal and stops outputting an electrical signal to the charging load.

[0035] In one embodiment, the above method further includes:

[0036] The first timing circuit transmits the first timing signal to the second timing circuit;

[0037] When the second timing circuit receives the first timing signal, it starts the timing function, and when the second preset time is reached, it transmits a second timing signal to the power adapter;

[0038] The power adapter receives the second timing signal and enters the normal charging mode.

[0039] In one embodiment, when the second timing circuit receives the first timing signal, starts the timing function, and when the second preset time is reached, transmits a second timing signal to the power adapter, it includes:

[0040] The capacitor power control module of the second timing circuit receives the first timing signal, releases the charging voltage, and provides an oscillation enable signal to the second oscillator of the second timing circuit;

[0041] The second oscillator receives the oscillation enable signal and generates a clock signal;

[0042] The second counter of the second timing circuit receives the first timing signal and the clock signal, starts counting, and transmits a second timing signal to the power adapter when the count reaches the second preset value.

[0043] In one embodiment, after the power adapter receives the second timing signal and enters the normal charging mode, the method further includes: the power adapter charges the capacitor power control module.

[0044] The technical solution provided by the above embodiments of the present application can stop power supply when the charging load is unplugged, thereby avoiding electric leakage and improving safety. Due to the possible situation of repeated plugging and unplugging, after the connection between the first timing circuit and the charging load is disconnected, the first timing circuit starts timing and only sends the first timing signal to the power adapter after the first preset time is reached, so that the power adapter stops power supply, thereby avoiding repeated power supply on and off caused by repeated plugging and unplugging and resulting in equipment failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below.

[0046] Figure 1 It is a schematic structural diagram of a charging control circuit provided by an embodiment of the present application;

[0047] Figure 2 It is a schematic structural diagram of a charging control circuit provided by another embodiment of the present application;

[0048] Figure 3 It is a schematic structural diagram of a charging control circuit provided by yet another embodiment of the present application;

[0049] Figure 4 It is a schematic structural diagram of a capacitor power control module provided by an embodiment of the present application;

[0050] Figure 5 It is a schematic flowchart of a charging control method provided by an embodiment of the present application;

[0051] Figure 6 is Figure 5 A schematic flowchart of a charging control method provided by another embodiment based on the corresponding embodiment;

[0052] Figure 7 is Figure 6 A detailed flowchart of step S620 in the corresponding embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0054] Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0055] Figure 1 It is a schematic structural diagram of a charging control circuit 1 provided by an embodiment of the present application. As Figure 1 shown, the charging control circuit 1 includes a power adapter 10 and a chip 20 including a first timing circuit 210. Among them, the power adapter 10 is connected to a charging load 2 through a data line. The chip 20 can be arranged inside the interface of the data line, in the middle of the data line, or inside the power adapter 10.

[0056] As Figure 1As shown, the chip 20 is respectively connected to the power adapter 10 and the charging load 2. The charging load 2 can be an electrical device such as a mobile phone, a tablet computer, a laptop computer, a smart bracelet, an electronic watch, etc.

[0057] The chip 20 includes a first timing circuit 210. The first timing circuit 210 is connected to the power adapter 10 and the charging load 2. When the charging load 2 is connected to the first timing circuit 210, the charging load 2 can continuously output a high level to the first timing circuit 210. Therefore, when the charging load 2 is unplugged, that is, when the charging load 2 is disconnected from the first timing circuit 210, the signal received by the first timing circuit 210 changes, triggering the first timing circuit 210 to start the timing function. When the first preset time is reached, the first timing circuit 210 transmits a first timing signal to the power adapter 10, for example, outputs a high level to the power adapter 10.

[0058] The power adapter 10 receives the first timing signal and stops outputting an electrical signal to the charging load 2. Thus, when the charging load 2 is unplugged, the power adapter 10 can stop outputting an electrical signal, improving safety. By timing through the first timing circuit 210 and transmitting the first timing signal to the power adapter 10 only when the first preset time is reached, it is possible to avoid repeatedly transmitting the first timing signal when the charging load 2 is repeatedly plugged and unplugged, causing a malfunction.

[0059] Figure 2 It is a schematic structural diagram of the charging control circuit 1 provided by another embodiment of the present application. As Figure 2 shown, the above chip 20 further includes a second timing circuit 220. The second timing circuit 220 is connected to the first timing circuit 210 and the power adapter 10. The first timing circuit 210 transmits the first timing signal to the power adapter 10 and can also transmit the first timing signal to the second timing circuit 220. For example, when the first timing circuit 210 times to the first preset time (such as 3 seconds), it can output a high level to the second timing circuit 220. When the second timing circuit 220 receives the first timing signal, it can start the timing function and transmit a second timing signal to the power adapter 10 when the timing reaches the second preset time. The second preset time and the first preset time can be equal, for example, both are 3 seconds, 5 seconds, etc., or they can be unequal, for example, the first preset time is 3 seconds and the second preset time is 5 seconds.

[0060] The power adapter 10 receives the second timing signal and can enter the normal charging mode. The normal charging mode is relative to the fast charging mode. The normal charging mode means outputting low voltage and low current, and the fast charging mode means outputting high voltage and high current. Normal charging and fast charging are relative, and the specific values of voltage or current are not limited. For example, when the second timing circuit 220 times to the second preset time, it can output a high level to the power adapter 10, so that the power adapter 10 outputs low voltage and low current and waits for the insertion of the charging load 2.

[0061] In the above embodiments, after the load is unplugged, the general charging mode can be switched. Compared with always being in the fast charging mode, the safety can be improved; compared with directly stopping power supply after the load is unplugged, charging can be resumed immediately after the charging load 2 is inserted, improving the charging efficiency.

[0062] Figure 3 The following is a schematic structural diagram of the charging control circuit 1 provided by another embodiment of the present application. As Figure 3 shown, the first timing circuit 210 includes a first oscillator 211 and a first counter 212 connected to the first oscillator 211. The first counter 212 is connected to the charging load 2. The first oscillator 211 is used to generate a clock signal and transmit it to the first counter 212. When the charging load 2 is unplugged, the connection end of the first counter 212 and the charging load 2 changes from high level to low level, triggering the first counter 212 to start timing. The first counter 212 can count the number of clock cycles of the clock signal. When the count reaches a first preset value, the first counter 212 transmits a first timing signal to the power adapter 10 (for example, outputs a high level to the power adapter 10).

[0063] As Figure 3 shown, the first timing circuit 210 may further include a resetter 213. The resetter 213 is connected to the first counter 212. The first counter 212 may also transmit the first timing signal to the resetter 213. When the resetter 213 receives the first timing signal, it can generate a reset signal to reset the first timing circuit 210.

[0064] As Figure 3 shown, the second timing circuit 220 may include a capacitor power control module 224, a second oscillator 223, and a second counter 222. Among them, the capacitor power control module 224 is connected to the power adapter 10, the first timing circuit 210, the second oscillator 223, and the second counter 222; in the power supply state of the power adapter 10, the electrical signal output by the power adapter 10 can be transmitted to the capacitor power control module 224 to charge the capacitor power control module 224. When the first counter 212 outputs the first timing signal, the power adapter 10 stops power supply after receiving the first timing signal. The capacitor power control module 224 releases the charging voltage to supply power to the first timing circuit 210, the second counter 222, and the second oscillator 223 after receiving the first timing signal. When the capacitor power control module 224 receives the first timing signal, it can also provide an oscillation enable signal to the second oscillator 223;

[0065] The second oscillator 223 receives the above-mentioned oscillation enable signal, generates a clock signal, and inputs the clock signal into the second counter 222. The second counter 222 is connected to the first timing circuit 210, the second oscillator 223, the power adapter 10, and the capacitor power control module 224. The second counter 222 receives the first timing signal transmitted by the first counter 212 and the clock signal transmitted by the second oscillator 223, starts counting, and when the count reaches a second preset value, the second counter 222 transmits a second timing signal to the power adapter 10 and a second timing signal to the capacitor power control module 224.

[0066] Upon receiving the second timing signal, the power adapter 10 outputs a low voltage and low current, thereby continuing to charge the capacitor power control module 224 and supplying power to the first timing circuit 210, enabling immediate charging when the charging load 2 is inserted.

[0067] Figure 4 FIG. is a schematic structural diagram of the capacitor power control module 224 provided by an embodiment of the present application. As Figure 4 shown, the capacitor power control module 224 includes: an XNOR gate, an N-type field effect transistor Q3, a capacitor C1, and an enable signal generation circuit 221.

[0068] The input terminals of the XNOR gate are connected to the first timing circuit 210 and the second counter 222, receiving the first timing signal Counter1_EN output by the first counter 212 of the first timing circuit 210 and the second timing signal Counter2_EN2 output by the second counter 222.

[0069] The gate of the N-type field effect transistor Q3 is connected to the output terminal of the XNOR gate for controlling the charging and discharging of the capacitor C1; the drain of the N-type field effect transistor Q3 is connected to the gates of the P-type field effect transistor Q33 and the P-type field effect transistor Q2. The capacitor C1 is connected in parallel with the N-type field effect transistor Q3. One end of the capacitor C1 is connected to the power supply (i.e., the power adapter 10) through the P-type field effect transistor Q33 and the P-type field effect transistor Q2; the other end of the capacitor C1 is grounded; when Counter1_EN is high and Counter2_EN2 is low, after passing through the XNOR gate, the signal line Net1 is low, turning off the N-type field effect transistor Q3. Further turning off the P-type field effect transistor Q33 and the P-type field effect transistor Q2: making the capacitor C1 in a discharging state. Conversely, it enters a charging state. Thus, when the first counter 212 outputs a high level and the second counter 222 outputs a low level, the power adapter 10 stops supplying power, and the capacitor C1 can supply power to the chip 20.

[0070] The enable signal generation circuit 221, connected to the power adapter 10, the capacitor C1, and the second oscillator 223, is used to output an oscillation enable signal OSCEn to the second oscillator 223.

[0071] As shown Figure 4 in FIG., the enable signal generation circuit 221 includes: a startup circuit, a voltage conversion circuit, and a NOR gate. The startup circuit is connected to the power adapter 10 and the capacitor C1, and is configured to generate a turn-on voltage. The startup circuit includes a diode D1, a resistor R4 connected in series with the diode D1, a resistor R2 connected in parallel with the diode D1, P-type field effect transistors Q34, Q30, Q29 connected in series with the resistor R2, N-type field effect transistors Q16, Q31, Q32 connected in series with the P-type field effect transistor Q29, and an N-type field effect transistor Q17. The source and drain of the N-type field effect transistor Q17 are connected in parallel with the N-type field effect transistors Q16, Q31, Q32. After the P-type field effect transistors Q34, Q30, Q29 and the N-type field effect transistors Q16, Q31, Q32 are connected in series, they are connected in parallel across both ends of the resistor R4.

[0072] The voltage conversion circuit is connected to the startup circuit and the power adapter 10, and is configured to convert the turn-on voltage into a control signal Net2. The voltage conversion circuit includes an N-type field effect transistor Q18 and an N-type field effect transistor Q20 connected in series. The gate of the N-type field effect transistor Q18 is connected to the drain of the P-type field effect transistor Q29. The gate of the N-type field effect transistor Q20 is connected to the N-type field effect transistor Q17. The voltage conversion circuit further includes an N-type field effect transistor Q19. The gate of the N-type field effect transistor Q19 is connected to the source of the N-type field effect transistor Q18, and the source and drain of the N-type field effect transistor Q19 are grounded. The voltage conversion circuit further includes a current mirror composed of P-type field effect transistors Q7, Q8, Q9, Q11, an N-type field effect transistor Q21 connected in series with the P-type field effect transistor Q7, an N-type field effect transistor Q23 connected in series with the P-type field effect transistor Q11, and resistors R5 and R6 connected in series with the P-type field effect transistor Q9. The gate of the N-type field effect transistor Q21 is connected to the source of the N-type field effect transistor Q18, and the gate of the N-type field effect transistor Q23 is connected to the gate of the N-type field effect transistor Q20.

[0073] The input end of the NOR gate is connected to the output end Net2 of the voltage conversion circuit and the output end Net1 of the exclusive-NOR gate. The output end of the NOR gate is connected to the second oscillator 223, and is configured to output an oscillation enable signal OSCEn to the second oscillator 223.

[0074] When the N-type field effect transistor Q3 is turned on, the P-type field effect transistors Q33 and Q2 are turned on, and the power adapter 10 starts to supply power. Under the action of the capacitor C1 (large capacitor), the gate voltage of the N-type field effect transistor Q5 rises to about 2.5V along with the voltage output by the power adapter 10. The N-type field effect transistor Q5 is turned on, and the Vout voltage follows the voltage output by the power adapter 10 to supply power to the chip 20.

[0075] Meanwhile, the left - hand startup circuit operates. The resistor R2 is in series with the inverse - ratio transistors Q34 / Q30 / Q29 to form a large resistor. The diode D1 serves as a gate - source clamping protection diode for the inverse - ratio transistors. As the power supply rises, Q16 / Q31 / Q32 conduct, the gate voltage of Q18 reaches 3VGS (i.e., the turn - on voltage), Q18 conducts, and charges Q19 connected in the capacitor configuration, causing the gate voltage of Q21 to rise to 2VGS, turning on Q21, enabling current to flow through R6 and Q7. Here, Q7 is in the diode configuration and forms a current mirror with Q8 / Q9 / Q11 / Q12. Q7 mirrors the current to Q9, and the mirrored current flows through R5 and then through R6, generating a voltage that turns on Q17 / Q20 / Q23.

[0076] Among them, turning on Q17 will pull down the gate voltage of Q18 from 3VGS to GND, turning off Q16 and Q18. Only a large - resistor path flows through Q17 to the ground. Q17 uses an inverse - ratio transistor to reduce power consumption.

[0077] Turning on Q20 will allow current to flow through Q8 to the ground. By setting the width - to - length ratio of Q8 and the inverse - ratio transistor of Q20, the gate voltage of Q21 is raised as much as possible, approaching Vout, generating the turn - on voltage of the subsequent - stage circuit. At this time, Q21 is in the linear region, V DS ≈0, V R6 ≈Vout - V GS , Ibias=(Vout - V GS ) / R6; Isource = M * Ibias, providing a bias current source ISource for the subsequent - stage oscillation circuit.

[0078] When Q23 is turned on, Net2 is low. At this time, if Net1 is low, after passing through the NOR gate NOR, the oscillation enable signal OSCEn of the subsequent - stage second oscillator 223 becomes high, and then oscillation is generated.

[0079] Figure 5 It is a schematic flow diagram of the charging control method provided by an embodiment of the present application. This method can be applied to the charging control circuit 1 in the above - mentioned embodiment and is executed by the charging control circuit 1 above. This method can include the following steps S510 - S530.

[0080] Step S510: When the charging load 2 is unplugged, trigger the first timing circuit 210 to start the timing function.

[0081] When the charging load 2 is unplugged, the connection terminal of the first timing circuit 210 and the charging load 2 changes from high level to low level, triggering the first timing circuit 210 to start the timing function.

[0082] Step S520: When the first preset time is reached, the first timing circuit 210 transmits a first timing signal to the power adapter 10.

[0083] The first timing circuit 210 can output a high level to the power adapter 10 when the number of clock cycles is greater than a first preset value by generating a clock signal.

[0084] Step S530: The power adapter 10 receives the first timing signal and stops outputting an electrical signal to the charging load 2.

[0085] Under normal circumstances, the power adapter 10 can output high voltage and high current to the charging load 2. When the power adapter 10 receives the high level sent by the first timing circuit 210, it stops outputting an electrical signal to the charging load 2. Therefore, when the charging load 2 is unplugged, there will be no high voltage and high current, improving safety and avoiding electric leakage.

[0086] In one embodiment, as Figure 6 shown, the charging control method provided by the embodiment of the present application further includes:

[0087] Step S610: The first timing circuit 210 transmits a first timing signal to the second timing circuit 220.

[0088] Step S620: When receiving the first timing signal, the second timing circuit 220 enables the timing function and transmits a second timing signal to the power adapter 10 when a second preset time is reached;

[0089] Step S630: The power adapter 10 receives the second timing signal and enters the normal charging mode.

[0090] Among them, the normal charging mode uses low voltage and low current compared to the fast charging mode (high voltage and high current). By transmitting the second timing signal to the power adapter 10 after the second preset time is reached by the second timing circuit 220, the power adapter 10 can be triggered to output low voltage and low current, so that when a charging load 2 such as a mobile phone is inserted, charging can start immediately. The voltage and current in the normal charging mode are lower than those in the fast charging mode, thus improving safety.

[0091] In one embodiment, as Figure 7 shown, the above step S620 specifically includes:

[0092] Step S621: The capacitor power control module 224 of the second timing circuit 220 receives the first timing signal, releases the charging voltage, and provides an oscillation enabling signal to the second oscillator of the second timing circuit 220;

[0093] Step S622: The second oscillator 223 receives the oscillation enabling signal and generates a clock signal;

[0094] Step S623: The second counter 222 of the second timing circuit 220 receives the first timing signal and the clock signal, starts counting, and transmits a second timing signal to the power adapter 10 when the count reaches a second preset value.

[0095] Wherein, after the power adapter 10 receives the second timing signal and enters the normal charging mode in step S630, the charging control method provided by the embodiment of the present application further includes: the power adapter 10 charges the capacitor power control module 224 and waits for the insertion of the charging load 2.

[0096] Wherein, after the first timing circuit 210 outputs the first timing signal, it can be reset. After the charging load 2 is re-inserted, the charging load 2 inputs a high level to the first timing circuit 210. Therefore, the signal received by the first timing circuit 210 changes from low level to high level, triggering the first timing circuit 210 to start timing, and sending a first timing signal to the power adapter 10 after reaching the first preset time. After receiving the first timing signal, the power adapter 10 can switch from the normal charging mode to the fast charging mode, and thus the charging load 2 enters the fast charging mode.

[0097] In the technical solution provided by the above embodiment of the present application, when the charging load 2 is unplugged, the power supply can be stopped, thereby avoiding electric leakage and improving safety. Due to the possible repeated plugging and unplugging situation, after the connection between the first timing circuit 210 and the charging load 2 is disconnected, the timing is started, and the first timing signal is sent to the power adapter 10 only after reaching the first preset time, so that the power adapter 10 stops supplying power, thereby avoiding repeated power on and off caused by repeated plugging and unplugging, resulting in equipment failure. Further, after the charging load 2 is unplugged for a period of time, it can be switched to the normal charging mode, which is convenient for immediate charging when the charging load 2 is inserted.

[0098] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the connections shown or discussed with each other can be direct connections or indirect connections, and the connection methods include communication connections or electrical connections.

Claims

1. A charging control circuit, characterized in that, Comprising: A power adapter; A chip for connecting the power adapter and a charging load; The chip includes a first timing circuit for connecting the power adapter and the charging load; When the charging load is disconnected from the first timing circuit, the first timing circuit enables its timing function and, when reaching a first preset time, transmits a first timing signal to the power adapter; The power adapter is used to receive the first timing signal, end the fast charging mode, and stop outputting an electrical signal to the charging load; The chip further includes a second timing circuit, the second timing circuit connecting the first timing circuit and the power adapter; the first timing circuit is further used to transmit the first timing signal to the second timing circuit; the second timing circuit is used to, when receiving the first timing signal, enable its timing function and, when reaching a second preset time, transmit a second timing signal to the power adapter; The power adapter is further used to receive the second timing signal and enter the normal charging mode from the mode of stopping outputting an electrical signal.

2. The charging control circuit according to claim 1, wherein The second timing circuit includes: A capacitor power control module connecting the power adapter, the first timing circuit, a second oscillator, and a second counter; the capacitor power control module is used to receive the first timing signal, release a charging voltage, and provide an oscillation enable signal to the second oscillator; A second oscillator for receiving the oscillation enable signal and generating a clock signal; A second counter connecting the first timing circuit, the second oscillator, the power adapter, and the capacitor power control module, for receiving the first timing signal and the clock signal, starting to count, and transmitting the second timing signal to the power adapter when counting to a second preset value.

3. The charging control circuit according to claim 2, wherein The capacitor power control module includes: An exclusive-NOR gate, the input terminals of the exclusive-NOR gate connecting the first timing circuit and the second counter; An N-type field effect transistor connecting the output terminal of the exclusive-NOR gate for controlling the charging and discharging of a capacitor; A capacitor connecting the power adapter and the N-type field effect transistor; An enable signal generation circuit connecting the power adapter, the capacitor, and the second oscillator for outputting an oscillation enable signal to the second oscillator.

4. The charging control circuit according to claim 3, wherein The enable signal generation circuit includes: A startup circuit connecting the power adapter and the capacitor for generating an enabling voltage; A voltage conversion circuit connecting the startup circuit and the power adapter for converting the enabling voltage into a control signal; A NOR gate, the input terminals of the NOR gate connecting the output terminal of the voltage conversion circuit and the output terminal of the exclusive-NOR gate, and the output terminal of the NOR gate connecting the second oscillator.

5. The charging control circuit according to claim 1, wherein The first timing circuit includes: A first oscillator for generating a clock signal; A first counter connecting the first oscillator for receiving the clock signal and counting, and transmitting the first timing signal to the power adapter when counting to a first preset value.

6. A charging control method, characterized in that, Comprising: When the charging load is unplugged, triggering the first timing circuit to enable its timing function; When reaching the first preset time, the first timing circuit transmits the first timing signal to the power adapter; The power adapter receives the first timing signal, ends the fast charging mode, and stops outputting an electrical signal to the charging load; The charging control method further includes: The first timing circuit transmits a first timing signal to the second timing circuit; When receiving the first timing signal, the second timing circuit enables the timing function, and when the second preset time is reached, transmits a second timing signal to the power adapter; The power adapter receives the second timing signal and enters the normal charging mode from the mode of stopping outputting an electrical signal.

7. The charging control method according to claim 6, wherein When receiving the first timing signal, the second timing circuit enables the timing function, and when the second preset time is reached, transmits a second timing signal to the power adapter, including: The capacitor power control module of the second timing circuit receives the first timing signal, releases the charging voltage, and provides an oscillation enable signal to the second oscillator of the second timing circuit; The second oscillator receives the oscillation enable signal and generates a clock signal; The second counter of the second timing circuit receives the first timing signal and the clock signal, starts counting, and transmits a second timing signal to the power adapter when the count reaches the second preset value.

8. The charging control method according to claim 7, wherein After the power adapter receives the second timing signal and enters the normal charging mode, the method further includes: The power adapter charges the capacitor power control module.

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