A source buffer configurable bias circuit

Abstract

The present invention discloses a source buffer configurable bias circuit, comprising a bias circuit and a current digital-to-analog converter IDAC, wherein the input end of the bias circuit is connected to the output end of the current digital-to-analog converter IDAC. The source buffer configurable bias circuit proposed by the present invention can flexibly adjust the working current of different regions, improve the consistency of the buffer circuit channel, and thus improve the display effect; the working current of different regions can be dynamically adjusted according to the characteristics of the display screen, such as dynamic or static images, so as to improve the display performance while saving the working current and power consumption of the chip; the designed multi-channel current output current digital-to-analog converter IDAC can reuse the main components in the same circuit, save the chip area by high and low bit segmentation, and the number of output current channels can also be flexibly configured.

Description

Technical Field

[0001] The present invention relates to the technical field of source buffer circuits, and in particular to a source buffer configurable bias circuit. Background Art

[0002] In the display driver chip, one of the very important functional modules is the source driver module, such as Figure 3 and Figure 4 Its driving part is also called source buffer circuit, which is implemented by analog circuit and is used to drive the source level line on the screen. The number of source drive channels will vary depending on the display resolution, but the number is generally in the order of hundreds to thousands.

[0003] According to the requirements of the buffer output drive voltage range, the source buffer circuit is basically implemented with devices with an operating voltage of more than 5V. This implementation method currently has some problems: the first is that the matching performance between devices of 5V or above is poor, which will lead to poor consistency between channels. One solution is to increase the area of ​​the device, but due to the large number of channels, this will significantly increase the area of ​​the chip, thereby increasing the cost of the chip. The second is that the number of buffer channels ranges from hundreds to thousands, and the distance between the two ends of the channel on the chip is very far. The gradient caused by chip production will seriously affect the consistency between channels, and thus seriously affect the display effect of the display screen.

[0004] How to improve the consistency between buffer circuits without significantly increasing the chip area, thereby improving the display effect of the display screen has become an urgent problem that technical personnel in this field need to solve. Based on this, a source buffer configurable bias circuit is proposed. Summary of the invention

[0005] The purpose of the present invention is to provide a source buffer configurable bias circuit, which can flexibly adjust the operating current of different areas, improve the consistency of the buffer circuit channel, and thus improve the display effect, save the operating current and power consumption of the chip, save the area of ​​the chip, and the number of output current channels can be flexibly configured to solve the problem raised in the above background technology of how to improve the consistency between buffer circuits to improve the display effect of the display screen without significantly increasing the chip area.

[0006] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a source buffer configurable bias circuit, comprising a bias circuit and a current digital-to-analog converter IDAC, wherein the input end of the bias circuit is connected to the output end of the current digital-to-analog converter IDAC; the bias circuit is connected to a plurality of bias circuits, which are respectively recorded as bias circuit A, bias circuit B-bias circuit N, and the current digital-to-analog converter IDAC is connected to a plurality of current digital-to-analog converters, which are respectively recorded as current digital-to-analog converters IDACa, current digital-to-analog converters IDACb-current digital-to-analog converters IDACn, wherein the input end of the bias circuit A is connected to the output end of the current digital-to-analog converter IDACa, the input end of the bias circuit B is connected to the output end of the current digital-to-analog converter IDACb, and so on, wherein the input end of the bias circuit N is connected to the output end of the current digital-to-analog converter IDACn.

[0007] Preferably, the current digital-to-analog converter IDAC includes MOS transistors PM1-MOS transistor PM26, switches K1-switch K8, the sources of MOS transistors PM1-MOS transistor PM13 are connected to the high level VDD, the gates of MOS transistors PM1-MOS transistor PM13 are connected in sequence, the drain of MOS transistor PM1 is connected to the gate and then connected to the source of MOS transistor PM14, the drain of MOS transistor PM2 is connected to the source of MOS transistor PM15, the drain of MOS transistor PM3 is connected to the source of MOS transistor PM16, and the drain of MOS transistor PM4 is connected to the source of MOS transistor PM1. The drain of MOS tube PM7 is connected to the source of MOS tube PM18, the drain of MOS tube PM6 is connected to the source of MOS tube PM19, the drain of MOS tube PM7 is connected to the source of MOS tube PM20, the drain of MOS tube PM8 is connected to the source of MOS tube PM21, the drain of MOS tube PM9 is connected to the source of MOS tube PM22, the drain of MOS tube PM10 is connected to the source of MOS tube PM23, the drain of MOS tube PM11 is connected to the source of MOS tube PM24, the drain of MOS tube PM12 is connected to the source of MOS tube PM25, the drain of MOS tube PM13 is connected to the source of MOS tube PM26, the drain of MOS tube PM14 is connected to the source of MOS tube PM27, the drain of MOS tube PM15 is connected to the source of MOS tube PM28, the drain of MOS tube PM16 is connected to the source of MOS tube PM29, the drain of MOS tube PM17 is connected to the source of MOS tube PM21, the drain of MOS tube PM18 is connected to the source of MOS tube PM22 The drain of MOS tube PM13 is connected to the source of MOS tube PM26; the gates of MOS tubes PM14 to PM26 are connected in sequence, the drain of MOS tube PM14 is connected to the gate and then connected to the input end of IBP; the drain of MOS tube PM15 is connected to the input end of switch K1, the drain of MOS tube PM16 is connected to the input end of switch K2, the drain of MOS tube PM17 is connected to the input end of switch K3, the drain of MOS tube PM18 is connected to the input end of switch K4, and the drain of MOS tube PM19 is connected to the input end of switch K5. The drain of the MOS transistor PM23 is connected to the input end of the switch K5, the drain of the MOS transistor PM24 is connected to the input end of the switch K6, the drain of the MOS transistor PM25 is connected to the input end of the switch K7, the drain of the MOS transistor PM26 is connected to the input end of the switch K8, the drain of the MOS transistor PM20, the output ends of the switches K1, K2, K7 and K8 are connected and then connected to the IBPO2 terminal output; the drain of the MOS transistor PM21, the output ends of the switches K3, K4, K5 and K6 are connected and then connected to the IBPO1 terminal output.

[0008] Preferably, the current digital-to-analog converter IDAC also includes bias MOS transistors PM27 to PM30, wherein the drain of the bias MOS transistor PM27 is connected to the drain of the MOS transistor PM19, and the drain of the bias MOS transistor PM28 is connected to the drain of the MOS transistor PM22; the gate of the bias MOS transistor PM27 is connected to the gate of the bias MOS transistor PM29, the source of the bias MOS transistor PM27 is connected to the drain of the bias MOS transistor PM28, the source of the bias MOS transistor PM29 is connected to the drain of the bias MOS transistor PM30, the gate of the bias MOS transistor PM28 is connected to the gate of the bias MOS transistor PM30, and the source of the bias MOS transistor PM28 and the source of the bias MOS transistor PM30 are both grounded to VSS.

[0009] Preferably, the bias current of the bias circuit comes from the current digital-to-analog converter IDAC2, the magnitude of the output current is configured by a digital signal, and the bit width of the digital control signal is selected according to the adjustment range and the adjustment accuracy.

[0010] Preferably, the implementation method of the current digital-to-analog converter IDACa-current digital-to-analog converter IDACn reuses main components in the same circuit to achieve multi-channel configurable current output.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: the source buffer configurable bias circuit proposed by the present invention has the following advantages:

[0012] 1. According to the changes in chip production process, the operating current in different areas can be flexibly adjusted to improve the consistency of the buffer circuit channel, thereby improving the display effect.

[0013] 2. The operating current of different areas can be dynamically adjusted according to the characteristics of the display screen, such as dynamic or static images, so as to improve the display performance while saving the operating current and power consumption of the chip.

[0014] 3. The designed current digital-to-analog converter IDAC with multiple current outputs can reuse the main components in the same circuit, save chip area by high and low bit segmentation, and the number of output current channels can also be flexibly configured. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of the configurable bias circuit of the present invention;

[0016] Figure 2 It is a schematic diagram of the structure of the current digital-to-analog conversion circuit of the present invention;

[0017] Figure 3 It is a schematic diagram of the circuit structure of the prior art;

[0018] Figure 4Schematic diagram of the existing driver chip structure.

[0019] In the figure: 1. Bias circuit; 2. Current digital-to-analog converter IDAC. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] See also Figure 1 A source buffer configurable bias circuit includes a bias circuit 1 and a current digital-to-analog converter IDAC2, wherein the input end of the bias circuit 1 is connected to the output end of the current digital-to-analog converter IDAC2; the bias circuit 1 is connected to a plurality of bias circuits 1, which are respectively denoted as current digital-to-analog converter IDACa, current digital-to-analog converter IDACb, and current digital-to-analog converter IDACn. The circuit wiring and component size of the plurality of current digital-to-analog converters IDAC2 are the same, the input end of the bias circuit A is connected to the output end of the current digital-to-analog converter IDACa, the input end of the bias circuit B is connected to the output end of the current digital-to-analog converter IDACb, and so on, the input end of the bias circuit N is connected to the output end of the current digital-to-analog converter IDACn.

[0022] See also Figure 2The current digital-to-analog converter IDAC2 includes MOS transistors PM1-MOS transistor PM26, switches K1-switch K8, the sources of MOS transistors PM1-MOS transistor PM13 are connected to the high level VDD, the gates of MOS transistors PM1-MOS transistor PM13 are connected in sequence, the drain of MOS transistor PM1 is connected to the gate and then connected to the source of MOS transistor PM14, the drain of MOS transistor PM2 is connected to the source of MOS transistor PM15, the drain of MOS transistor PM3 is connected to the source of MOS transistor PM16, the drain of MOS transistor PM4 is connected to the source of MOS transistor PM17, the drain of MOS transistor PM5 is connected to MOS The drain of MOS tube PM12 is connected to the source of MOS tube PM25; the drain of MOS tube PM13 is connected to the source of MOS tube PM26.

[0023] See also Figure 2 , the gates of MOS transistors PM14 to PM26 are connected in sequence, the drain of MOS transistor PM14 is connected to the gate and then connected to the input end of IBP; the drain of MOS transistor PM15 is connected to the input end of switch K1, the drain of MOS transistor PM16 is connected to the input end of switch K2, the drain of MOS transistor PM17 is connected to the input end of switch K3, the drain of MOS transistor PM18 is connected to the input end of switch K4, the drain of MOS transistor PM23 is connected to the input end of switch K5, the drain of MOS transistor PM24 is connected to the input end of switch K6, the drain of MOS transistor PM25 is connected to the input end of switch K7, the drain of MOS transistor PM26 is connected to the input end of switch K8, the drain of MOS transistor PM20, the output ends of switch K1, switch K2, switch K7 and switch K8 are connected and then connected to the IBPO2 terminal output; the drain of MOS transistor PM21, the output ends of switch K3, switch K4, switch K5 and switch K6 are connected and then connected to the IBPO1 terminal output.

[0024] See also Figure 2The current digital-to-analog converter IDAC2 also includes bias MOS transistors PM27 to PM30, wherein the drain of the bias MOS transistor PM27 is connected to the drain of the MOS transistor PM19, and the drain of the bias MOS transistor PM28 is connected to the drain of the MOS transistor PM22; the gate of the bias MOS transistor PM27 is connected to the gate of the bias MOS transistor PM29, the source of the bias MOS transistor PM27 is connected to the drain of the bias MOS transistor PM28, the source of the bias MOS transistor PM29 is connected to the drain of the bias MOS transistor PM30, the gate of the bias MOS transistor PM28 is connected to the gate of the bias MOS transistor PM30, and the source of the bias MOS transistor PM28 and the source of the bias MOS transistor PM30 are both grounded to VSS.

[0025] The source buffer can be configured with a bias circuit, and a plurality of bias circuits 1 are connected to the source buffer respectively, such as Figure 1 As shown, each source buffer is denoted as S1, S2-Sn, and between the channels from source buffer S1 to source buffer Sn, bias circuits 1 are relatively evenly inserted for each certain number of channels. The number of bias circuits 1 can be increased or decreased according to the number of channels. Each bias circuit 1 is responsible for providing bias circuits 1 to multiple adjacent source buffers.

[0026] The bias current of the bias circuit 1 comes from the current digital-to-analog converter IDAC2. The output current is configured by a digital signal. The bit width of the digital control signal can be selected according to the adjustment range and adjustment accuracy. By adopting the above scheme, the bias current of the bias circuit 1 can be allocated and configured by region:

[0027] First, it can adapt to changes in gradient distribution during the chip production process. For example, from source buffer S1 to source buffer Sn, due to the influence of the gradient, the current of each channel decreases successively. Then, the current digital-to-analog converter IDAC2 can be configured, and the current output from the current digital-to-analog converter IDACa to the current digital-to-analog converter IDACn becomes larger successively. In this way, the changes in channel current can be compensated, thereby improving the consistency between channels.

[0028] Second, the operating current of different areas or the whole can be dynamically adjusted according to the characteristics of the screen display, such as dynamic or static images, so as to improve the display performance while saving the chip's operating current and power consumption.

[0029] See also Figure 2The implementation method of the current digital-to-analog converter IDACa-current digital-to-analog converter IDACn can reuse the main circuit to realize multiple configurable current outputs. It sets two configurable current outputs, namely IBPO1 and IBPO2. Each configurable current is divided into two sections by dividing the high bit and the low bit, which are the high 2 bits and the low 2 bits. The weights of the high 2 bits and the low 2 bits are adjusted by MN1 and MN2. The number of sections divided by the high and low bits and the output current channels can be flexibly configured according to actual needs.

[0030] In summary, the source buffer configurable bias circuit proposed in the present invention has the following advantages:

[0031] 1. According to the changes in chip production process, the operating current in different areas can be flexibly adjusted to improve the consistency of the buffer circuit channel, thereby improving the display effect.

[0032] 2. The operating current of different areas can be dynamically adjusted according to the characteristics of the display screen, such as dynamic or static images, so as to improve the display performance while saving the operating current and power consumption of the chip.

[0033] 3. The designed current digital-to-analog converter IDAC2 with multiple current outputs can reuse the main components in the same circuit, save chip area by high and low bit segmentation, and the number of output current channels can also be flexibly configured.

[0034] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A source buffer configurable bias circuit, characterized in that: The invention comprises a bias circuit (1) and a current digital-to-analog converter IDAC (2), wherein the input end of the bias circuit (1) is connected to the output end of the current digital-to-analog converter IDAC (2); the bias circuit (1) is connected to a plurality of bias circuits, which are respectively recorded as bias circuit A, bias circuit B, and bias circuit N; the current digital-to-analog converter IDAC (2) is connected to a plurality of current digital-to-analog converters, which are respectively recorded as current digital-to-analog converters IDACa, current digital-to-analog converters IDACb, and current digital-to-analog converters IDACn; the input end of the bias circuit A is connected to the output end of the current digital-to-analog converter IDACa, the input end of the bias circuit B is connected to the output end of the current digital-to-analog converter IDACb, and so on; the input end of the bias circuit N is connected to the output end of the current digital-to-analog converter IDACn; the implementation method of the current digital-to-analog converters IDACa and IDACn reuses the main components in the same circuit to realize multi-channel configurable current output; The current digital-to-analog converter IDAC (2) comprises MOS transistors PM1 to PM26, switches K1 to K8, the sources of the MOS transistors PM1 to PM13 are connected to a high level VDD, the gates of the MOS transistors PM1 to PM13 are connected in sequence, the drain of the MOS transistor PM1 is connected to the gate and then to the source of the MOS transistor PM14, the drain of the MOS transistor PM2 is connected to the source of the MOS transistor PM15, the drain of the MOS transistor PM3 is connected to the source of the MOS transistor PM16, the drain of the MOS transistor PM4 is connected to the gate of the MOS transistor PM5. The drain of MOS tube PM10 is connected to the source of MOS tube PM23, the drain of MOS tube PM11 is connected to the source of MOS tube PM24, the drain of MOS tube PM12 is connected to the source of MOS tube PM13, the drain of MOS tube PM14 is connected to the source of MOS tube PM15, the drain of MOS tube PM16 is connected to the source of MOS tube PM17, the drain of MOS tube PM17 is connected to the source of MOS tube PM18, the drain of MOS tube PM6 is connected to the source of MOS tube PM19, the drain of MOS tube PM7 is connected to the source of MOS tube PM20, the drain of MOS tube PM8 is connected to the source of MOS tube PM21, the drain of MOS tube PM9 is connected to the source of MOS tube PM22, the drain of MOS tube PM10 is connected to the source of MOS tube PM23, the drain of MOS tube PM11 is connected to the source of MOS tube PM24, the drain of MOS tube PM12 is connected to the source of MOS tube PM13. The drain of MOS tube PM13 is connected to the source of MOS tube PM26; the gates of MOS tubes PM14 to PM26 are connected in sequence, the drain of MOS tube PM14 is connected to the gate and then connected to the input end of IBP; the drain of MOS tube PM15 is connected to the input end of switch K1, the drain of MOS tube PM16 is connected to the input end of switch K2, the drain of MOS tube PM17 is connected to the input end of switch K3, the drain of MOS tube PM18 is connected to the input end of switch K4, and the drain of MOS tube PM19 is connected to the input end of switch K5. The drain of the MOS transistor PM23 is connected to the input end of the switch K5, the drain of the MOS transistor PM24 is connected to the input end of the switch K6, the drain of the MOS transistor PM25 is connected to the input end of the switch K7, the drain of the MOS transistor PM26 is connected to the input end of the switch K8, the drain of the MOS transistor PM20, the output ends of the switches K1, K2, K7 and K8 are connected and then connected to the IBPO2 terminal output; the drain of the MOS transistor PM21, the output ends of the switches K3, K4, K5 and K6 are connected and then connected to the IBPO1 terminal output; The current digital-to-analog converter IDAC (2) further comprises bias MOS transistors PM27 to PM30, wherein the drain of the bias MOS transistor PM27 is connected to the drain of the MOS transistor PM19, and the drain of the bias MOS transistor PM29 is connected to the drain of the MOS transistor PM22; the gate of the bias MOS transistor PM27 is connected to the gate of the bias MOS transistor PM29, the source of the bias MOS transistor PM27 is connected to the drain of the bias MOS transistor PM28, the source of the bias MOS transistor PM29 is connected to the drain of the bias MOS transistor PM30, the gate of the bias MOS transistor PM28 is connected to the gate of the bias MOS transistor PM30, and the source of the bias MOS transistor PM28 and the source of the bias MOS transistor PM30 are both connected to the ground VSS.

2. A source buffer configurable bias circuit as claimed in claim 1, characterized in that: The bias current of the bias circuit (1) comes from the current digital-to-analog converter IDAC2. The magnitude of the output current is configured by a digital signal, and the bit width of the digital control signal is selected according to the adjustment range and adjustment accuracy.

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