Connection of several circuits of an electronic chip

Abstract

Embodiments of the present disclosure relate to the connection of several circuits of an electronic chip. An electronic chip includes a circuit, which is linked to a shared strip by tracks. The shared strip is at least partially conductive and is linked to a node for applying a fixed potential.

Description

[0001] Priority claim

[0002] This application claims priority from French patent application No. 1906583, filed on June 19, 2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices, and in particular to integrated circuit electronic chips. Background Art

[0004] Certain electronic devices, such as integrated circuit electronic chips, receive and / or provide electrical potentials on contact pads that are connected to one or more other devices. For example, the electronic chip is linked to a power supply and receives a power supply voltage. The electrical potential is then distributed to the various electronic circuits located in the chip.

[0005] There is a need in the art to address all or some of the shortcomings of known electronic chips. Summary of the invention

[0006] One embodiment provides an electronic chip that makes it easier to generate and / or provides a better potential distribution between electronic circuits of the chip than known electronic chips.

[0007] Thus, one embodiment provides an electronic chip comprising several circuits linked by tracks to a shared strip, the shared strip being at least partially conductive and linked to a node for applying a fixed potential.

[0008] According to one embodiment, the nodes are defined by connection pads of the chip.

[0009] According to one embodiment, the resistance per unit length of the shared strip is lower than the resistance per unit length of the tracks.

[0010] According to one embodiment, the circuit is at least partially analog.

[0011] According to one embodiment, each circuit includes an IP core.

[0012] According to one embodiment, each track links a single one of the IP cores to a shared stripe.

[0013] According to one embodiment, for each of said tracks, the conductive sections of the surface of the shared strip are larger than the conductive sections of the surface of the track and / or comprise a conductive material having a greater conductivity than the conductive material of the track.

[0014] According to one embodiment, the shared strip is made of one metal strip or several metal strips.

[0015] According to one embodiment, the total width and / or total thickness of the metal strip(s) is greater than the total width and / or total thickness of the track.

[0016] According to one embodiment, adjacent and side-by-side metal strips are separated by a distance between the metal strips that is smaller than the width of the metal strip, preferably less than 30% of the width of the metal strip.

[0017] According to one embodiment, the metal strips of the metal strips are overlapping.

[0018] According to one embodiment, the tracks and the shared strips are located at different metal levels.

[0019] According to one embodiment, the tracks and the shared strips are separated orthogonally thereto.

[0020] According to one embodiment, each track is linked to a shared strip through one via or several vias preferably arranged in a matrix.

[0021] One embodiment provides a method comprising steps for designing the above-mentioned electronic chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features and advantages will be described in detail in the following description of specific embodiments given by way of illustration and without limitation with reference to the accompanying drawings, in which:

[0023] Figure 1 shows a schematic top view of an embodiment of an electronic chip;

[0024] Figure 2 Schematically shows the Figure 1 Different proportions Figure 1 A cross-sectional view of a chip; and

[0025] Figure 3 Shows different proportions Figure 1 A top view of a portion of a chip. DETAILED DESCRIPTION

[0026] The same features are denoted by the same reference symbols in the various drawings. In particular, the same structural and functional features in the various embodiments may have the same reference symbols and may address the same structures, dimensions and material properties.

[0027] For the sake of clarity, the operation and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, the electronic chip circuit is not described in detail, and the embodiments described are compatible with the usual electronic chip circuit.

[0028] Unless otherwise specified, when reference is made to two elements being connected together, this refers to a direct connection without any intermediate elements other than conductors, and when reference is made to two elements being coupled together, this refers to the two elements may be connected or may be coupled via one or more other elements.

[0029] In the following disclosure, unless otherwise specified, when referring to absolute position qualifiers (such as terms "front", "rear", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "high", "low", etc.) or directional qualifiers (such as "horizontal", "vertical", etc.), reference is made to Figure 2 Orientation shown.

[0030] Unless otherwise specified, the expressions “approximately,” “approximately,” “substantially,” and “about” mean within 10%, and preferably within 5%.

[0031] Figure 1 A schematic top view of one embodiment of an electronic chip 100 is shown. Figure 2 With Figure 1 Different scales are schematically shown Figure 1 Cross-sectional view of the chip (cross-section AA).

[0032] The chip 100 may be made of a substrate 110 (such as a semiconductor wafer portion) and components located on the substrate 110. These components include components in and on the wafer (front side, i.e., facing the wafer). Figure 1 in front and Figure 2 The chip 100 is preferably a chip of the SOC (system on chip) type. SOC type chips are particularly used for embedded or mobile applications, such as mobile phones, connected objects, appliances or transportation. Preferably, the chip 100 is intended to be arranged in an integrated circuit housing (not shown). The housing is preferably intended to be connected (e.g. welded or soldered) to external electronic devices (such as a printed circuit of the PCB (printed circuit board) type) (e.g. ultrasonically).

[0033] Preferably, the chip 100 comprises a set 120 of digital circuits. This set 120 generally comprises at least one sequential data processing unit, for example of the microprocessor (CPU) type, and various peripheral components, such as memories and / or digital communication interfaces.

[0034] The electronic chip 100 includes connection pads. For example, Figure 1A single pad 130 is shown. However, the chip preferably includes several connecting pads. The connecting pads are generally formed by a conductive area located in front of the chip 100 (e.g., a metal area). For example, the pads have the same rectangular or square shape, or even an octagon. The length d1 of each side of the pad is preferably between 50 μm and 150 μm. For example, the length d1 is considered to be parallel to the edge of the chip closest to the pad 130. The length d1 can also be considered to be orthogonal to the edge, and the pad 130 can then include several parts with different widths. Preferably, the pad 130 is located at a position more than 40 μm from the edge of the chip. The connecting pads can be connected to a circuit outside the chip, preferably to a housing in which the chip is intended to be arranged. Preferably, the pads can be connected to the pins of the housing by, for example, welding or soldering (e.g., ultrasonically). These pins are intended to be soldered or soldered to a device outside the housing.

[0035] The electronic chip 100 further includes an electronic circuit 140. Each electronic circuit 140 is defined by a number of components (such as transistors and / or diodes and / or capacitors and / or resistors, etc., not shown), and is defined by a link linking these components to another component and / or node. For each electronic circuit 140, at least two nodes (nodes 142 and 144) of the nodes of the electronic circuit 140 are nodes for applying a fixed potential. The fixed or continuous potential is defined by the potential maintained at a constant level when the device is operating. During operation, the electronic circuit 140 receives a fixed potential at nodes 142 and 144. For example, nodes 142 and 144 are nodes for applying a DC power supply voltage of the circuit.

[0036] Preferably, each electronic circuit 140 includes input and / or output nodes (not shown). The circuit 140 is then configured to perform a given function according to the signal applied to the input node. Such a function usually generates one or several signals on one or several output nodes and / or modifies the state of a memory inside the circuit, for example.

[0037] Preferably, each circuit is at least partially analog, i.e., the circuit is configured to receive and / or generate at least one analog signal and / or use an analog signal inside the circuit. An analog signal is a signal capable of assuming a set of continuous values ​​(e.g. a set of voltage or current values ​​applied to a node) within a given range. Each circuit is then preferably configured to compare the analog value with a threshold value (comparator circuit COMP), and / or to convert the analog value to a digital value (analog-to-digital converter ADC), and / or to convert the digital value to an analog value (digital-to-analog converter DAC).

[0038] Preferably, each electronic circuit 140 includes, for example, an intellectual property core or an IP core-type circuit. In fact, in order to design an electronic chip, a design core library is usually used to implement a computer-aided design method. Each core defines an electronic component or a group of components and the connections between these components. During the design period, the connections between the cores are defined. The IP core is then defined by the electronic circuit corresponding to the design core during the chip design period.

[0039] The chip comprises a shared strip 150 which is at least partially conductive, i.e. comprises conductive material. The strip is defined by a structure having an elongated direction, which is conductive at least in the elongated direction. The electronic circuits 140 are linked (preferably connected) to the shared strip 150 via conductive tracks 160. More specifically, several of the electronic circuits 140 each have a node 144 of conductive material linked (preferably connected) to the shared strip 150 via tracks 160. For example, at least five electronic circuits 140 (preferably more than ten electronic circuits 140) are linked (e.g. connected) to the same strip 150.

[0040] Preferably, the ratio between the length (dimension in the elongated direction) and the width (lateral dimension parallel to the front) of the shared strip 150 is greater than 2, more preferably greater than 10, for example greater than 50. The shared strip 150 can be completely straight or a straight portion of a structure that extends further than the strip 150. For example, the shared strip is a portion of a longer strip having one or several curves and / or one or several angles (preferably one or several right angles). In a variant, the shared strip has one or several curves and / or one or several angles. For example, the shared strip has one or more right angles, and the track 160 can be connected to different straight portions of the shared strip 150.

[0041] The shared strip 150 is linked (preferably connected) to a node for applying a fixed potential. Preferably, this node for applying a fixed potential comprises a pad 130 or is formed by a pad 130, as shown.

[0042] During operation, this makes it possible to simultaneously apply the same fixed potential to the circuits 140 linked to the common strip 150 . In the example shown, the fixed potential of the pad 130 is applied to a node 144 of each electronic circuit 140 .

[0043] In an example where nodes 144 and 142 are nodes for applying a supply voltage relative to a ground reference, node 142 may be linked (preferably connected) to ground. Circuit 140 is powered by a single application of a supply voltage between ground and pad 130. The link between node 142 and ground may be formed by any standard link between a number of nodes and ground. However, the link between node 142 and ground is preferably formed by a conductive track that is linked (preferably connected) to another shared strip (not shown).

[0044] This example is not limiting, and nodes 144 and 142 can be nodes for applying any shared fixed potential to several circuits. In addition, nodes other than nodes 142 and / or 144 of several circuits 140 can be linked (preferably connected) to one or several other shared stripes. Then each circuit 140 can be linked to no shared stripe, to a single shared stripe, or to several shared stripes.

[0045] It has been considered to link each node 144 by a link directly connected to pad 130 without the need for an intermediate element of shared strip 150. It would then be considered to connect a large number of tracks (typically more than five tracks, or even more than ten tracks) directly to pad 130.

[0046] By comparison, providing the shared strip 150 makes it possible to simplify the design of the link between the node 144 and the same node (here, the pad 130). For this reason, preferably, the track 160 is designed after designing the shared strip 150. In particular, the surface occupied by the track and the strip 150 can be easily reduced relative to the surface occupied by the track directly connected to the node 130.

[0047] Preferably, the resistance per unit length of the shared strip 150 is less than the resistance per unit length of the tracks 160. Preferably, for each track, the resistance per unit length of the strip is less than 20% (preferably 10%) of the resistance per unit length of each track. For example, the total resistance of the shared strip 150 and its connection to the pad 130 (or to the node for applying the potential of the pad 130) is less than 10Ω, preferably less than 1Ω, and more preferably less than 0.1Ω. Reducing the resistance of the shared strip 150 thus makes it possible to reduce stray interactions between the circuits 140 (e.g., changes in the supply voltage of one of the circuits 140 when the current consumed by another of the circuits 140 changes). In other words, the resistance of the shared strip 150 is low enough so that during operation, the potential is substantially constant or uniform throughout the strip 150. For example, the total resistance (sum of resistances) of the shared strip 150 and its connections to the pads is low enough so that during operation, the potential in the entire shared strip 150 is equal to the potential of the pad 130, within 10% (preferably within 5%) of the operational allowable interval of each circuit 140 for the potential applied to its node 144. In particular, this makes it possible to reduce the noise level in the signal generated by the circuit 140, which corresponds to an improvement in chip operation.

[0048] Preferably, each track 160 link connects a single circuit in the electronic circuit 140 to a shared strip 150. Due to the low resistance value of the shared strip 150 and preferably its connection to the pad 130 defined above, during operation, the entire strip acts as a node for applying a fixed potential to the pad 130. The circuit 140 is therefore linked (preferably connected) to the node in a star shape. This makes it possible to prevent stray interactions (for example following changes in the current consumed by one of the circuits) in several circuits connected to the same track. Therefore, during chip design, providing such a star connection makes it possible to ensure that the noise and interference levels in the circuit are low enough to avoid the risk of misoperation or failure of the chip. As described above, a star connection including a shared strip 150 is easier to produce and can occupy a smaller surface than a star connection without a shared strip (such as strip 150).

[0049] Preferably, the shared strip 150 is located in the metal level of the electronic chip 100, ie in the layer 210 comprising the metal area 212 (in Figure 2 The metal region 212 is surrounded by an electrical insulation 214 and is included between an electrical insulation layer 220 covering the front side of the chip (indicated by dashed lines in FIG. 1 ). In an example not shown, the shared strip 150 includes a metal region in the form of a strip or ribbon, i.e. a metal strip located in a single metal level 210.

[0050] Preferably, each conductive track 160 comprises a metal strip 212B located in a single metal level 210. In a variant, each track 160 may comprise several parallel metal strips preferably located in the same metal level 210. Preferably, each conductive track 160 is located in a different metal level than the shared strip 150 and is connected to the conductive strip by a via 230. Each via is defined by a conductive element (preferably metallic) that passes through one or several insulating layers 220 and links (preferably connects) metal regions 212 located in different metal layers. More preferably, the conductive tracks 160 linked to the same shared strip 150 are located in the same metal level 210. Each track 160 is connected to a metal region defining a node 144 of the associated circuit 140. In a variant, the node 144 corresponds to a portion of the track 160, such as an end portion.

[0051] Preferably, the shared strip 150 includes several metal strips 212A (more preferably, parallel to each other). In the example shown, the shared strip 150 includes six metal strips 212A. The metal strips 212A are, for example, linked (preferably connected) to the connection pads 130. The link or connection between the metal strips and the connection pads can be direct, or through conductive vias and / or conductive tracks.

[0052] Preferably, the sum of the widths of the metal strips 212A is greater than the width of the tracks 160, and / or the sum of the thicknesses of the metal strips 212A is greater than the thickness of each track 160. Thus, the surface of the conductive segments of the shared strip 150 (i.e., the cross-section of the shared strip 150 ( Figure 2 The surface covered by the conductive material of the shared strip 150 in the plane of the metal strip 212A is several times larger than that of the metal strip 212A. The surface of the conductive section of the shared strip 150 is therefore larger than that of the track 160, making it possible to obtain a lower resistance per unit length of the conductive strip 160 than that of the track, for example, if the metal strip 212A and the track 160 are made of the same metal.

[0053] For example, the width of each track 160 is between 2 μm and 35 μm, preferably equal to 20 μm. For example, the width of the metal strip 212A is between 2 μm and 35 μm, preferably equal to 12 μm. For example, as can be seen above, the shared strip 150 has a width between 30 μm and 150 μm between the opposite edges of the set of metal strips 212A. For example, the thickness of each track 160 and each metal strip is between 0.8 μm and 3.4 μm.

[0054] The shared strip 150 may assume any suitable cross-sectional shape in cross section, the surface of which is greater than the surface of the conductive segments of the track 160. However, assuming that the shared strip 150 is formed by several conductive strips 212A, this makes it possible to use, for forming the strip 150, a metal strip 212A, the width and thickness of which are easily compatible with typical methods for designing and producing metal strips in insulating layers of electronic chips. Thus, with respect to a shared strip 150 formed by a single metal strip, a shared strip 150 comprising several metal strips 212A makes it possible to more easily obtain a low resistance value of the shared strip 150 as described above.

[0055] Preferably, in a shared strip 150 formed of several metal strips, adjacent metal strips of the same metal level are separated by a distance d that is less than the width of the metal strip 212A, more preferably less than 30% of the width of the metal strip 212A. For example, the distance d is between 2 μm and 5 μm, for example equal to 3.5 μm. Reducing the distance d makes it possible to reduce the surface area occupied by the shared strip 150.

[0056] In the example shown, the metal strips 212A of the shared strip 150 are located in different metal levels 210 and preferably at least partially overlap. This makes it possible to reduce the surface area occupied by the shared strip 150 relative to non-overlapping metal strips 212A. Preferably, the overlapping metal strips 212A are connected to each other by vias 230A. For example, the vias 230A overlap on the connecting vias 230 between the shared strip 150 and the track 160. During operation, the vias 230A make it possible to balance the potentials within the strips 150, which, as described above, improves the operation of the chip.

[0057] In a preferred example, the metal strip 212A of the shared strip 150 is located in the same metal level. Then the via 230A is omitted. The shared metal level preferably has the best conductivity between the metals of the metal level. Therefore, the metal strip 212A is made of a material with better conductivity than the track 160. For example, the shared metal level is higher, that is, farther from the substrate 110 than the track 160.

[0058] Assuming that the shared strip 150 is formed of a metal strip made of a metal with better conductivity than the track 160, or that at least some of the metal strips 212A of the strip 150 are made of a material with better conductivity than the track 160, then for the same conductive section surface of the strip 150 and the track 160, a lower resistance per unit length of the shared strip 150 than the resistance per unit length of the track 160 can be obtained. This can be combined with a conductive portion of the shared strip 150 being larger than the conductive portion of the track 160, making it possible to further reduce the resistance ratio between the strip 150 and the track 160. As described above, the operation of the chip is thus improved.

[0059] For example, the metal strip(s) 212A of the shared strip 150 are made of copper, and the track 160 is made of aluminum. In a variation, the track 160 may include a metal that is more conductive than the metal strips, for example the metal strip(s) 212A are made of aluminum, and the track 160 is made of copper. In a variation, the track 160 includes several different metals, and / or the metal strip 212A includes several different metals.

[0060] According to one embodiment, the shared strips 150 are located at the same metal level as the pads 130, or at least some of the metal strips 212A are located at the same metal level as the pads 130. The shared strips 150 may then at least partially form an extension of the pads 130, i.e. the pads 130 and at least a portion of the shared strips 150 are formed by the same metal area made of the same material.

[0061] According to an embodiment, shared strips 150 may be located in one or several metal levels different from pads 130, or at least some metal strips 212A may be located in one or several metal levels different from pads 130. The shared strips may then be linked to pads 130 through vias.

[0062] According to one embodiment, shared strip 150 is connected to pads 130 through metal regions 212 of metal level 212. These regions may be located at one or several metal levels different from shared strip and / or pads 130. These regions may then be connected to pads 130 and / or shared strip 150 through vias.

[0063] Figure 3 With Figure 1 Different ratios show Figure 1 More specifically, Figure 3 A connection is shown between the shared strip 150 and one of the tracks 160. In this example, the shared strip 150 includes two metal strips 212A, but the strip 150 may include a different number of metal strips 212A.

[0064] In the example shown, the track 160 and the shared strip 150 are separated orthogonally thereto. In other words, the shared strip 150 has a longitudinal direction 310, or a main direction or an elongated direction, and the track 160 has a longitudinal direction 320 orthogonal to the longitudinal direction 310 of the shared strip 150. More specifically, the longitudinal directions 310 and 320 are directions of a portion relatively close to the contact portion shown between the shared strip 150 and the track 160, and the shared strip 150 and / or the track 160 can change the direction of a portion relatively far from the contact portion. The portion of the track 160 close to the contact portion is preferably an end portion of the track 160. This example is not restrictive, and the angle between the directions 310 and 320 may not be equal to 90°. However, the fact that the track is separated orthogonally from the shared strip relative to the angle between the directions 310 and 320 not equal to 90° makes it possible to facilitate the design and production of the track 160 and the shared strip 150.

[0065] For each metal strip 212A, the track 160 and a portion 330 of the metal strip 212A overlap. The overlapping portion has a rectangular shape as seen above. The location of the via 20 between the track 160 and the metal strip 212A is shown.

[0066] Preferably, there are several vias 230 between each metal strip 212A and the track 160, for example two, four, eight, twelve or sixteen vias. These vias are preferably arranged in a matrix. Therefore, the connection between each metal strip 212A and the track 160 has a lower resistance than a single via 230. Therefore, it is possible to use a single via whose width (or dimension in a direction parallel to the front of the chip) is larger than the width of the via 230. However, standard methods for designing and manufacturing vias are easier to implement for several vias 230, especially when they are arranged in a matrix, relative to a single via that is wider than the via 230. For example, the width of the via is between 0.36 μm and 3 μm.

[0067] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0068] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional descriptions herein above.

Claims

1. An electronic chip, comprising: Multiple IP core circuits; a shared strip, at least partially conductive and connected to a node for applying a fixed potential, wherein the shared strip comprises a plurality of metal strips, wherein adjacent and side-by-side metal strips are separated by a distance less than a width of the metal strips; a plurality of tracks for electrically connecting the plurality of IP core circuits to the shared strip; Each individual track of the plurality of tracks individually connects a single one of the IP core circuits to the shared stripe. 2 . The electronic chip of claim 1 , wherein the nodes are defined by connection pads of the electronic chip. 3 . The electronic chip of claim 1 , wherein the resistance per unit length of the shared strip is lower than the resistance per unit length of the tracks. The electronic chip of claim 1 , wherein the plurality of IP core circuits are at least partially analog. 5 . The electronic chip of claim 1 , wherein for each track of the plurality of tracks, a conductive section of the surface of the shared strip is larger than a conductive section of the surface of the track. 6 . The electronic chip of claim 1 , wherein for each track of the plurality of tracks, the shared strip comprises a conductive material having a conductivity greater than a conductivity of the conductive material of the track.

7. The electronic chip of claim 1, wherein a total width of the shared strip is greater than a total width of the plurality of tracks.

8. The electronic chip of claim 1, wherein a total thickness of the shared strip is greater than a total thickness of the plurality of tracks.

9. The electronic chip of claim 1, wherein the distance is less than 30% of a width of the plurality of metal strips.

10. The electronic chip of claim 1, wherein at least some of the plurality of metal strips overlap one another.

11. The electronic chip of claim 1, wherein the plurality of tracks and the shared strip are located in different metal levels.

12. The electronic chip of claim 1, wherein the plurality of tracks extend from the shared strip orthogonally thereto.

13. The electronic chip of claim 1, wherein each track of the plurality of tracks is connected to the shared strip through at least one via arranged in a matrix.

14. An electronic chip comprising: Multiple IP core circuits; a shared strip, wherein the shared strip comprises a plurality of metal strips, wherein adjacent and side-by-side metal strips are separated by a distance less than a width of the metal strip; as well as a plurality of tracks for electrically connecting the plurality of IP core circuits to the shared strip; Each individual track of the plurality of tracks individually connects a single one of the IP core circuits to the shared stripe.

15. The electronic chip of claim 14, wherein the resistance per unit length of the shared strip is lower than the resistance per unit length of the plurality of tracks.

16. The electronic chip of claim 14, wherein a conductive section of a surface of the shared strip is larger than a conductive section of a surface of at least one track of the plurality of tracks.

17. The electronic chip of claim 14, wherein the shared strip comprises a conductive material having a greater conductivity than a conductive material of at least one track of the plurality of tracks.

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