Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device is manufactured by applying an uncured resin or adhesive on a substrate to expand it and then curing it. The semiconductor device has a structure that allows the uncured resin or adhesive to remain in a desired area and is miniaturized. The semiconductor device has a substrate on which a semiconductor element is mounted and a metal pattern formed on the substrate. The metal pattern has a first metal pattern and a second metal pattern that are separately arranged on the substrate, and a through electrode that is arranged between the first metal pattern and the second metal pattern and penetrates the substrate in the thickness direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which a semiconductor element such as a light-emitting element is mounted on a substrate, and more particularly to a semiconductor device manufactured by applying an uncured sealing resin or a die bonding agent on a substrate, spreading it, and curing it. Background Art

[0002] LED packages are known in which an LED (light emitting element) is mounted on a substrate and the periphery of the LED is sealed with resin. For example, Patent Document 1 discloses a package in which an LED is mounted on a planar substrate, uncured resin is dripped from above the LED, the uncured resin is raised into a hemispherical shape by utilizing the surface tension of the uncured resin, and the uncured resin is cured while maintaining the shape, thereby sealing the LED.

[0003] In such an LED package, in order to prevent the uncured resin from wetting and spreading to undesired areas on the substrate, the following structure is used: a ring-shaped metal pattern is set around the LED, and the surface tension of the uncured resin on the steps at the edge of the metal pattern is used to prevent the resin from wetting and spreading to the outside.

[0004] In particular, in LED packages using blue LEDs, a two-layer package with a sealing resin of soft silicone resin and hard silicone resin is used. By configuring the soft silicone resin on the inside, cracks are less likely to occur in the sealing resin, and by configuring the hard silicone resin on the outside, deformation of the soft silicone resin can be suppressed. This achieves a longer life of the blue LED package.

[0005] When forming a sealing resin with a two-layer structure, it is necessary to provide a double ring-shaped metal pattern for restricting the wetting spread in a concentric circle shape.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2003-258313 Summary of the invention

[0009] [Problems to be solved by the invention]

[0010] In the case of forming a two-layered sealing resin, for example Fig.10 (a) or Fig.10As shown in (b), double annular metal patterns 101 and 102 are formed, and the two resins are prevented from further wetting and spreading to the outside by the steps between the peripheries of the metal patterns 101 and 102 and the substrate 104. Therefore, since the film thickness of the metal patterns 101 and 102 needs to have a step thickness that can retain the resin, they are generally formed by electrolytic plating that can form a thick film.

[0011] Here, when the ring-shaped metal pattern is formed by electrolytic plating, a thin metal film is temporarily formed by another method, and after being processed into the shape of the ring-shaped metal patterns 101 and 102, the substrate 104 is immersed in an electrolyte, and the metal in the electrolyte is precipitated on the surface of the metal patterns 101 and 102 by supplying power to the ring-shaped metal patterns 101 and 102. Therefore, wiring for supplying power to the ring-shaped metal patterns 101 and 102 is required.

[0012] For example Fig.10 As shown in (a), a structure in which a power supply wiring 103 is arranged on the surface of a substrate 104 is considered. The power supply wiring 103 extends to the end of the substrate 104, and in the manufacturing process, the metal patterns 101 and 102 can be electroplated together with the substrate 104 for the semiconductor device arranged adjacently on a plurality of collective substrates that can be obtained.

[0013] However, since there is no step at the portion where the ring-shaped metal pattern 101 and the power supply wiring 103 are connected, there is a problem that uncured resin may flow out from the connection portion to the power supply wiring.

[0014] On the other hand, Fig.10 As shown in (b), it is also possible to consider a structure in which an electrode (through hole) is provided directly below the annular metal pattern and passes through the substrate in the thickness direction of the substrate, and power is supplied to the annular metal pattern from the back side of the substrate through the through hole. Fig.10 As shown in (b), the width of the annular metal pattern 101 needs to be larger than the diameter of the through hole 105, and the area occupied by the annular metal pattern 101 increases, which hinders the miniaturization of the LED package. Specifically, for example, if the minimum diameter of the practical through hole 105 is 0.1 mm, when the design tolerance (about 0.2 mm) is taken into account, the width of the annular metal pattern 101 directly below the through hole 105 needs to be 0.3 mm or more. In addition, when the through hole diameter is 0.1 mm, in order to form the through hole 105, the thickness of the substrate 104 needs to be less than 0.1 mm, which also causes the problem that the thickness of the substrate 104 is limited.

[0015] In addition, it is also possible to form a double annular metal pattern by etching (half etching) until the middle of the thickness direction of the metal layer after forming a thick metal layer on the substrate as a whole. However, in order to control the half etching, the metal pattern (e.g., copper pattern) needs to be thickened (e.g., 70 μm or more), and film formation takes time. In addition, in order to etch the thick copper pattern, it is necessary to expand the gap width between the inner annular metal pattern and the outer annular pattern. Moreover, half etching has problems such as difficulty in stabilizing the pattern size.

[0016] In addition, such a problem is not limited to the problem of controlling the wetting and spreading of the sealing resin in the ring-shaped metal pattern, but also occurs when adjacent metal patterns are arranged in a predetermined area on the substrate for various purposes. For example, such a problem also occurs in a structure that controls the wetting and spreading of the die bonding agent or solder used when fixing the LED to the metal pattern on the substrate from the desired area to the outside.

[0017] The present invention aims to provide a semiconductor device having a plurality of metal patterns in a predetermined area on a substrate, and the spacing between the metal patterns is reduced to make the device compact. In particular, the present invention provides a semiconductor device manufactured by a process of applying an uncured resin or adhesive on a substrate to spread the uncured resin or adhesive and curing the uncured resin or adhesive, and the semiconductor device has a structure that allows the uncured resin or adhesive to remain in a desired area and is compact.

[0018] [Methods used to solve the problem]

[0019] In order to achieve the above-mentioned object, the semiconductor device of the present invention has a substrate on which a semiconductor element is mounted and a metal pattern formed on the substrate. The metal pattern has a first metal pattern and a second metal pattern separately arranged on the substrate, and a through electrode arranged between the first metal pattern and the second metal pattern and penetrating the substrate in the thickness direction. At least a portion of the first metal pattern and the second metal pattern is in contact with the upper surface of the through electrode. A continuous plating layer is arranged on the first metal pattern, the second metal pattern and the through electrode, and the first metal pattern, the second metal pattern and the through electrode are electrically connected through the plating layer.

[0020] [Effects of the invention]

[0021] According to the present invention, power can be supplied to both the first and second metal patterns from the back side of the substrate through the through electrode, and the first and second metal patterns can be formed by electroplating. Therefore, a structure in which uncured resin or adhesive is retained in a desired area can be formed by electroplating, and a small semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1(a) is a top view of a substrate of the semiconductor device of Embodiment 1, (b) is a top view of the entire semiconductor device, (c) is an AA' cross-sectional view of the semiconductor device, (d) is a bottom view of the semiconductor device, and (e) is a BB' cross-sectional view of the semiconductor device.

[0023] Figure 2 (a) is a plan view of the semiconductor device according to the first embodiment, and (b) is an enlarged cross-sectional view of the vicinity of the through-electrode 13 .

[0024] Figure 3 (a) to (f) are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

[0025] Figure 4 (a) to (c) are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment.

[0026] Figure 5 (a) is a plan view of the semiconductor device according to the second embodiment, and (b) is an enlarged cross-sectional view of the vicinity of the through-electrode 13 .

[0027] Figure 6 (a) is a plan view of the semiconductor device according to the third embodiment, and (b) is an enlarged cross-sectional view of the vicinity of the through-electrode 13 .

[0028] Figure 7 (a) is a cross-sectional view of a substrate at a stage where an electrode (metal pattern) 15 for mounting a component is formed in the process of manufacturing a semiconductor device of embodiment 4, and (b) is a cross-sectional view of a completed substrate, which is a cross-sectional view of the substrate of a semiconductor device of embodiment 4.

[0029] Figure 8 (a) is a top view of a semiconductor device of a comparative example of the fourth embodiment, and (b) is a cross-sectional view thereof.

[0030] Fig. 9 (a) is a top view of the semiconductor device of Embodiment 5, (b) is a cross-sectional view, and (c) is a bottom view.

[0031] Fig.10 (a) is a top view of a conventional semiconductor device having a plating power supply wiring on a substrate surface, and (b) is a top view of a semiconductor device having a plating power supply through-electrode (through hole).

[0032] Description of symbols

[0033] 10…substrate, 10a…insulating layer, 10b, 10c…copper foil, 11…first metal pattern, 12…second metal pattern, 13…through electrode, 14…gap region, 15…metal pattern (electrode) for mounting element, 17…semiconductor element, 18…Zener diode, 21…first sealing resin, 22…second sealing resin, 31…back electrode, 32…back electrode, 33a, 33b…wiring, 91, 92, 93a, 93b, 93c…metal pattern, 96, 97, 98a, 98b, 93c…groove, 131…groove, 132…resin, 162…resin, 171…bonding wire, 201…copper plate, 202…support layer, 203a, 203b…copper plating, 204a, 204b…plating DETAILED DESCRIPTION

[0034] Hereinafter, one embodiment of the present invention will be described using the accompanying drawings.

[0035] <<Implementation Method 1>>

[0036] use Figure 1 etc. describe the semiconductor device according to the first embodiment. Figure 1 (a) is a top view of a substrate of the semiconductor device according to Embodiment 1, Figure 1 (b) is a top view of the entire semiconductor device. Figure 1 (c) is a cross-sectional view of the semiconductor device taken along the line AA'. Figure 1 (d) is a bottom view of the semiconductor device, and (e) is a BB' cross-sectional view of the semiconductor device.

[0037] like Figure 1 As shown, the semiconductor device of the first embodiment includes a substrate 10 on which a semiconductor element 17 is mounted, metal patterns 11 , 12 , and 15 formed on the substrate 10 , and a first sealing resin 21 and a second sealing resin 22 that doubly seal the semiconductor element 17 .

[0038] The semiconductor element 17 is fixed to the element mounting metal pattern 15 arranged in the center among the metal patterns 11, 12, and 15. Here, the semiconductor element 17 is a light emitting element, and has an upper surface electrode and a back electrode with different polarities, and the back electrode is fixed by bonding to the element mounting metal pattern 15 by solder or the like.

[0039] The metal pattern 11 (hereinafter also referred to as the first metal pattern) is arranged to surround the device mounting metal pattern 15, and the metal pattern 12 (hereinafter also referred to as the second metal pattern) is arranged to surround the metal pattern 11. The outer periphery of the metal pattern 11 is circular, and the metal pattern 12 is roughly annular. The outer periphery of the metal pattern 11 and the inner and outer peripheries of the metal pattern 12 roughly form concentric circles.

[0040] The outer periphery of the first metal pattern 11 is separated from the inner periphery of the second metal pattern 12, and the area between them forms a region 14 where the surface of the substrate 10 is exposed. In addition, outside the second metal pattern 12, the surface of the substrate 10 is also exposed.

[0041] Thus, a step corresponding to the thickness of the first metal pattern 11 is formed between the outer peripheral edge of the first metal pattern 11 and the upper surface of the substrate 10. If the uncured first sealing resin 21 is wetted and spread during the manufacturing process, the uncured first sealing resin 21 will stay due to the surface tension when it reaches the step and will not spread to the outside of the first metal pattern 11. Therefore, if Figure 1 As shown in (c) and (e) of FIG. 1 , the first sealing resin 21 seals the semiconductor element 17 in a region inside the outer periphery of the first metal pattern 11 .

[0042] In addition, a step corresponding to the thickness of the second metal pattern 12 is also formed between the outer peripheral edge of the second metal pattern 12 and the upper surface of the substrate 10. Therefore, if the uncured second sealing resin 22 is wetted and spread during the manufacturing process, the uncured second sealing resin 22 will stay due to the surface tension when it reaches the step and will not spread to the outside of the second metal pattern 12. Therefore, if Figure 1 As shown in (c) and (e) of FIG. 1 , the second sealing resin 22 seals the first sealing resin 21 and the semiconductor element 17 in a region inside the outer periphery of the second metal pattern 12 .

[0043] That is, the outer peripheral edges of the first metal pattern 11 and the second metal pattern 12 each function as a resin dam that blocks the so-called uncured resin.

[0044] A through electrode 13 penetrating the substrate in the thickness direction is disposed in a portion of a region 14 between the first metal pattern 11 and the second metal pattern 12. The through electrode 13 is disposed so as to straddle the first metal pattern 11 and the second metal pattern 12, and portions of the first metal pattern 11 and the second metal pattern 12 are in contact with the upper surface of the through electrode 13.

[0045] Figure 2 (a) and (b) show an enlarged view of the upper surface of the semiconductor device and an enlarged cross-sectional view of the vicinity of the through electrode 13. Figure 2 As shown in (b), a continuous plating layer 204 a is arranged on the first metal pattern 11 , the second metal pattern 12 , and the through-electrode 13 , and the first metal pattern 11 , the second metal pattern 12 , and the through-electrode 13 are electrically connected via the plating layer 204 .

[0046] In this way, by arranging the through-electrode 13 so as to straddle the first and second metal patterns 11 and 12, power can be supplied to the first and second metal patterns 11 and 12 from the back side of the substrate 10 via the through-electrode 13. Therefore, the plating layer 204 can be deposited on the surface of the first and second metal patterns 11 and 12 by electrolytic plating to make them thicker. Thus, the first and second metal patterns 11 and 12 can be formed into thick films, wherein the first and second metal patterns 11 and 12 can form a step that can function as a resin dam at the boundary with the substrate 10.

[0047] In addition, by arranging the through electrode 13 so as to straddle the first and second metal patterns 11 and 12, the width of the ring of the first and second metal patterns 11 and 12 can be made narrower than the diameter of the through electrode 13. That is, since the width of the ring of the first and second metal patterns 11 and 12 can be made narrower than the minimum diameter that can be formed as the through electrode 13, it is possible to reduce the dedicated area of ​​the first and second metal patterns 11 and 12. Therefore, according to this structure, a small semiconductor device can be provided.

[0048] In addition, a groove 131 is provided in the region between the first metal pattern 11 and the second metal pattern 12 on the through electrode 13. Thus, the outer peripheral edge of the first metal pattern 11 also has a step due to the groove 131 in the region where the through electrode 13 is arranged, and thus functions as a resin dam. Therefore, even at the position of the through electrode 13, the first metal pattern 11 does not cause the uncured first sealing resin to flow out, and the shape of the first sealing resin 21 can be raised into a dome shape. In addition, the plating layer also covers the inner wall of the groove 131.

[0049] In addition, if Figure 1 (a), (b) and Figure 2 As shown in (a), the width of the groove 131 (the interval between the first metal pattern 11 and the second metal pattern 12 on the through electrode 13) is designed to be narrower than the interval between the first metal pattern 11 and the second metal pattern 12 in the region where the through electrode 13 is not arranged. Therefore, in the manufacturing process described later, the depth of the groove 131 is controlled not to become too deep.

[0050] On the substrate 10, a through electrode 16 is provided below the device mounting metal pattern 15. The upper surface electrode of the semiconductor device 17 is connected to the first metal pattern 11 via two bonding wires 171.

[0051] The back side of the substrate 10 includes a back electrode 31 disposed at the position of the through electrode 13 , a back electrode 32 disposed at the position of the through electrode 16 , and wirings 33 a and 33 b connected to the back electrodes 31 and 32 , respectively.

[0052] Thus, the bonding wire 171, the first metal pattern 11, the through electrode 13, the back electrode 33, and the wiring 33a are electrically connected to the upper surface electrode of the semiconductor element 17. In addition, the element mounting pattern 15, the through electrode 16, the back electrode 32, and the wiring 33b are electrically connected to the lower surface electrode of the semiconductor element 17. Therefore, by supplying current between the wirings 33a and 33b on the back side of the substrate 10, current can be supplied to the semiconductor element 17 via the through electrodes 13 and 16, the first metal pattern 11, etc., and it can emit light. The emitted light is emitted to the outside through the first and second sealing resins 21 and 22.

[0053] Furthermore, the first and second sealing resins seal the semiconductor element 17 to protect the semiconductor element 17 from moisture and impact.

[0054] <Manufacturing method>

[0055] use Figure 3 and Figure 4 A method for manufacturing the semiconductor device according to the first embodiment will be described.

[0056] In addition, for the sake of convenience, the following description will be given of a process of manufacturing one semiconductor device on the substrate 10 , but it is also possible to prepare to manufacture a plurality of semiconductor devices in a state where a plurality of substrates 10 are available.

[0057] like Figure 3 As shown in (a), a copper plate 201 having a thickness equal to that of the substrate 10 (eg, about 100 to 400 μm) is prepared, a support layer 202 is attached to the back surface, and the copper plate 201 is processed by etching into the shape of the through electrodes 13 and 16. The copper plate 201 is made of rolled bulk copper.

[0058] like Figure 3 As shown in (b), a substrate 10 is prepared in which copper (Cu) foils 10b and 10c are attached to both sides of an insulating layer (here, a resin layer) 10a, and through holes are provided at the positions of through electrodes 13 and 16. The substrate 10 is covered on the supporting layer 202 of the through electrodes 13 and 16 in such a manner that the through electrodes 13 are inserted into the through holes.

[0059] like Figure 3 As shown in (c), the gaps between the through holes and the through electrodes 13 and 16 are filled with resin 132 and 162 and cured. If necessary, the through electrodes 13 and 16 protruding from the surface of the substrate 10 are removed by grinding or the like to make the surface of the substrate 10 flat. The supporting layer 202 of the through electrodes 13 and 16 is removed.

[0060] like Figure 3As shown in (d), after copper plating layers 203a and 203b are formed on both surfaces of the substrate 10 by electroless plating, current is supplied to the formed copper plating layers, and the copper plating layers 203a and 203b are grown into thick films (for example, a thickness of about 15 to 100 μm) by electrolytic plating.

[0061] like Figure 3 As shown in (e), the region of the upper surface of the substrate 10 that becomes the metal pattern 15 for mounting the element, the first and second metal patterns 11, 12, and the region of the back surface of the substrate 10 that becomes the back electrodes 31, 32 and wirings 33a, 33b are retained, and the copper plating 203a, 203b and the copper foils 10b, 10c of the other parts are removed by etching. At this time, a groove 131 is formed between the first metal pattern 11 and the second metal pattern 12 on the through electrode 13. In the etching process, in order to pattern the metal pattern 15 for mounting the element, the back electrodes 31, 32 and wirings 33a, 33b, over-etching is performed in the etching region to reliably remove the copper plating 203a, 203b, the copper foils 10b, 10c, and expose the surface of the glass epoxy substrate. As a result, a part of the surface of the through electrode 13 is etched, and the through electrode 13 is also exposed on the inner wall of the groove.

[0062] The through-electrode 13 is not limited to being formed of bulk copper as in the present embodiment, and may be filled with copper plating. However, by using bulk copper having a slower etching speed than copper plating, management of the etching amount becomes easier, and a semiconductor device with high reliability can be provided.

[0063] At this time, since the width of the groove 131 is designed to be narrower than the interval between the first metal pattern 11 and the second metal pattern 12 in the area where the through electrode 13 is not configured, the depth of the groove 131 will not be too deep, and the etching time can be easily set so that the insulating layer 10a of the substrate 10 is exposed in the area 14 between the first metal pattern 11 and the second metal pattern 12 in the area where the through electrode 13 is not configured.

[0064] like Figure 3 As shown in (f), current is supplied to the copper plating layer 203a of the first and second metal patterns 11 and 12 and the element mounting metal pattern 15 via the wiring 33a, 33b, the back electrodes 32, 31 and the through electrodes 13, 16 on the back side of the substrate 10, and a nickel (Ni) layer (for example, a thickness of about 3 to 15 μm) and a gold (Au) layer (for example, a thickness of about 0.05 to 0.3 μm) are sequentially formed by electrolytic plating, thereby forming plating layers 204a and 204b on both sides. The plating layer 204a is formed on the upper part of the through electrode 13 so as to be continuous with the upper part of the first and second metal patterns 11, 12 and the through electrode 13, so that they are electrically connected through the plating layer 204a.

[0065] Then, if Figure 4 As shown in (a), a semiconductor element 17 is mounted on the element mounting metal pattern 15, and the back electrode of the semiconductor element 17 is bonded to the element mounting metal pattern 15 via a solder layer 172. In addition, the upper surface electrode of the semiconductor element 17 is connected to the first metal pattern 11 via a bonding wire 171.

[0066] like Figure 4 As shown in (b), an uncured first sealing resin (which becomes a soft silicone resin after curing) 21 is dripped (potting) onto the semiconductor element 17. The uncured first sealing resin 21 wets and spreads, and stays in a dome shape due to the surface tension generated at the periphery of the outer side of the first metal pattern 11, the step between the first metal pattern 11 and the substrate 10, and the step between the first metal pattern 11 and the groove 131. In this state, the first sealing resin 21 is cured.

[0067] like Figure 4 As shown in (c), an uncured second sealing resin (a silicone resin that is harder than the first sealing resin 21 after curing) 22 is dripped (potted) onto the first sealing resin 21. The uncured second sealing resin 22 wets and spreads, and stays in a hemispherical shape due to the surface tension generated by the step between the second metal pattern 12 and the substrate 10 at the periphery of the outer side of the second metal pattern 12. In this state, the second sealing resin 22 is cured.

[0068] The semiconductor device of this embodiment can be manufactured through the above-mentioned steps.

[0069] According to the first embodiment, power can be supplied to both the first and second metal patterns 11 and 12 from the back side of the substrate 10 through the through electrode 13, and the first and second metal patterns 11 and 12 can be formed by electrolytic plating. Therefore, a resin dam structure that allows the uncured first and second sealing resins 21 and 22 to stay in a desired area can be formed by electroplating. Moreover, the width of the first and second metal patterns 11 and 12 (in this embodiment, only the width of the second metal pattern 12) can be made smaller than the diameter of the through electrode 13. In addition, a structure in which the through electrode 13 does not extend outside the second metal pattern 12 can be formed. As a result, the substrate 10 can be miniaturized, and a small semiconductor device can be provided.

[0070] In this embodiment, the through electrodes 13 and 16 are formed of a copper core formed by etching the copper plate 201, so the through electrodes 13 and 16 have high thermal conductivity. Therefore, the heat of the semiconductor element 17 can be efficiently conducted to the back side of the substrate 10 for heat dissipation.

[0071] In addition, in this embodiment, by sequentially forming the plating layers 204a and 204b of the Ni layer and the Au layer, it is possible to cover not only the upper surface of the copper plating layers 203a and 203b and the copper foils 10b and 10c, but also the side surfaces. Therefore, the copper plating layers 203a and 203b and the copper foils 10b and 10c do not contact the first and second sealing resins 21 and 22, and it is possible to prevent copper corrosion and improve reliability.

[0072] <<Implementation Method 2>>

[0073] use Figure 5 A semiconductor device according to Embodiment 2 will be described.

[0074] The semiconductor device of the second embodiment has the same structure as the semiconductor device of the first embodiment, but is different from the first embodiment in that the through electrode 13 is not made of a copper core but is made of a copper core. Figure 5 As shown in (a) and (b), a through hole 113a is provided by drilling or the like, its inner wall is covered with a copper plating layer 203c, and the through hole 113a is filled with a resin 113b to form a through hole structure. The plating layer 204a covers a portion of the upper surface of the through electrode 113. A portion of the copper plating layer 203a is in contact with the copper plating layer 203c formed on the upper surface of the through electrode 13, especially the inner wall of the through hole 113a. That is, a portion of the first metal pattern 11 and the second metal pattern 12 are in contact with the through electrode 13.

[0075] The plated layer 204a and the copper plated layer 203a are electrically connected to the copper plated layer 203c formed on the inner wall of the through hole 113a. That is, the first metal pattern 11 and the second metal pattern 12 are electrically connected to the copper plated layer 203c formed on the inner wall of the through hole 113a.

[0076] A groove where the resin 113b is exposed from the plating layer 204a is formed in the region between the first metal pattern 11 and the second metal pattern 12. The groove can be formed by forming the copper plating layer 203a covering the upper surface of the through electrode, partially removing the region by etching, etc., and then forming the plating layer 204a in which the Au plating layer is stacked on the Ni plating layer.

[0077] The semiconductor device of the second embodiment is also similar to the first embodiment, in that the through-electrode 13 is electrically connected to the first and second metal patterns 11 and 12 , and therefore the same effects as those of the first embodiment can be obtained.

[0078] In the semiconductor device of the second embodiment, similarly to the first embodiment, the groove 131 has an effect of causing the uncured first sealing resin 21 to stay at the ends of the first and second metal patterns 11 and 12 at the step between the groove 131 .

[0079] <<Implementation Method 3>>

[0080] use Figure 6 A semiconductor device according to a third embodiment will be described.

[0081] In the first embodiment, the depth of the groove 131 formed on the through electrode 13 by etching is controlled so that the width of the groove 131 is narrowed. However, in the present embodiment, Figure 6 As shown in (a) and (b), a groove is not formed but a resist layer 61 is arranged.

[0082] That is, in Figure 3 After the step (c), Figure 3 Before the step (d) of FIG. 1 , the resist layer 61 is disposed only in the region where the groove 131 is to be formed. Then, the process from Figure 3 The following steps are started from (d). Figure 6 As shown in (a) and (b) of FIG. 1 , the first and second metal patterns 11 and 12 separated by the resist layer 61 can be formed on the through-electrode 13 .

[0083] Figure 6 The structures of (a) and (b) do not require the control of the depth of the groove 131 required in the first embodiment, and have the advantage of being able to reduce the variation in the shape of the product.

[0084] In addition, Figure 6 In the structures of (a) and (b), a step corresponding to the thickness of the copper plating layer 203 a and the plating layer 204 a is formed on the outer periphery of the first metal pattern 11 , so that the wetting and spreading of the first sealing resin 21 on the first metal pattern 11 can also be stopped.

[0085] <<Implementation Method 4>>

[0086] use Figure 7 (a) and Figure 7 (b) illustrates the semiconductor device of embodiment 4.

[0087] The semiconductor device of the fourth embodiment can have the same structure as any one of the first to third embodiments except for the vicinity of the through-electrode 16 .

[0088] therefore, Figure 7 (a) and Figure 7 (b) shows only the vicinity of the through-electrode 16, omitting the structures on the left and right sides.

[0089] Figure 7 (a) is a diagram showing a stage in which a metal pattern for mounting a device (hereinafter referred to as a device mounting electrode) 15 is formed in the process of manufacturing the semiconductor device of the fourth embodiment. Figure 7(b) is a diagram showing a stage in which the substrate for mounting the semiconductor element 17 is completed.

[0090] The semiconductor device of Embodiment 4 can be applied in combination with any one of Embodiments 1 to 3.

[0091] The semiconductor device of the fourth embodiment has the structure including the first metal pattern 11 , the second metal pattern 12 , and the through electrode 13 (or 113 ) similarly to the semiconductor devices of the first to third embodiments.

[0092] That is, similar to Embodiments 1 to 3, the first metal pattern 11 and a portion of the second metal pattern 12 are arranged on the through electrode 13, and the plating layer 204a is provided to continuously cover the first metal pattern 11, the second metal pattern 12, and the through electrode 13. Therefore, a small semiconductor device can be provided in which the first metal pattern 11 and the second metal pattern 12 are arranged close to each other.

[0093] Furthermore, the semiconductor device of the fourth embodiment is configured such that the element mounting electrode 15 can be made smaller than the through-electrode 16 in a desired range, and accordingly, the through-electrode 16 can be made larger.

[0094] Furthermore, the semiconductor device of the fourth embodiment is configured such that when the semiconductor element 17 is fixed to the element mounting electrode 15 by the solder layer 172 , the range of wetting and spreading of the molten solder layer 172 can be controlled to be substantially equal to the bottom surface of the semiconductor element.

[0095] That is, it is a semiconductor device in which the semiconductor element 17 is mounted using the solder layer 172 (AuSn) on the element mounting electrode 15 (a pattern capable of self-alignment under the tension of AuSn) in which the through electrode 16 is larger than the semiconductor element 17 and has approximately the same size as the semiconductor element 17 .

[0096] At this time, the resist layer 71 is arranged so as to cover the region where the through electrode 16 is exposed from the element mounting electrode 15 and the boundary between the exposed region and the substrate 10 .

[0097] By adopting such a structure, the melted solder layer 172 does not wet and spread to the resist layer 71, so the semiconductor element 17 can be mounted accurately at the position of the element mounting electrode 15. In addition, the through electrode 16 larger than the semiconductor element 17 can be buried in the substrate 10. Therefore, the heat of the semiconductor element 17 can be well dissipated by the large through electrode 16.

[0098] Compare for example Figure 8In the comparative example, when the core (through electrode 16) is etched, the core (through electrode 16) may be penetrated due to excessive etching. In addition, in the substrate 10 using the core (through electrode 16), in order to accurately position the semiconductor element 17, the core (through electrode 16) is made smaller than the element, forming Figure 8 Therefore, efficient heat dissipation cannot be achieved.

[0099] In contrast, the fourth embodiment Figure 7 The structure can increase the size of the core (through electrode 16), thereby enabling good heat dissipation.

[0100] The semiconductor device of the fourth embodiment can be manufactured by Figure 3 After the process (c), Figure 3 Before the step (d), if Figure 7 The resist layer 71 is formed on the core (through electrode 16) as shown in the figure. In addition, the resist layer 71 can be formed at the same time as the resist layer 61 in the semiconductor device of the third embodiment. Then, the resist layer 71 is formed from the core (through electrode 16) in the same manner as the first embodiment. Figure 3 (d) The following process starts.

[0101] <<Implementation Method 5>>

[0102] use Fig. 9 (a) to (c) illustrate the semiconductor device of embodiment 5.

[0103] The semiconductor device of the fifth embodiment has a structure in which, when the semiconductor element 17 is fixed to the element mounting electrode 15 by the die bonding agent or the solder layer 172 , the range of wetting and spreading of the uncured die bonding agent or the molten solder layer 172 is controlled.

[0104] like Fig. 9 As shown in (a) to (b) of the present invention, the semiconductor device of the fifth embodiment includes a substrate 10 on which three semiconductor elements 17a, 17b, and 17c are mounted, and metal patterns 91, 92, and 93a to 93c formed on the substrate 10. The first metal pattern 91, the second metal pattern 92, and the third metal pattern 93 are separately arranged on the substrate 10. A through electrode 94 that penetrates the substrate 10 in the thickness direction is provided between the first metal pattern 91, the second metal pattern 92, and the third metal pattern 93. The third metal patterns 93a to 93c on which the semiconductor elements 17a to 17c are mounted are arranged on the through electrode 94.

[0105] Parts of the first metal pattern 91 , the second metal pattern 92 , and the third metal pattern 93 are in contact with the upper surface of the through-electrode 94 .

[0106] A continuous plating layer 95 is disposed on the first metal pattern 91 , the second metal pattern 92 , the third metal patterns 93 a to 93 c , and the through-electrode 94 . The first metal pattern 91 , the second metal pattern 92 , and the through-electrode 94 are electrically connected by the plating layer 95 .

[0107] A groove portion 96 adjacent to the first metal pattern 91 and a groove portion 97 adjacent to the second metal pattern 92 are arranged on the upper surface of the through-electrode 94 . The inner walls of the groove portions 96 and 97 are covered with a plating layer 95 .

[0108] Thus, when the semiconductor elements 17a to 17c are mounted on the plating layer 95 on the metal patterns 93a to 93c located between the grooves 96 and 97, even when a die bonding agent or a solder layer is used, the die bonding agent or the molten solder layer will stay due to the surface tension generated at the step between the grooves 96 and 97. Therefore, the die bonding agent or the molten solder layer will not flow onto the first and second metal patterns 91 and 92, and the first and second metal patterns 91 and 92 can be arranged close to the third metal patterns 93a to 93c.

[0109] For example, the substrate 10 may be formed of a glass epoxy substrate, the first metal pattern 91 and the second metal pattern 92 may be formed of a laminated structure of copper foil and copper plating, and the plating layer 95 may be formed of a laminated structure of Ni plating and Au plating.

[0110] Even when the semiconductor element 17a is mounted on the plating layer 95 on the third metal pattern 93a by die bonding agent or solder, the die bonding agent or solder does not reach the first metal pattern 91 and the third metal pattern 93b, so the first metal pattern 91 and the third metal pattern 93b are not contaminated by the die bonding agent or solder. Thus, the bonding of the bonding wire 84 that electrically connects the semiconductor element 17a and the first metal pattern 91 is not hindered.

[0111] In addition, even when the Zener diodes 81 and 82 are fixed to the first and second metal patterns 91 and 92 respectively by die bonding agent or solder layer, the uncured die bonding agent or melted solder layer in the process of fixing the Zener diodes 81 and 82 will stay at the edges of the first and second metal patterns 91 and 92 due to the steps formed by the grooves 96 and 97. Therefore, the semiconductor elements 17a to 17c and the Zener diodes 81 and 82 can be arranged close to each other. Thus, a small semiconductor device can be provided.

[0112] Furthermore, a back surface electrode 85 connected to the through-electrode 94 is disposed on the back surface of the substrate 10. A potential of the same polarity is supplied from the back surface electrode 85 through the through-electrode 94 to the metal patterns 91, 92, and 93a to 93c.

[0113] Furthermore, by forming the grooves 98a and 98b also between the semiconductor elements 17a, 17b, and 17c, the die bonding agent or molten solder layer of each element does not reach the adjacent element, so that the elements can be arranged close to each other.

[0114] In addition, one or more (here, three) metal patterns 99 as electrodes of opposite polarity to the metal patterns 91, 92, 93a to 93c may be arranged around the metal patterns 91, 92, 93a to 93c, and connected to the semiconductor elements 17a to 17c and the Zener diodes 81 and 82 via bonding wires 84. In this case, by providing a through electrode directly below the metal pattern 99 and supplying a potential to the metal pattern 99 from the back electrode 86 arranged on the back side of the substrate 10, the substrate 10 can be miniaturized.

[0115] In addition, if Fig. 9 As shown in (a), an auxiliary through-electrode 83 may be further arranged below the third metal pattern 93c.

[0116] In addition, the present embodiment Fig. 9 The semiconductor devices of (a) to (c) can be realized by Figure 3 and Figure 4 The same manufacturing process as the manufacturing process of Figure 3 In the step (e), the grooves 96, 97, 98a, and 98b may be formed to have an appropriate depth.

[0117] The semiconductor device according to each of the above-described embodiments can be used as an LED lighting device or the like.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes a substrate on which a semiconductor element is mounted, and a metal pattern formed on the substrate. The metal pattern includes: a first metal pattern and a second metal pattern which are separately provided on the substrate, and a through electrode which is arranged between the first metal pattern and the second metal pattern and penetrates the substrate in a thickness direction. The through electrode is arranged so as to straddle the first metal pattern and the second metal pattern. Parts of the first metal pattern and the second metal pattern are in contact with an upper surface of the through-electrode, and the first metal pattern, the second metal pattern, and the through-electrode are electrically connected.

2. The semiconductor device according to claim 1, wherein: A continuous plating layer is disposed on the first metal pattern, the second metal pattern, and the through-electrode, and the first metal pattern, the second metal pattern, and the through-electrode are electrically connected via the plating layer.

3. The semiconductor device according to claim 2, wherein: A groove is provided on the through electrode between the first metal pattern and the second metal pattern, and the plating layer also covers the inner wall of the groove.

4. The semiconductor device according to claim 3, wherein: The width of the groove is narrower than a distance between the first metal pattern and the second metal pattern in a region where the through electrode is not arranged.

5. The semiconductor device according to claim 1, wherein: A resist layer is formed on the through electrode between the first metal pattern and the second metal pattern.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that The first metal pattern is formed in a shape surrounding the semiconductor element. The second metal pattern is formed in a shape surrounding the first metal pattern.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further includes: a first sealing resin that seals a region on the substrate that is inside the outer periphery of the first metal pattern; and a second sealing resin that seals a region on the substrate that is inside the outer periphery of the second metal pattern.

8. The semiconductor device according to claim 2, wherein: The first metal pattern and the second metal pattern include a copper layer, and the plating layer covers the upper surface and the side surface of the copper layer.

9. A method for manufacturing a semiconductor device, characterized in that: The following processes are available: forming a metal layer on the entire surface of a substrate, the substrate having a through electrode penetrating in a thickness direction; The metal layer is etched into the shape of a first metal pattern and a second metal pattern separated by a predetermined width on the through electrode and both in contact with the through electrode, and a groove is formed at an upper portion of the through electrode below a gap between the separated first metal pattern and the second metal pattern; as well as Current is simultaneously supplied to the first metal pattern and the second metal pattern from the back side of the substrate through the through-electrode, and a plated layer covering the first metal pattern, the second metal pattern, and the inner wall of the groove is formed by electrolytic plating.

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