Solid-state imaging device and method for manufacturing the same

Abstract

[Problem] Provided are a solid-state imaging device having a pixel transistor and wiring, and a method of manufacturing the same. The solid-state imaging device can effectively output and transmit a pixel signal from a stacked photoelectric conversion film while suppressing an increase in manufacturing cost. [Solution] Provided is such a solid-state imaging device including: a semiconductor substrate; a first photoelectric conversion unit provided on the semiconductor substrate; and a control unit provided to be stacked with the first photoelectric conversion unit and including a plurality of pixel transistors for controlling the first photoelectric conversion unit. Among them, the first photoelectric conversion unit includes: a second electrode; a first photoelectric conversion film provided above the second electrode and configured to convert light into charges; and a first electrode provided on the first photoelectric conversion film. The plurality of pixel transistors include an amplification transistor that amplifies the charges and outputs the charges as a pixel signal, and a channel formation region of the amplification transistor is formed of an oxide semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and a method for manufacturing the same. Background Art

[0002] In recent years, in charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors (solid-state imaging devices), as the pixel size has decreased, the amount of light incident on a unit pixel has also decreased. As a result, the sensitivity has decreased and the signal-to-noise ratio (S / N) has decreased. In addition, in the above-described various image sensors, a configuration is generally used in which pixels that respectively detect red light, green light, and blue light using primary color filters are arranged on a plane (for example, a Bayer array). In the case of the above configuration, for example, in a pixel that detects red light, since green light and blue light hardly pass through the color filter included in the pixel, photoelectric conversion of green light and blue light is not performed in the pixel, that is, green light and blue light are not detected. Therefore, in the case of the above configuration, in each pixel, one specific color of light can be detected, and other colors of light cannot be detected. Therefore, it cannot be said that the light incident on each pixel is fully utilized. In other words, from the viewpoint of pixel sensitivity, a loss occurs.

[0003] As a method for solving the above situation, an image sensor can be shown in which three-layer photoelectric conversion films capable of performing photoelectric conversion of red light, green light, and blue light are stacked vertically in a unit pixel, and one unit pixel can detect three colors of light (for example, Patent Document 1 described below). In addition, as another image sensor capable of detecting three colors of light by one unit pixel, an image sensor can be shown that has: a silicon substrate on which two photodiodes (PDs) that respectively detect red light and blue light are stacked; and a photoelectric conversion film that is provided above the silicon substrate and can perform photoelectric conversion of green light (for example, Patent Document 2 described below).

[0004] Specifically, the construction of a circuit for extracting pixel signals in an image sensor is shown below. The image sensor has a silicon substrate with two PDs stacked thereon and a photoelectric conversion film disposed above the silicon substrate (which is disclosed in Patent Document 2 described below). For example, as disclosed in Patent Document 3 described below, a back-illuminated structure can be shown, in which a circuit formation layer on which the above circuit is formed is formed on the side opposite to the light-receiving surface (the side where incident light enters) of the image sensor. Further, as disclosed in Patent Document 4 described below, a structure can be shown in which, directly below the photoelectric conversion film disposed above the silicon substrate, a semiconductor layer for accumulating and transferring charges obtained through photoelectric conversion and a storage electrode facing the semiconductor layer are provided, and an insulating film is provided between the semiconductor layer and the storage electrode. Further, Patent Documents 5 and 6 disclose that channel formation regions of various pixel transistors included in the above circuit construction are formed of an oxide semiconductor layer.

[0005] Citation List

[0006] Patent Document

[0007] Patent Document 1: Japanese Patent Laid-Open No. 2005-51115

[0008] Patent Document 2: Japanese Patent Laid-Open No. 2003-332551

[0009] Patent Document 3: Japanese Patent Laid-Open No. 2011-29337

[0010] Patent Document 4: Japanese Patent Laid-Open No. 2017-157816

[0011] Patent Document 5: Japanese Patent Laid-Open No. 2009-105381

[0012] Patent Document 6: Japanese Patent Laid-Open No. 2009-267912

[0013] Patent Document 7: Japanese Patent Laid-Open No. 2009-535819 Summary of the Invention

[0014] Technical Problem

[0015] In the above-described image sensor (solid-state imaging device), in order to output the charge generated in the photoelectric conversion film provided above the substrate as a pixel signal, a plurality of pixel transistors (for example, an amplification transistor, a transfer transistor, a reset transistor, etc.) and wirings for connecting these pixel transistors are provided. In order to improve the characteristics of the image sensor and suppress an increase in manufacturing cost, it is necessary to provide pixel transistors and wirings having an appropriate structure at appropriate positions. However, in a conventional scheme, the appropriate structure and position of the pixel transistors and wirings have not been specifically examined. In addition, even if the structure and position of the pixel transistors are disclosed, it is difficult to say that the disclosure has an effective structure and arrangement capable of effectively outputting and transmitting pixel signals and capable of suppressing an increase in manufacturing cost.

[0016] Therefore, in view of the above circumstances, the present disclosure proposes a novel and improved solid-state imaging device having pixel transistors and wirings and a manufacturing method thereof, which can effectively output and transmit pixel signals while suppressing an increase in manufacturing cost.

[0017] Technical solutions for solving the problems

[0018] According to the present disclosure, there is provided such a solid-state imaging device, which includes: a semiconductor substrate; a first photoelectric conversion unit provided on the semiconductor substrate; and a control unit provided to be stacked with the first photoelectric conversion unit and including a plurality of pixel transistors for controlling the first photoelectric conversion unit, wherein the first photoelectric conversion unit includes: a second electrode; a first photoelectric conversion film provided above the second electrode and converting light into charge; and a first electrode provided on the first photoelectric conversion film, the plurality of pixel transistors include an amplification transistor that amplifies the charge and outputs the charge as a pixel signal, and a channel formation region of the amplification transistor is formed of an oxide semiconductor layer.

[0019] In addition, according to the present disclosure, there is provided a manufacturing method of a solid-state imaging device, which includes: forming an oxide semiconductor layer serving as a channel formation region of a pixel transistor above a semiconductor substrate; forming a gate electrode layer including a plurality of gate electrodes of a plurality of pixel transistors above the oxide semiconductor layer; forming a power signal wiring layer above the gate electrode layer, the power signal wiring layer including a plurality of power lines for applying a power supply voltage to the plurality of pixel transistors and a plurality of signal lines for transmitting pixel signals; forming a drive wiring layer above the power signal wiring layer, the drive wiring layer including a plurality of drive lines for driving the plurality of pixel transistors; forming a second electrode above the drive wiring layer; forming a first photoelectric conversion film above the second electrode; and forming a first electrode on the first photoelectric conversion film.

[0020] Advantages of the Present Invention

[0021] As described above, according to the present disclosure, a solid-state imaging device having pixel transistors and wirings and a method of manufacturing the same can be provided, which can effectively output and transmit pixel signals while suppressing an increase in manufacturing cost.

[0022] Note that the above effects are not necessarily restrictive, and any effects described in this specification or other effects obtained from this specification may be shown in addition to or instead of the above effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is an explanatory diagram showing an example of a planar structure of a solid-state imaging device 1 according to a first embodiment of the present disclosure.

[0024] Figure 2 is a schematic diagram of a planar structure of a solid-state imaging device 1 according to a first embodiment of the present disclosure.

[0025] Figure 3 is a cross-sectional view of the solid-state imaging device 1 taken along line A-A′ of Figure 2

[0026] Figure 4 is a cross-sectional view of the solid-state imaging device 1 taken along line B-B′ of Figure 2

[0027] Figure 5 is an equivalent circuit diagram of PD1 and PD2 according to a first embodiment of the present disclosure.

[0028] Figure 6 is an equivalent circuit diagram of PD3 according to a first embodiment of the present disclosure.

[0029] Figure 7 shows a part of a cross-sectional view of a pixel 100 according to a first embodiment of the present disclosure.

[0030] Figure 8 is a cross-sectional view of the pixel 100 taken along line a-a′ of Figure 7

[0031] Figure 9 is a cross-sectional view of the pixel 100 taken along line b-b′ of Figure 7

[0032] Figure 10 is a cross-sectional view of the pixel 100 taken along line c-c′ of Figure 7

[0033] Figure 11 is a cross-sectional view of the pixel 100 taken along line of Figure 7Cross-sectional view of pixel 100 taken along line d-d'.

[0034] Figure 12 It is a cross-sectional view (1) for explaining the manufacturing steps of pixel 100 according to the first embodiment of the present disclosure.

[0035] Figure 13 It is a cross-sectional view (2) for explaining the manufacturing steps of pixel 100 according to the first embodiment of the present disclosure.

[0036] Figure 14 It is a cross-sectional view (3) for explaining the manufacturing steps of pixel 100 according to the first embodiment of the present disclosure.

[0037] Figure 15 It shows a part of the cross-sectional view of pixel 100 according to the second embodiment of the present disclosure.

[0038] Figure 16 It is a cross-sectional view for explaining the manufacturing steps of pixel 100 according to the second embodiment of the present disclosure.

[0039] Figure 17 It is an explanatory diagram showing an example of an electronic device including an imaging device having a solid-state imaging device 1 according to an embodiment of the present disclosure.

[0040] Figure 18 It shows a part of the cross-sectional view of pixel 100 according to the fourth embodiment of the present disclosure.

[0041] Figure 19 It is along Figure 18 Cross-sectional view of pixel 100 taken along line f-f'.

[0042] Figure 20 It is along Figure 18 Cross-sectional view of pixel 100 taken along line e-e'.

[0043] Figure 21 It is along Figure 18 Cross-sectional view of pixel 100 taken along line b-b'.

[0044] Figure 22 It shows a part of the cross-sectional view of pixel 100 according to the first modification of the fourth embodiment of the present disclosure.

[0045] Figure 23 It shows a part of the cross-sectional view of pixel 100 according to the second modification of the fourth embodiment of the present disclosure.

[0046] Figure 24 It is a diagram showing an example of the schematic configuration of an endoscopic surgical system.

[0047] Figure 25It is a block diagram showing an example of the functional configuration of a camera and a CCU.

[0048] Figure 26 It is a block diagram showing an example of the schematic configuration of a vehicle control system.

[0049] Figure 27 It is an explanatory diagram showing an example of the installation positions of an out-of-vehicle information detection unit and a camera unit. Detailed Description of the Preferred Embodiments

[0050] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that, in this specification and the drawings, redundant descriptions of components having substantially the same functional configuration are omitted by assigning the same reference numerals.

[0051] In addition, in this specification and the drawings, a plurality of components having substantially the same or similar functional configurations may be distinguished from each other by adding different numbers after the same reference numeral. However, when it is not necessary to particularly distinguish each of the plurality of components having substantially the same or similar functional configurations, only the same reference numeral is assigned. In addition, similar components in different embodiments may be distinguished from each other by adding different letters after the same reference numeral. However, when it is not necessary to particularly distinguish each of the similar components, only the same reference numeral is assigned.

[0052] In addition, the accompanying drawings referred to in the following description are diagrams for making the description easier and for more easily understanding the embodiments of the present disclosure. For ease of understanding, the shapes, sizes, ratios, etc. shown in the drawings may be different from the actual situation. In addition, considering the following description and known technologies, the solid-state imaging device shown in the drawings can be appropriately changed in design. In addition, in the description of the cross-sectional view of the solid-state imaging device, the up-down direction of the stacked structure of the solid-state imaging device corresponds to the relative direction when the light incident surface of the solid-state imaging device faces upward, and may be different from the up-down direction according to the actual acceleration due to gravity.

[0053] In addition, in the following description, expressions regarding dimensions and shapes not only mean the same as the values defined mathematically and the values of the shapes defined geometrically, but also include cases where there are industrially acceptable differences in the manufacturing steps of the solid-state imaging device and in shapes similar to the shape.

[0054] In addition, in the following description of the circuit configuration, unless otherwise specified, "connected" means electrically connecting a plurality of elements. In addition, "connected" in the following description includes not only cases where a plurality of elements are directly electrically connected, but also cases where a plurality of elements are indirectly electrically connected through other elements.

[0055] Note that the description will be given in the following order.

[0056] 1. Background of the Embodiment of the Present Disclosure on the Inventor's Side

[0057] 2. First Embodiment

[0058] 2.1 Schematic Structure of the Solid-State Imaging Device

[0059] 2.2 Schematic Structure of the Pixel

[0060] 2.3 Equivalent Circuit of the Pixel

[0061] 2.4 Detailed Structure of the Multilayer Wiring Layer

[0062] 2.5 Manufacturing Method

[0063] 2.6 Modification Example

[0064] 3. Second Embodiment

[0065] 3.1 Detailed Structure of the Multilayer Wiring Layer

[0066] 3.2 Manufacturing Method

[0067] 4. Third Embodiment

[0068] 5. Fourth Embodiment

[0069] 5.1 Embodiment

[0070] 5.2 First Modification Example

[0071] 5.3 Second Modification Example

[0072] 6. Application of the Endoscopic Surgery System

[0073] 7. Application of the Moving Body

[0074] 8. Conclusion

[0075] 9. Supplementary

[0076] "1. Background of the Embodiment of the Present Disclosure on the Inventor's Side"

[0077] First, before explaining the details of each embodiment according to the present disclosure, the background of the embodiment of the present disclosure on the inventor's side will be explained.

[0078] As described above, in an image sensor, as the pixel size decreases, the amount of light incident on a unit pixel decreases, resulting in a decrease in sensitivity and a decrease in the S / N ratio. In addition, in an image sensor, for example, a configuration is generally used in which pixels that respectively detect red light, green light, and blue light using primary color filters are arranged in a Bayer array on a plane. In the case of the above configuration, in each pixel, light of a specific color can be detected, but light of other colors cannot be detected. Therefore, it can be said that since the light incident on each pixel is not fully utilized, a loss occurs from the viewpoint of pixel sensitivity. In addition, it is conceivable to perform interpolation processing to interpolate such a loss. However, when a color signal of a color that is not actually detected in a pixel is generated by interpolation processing, a color signal different from the actual color may be generated, that is, false colors may be generated.

[0079] Therefore, as a method for solving the above situation, an image sensor can be shown in which, in a unit pixel, three photoelectric conversion films capable of photoelectrically converting red light, green light, and blue light are stacked vertically, and one unit pixel can detect light of three colors (for example, the above-mentioned Patent Document 1). In addition, as another image sensor capable of detecting light of three colors by one unit pixel, an image sensor can be shown that has: a silicon substrate on which two PDs that respectively detect red light and blue light are stacked; and a photoelectric conversion film that is provided above the silicon substrate and can photoelectrically convert green light (for example, the above-mentioned Patent Document 2).

[0080] In addition, as described above, a circuit configuration for extracting a pixel signal in an image sensor is shown below. The image sensor has a silicon substrate on which two PDs are stacked and a photoelectric conversion film provided above the silicon substrate. For example, as disclosed in the above-mentioned Patent Document 3, a back-illuminated structure can be shown in which a circuit formation layer on which the above circuit is formed is formed on the side opposite to the light receiving surface of the image sensor. In the case of the above structure, no circuits, wirings, etc. are provided between the PDs in the silicon substrate and the photoelectric conversion film provided above the silicon substrate. Therefore, according to the above structure, the distance between the PD and the photoelectric conversion film in the same pixel in the stacking direction (vertical direction) can be shortened. As a result, in the above structure, the F value dependence of each color can be suppressed, and the sensitivity difference between each color can be reduced.

[0081] In addition, as disclosed in Patent Document 4 described above, a structure can be shown in which a semiconductor layer for accumulating and transporting charges obtained by photoelectric conversion and a storage electrode facing the semiconductor layer are provided directly below a photoelectric conversion film provided above a silicon substrate, and an insulating film is provided between the semiconductor layer and the storage electrode. In the above structure, the charges generated by the photoelectric conversion of the photoelectric conversion film can be effectively stored in the photoelectric conversion film like a capacitor. In addition, in the above structure, since the charges can be stored in the photoelectric conversion film, at the start of exposure, the charge storage unit (floating diffusion unit) provided in the silicon substrate can be completely depleted and the charges can be erased. As a result, according to the above structure, the occurrence of the following phenomena can be suppressed: the kTC noise (noise caused by the thermal fluctuation of charges) increases due to the charges in the charge storage unit, the random noise deteriorates, and the image quality of the image captured by the image sensor decreases.

[0082] In addition, in the above various image sensors (solid-state imaging elements), in order to output the charges generated in the photoelectric conversion film provided above the substrate as pixel signals, a plurality of pixel transistors and wirings for connecting the pixel transistors are provided. In order to improve the characteristics of the image sensor and suppress the increase in manufacturing cost, pixel transistors and wirings having an appropriate structure must be arranged at appropriate positions.

[0083] However, in the conventional solutions, the appropriate structures and positions of the pixel transistors and wirings have not been specifically examined. In addition, even if the structures and positions of the pixel transistors are disclosed, it is difficult to say that the disclosure has an effective structure and arrangement capable of effectively outputting and transporting pixel signals and capable of suppressing the increase in manufacturing cost.

[0084] Therefore, in view of the above situation, the inventors have created embodiments related to solid-state imaging elements having pixel transistors and wirings, which can effectively output and transport pixel signals by the charges generated in the photoelectric conversion film provided above the substrate while suppressing the increase in manufacturing cost. The details of the embodiments according to the present disclosure will be described sequentially below.

[0085] 《2. First Embodiment》

[0086] <2.1 Schematic Structure of Solid-State Imaging Device>

[0087] First, reference will be made to Figure 1 describe the schematic structure of the solid-state imaging device 1 according to the first embodiment of the present disclosure. Figure 1 is an explanatory diagram showing an example of the planar structure of the solid-state imaging device 1 according to the present embodiment. As Figure 1As shown, the solid-state imaging device 1 according to the present embodiment has: a pixel array unit 10 in which a plurality of pixels (solid-state imaging elements) 100 are arranged in a matrix form on a semiconductor substrate 300 made of, for example, silicon; and a peripheral circuit unit 80 provided to surround the pixel array unit 10. Further, as the peripheral circuit unit 80, the solid-state imaging device 1 includes a vertical drive circuit unit 32, a column signal processing circuit unit 34, a horizontal drive circuit unit 36, an output circuit unit 38, a control circuit unit 40, and the like. Hereinafter, details of each block of the solid-state imaging device 1 according to the present embodiment will be described.

[0088] (Pixel Array Unit 10)

[0089] The pixel array unit 10 has a plurality of pixels 100, and the plurality of pixels 100 are two-dimensionally arranged in a matrix form on the semiconductor substrate 300. The plurality of pixels 100 include: normal pixels for generating pixel signals for image generation; and a pair of phase difference detection pixels for generating pixel signals for focus detection. Here, the pixel 100 refers to a solid-state imaging element (unit pixel), and when detecting light of each color and outputting a detection result, the solid-state imaging element can be regarded as a unit that outputs one result for each color. Each pixel 100 has a plurality of photoelectric conversion elements and a plurality of pixel transistors (e.g., metal-oxide-semiconductor (MOS) transistors) (not shown). More specifically, for example, the pixel transistors can include transfer transistors, selection transistors, reset transistors, and amplification transistors. Note that details of the circuit (connection configuration) using these pixel transistors will be described later.

[0090] (Vertical Drive Circuit Unit 32)

[0091] The vertical drive circuit unit 32 includes a shift register. For example, the vertical drive circuit unit 32 selects a pixel drive line 42, supplies a pulse for driving the pixel 100 to the selected pixel drive line 42, and drives the pixel 100 in units of rows. That is, the vertical drive circuit unit 32 sequentially and selectively scans each pixel 100 of the pixel array unit 10 in the vertical direction ( Figure 1 the up-and-down direction in) and supplies a pixel signal based on charges generated according to the amount of light received by the photoelectric conversion elements of the respective pixels 100 to the column signal processing circuit unit 34 through a vertical signal line 44. The column signal processing circuit unit 34 will be described later.

[0092] (Column Signal Processing Circuit Unit 34)

[0093] For each column of pixels 100, a column signal processing circuit unit 34 is provided, and the column signal processing circuit unit 34 performs signal processing on the pixel signals output from one row of pixels 100 (such as noise removal for each pixel column). For example, the column signal processing circuit unit 34 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion to remove fixed pattern noise specific to the pixels.

[0094] (Horizontal drive circuit unit 36)

[0095] The horizontal drive circuit unit 36 includes a shift register. For example, the horizontal drive circuit unit 36 sequentially outputs horizontal scan pulses to sequentially select each of the above column signal processing circuit units 34, and outputs the pixel signals of each column signal processing circuit unit 34 to the horizontal signal line 46.

[0096] (Output circuit unit 38)

[0097] The output circuit unit 38 can perform signal processing on the pixel signals sequentially provided from each of the above column signal processing circuit units 34 through the horizontal signal line 46, and can output signals. The output circuit unit 38 can be used as, for example, a functional unit that performs buffering, or can perform processes such as black level adjustment, column change correction, and various digital signal processes. Note that buffering means temporarily storing pixel signals to compensate for the difference in processing speed and transmission speed when exchanging pixel signals. In addition, the input / output terminal 48 is a terminal for exchanging signals with an external device.

[0098] (Control circuit unit 40)

[0099] The control circuit unit 40 can receive an input clock and data for giving instructions regarding an operation mode, etc., and can output data such as internal information of the pixels 100. That is, the control circuit unit 40 generates a clock signal and a control signal that serve as a reference for the operations of the vertical drive circuit unit 32, the column signal processing circuit unit 34, or the horizontal drive circuit unit 36, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock. Then, the control circuit unit 40 outputs the generated clock signal and control signal to the vertical drive circuit unit 32, the column signal processing circuit unit 34, or the horizontal drive circuit unit 36, etc.

[0100] Note that the planar configuration example of the solid-state imaging device 1 according to the present embodiment is not limited to Figure 1 the example shown, and may include, for example, another circuit unit, etc., and is not particularly limited.

[0101] <Schematic configuration of 2.2 pixels>

[0102] The schematic configuration of the solid-state imaging device 1 according to the present embodiment has been described above. Next, with reference to Figures 2 to 4 the schematic stacked configuration of the pixel 100 according to the present embodiment will be described. Figure 2 is a schematic diagram schematically showing the planar configuration of the solid-state imaging device 1 according to the present embodiment. In addition, Figure 3 is Figure 2 a cross-sectional view of the solid-state imaging device 1 taken along line A-A' of Figure 4 is Figure 2 a cross-sectional view of the solid-state imaging device 1 taken along line B-B' of Figure 3 and Figure 4 In, for easy understanding, the stacked structure of the multilayer wiring layer 120 and the like is shown in a simplified manner.

[0103] Note that in the following first embodiment, unless otherwise specified, according to Figure 3 , Figure 4 and Figure 7 the positions in the stacked structure of the pixel 100 shown in define the upper electrodes (first electrodes) 110 and 210 and the lower electrodes (second electrodes) 116 and 216 of PD1 and PD2. However, in the second embodiment, the upper electrodes 110 and 210 and the lower electrodes 116 and 216 of PD1 and PD2 are not defined according to the positions in the stacked structure of the pixel 100 shown in Figure 15 The electrodes having the same functions as the upper electrodes 110 and 210 in the first embodiment are referred to as the upper electrodes 110 and 210, and the electrodes having the same functions as the lower electrodes 116 and 216 in the first embodiment are referred to as the lower electrodes 116 and 216.

[0104] As Figure 2 shown, as described above, the solid-state imaging device 1 according to the present embodiment has a pixel array unit 10 in which a plurality of pixels 100 arranged in the center are arranged in a matrix. In addition, the solid-state imaging device 1 has: a pixel transistor region 70 in which a part (not shown) of the corresponding pixel transistor of each pixel 100 is arranged to surround the pixel array unit 10; and a peripheral circuit unit 80 provided in the peripheral part of the pixel transistor region 70. In particular, Figure 3 corresponds to a cross-sectional view when the solid-state imaging device 1 is cut along line A-A' of Figure 2 , that is, a cross-sectional view when the solid-state imaging device 1 is cut so as to straddle the pixel array unit 10 and the pixel transistor region 70. In addition, Figure 4 corresponds to a cross-sectional view when the solid-state imaging device 1 is cut along line B-B' of Figure 2 , that is, a cross-sectional view when the pixel array unit 10 is cut. In addition,Figure 4 A cross-section of two pixels 100 two-dimensionally arranged on a plane of a semiconductor substrate 300 is shown.

[0105] In the following description, the stacked structure of the pixel 100 will be described in the order from the semiconductor substrate 300 located below the pixel 100 to the photoelectric conversion elements (PDs) 2 and PD1 located above the semiconductor substrate 300. In other words, in the following description, it will be described in the order from Figure 3 and Figure 4 the semiconductor substrate 300 shown on the lower side to the PD2 and PD1 shown on the upper side of the pixel 100.

[0106] Specifically, as Figure 3 and Figure 4 shown, in the pixel 100 (or pixels 100a and 100b), a semiconductor region 312a of a second conductivity type (e.g., N-type) is provided in a semiconductor region of a first conductivity type (e.g., P-type) of the semiconductor substrate 300 made of, for example, silicon. The photoelectric conversion element (PD) 3 (second photoelectric conversion unit) is formed by a PN junction of the semiconductor region 312a and a semiconductor region 312b of a first conductivity type (e.g., P-type) located directly below the semiconductor region 312a. Note that, in the present embodiment, PD3 is, for example, a photoelectric conversion element that absorbs red light (e.g., light having a wavelength of 620 nm to 750 nm) and generates charges.

[0107] In addition, on the side of the semiconductor substrate 300 opposite to the semiconductor region 312a (in other words, the opposite side of the light-receiving surface) ( Figure 3 and Figure 4 the lower side in), a wiring layer including wirings 306 formed of, for example, tungsten (W), aluminum (Al), or copper (Cu) is provided. In the wiring layer, a plurality of electrodes 310 formed of W, Al, or Cu or the like are provided as gate electrodes of a plurality of pixel transistors to read the charges generated by the above PD3. Specifically, the electrodes 310 are provided to face a semiconductor region of a first conductivity type (e.g., P-type) in the semiconductor substrate 300, and an insulating film 324 is provided between the electrodes 310 and the semiconductor region of a first conductivity type (e.g., P-type). In addition, in the semiconductor substrate 300, a semiconductor region 322a of a second conductivity type (e.g., N-type) is provided to sandwich the semiconductor region of the first conductivity type therebetween, and the semiconductor region 322a can be used as a source / drain region of the pixel transistor.

[0108] In addition, as Figure 3 and Figure 4As shown, in the semiconductor substrate 300, the through electrode 302 is provided to penetrate the semiconductor substrate 300, and the through electrode 302 is used to extract the charges generated in the photoelectric conversion films 112 and 212 described later to the wiring 306. Note that Figure 3 and Figure 4 The through electrode 302 for extracting the charges generated in the photoelectric conversion film 212 is shown. On the other hand, for example, a through electrode (not shown) for extracting the charges generated in the photoelectric conversion film 212 can be provided around the pixel array unit 10 in the same manner as the through electrode 302.

[0109] In addition, an insulating film 218 made of an alumina film (Al2O3) or the like is formed on the outer periphery of the through electrode 302 to prevent a short circuit between the through electrode 302 and the semiconductor substrate 300. The insulating film 218 preferably has a low interface state in order to reduce the interface state between the semiconductor substrate 300 and the insulating film 218 and suppress the generation of dark current from the interface between the semiconductor substrate 300 and the insulating film 218. As an example of the insulating film 218, in addition to the alumina film, a silicon oxide (SiO2) film, a silicon nitride (Si3N4) film, a silicon oxynitride (SiON) film, a silicon carbide (SiC) film, or a silicon oxide added with carbon (SiCO) film, etc. can also be used, and there is no particular limitation on the insulating film 218. Examples of the method for forming these films can include: chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, and atomic layer deposition (ALD) method, etc. However, in this embodiment, there is no particular limitation on the material and method for forming the insulating film 218.

[0110] In addition, the through electrode 302 can be connected to the floating diffusion unit 322b or the electrode 310 through the wiring 306 provided in the above wiring layer, and the electrode 310 is provided in the semiconductor region of the second conductivity type (for example, N-type) provided in the semiconductor substrate 300. The floating diffusion unit 322b is a region for temporarily storing the charges generated in the photoelectric conversion films 112 and 212. In addition, in the semiconductor substrate 300, the isolation insulating film 320 can be provided adjacent to the floating diffusion unit 322b or the source / drain region 322a of each pixel transistor.

[0111] Then, as Figure 3 and Figure 4 shown, an insulating film 218 made of, for example, an Al2O3 film and capable of transmitting light is provided on the semiconductor substrate 300. Since the insulating film 218 can transmit light, the PD3 provided below the insulating film 218 can receive light and can perform photoelectric conversion, that is, can detect light.

[0112] In addition, a wiring 250 is provided in the insulating film 218. The wiring 250 is electrically connected to the through electrode 302 and serves as a light-shielding film. For the wiring 250, for example, a laminated film of W and titanium (Ti) film and titanium nitride (TiN) film as a barrier metal can be used. However, in this embodiment, there is no particular limitation on the material constituting the wiring 250.

[0113] Above the insulating film 218, a photoelectric conversion film (third photoelectric conversion film) 212 is provided. The photoelectric conversion film 212 is sandwiched between the upper electrode 210 and the lower electrode 216. In addition, the photoelectric conversion film 212, the upper electrode 210, and the lower electrode 216 can form a PD2 (third photoelectric conversion unit). In this embodiment, the PD2 is, for example, a photoelectric conversion element that absorbs green light (for example, light with a wavelength of 495 nm to 570 nm) and generates charges (photoelectric conversion).

[0114] Note that the upper electrode 210 and the lower electrode 216 can be made of a transparent conductive film capable of transmitting light, such as indium tin oxide (ITO, including crystalline ITO and amorphous ITO) film. However, in this embodiment, the materials constituting the upper electrode 210 and the lower electrode 216 are not limited to the above-mentioned ITO, and other materials can be used. For example, the transparent conductive film is preferably made of a material having a bandgap of 2.5 eV or more (preferably 3.1 eV or more). For example, as the transparent conductive film, among tin oxide-based materials, tin oxide, antimony tin oxide (Sb is added as a dopant to SnO2, for example, ATO), or fluorine tin oxide (F is added as a dopant to SnO2, for example, FTO) can be shown. Among zinc oxide-based materials, examples include aluminum zinc oxide (Al is added as a dopant to ZnO, for example, AZO), gallium zinc oxide (Ga is added as a dopant to ZnO, for example, GZO), indium zinc oxide (In is added as a dopant to ZnO, for example, IZO), indium gallium zinc oxide (In and Ga are added as dopants to ZnO, for example, IGZO), or indium tin zinc oxide (In and Sn are added as dopants to ZnO, for example, ITZO). In addition, examples include indium gallium oxide (In is added as a dopant to Ga2O3, for example, IGO), CuInO2, MgIn2O4, CuI, InSbO4, ZnMgO, CdO, or ZnSnO3. In addition, the details of the material of the photoelectric conversion film 212 will be described later.

[0115] In addition, for example, Figure 3The wiring 206 connected to the upper electrode 210 shown can also be used as a light-shielding film and can be made of materials such as W, Ti, TiN, Al, or Cu. Note that in this embodiment, the material of the wiring 206 is not limited to this, and the wiring 206 can be made of other materials.

[0116] In addition, as Figure 3 and Figure 4 shown, in order to temporarily accumulate the charges generated by the photoelectric conversion film 212 in the photoelectric conversion film 212, the PD2 has storage electrodes 214 (214a and 214b) facing the upper electrode 210, and the photoelectric conversion film 212 is inserted between the storage electrode 214 and the upper electrode 210. Specifically, the storage electrode 214 is in contact with the photoelectric conversion film 212 via the insulating film 218 or via the insulating film 218 and a semiconductor layer (not shown), and the insulating film 218 or the insulating film 218 and the semiconductor layer (not shown) is interposed between the storage electrode 214 and the photoelectric conversion film 212.

[0117] The wirings 206 and 250 are electrically connected to the upper electrode 210, the lower electrode 216, and the storage electrode 214, and by using these wirings 206 and 250, a desired potential is applied to the upper electrode 210, the lower electrode 216, and the storage electrode 214. In addition, the lower electrode 216 is connected to a floating diffusion unit 322b provided in the semiconductor substrate 300 via a through electrode 302. In this embodiment, by controlling the potentials applied to the lower electrode 216 and the storage electrode 214, the charges generated by the photoelectric conversion film 212 can be stored in the photoelectric conversion film 212, or these charges can be extracted to the floating diffusion unit 322b. In other words, the storage electrode 214 can be used as a charge storage electrode for attracting the charges generated by the photoelectric conversion film 212 according to the applied potential and storing the charges in the photoelectric conversion film 212. Note that in this embodiment, in order to effectively utilize the light incident on the pixel 100, preferably, the storage electrode 214 is arranged such that when viewed from above the light receiving surface, the area of the storage electrode 214 is larger than the area of the lower electrode 216.

[0118] Note that in this embodiment, in order to store charges more effectively, an oxide semiconductor layer 240 capable of transmitting light can be provided between the insulating film 218 and the photoelectric conversion film 212 (refer to Figure 7)。In this embodiment, as the material of the oxide semiconductor layer 240, for example, among tin oxide-based materials, it can be exemplified by SnO2 (dopant added) and tin oxide added with dopants such as zinc tin oxide, and among zinc oxide-based materials, it can be exemplified by aluminum zinc oxide (e.g., AZO), gallium zinc oxide (e.g., GZO), indium zinc oxide (e.g., IZO), IGZO, and ITZO, etc. In addition, as the material of the oxide semiconductor layer 240, for example, it can be exemplified by InSbO4, ZnMgO, CuInO2, MgIn2O4, CdO, GeO, and TiO2, etc.

[0119] In addition, an electrode (not shown) can be provided between the lower electrode 216 and the storage electrode 214, and this electrode is in contact with the oxide semiconductor layer 240 through an insulating film interposed between the electrode and the oxide semiconductor layer 240 (refer to Figure 7 ), and is electrically insulated from the lower electrode 216 and the storage electrode 214. The above electrode can be used as the gate electrode of a pixel transistor (specifically, a transfer transistor) including the oxide semiconductor layer 240 as a channel formation region.

[0120] Similar to the above upper electrode 210 and lower electrode 216, the storage electrode 214 is made of a transparent conductive film. As described above, in this embodiment, by forming the upper electrode 210, the lower electrode 216, and the storage electrode 214 using a transparent conductive film, it is also possible to detect light incident on the pixel 100 through PD3. Note that the film thickness of the upper electrode 210, the lower electrode 216, and the storage electrode 214 is 5 nm to 200 nm, and preferably about 30 nm to 100 nm.

[0121] In addition, an insulating film 218 is provided between the lower electrode 216 and the storage electrode 214 and between the photoelectric conversion film 212 and the storage electrode 214 to electrically insulate them. Note that the insulating film 218 can be a film having fixed charges, and the polarity of the fixed charges is the same as the polarity of the charges generated by the photoelectric conversion film 212.

[0122] In addition, a multilayer wiring layer (control unit) 120 is provided above the upper electrode 210, and a sealing film 204 is interposed between the upper electrode 210 and the multilayer wiring layer 120. Note that in this embodiment, examples of the material of the sealing film 204 can include Al2O3, etc. that can transmit light. As the material of the sealing film 204, in addition to Al2O3, SiO2, Si3N4, SiON, SiC, or SiCO, etc. can also be used, and there is no particular limitation on this material. Details of the multilayer wiring layer 120 will be described later.

[0123] In addition, similar to the above-mentioned PD2, a PD1 (first photoelectric conversion unit) is provided above the multilayer wiring layer 120, and a sealing film 204 or an insulating film or the like is inserted therebetween. The PD1 is, for example, a photoelectric conversion element that absorbs blue light (for example, light with a wavelength of 425 nm to 495 nm) and generates charges (photoelectric conversion). Since the stacked structure of the PD1 is the same as that of the above-mentioned PD2, its detailed description is omitted here. That is, the lower electrode 116, the storage electrode 114, the insulating film 118, the photoelectric conversion film (first photoelectric conversion film) 112, and the upper electrode 110 are stacked in this order as the PD1 above the sealing film 204.

[0124] The above-mentioned photoelectric conversion films 112 and 212 can be composed of an organic material (organic photoelectric conversion film) or an inorganic material (inorganic photoelectric conversion film). For example, when the photoelectric conversion film is composed of an organic material, one mode can be selected from the following four modes: (a) a P-type organic semiconductor material, (b) an N-type organic semiconductor material, (c) a stacked structure of at least two of a P-type organic semiconductor material layer, an N-type organic semiconductor material layer, and a mixed layer (bulk heterostructure) of a P-type organic semiconductor material and an N-type organic semiconductor material, and (d) a mixed layer of a P-type organic semiconductor material and an N-type organic semiconductor material. Note that the photoelectric conversion film using an organic material also includes the following stacked structure: an electron blocking film / buffer film, a photoelectric conversion film, a hole blocking film, a hole blocking / buffer film, and a work function adjusting film are stacked on the lower electrode.

[0125] Specifically, examples of the P-type organic semiconductor material can include: naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, pentacene derivatives, quinacridone derivatives, coumarin derivatives, pyrromethene derivatives, pyran derivatives, benzoxazolone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothiophene benzothiophene (BTBT) derivatives, dinaphthothiophenothiophene (DNTT) derivatives, dianthrathiophenothiophene (DATT) derivatives, benzo dibenzothiophene (BBBT) derivatives, naphthalene bisbenzothiophene (NBBT), thiopheno dibenzothiophene (TBBT) derivatives, dibenzothiophene dibenzothiophene (DBTBT) derivatives, dithienobenzo dibenzothiophene (DTBDT) derivatives, dibenzothiophene dithiophene (DBTDT) derivatives, benzodithiophene (BDT) derivatives, naphthalene dithiophene (NDT) derivatives, anthracene dithiophene (ADT) derivatives, tetracene benzodithiophene (TDT) derivatives, pentacene benzodithiophene (PDT) derivatives, triallylamine derivatives, carbazole derivatives, picene derivatives, Derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrazine derivatives, metal complexes having heterocyclic compounds as ligands, polythiophene derivatives, polybenzothiadiazole derivatives, polyfluorene derivatives, etc.

[0126] In addition, examples of N-type organic semiconductor materials can include: fullerenes and fullerene derivatives (e.g., fullerenes such as C60, C70, and C74 (higher fullerenes, endohedral fullerenes, etc.) or fullerene derivatives (e.g., fullerene fluorides, or phenyl-C61-butyric acid isomethyl ester (PCBM) fullerene compounds, fullerene polymers, etc.), organic semiconductors having a highest occupied molecular orbital (HOMO) and a lowest unoccupied molecular orbital (LUMO) deeper than those of p-type organic semiconductors, and inorganic metal oxides capable of transmitting light. More specifically, examples of N-type organic semiconductor materials can include heterocyclic compounds containing nitrogen atoms, oxygen atoms, and sulfur atoms, e.g., organic molecules including: pyridine derivatives, pyrromethene derivatives, pyrazine derivatives, pyrimidine derivatives, triazine derivatives, quinoline derivatives, quinoxaline derivatives, isoquinoline derivatives, coumarin derivatives, pyran derivatives, phenoxazinone derivatives, perylene derivatives, acridine derivatives, phenazine derivatives, phenanthroline derivatives, tetrazole derivatives, pyrazole derivatives, imidazole derivatives, thiazole derivatives, oxazole derivatives, imidazole derivatives, benzimidazole derivatives, benzotriazole derivatives, benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, subporphyrazine derivatives, poly(phenylene vinylene) derivatives, polybenzothiadiazole derivatives, polyfluorene derivatives, etc., organometallic complexes, and subphthalocyanine derivatives. In addition, examples of groups contained in fullerene derivatives can include: branched or cycloalkyl or phenyl groups; groups having linear or fused-ring aromatic compounds; groups having halides; partial fluoroalkyl groups; perfluoroalkyl groups; silylalkyl groups; silylalkoxy groups; arylsilyl groups; arylthioalkyl groups; alkylthioalkyl groups; arylsulfonyl groups; alkylsulfonyl groups; arylthio groups; alkylthio groups; amino groups; alkylamino groups; arylamino groups; hydroxyl groups; alkoxy groups; acylamino groups; acyloxy groups; carbonyl groups; carboxyl groups; carboxylamide groups; carbalkoxy groups; acyl groups; sulfonyl groups; cyano groups; nitro groups; groups having chalcogenides; phosphine groups; phosphon groups; and their derivatives. Note that the film thickness of the photoelectric conversion film made of an organic material is not limited, but the above thickness can be, for example, 1×10 -8 m to 5×10 -7 m, preferably, 2.5×10 -8 m to 3×10 -7 m, more preferably, 2.5×10 -8 m to 2×10 -7m. Further, in the above description, the organic semiconductor materials are classified into P-type and N-type. Among them, P-type means easy to transport holes, and N-type means easy to transport electrons. That is, in the organic semiconductor materials, different from the case of inorganic semiconductor materials, the above types are not limited to the explanation of having holes or electrons as the majority carriers of thermal excitation.

[0127] Further, when the photoelectric conversion films 112 and 212 are made of inorganic materials, examples of the inorganic semiconductor materials can include: crystalline silicon; amorphous silicon; microcrystalline silicon; crystalline selenium; amorphous selenium; chalcopyrite compounds such as CIGS (CuInGaSe), CIS (CuInSe2), CuInS2, CuAlS2, CuAlSe2, CuGaS2, CuGaSe2, AgAlS2, AgAlSe2, AgInS2 and AgInSe2; or group III-V compounds such as GaAs, InP, AlGaAs, InGaP, AlGaInP and InGaAsP; and compound semiconductors such as CdSe, CdS, In2Se3, In2S3, Bi2Se3, Bi2S3, ZnSe, ZnS, PbSe and PbS. Additionally, in this embodiment, quantum dots composed of these materials can be used as the photoelectric conversion films 112 and 212.

[0128] Further, the photoelectric conversion films 112 and 212 can be composed of polymers such as phenylene vinylene, fluorene, carbazole, indole, pyrene, pyrrole, methylpyridine, thiophene, acetylene and diacetylene or their derivatives.

[0129] Further, in order to detect blue light and green light, in the photoelectric conversion films 112 and 212, for example, preferably, the following can be used: metal complex dyes; rhodamine dyes; cyanine dyes; merocyanine dyes; phenylxanthene dyes; triphenylmethane dyes; rhodacyanine dyes; xanthene dyes; macrocyclic azaannulene dyes; azo dyes; naphthoquinone; anthraquinone dyes; condensed polycyclic aromatic compounds such as anthracene and pyrene and chain compounds condensed with aromatic or heterocyclic compounds; two nitrogen-containing heterocycles such as quinoline, benzothiazole and benzoxazole, which have a squarylium group and a croconitcoumethine group as binding chains; or cyanine dyes bonded through a squarylium group and a croconitumethine group. Further, among the above metal complex dyes, dithiol metal complex dyes, metal phthalocyanine dyes, metal porphyrin dyes or ruthenium complex dyes are preferred, and ruthenium complex dyes are particularly preferred. However, the present disclosure is not limited thereto.

[0130] In addition, when the photoelectric conversion films 112 and 212 are used as the photoelectric conversion films for detecting red light, the photoelectric conversion films can contain phthalocyanine dyes and subphthalocyanine dyes (subphthalocyanine derivatives), etc.

[0131] In addition, as Figure 3 and Figure 4 shown, for example, similar to the sealing film 204, a sealing film 104 made of SiN or the like is provided above the PD1. Examples of the material of the sealing film 104 can include Al2O3, etc., and the Al2O3 can transmit light. In addition to Al2O3, as the material of the sealing film 104, SiO2, Si3N4, SiON, SiC, or SiCO, etc. can also be used, and there is no particular limitation on this material. In addition, as Figure 3 and Figure 4 shown, a high refractive index layer (not shown) made of an inorganic film such as a silicon nitride film, a silicon oxynitride film, or a silicon carbide (SiC) film is provided on the sealing film 104. In addition, for each pixel 100, an on-chip lens 102 (102a and 102b) is provided on the high refractive index layer. The on-chip lens 102 can be composed of, for example, a silicon nitride film or a resin material (e.g., styrene resin, acrylic resin, styrene-acrylic copolymer, or silicone resin).

[0132] As described above, the pixel 100 included in the solid-state imaging device 1 according to the embodiment of the present disclosure has a stacked structure in which PD1, PD2, and PD3 that respectively detect light of three colors are stacked. That is, it can be said that the above pixel 100 is a vertical spectral type solid-state imaging element, which performs photoelectric conversion on blue light through the photoelectric conversion film 112 (PD1) formed above the semiconductor substrate 300, performs photoelectric conversion on green light through the photoelectric conversion film 212 (PD2) provided below the PD1, and performs photoelectric conversion on red light through the PD3 provided in the semiconductor substrate 300.

[0133] Note that in the embodiment of the present disclosure, the pixel 100 is not limited to the above vertical spectral type stacked structure. For example, the photoelectric conversion film 112 (PD1) provided above the semiconductor substrate 300 can perform photoelectric conversion on green light, and the photoelectric conversion film 212 (PD2) provided below the PD1 can perform photoelectric conversion on blue light. The pixel 100 can further have a photoelectric conversion film for detecting infrared rays. In addition, in the embodiment of the present disclosure, the above pixel 100 can have a structure in which PD1 having the photoelectric conversion film 112 provided above the semiconductor substrate 300 and PD2 and PD3 provided in the semiconductor substrate 300 are stacked. That is, the pixel 100 according to the present embodiment can have a structure in which PD2 and PD3 are stacked in the semiconductor substrate 300.

[0134] <Equivalent circuit of 2.3 pixels>

[0135] The schematic stacked structure of pixel 100 according to this embodiment has been described above. Next, before describing the detailed structure of the multi-layer wiring layer 120 included in the stacked structure of pixel 100, in order to facilitate understanding of the circuit structure included in the multi-layer wiring layer 120, reference will be made to Figure 5 and Figure 6 to describe the equivalent circuits of PD1, PD2, and PD3 included in pixel 100. Figure 5 is the equivalent circuit diagram of PD1 and PD2 according to this embodiment, Figure 6 is the equivalent circuit diagram of PD3 according to this embodiment.

[0136] PD1 and PD2 have Figure 5 the stacked structure shown in the upper left. Specifically, PD1 and PD2 have an upper electrode 110(210), a lower electrode 116(216), and a photoelectric conversion film 112(212) sandwiched between the upper electrode 110(210) and the lower electrode 116(216). In addition, PD1 and PD2 have storage electrodes 114a and 114b(214a and 214b) that are in contact with the photoelectric conversion film 112(212) via an insulating film 118(218), and this insulating film 118(218) is between the storage electrodes 114a and 114b(214a and 214b) and the photoelectric conversion film 112(212). Note that as Figure 5 shown, when looking at pixel 100 from above the light receiving surface, the storage electrodes 114a and 114b(214a and 214b) are arranged to be line-symmetrical with respect to the lower electrode 116 therebetween. Details of the planar structure of the storage electrode 114(214) will be described later. In addition, in the following description, the equivalent circuit of PD1 included in pixel 100 will be described, but the equivalent circuit of PD2 is the same as that of PD1.

[0137] As Figure 5 shown, the lower electrode 116 is electrically connected via wiring to pixel transistors (amplification transistor Tr Figure 7 ), selection transistor TR amp , and reset transistor TR sel and reset transistor TR rst ) provided in the multi-layer wiring layer 120 and the oxide semiconductor layer 142 (refer to rst ). Specifically, the lower electrode 116 is electrically connected via wiring or the like to one of the drain / source of the reset transistor TR rstThe gate of is electrically connected to a reset signal line (not shown), and is further electrically connected to the above-described vertical drive circuit unit 32. Further, the reset transistor TR rst The other of the drain / source (the side not connected to the lower electrode 116) is electrically connected to the power supply circuit V DD .

[0138] Further, the lower electrode 116 is electrically connected to the gate of the amplifying transistor TR amp The amplifying transistor TR amp amplifies (converts) the charge and outputs a pixel signal. Further, one of the source / drain of the amplifying transistor Tr amp is electrically connected to one of the source / drain of the selection transistor TR sel The selection transistor TR sel outputs the pixel signal to the signal line VSL according to the selection signal. Further, the other of the source / drain of the amplifying transistor TR amp (the side not connected to the selection transistor TR sel ) is electrically connected to the power supply circuit V DD .

[0139] Further, the other of the source / drain of the selection transistor TR sel (the side not connected to the amplifying transistor Tr amp ) is electrically connected to the signal line VSL, and is further electrically connected to the above-described column signal processing circuit unit 34. Further, the gate of the selection transistor TR sel is electrically connected to a selection line (not shown), and is further electrically connected to the above-described vertical drive circuit unit 32.

[0140] In addition, the storage electrodes 114a and 114b are electrically connected to the above-described vertical drive circuit unit 32 via wiring. The detailed stacked structure of the above-described pixel transistors (amplifying transistor Tr amp , reset transistor TR rst and selection transistor TR sel ) will be described later.

[0141] Although not shown in Figure 5 , PD1 and PD2 can be electrically connected to a transfer transistor, similar to PD3 described later.

[0142] Next, for reference, the equivalent circuit of PD3 will be described with reference to Figure 6 . As shown in Figure 6 , PD3 provided in the semiconductor substrate 300 is connected to a pixel transistor (amplifying transistor TR amp , transfer transistor TR trs, reset transistor TR rst and select transistor TR sel Specifically, one side of the PD3 is electrically connected to a transfer transistor TR for transferring charge via wiring. trs In addition, the transfer transistor TR trs The other of the source / drain (the side not connected to PD3) is electrically connected to the reset transistor TR via wiring. rst In addition, the transfer transistor TR trs The gate of the reset transistor TR is electrically connected to a transmission gate line (not shown), and is further connected to the vertical driving circuit unit 32 described above. rst The other of the source / drain of the transfer transistor TR trs The side connected) is electrically connected to the power supply circuit V DD In addition, the gate of the reset transistor TRrst is electrically connected to a reset line (not shown), and is further connected to the above-mentioned vertical driving circuit unit 32.

[0143] In addition, the transfer transistor TR trs The other of the source / drain (the side not connected to PD3) is electrically connected to the amplifier transistor Tr via wiring. amp The gate of the amplifying transistor Tr amp The charge is amplified (converted) and a pixel signal is output. amp One of the source / drain is electrically connected to the selection transistor TR via wiring. sel One of the source / drain of the selection transistor TR sel The pixel signal is output to the signal line VSL according to the selection signal. amp The other of the source / drain of the select transistor TR sel The side connected to the power supply circuit VDD is electrically connected to the power supply circuit VDD. In addition, the selection transistor TR sel The other of the source / drain (not connected to the amplifier transistor Tr amp The side connected to the transistor TR is electrically connected to the signal line VSL, and is further electrically connected to the column signal processing circuit unit 34 described above. sel The gate electrode is electrically connected to a selection line (not shown), and is further electrically connected to the vertical driving circuit unit 32 described above.

[0144] <2.4 Detailed Structure of Multilayer Wiring Layer>

[0145] The equivalent circuits of PD1, PD2 and PD3 according to this embodiment have been described above. Figures 7 to 11Describe the detailed stacked structure of the multilayer wiring layer 120. Figure 7 A partial cross-sectional view of the pixel 100 (specifically, pixels 100a and 100b) according to the present embodiment is shown. Specifically, Figure 7 The portion between PD2 and PD1 is mainly shown, where the multilayer wiring layer 120 is interposed between PD2 and PD1. In addition, Figure 8 is a cross-sectional view of the pixel 100 taken along the line a-a' of Figure 7 . Figure 9 is a cross-sectional view of the pixel 100 taken along the line b-b' of Figure 7 . Figure 10 is a cross-sectional view of the pixel 100 taken along the line c-c' of Figure 7 . In addition, Figure 11 is a cross-sectional view of the pixel 100 taken along the line d-d' of Figure 7 .

[0146] Specifically, in the present embodiment, as shown in Figure 7 , the pixel 100 has a lower electrode 216, a storage electrode 214, a shielding electrode 208, a photoelectric conversion film 212, and an upper electrode 210 provided as PD2. In addition, an oxide semiconductor layer 142 capable of transmitting light is provided on the sealing film 204 provided above the upper electrode 210. In the present embodiment, examples of the material for forming the oxide semiconductor layer 142 can include: amorphous silicon; SnO2 (doped with a dopant) as a tin oxide-based material and tin oxide doped with a dopant such as zinc tin oxide; and aluminum zinc oxide (e.g., AZO), gallium zinc oxide (e.g., GZO), indium zinc oxide (e.g., IZO), IGZO, and ITZO, etc. as zinc oxide-based materials. In addition, examples of the material of the oxide semiconductor layer 142 can include InSbO4, ZnMgO, CuInO2, MgIn2O4, CdO, GeO, and TiO2, etc. The oxide semiconductor layer 142 can be used as a channel formation region or a source / drain region shared with pixel transistors (e.g., amplification transistor Tr amp , transfer transistor TR trs , reset transistor TR rst and selection transistor TR sel ) connected to PD1. That is, by forming the channel formation region of the pixel transistor connected to PD1 with the oxide semiconductor layer 142 capable of transmitting light, light can also be transmitted to PD2 and PD3 provided below the pixel transistor. In other words, by forming the channel formation region of the pixel transistor connected to PD1 with the oxide semiconductor layer 142 capable of transmitting light, the pixel transistor of PD1 can be stacked with PD1, and the pixel transistor can be further stacked above PD2 and PD3.

[0147] In addition, an insulating film 132 is provided on the oxide semiconductor layer 142. The insulating film 132 can be formed of an HfO2 film, an SiO2 film, or the like that can transmit light.

[0148] In addition, a multilayer wiring layer 120 including wirings and electrodes is provided above the insulating film 132. Further, a lower electrode 116, a storage electrode 114, an insulating film 118, an oxide semiconductor layer 140, a photoelectric conversion film 112, and an upper electrode 110 that constitute PD1 are provided above the multilayer wiring layer 120. That is, in the stacked structure of the pixel 100, the multilayer wiring layer 120 is provided between PD1 and the semiconductor substrate 300. Hereinafter, the detailed stacked structure of the multilayer wiring layer 120 will be described with reference to Figures 7 to 11 The detailed stacked structure of the multilayer wiring layer 120 will be described. In the following description, for easy understanding, the description will start from PD1. In other words, the stacked structure will be described from the upper side to the lower side of the multilayer wiring layer 120.

[0149] First, as Figure 7 shown, the storage electrodes 114a and 114b of PD1 and the lower electrode 116 are provided directly below the insulating film 118. As Figure 8 shown, the storage electrodes 114a and 114b are arranged such that the rectangular storage electrodes 114a and 114b and the strip-shaped lower electrode 116 are line-symmetrical on the left and right sides in the figure, with the lower electrode 116 being interposed between the storage electrodes 114a and 114b. According to the present embodiment, by arranging the storage electrodes 114a and 114b symmetrically as described above, the photoelectric conversion film 112 can detect light that is optically symmetrical to the incident light. Further, as described above, the areas of the storage electrodes 114a and 114b are preferably larger than the area of the lower electrode 116. Note that the shapes of the lower electrode 116 and the storage electrodes 114a and 114b are not limited to Figure 8 the shapes shown, and there is no particular limitation on their shapes as long as the storage electrodes 114a and 114b are symmetrical with respect to the lower electrode 116 interposed therebetween.

[0150] In addition, as Figure 8 shown, the lower electrode 116 and the storage electrodes 114a and 114b each have a contact 128 for electrical connection to the wiring. Therefore, through the contacts 128, the storage electrodes 114a and 114b and the lower electrode 116 can be electrically connected to the driving lines 122a, 122b, and 122f provided below the storage electrodes 114a and 114b and the lower electrode 116 (refer to Figure 9 ).

[0151] In addition, as Figure 8As shown, the strip-shaped shielding electrode 108 is disposed to surround a lower electrode 116 and storage electrodes 114a and 114b that sandwich the lower electrode 116 in the horizontal direction in the figure. In other words, it is disposed to surround two pixels 100 (100a and 100b). In this embodiment, for example, similar to the lower electrode 116 and the storage electrodes 114a and 114b, the shielding electrode 108 can be formed of a transparent conductive film or the like. According to this embodiment, by providing such a shielding electrode 108, leakage from the pixel transistors of another pixel 100 not surrounded by the same shielding electrode 108 can be suppressed.

[0152] In addition, return Figure 7 , the driving lines 122a, 122b, 122f, 122s, and 122r are provided below the storage electrodes 114a and 114b and the lower electrode 116 via an insulating film 130, and the insulating film 130 is interposed between the driving lines 122a, 122b, 122f, 122s, and 122r and the storage electrodes 114a and 114b and the lower electrode 116. In the following description, the layer provided with the driving lines 122a, 122b, 122f, 122s, and 122r is referred to as the driving wiring layer.

[0153] Specifically, as Figure 9 shown, in the driving wiring layer, the rectangular driving line 122f electrically connected to the lower electrode 116 via a contact 128 is disposed in the center. In addition, the driving line 122f is electrically connected via a contact 128 to a driving line 124f provided below the driving line 122f (refer to Figure 10 ), and is further electrically connected to a gate electrode 126am (refer to Figure 11 ), and the gate electrode 126am is the gate electrode of the amplification transistor Tr amp provided below the driving line 122f.

[0154] In addition, as Figure 9 shown, the driving lines 122a, 122b, 122s, and 122r extending in a strip shape are provided in the horizontal direction in the figure, and the driving lines 122a, 122b, 122s, and 122r sandwich the driving line 122f in the vertical direction in the figure. More specifically, the driving line 122a is electrically connected to the storage electrode 114a of PD1 via a contact 128, and the driving line 122b is electrically connected to the storage electrode 114b of PD1 via a contact 128. Although not shown, the driving lines 122a and 122b are drawn to the periphery of the pixel 100 and are electrically connected to a vertical driving circuit unit 32 that controls the voltages applied to the storage electrodes 114a and 114b of PD1.

[0155] In addition, the driving line 122s is electrically connected via the contact 128 to the driving line 124s disposed below the driving line 122s (refer to Figure 10 ), and is further electrically connected to the gate electrode 126s (refer to Figure 11 ), which is the gate electrode of the selection transistor TR sel disposed below the driving line 122s. Although not shown, the driving line 122s is drawn to the periphery of the pixel 100, is electrically connected to a selection line (not shown) for applying a voltage to the gate of the selection transistor TR sel , and is further electrically connected to the vertical driving circuit unit 32.

[0156] Furthermore, the driving line 122r is electrically connected via the contact 128 to the driving line 124r disposed below the driving line 122r (refer to Figure 10 ), and is further electrically connected to the gate electrode 126r (refer to Figure 11 ), which is the gate electrode of the reset transistor TR rst disposed below the driving line 122r. Although not shown, the driving line 122r is drawn to the periphery of the pixel 100, is electrically connected to a reset line (not shown) for applying a voltage to the gate of the reset transistor TR rst , and is further electrically connected to the vertical driving circuit unit 32.

[0157] In the present embodiment, the above-described driving lines 122a, 122b, 122f, 122s, and 122r are preferably formed of a low-resistance wiring material, for example, materials such as Cu, Al, W, Ti, TiN, Ta, and TaN. In the present embodiment, by using the low-resistance wiring material for the driving lines 122a, 122b, 122f, 122s, and 122r, the driving speed of the pixel transistors (the selection transistor TR sel and the reset transistor TR rst , etc.) and the transfer speed of the charges generated by the photoelectric conversion film 112 can be increased.

[0158] Furthermore, in the present embodiment, by using the driving lines 122a and 122b for driving the storage electrodes 114a and 114b and the driving line for driving the reset transistor TR rstThe drive lines 122r and 122s, etc., are provided in the same layer, which can reduce the number of layers in the stacked structure of the pixel 100. As a result, according to this embodiment, an increase in the manufacturing cost of the solid-state imaging device 1 including the pixel 100 can be suppressed. In addition, in this embodiment, the distance in the stacking direction between PD1, PD2, and PD3 within the same pixel 100 can be shortened. As a result, in this embodiment, the F-value dependence of each color can be suppressed, and the sensitivity difference between the colors can be reduced. Note that in this embodiment, the shapes of the drive lines 122a, 122b, 122f, 122s, and 122r are not limited to Figure 9 the shape shown.

[0159] In addition, returning Figure 7 , drive lines 124f, 124r, and 124s, a power supply line 124vd, and a signal line 124vs are provided below the drive lines 122a, 122b, 122f, 122s, and 122r through an insulating film 130. The insulating film 130 is interposed between the drive lines 122a, 122b, 122f, 122s, and 122r and the drive lines 124f, 124r, and 124s, the power supply line 124vd, and the signal line 124vs. In the following description, the layer provided with the drive lines 124f, 124r, and 124s, the power supply line 124vd, and the signal line 124vs is referred to as the power supply / signal wiring layer.

[0160] Specifically, as Figure 10 shown, in the power supply / signal wiring layer, a rectangular signal line 124vs, which is a part of the signal line VSL, is provided on the right side of the figure. The signal line 124vs is electrically connected to an oxide semiconductor layer 142 provided below the signal line 124vs via a contact 128.

[0161] In addition, as Figure 10 shown, a rectangular drive line 124s electrically connected to the above-mentioned drive line 122s via a contact 128 is provided on the left side of the signal line 124vs in the figure. In addition, the drive line 124s is electrically connected to a gate electrode 126s (refer to Figure 11 ) provided below the drive line 124s via a contact 128. The gate electrode 126s is the gate electrode of the selection transistor TR sel .

[0162] In addition, as Figure 10 shown, a strip-shaped power supply line 124vd drawn in a horizontal "U" shape is provided on the left side of the drive line 124s in the figure. Although not shown, the power supply line 124vd is drawn to the periphery of the pixel 100 and electrically connected to a power supply circuit V DD , and this power supply circuit V DD applies a power supply voltage to the pixel transistor (amplification transistor TRamp and a reset transistor TR rst ). Further, a power supply line 124vd is electrically connected via a contact 128 to an oxide semiconductor layer 142 disposed below the power supply line 124vd, and the contact 128 is provided in a rectangular wiring at two ends of the above-mentioned "U" shape.

[0163] Further, as Figure 10 shown, a drive line 124f drawn in a horizontal "T" shape is provided on the left side of the power supply line 124vd in the figure. As Figure 10 shown, the drive line 124f is electrically connected via a contact 128 to a drive line 122f disposed above the drive line 124f, and the contact 128 is provided at the right end of a portion extending in the longitudinal direction of the "T" shape (the portion extending in the horizontal direction in the figure). Further, the drive line 124f is electrically connected via a contact 128 to a gate electrode 126am disposed below the drive line 124f (refer to Figure 11 ), and the gate electrode 126am is the gate electrode of an amplification transistor TR amp .

[0164] As Figure 10 shown, the drive line 124f is electrically connected via a contact 128 to an oxide semiconductor layer 142 disposed below the drive line 124f, and the contact 128 is provided at both ends of a portion extending in the lateral direction of the "T" shape (the portion extending in the up and down direction in the figure).

[0165] Further, as Figure 10 shown, a rectangular drive line 124r is provided on the left side of the power supply line 124vd in the figure, and the drive line 124r is electrically connected via a contact 128 to a drive line 122r disposed above the drive line 124r. Further, the drive line 124r is electrically connected to a gate electrode 126r disposed below the drive line 124r (refer to Figure 11 ), and the gate electrode 126r is the gate electrode of a reset transistor TR rst .

[0166] In the present embodiment, the drive lines 124f, 124r and 124s, the power line 124vd, and the signal line 124vs are preferably composed of a transparent conductive film (e.g., ITO). In the present embodiment, the drive lines 124f, 124r and 124s, the power line 124vd, and the signal line 124vs are composed of a transparent conductive film so that the light incident on the pixel 100 can be detected in PD2 and PD3. In addition, in the present embodiment, preferably, the signal line 124vs and the power line 124vd are preferably set to have a larger wiring width than the drive lines 124f, 124r and 124s. According to the present embodiment, by increasing the wiring width of the signal line 124vs and the power line 124vd, for example, the time (stable period) before the signal transmitted through the signal line 124vs as a part of the signal line VSL is stabilized can be shortened.

[0167] In addition, in this embodiment, if Figure 10 As shown, it is preferable to provide a plurality of contacts 128 for electrically connecting the drive line 124f, the power line 124vd, and the signal line 124vs to the oxide semiconductor layer 142. According to this embodiment, by providing a plurality of contacts 128, the contact resistance can be reduced. Note that in this embodiment, the shapes of the drive lines 124f, 124r, and 124s, the power line 124vd, and the signal line 124vs are not limited to Figure 10 The form shown.

[0168] In addition, return to Figure 7 Gate electrodes 126r, 126am, and 126s are provided below the driving lines 124f, 124r, and 124s, the power line 124vd, and the signal line 124vs via the insulating film 130. Note that in the following description, a layer provided with the gate electrodes 126r, 126am, and 126s is referred to as a gate electrode layer.

[0169] Specifically, Figure 11 As shown, in the gate electrode layer, a rectangular gate electrode 126s connected to the driving line 124s disposed above via a contact 128 is disposed on the right side of the figure. The gate electrode 126s serves as a selection transistor TR sel of the gate electrode.

[0170] In addition, if Figure 11 As shown, a rectangular gate electrode 126am electrically connected to the driving line 124f disposed above via a contact 128 is disposed on the left side of the gate electrode 126s in the figure. The gate electrode 126am serves as an amplifying transistor TR amp of the gate electrode.

[0171] In addition, if Figure 11As shown, a rectangular gate electrode 126r electrically connected to the upper driving line 124r via a contact 128 is disposed on the left side of the gate electrode 126am in the figure. The gate electrode 126r serves as the gate electrode of the reset transistor TR rst .

[0172] In addition, as Figure 11 shown, a strip-shaped shielding electrode 134 is provided to surround the gate electrodes 126r, 126am, and 126s of a plurality of pixel transistors. In the present embodiment, similar to the gate electrodes 126r, 126am, and 126s, the shielding electrode 134 can be formed of, for example, a transparent conductive film or the like. In other words, similar to the above-described shielding electrode 108, the shielding electrode 134 is provided so as to surround two pixels 100 (100a and 100b). According to the present embodiment, by providing the shielding electrode 134, leakage from the pixel transistors of another pixel 100 not surrounded by the same shielding electrode 134 can be suppressed.

[0173] In addition, in the present embodiment, the gate electrodes 126r, 126am, and 126s and the shielding electrode 134 are preferably formed of a transparent conductive film such as ITO. In the present embodiment, by forming the gate electrodes 126r, 126am, and 126s and the shielding electrode 134 with a transparent conductive film, light incident on the pixel 100 can be detected by PD2 and PD3. Note that, in the present embodiment, the shapes of the gate electrodes 126r, 126am, and 126s and the shielding electrode 134 are not limited to Figure 11 the form shown.

[0174] In addition, as described above, an oxide semiconductor layer 142 is disposed below the multilayer wiring layer 120, and an insulating film 132 is interposed between the oxide semiconductor layer 142 and the multilayer wiring layer 120. The oxide semiconductor layer 142 can be used as a channel formation region (a portion facing each gate electrode 126) or a source / drain region (a portion connected to each wiring 124, etc.) shared with pixel transistors (e.g., an amplifying transistor TR amp , a transfer transistor TR trs , a reset transistor TR rst , and a selection transistor TR sel ) connected to PD1. Although not shown in Figure 7 , similar to PD3 described later, the pixel 100 may also be provided with a transfer transistor TR trs of PD1. In this case, a channel formation region or a source / drain region of the transfer transistor TR trs can be provided in the oxide semiconductor layer 142.

[0175] In addition, preferably, the contact 128 is made of polysilicon doped with impurities, high melting point metals or metal silicides such as W, Ti, Pt (platinum), Pd (lead), Cu, TiW, TiN, TiNW, WSi2 or MoSi2, or a stacked structure of layers made of these materials (for example, Ti / TiN / W), etc.

[0176] In addition, the film thicknesses of the driving wiring layer, the power supply / signal wiring layer, and the gate electrode layer included in the multilayer wiring layer 120 and described above are preferably about 50 nm to 100 nm, for example.

[0177] In addition, the insulating film 130 provided between the driving wiring layer, the power supply / signal wiring layer, and the gate electrode layer described above can be formed of, for example, an HfO2 film or an SiO2 film that can transmit light. In addition to the above materials, as the material of the insulating film 130, Al2O3, Si3N4, SiON, SiC, or SiCO, etc. can be used, and there is no particular limitation on this material.

[0178] In addition, a sealing film 204, an upper electrode 210 of PD2, a photoelectric conversion film 212, a lower electrode 216, and storage electrodes 214a and 214b are provided below the oxide semiconductor layer 142. Note that, similar to PD1, the storage electrodes 214a and 214b of PD2 are also preferably arranged such that when viewed from above the light receiving surface, the storage electrodes 214a and 214b of PD2 are line-symmetrical with respect to the lower electrode 216. According to this embodiment, by arranging the storage electrodes 214a and 214b symmetrically as described above, the photoelectric conversion film 212 can detect light having optical symmetry with respect to the incident light. That is, PD1 and PD2 are configured to include two pixels (pixel division) 100 (specifically, pixels 100a and 100b) that are line-symmetrical with each other in a plane, so as to have optical symmetry.

[0179] <2.5 Manufacturing Method>

[0180] The detailed stacked structure of the multilayer wiring layer 120 according to this embodiment has been described above. Next, with reference to Figures 12 to 14 description Figure 7 the manufacturing method of the pixel 100 according to the first embodiment of the present disclosure shown. Figures 12 to 14 is a cross-sectional view for explaining the manufacturing method of the pixel 100 according to the first embodiment of the present disclosure.

[0181] First, a silicon layer (not shown) is formed on the surface of a silicon on insulator (SOI) substrate (not shown) by using an epitaxial growth method, and PD3 (reference Figure 3 and Figure 4Semiconductor regions 312a and 312b, etc. In addition, pixel transistors such as PD2 and PD3 are formed on the silicon layer. In addition, electrodes 310, wirings 306, insulating films 324, etc. are formed on the silicon layer (see Figure 3 and Figure 4 ). After that, a support substrate (not shown) is attached to the insulating film 324. Then, the SOI substrate is removed to expose the silicon layer. Next, openings are formed in the exposed silicon layer, and insulating films and metal films are embedded to form the via electrode 302 (see Figure 3 and 4 ).

[0182] Next, an insulating film 218 is laminated on the via electrode 302 (see Figure 3 and Figure 4 ). As described above, the insulating film 218 preferably has low interface states in order to reduce the interface states between the silicon layer and the insulating film 218 and suppress dark current generated from the interface between the silicon layer and the insulating film 218. Examples of the material of the insulating film 218 can include a stacked structure of an HfO2 film or an Al2O3 film formed by ALD and a SiO2 film formed by plasma CVD.

[0183] Next, after depositing the insulating film 218, a wiring 250 that also serves as a light-shielding film is formed (see Figure 3 and Figure 4 ). The wiring 250 is formed by processing to leave a portion to be shielded from light. Since the wiring 250 is electrically connected to the via electrode 302 and also serves as a light-shielding film, it is preferably composed of a stacked film of W and Ti and TiN as a barrier metal.

[0184] Then, a lower electrode 216, a storage electrode 214, and a shielding electrode 208 having a desired shape are formed on the insulating film 218 by using photolithography or etching, etc. Specifically, for example, after laminating ITO, etc. using sputtering and then patterning using photolithography, and processing using dry etching or wet etching, the storage electrode 214, etc. can be formed into a film having a desired shape. Note that preferably, the space between the lower electrode 216, the storage electrode 214, and the shielding electrode 208 is filled with an insulating film 218 formed by plasma CVD, etc., and the top surfaces of the lower electrode 216, the storage electrode 214, and the shielding electrode 208 and the top surface of the insulating film 218 therebetween are preferably planarized by chemical mechanical polishing (CMP).

[0185] Next, an insulating film 218 is formed on the lower electrode 216, the storage electrode 214, and the shielding electrode 208, and an opening is formed in the insulating film 218 using photolithography or the like so that a part of the lower electrode 216 is exposed. Further, a metal material such as W, Al, or Cu is embedded in the opening, and then an oxide semiconductor layer 240 is formed above the insulating film 218. Note that before forming the oxide semiconductor layer 240, the top surface of the insulating film 218 may be planarized by CMP or the like.

[0186] Further, a photoelectric conversion film 212, an upper electrode 210, and a sealing film 204 are sequentially stacked on the oxide semiconductor layer 240. In this way, the Figure 12 structure shown can be obtained. The photoelectric conversion film 212 can be formed by using spin coating, vacuum deposition, or the like. Further, it is known that the characteristics of the photoelectric conversion film 212 usually vary significantly due to the influence of moisture, oxygen, hydrogen, and the like. Therefore, it is preferable to form the upper electrode 210 on the photoelectric conversion film 212 in a vacuum consistent with the photoelectric conversion film 212. Further, before and after forming the sealing film 204, post-treatments such as ashing or organic cleaning can be performed to remove deposits and residues. In Figure 12 , for easy understanding, the illustration of the silicon layer, PD3, pixel transistors, wiring 306, etc. is omitted, and they are illustrated together as a semiconductor substrate 300a. Further, the same applies to the following Figure 13 and Figure 14 .

[0187] Then, an oxide semiconductor layer 142 is stacked on the sealing film 204, and an insulating film 132 is stacked on the oxide semiconductor layer 142. Further, a gate electrode 126 and a shielding electrode 134 having a desired shape are formed on the insulating film 132, and then an insulating film 130 is stacked. Then, an opening is formed that penetrates the stacked insulating film 130 and extends to the gate electrode 126, or further penetrates the insulating film 130 and extends to the oxide semiconductor layer 142. A metal film or the like is embedded in the formed opening to form a contact 128.

[0188] Next, a wiring 124 having a desired shape is formed on the contact 128 and the insulating film 130, and a contact 128 for connecting the gate electrode 126 and the wiring 124 is formed in the same manner as described above. Further, a driving line 122 having a desired shape is formed on the contact 128 and the insulating film 130, and a contact 128 for connecting the wiring 124 and the driving line 122 is formed in the same manner as described above. Then, a lower electrode 116, a storage electrode 114, and a shielding electrode 108 having a desired shape are formed on the contact 128 and the insulating film 130 in a desired shape, and an insulating film 118 is stacked on these electrodes. In this way, the Figure 13 structure shown can be obtained.

[0189] Then, an oxide semiconductor layer 140, a photoelectric conversion film 112, and an upper electrode 110 are sequentially stacked on the insulating film 118. In this way, the structure shown can be obtained. Figure 14 Then, by forming the sealing film 104, the pixel 100 shown can be obtained. Figure 7 The pixel 100 shown.

[0190] Examples of methods for forming the above layers can include PVD methods and CVD methods, etc. Examples of PVD methods can include: vacuum deposition methods using resistance heating or high-frequency heating, electron beam (EB) deposition methods, various sputtering methods (magnetron sputtering methods, RF-DC coupled bias sputtering methods, electron cyclotron resonance (ECR) sputtering methods, face-target sputtering methods, and high-frequency sputtering methods, etc.), ion plating methods, laser ablation methods, molecular beam epitaxy (MBE) methods, and laser transfer methods, etc. Examples of CVD methods can include: plasma CVD methods, thermal CVD methods, metal organic (MO) CVD methods, and optical CVD methods, etc. In addition, examples of other methods can include: electrolytic electroplating methods; electroless plating methods; spin coating methods; dipping methods; casting methods; microcontact printing methods; drop casting methods; various printing methods, such as screen printing methods, inkjet printing methods, offset printing methods, gravure printing methods, and flexographic printing methods; stamping methods; spraying methods; and various coating methods, such as air knife coating methods, doctor blade coating methods, bar coating methods, blade coating methods, extrusion coating methods, reverse roll coating methods, transfer roll coating methods, gravure coating methods, kiss coating methods, casting coating methods, spray coating methods, slit hole coating methods, and calendar coater. Examples of patterning methods for each layer can include: shadow masks, laser transfer, chemical etching such as photolithography, and physical etching using ultraviolet light or lasers, etc. Additionally, examples of planarization techniques can include CMP methods, laser planarization methods, and reflow methods, etc.

[0191] As described above, according to the present embodiment, a pixel 100 having pixel transistors (amplifying transistor TR amp , selection transistor TR sel and reset transistor TR rst ) and wirings can be provided. The pixel 100 can effectively output and transmit pixel signals through the charges generated in the photoelectric conversion film 112 while suppressing an increase in manufacturing cost.

[0192] Specifically, in the present embodiment, the pixel transistors (amplifying transistor TR amp , selection transistor TR sel and reset transistor TR rst) The channel formation region, etc. are formed of an oxide semiconductor layer 142 that can transmit light, so that they can be stacked above PD2 and PD3. In addition, in this embodiment, by providing drive lines 122a and 122b for driving storage electrodes 114a and 114b and drive lines 122r and 122s for driving reset transistors TR rst etc. in the same layer, the number of layers in the stacked structure of pixel 100 can be reduced. As a result, according to this embodiment, an increase in the manufacturing cost of the solid-state imaging device 1 including pixel 100 can be suppressed. In addition, in this embodiment, compared with the case where pixel transistors are provided in semiconductor substrate 300, the photoelectric conversion film 112 of PD1 and the pixel transistors of PD1 can be arranged closer to each other, and by forming drive lines 122a, 122b, 122f, 122s, and 122r using a low-resistance wiring material, the driving speed of the pixel transistors and storage electrodes 114a and 114b and the transfer speed of charges generated in the photoelectric conversion film 112 can be increased.

[0193] In addition, according to this embodiment, by increasing the wiring widths of signal lines 124vs and power supply lines 124vd, the time (stable period) before the signal transmitted through signal line 124vs, which is a part of signal line V SL , becomes stable can be shortened, and pixel signals can be effectively transmitted.

[0194] In addition, in this embodiment, by providing shielding electrodes 108 and 134, leakage from the pixel transistors of another pixel 100 not surrounded by the same shielding electrodes 108 and 134 can be suppressed. In addition, according to this embodiment, by arranging storage electrodes 114a, 114b, 214a, and 214b symmetrically, the photoelectric conversion films 112 and 212 can detect light that is optically symmetric with respect to incident light.

[0195] <2.6 Variation Example>

[0196] In the above-described first embodiment, the pixel transistors of PD2 (amplification transistor TR amp , reset transistor TR rst , selection transistor TR sel) is provided in the semiconductor substrate 300. However, in this embodiment, the pixel transistors of PD2 are not limited to being provided in the semiconductor substrate 300. Similar to PD1, the pixel transistors can be formed by an oxide semiconductor layer (not shown) provided above the semiconductor substrate 300 and a multilayer wiring layer (not shown) provided below the oxide semiconductor layer. That is, in this modified example, the pixel transistors of PD2 are formed by a multilayer wiring layer provided below the lower electrode 216 of PD2 and an oxide semiconductor layer provided below the multilayer wiring layer. According to this modified example, with the above configuration, the region where PD3 can be formed in the semiconductor substrate 300 can be expanded, so that PD3 can effectively utilize the light incident on the pixel 100, and the characteristics of PD3 can be improved.

[0197] 《3. Second Embodiment》

[0198] In addition, in the embodiments of the present disclosure, the positions of PD1 and the multilayer wiring layer 120 in the stacked structure of the pixel 100 in the above first embodiment can be reversed in the vertical direction. Hereinafter, a second embodiment of the present disclosure will be described, in which the positions of PD1 and the multilayer wiring layer 120 are opposite to those in the first embodiment.

[0199] As described above, in the second embodiment, the upper electrodes 110 and 210 and the lower electrodes 116 and 216 of PD1 and PD2 are not defined according to Figure 15 the positions in the stacked structure of the pixel 100 shown, and the electrodes having the same functions as the upper electrodes 110 and 210 in the first embodiment are referred to as the upper electrodes 110 and 210, and the electrodes having the same functions as the lower electrodes 116 and 216 in the first embodiment are referred to as the lower electrodes 116 and 216.

[0200] <3.1 Detailed Structure of Multilayer Wiring Layer>

[0201] First, the detailed structures of PD1 and the multilayer wiring layer 120a according to this embodiment will be described with reference to Figure 15 FIG. Figure 15 FIG. shows a part of the cross-sectional view of the pixel 100 according to this embodiment, and Figure 15 corresponds to a part of the cross-sectional view of the pixel 100 according to the first embodiment shown in Figure 7 FIG. Note that the cross-section when the pixel 100 is cut along the line a-a' corresponds to the cross-sectional view of the pixel 100 according to the first embodiment in Figure 15 FIG., and the cross-section when the pixel 100 is cut along the line b-b' corresponds to the cross-sectional view of the pixel 100 according to the first embodiment in Figure 8 FIG. In addition, along Figure 15 the cross-section when the pixel 100 is cut along the line b-b' corresponds to the cross-sectional view of the pixel 100 according to the first embodiment in Figure 9 FIG. In addition, along Figure 15The cross-section when the pixel 100 is cut along the line c-c' corresponds to Figure 10 the cross-sectional view of the pixel 100 according to the first embodiment, along Figure 15 the cross-section when the pixel 100 is cut along the line d-d' corresponds to Figure 11 the cross-sectional view of the pixel 100 according to the first embodiment.

[0202] As Figure 15 shown, similar to the pixel 100 of the first embodiment shown in Figure 7 the pixel 100 according to the present embodiment has a lower electrode 216 set to PD2, a storage electrode 214, a shielding electrode 208, a photoelectric conversion film 212, and an upper electrode 210. In addition, in the present embodiment, a sealing film (second sealing film) 204 is provided above the upper electrode 210.

[0203] In addition, the difference between the present embodiment and the first embodiment is that: as Figure 15 shown, a sealing film (first sealing film) 144, an upper electrode 110, a photoelectric conversion film 112, an oxide semiconductor layer 140, and an insulating film 118 are sequentially stacked above the sealing film 204. Note that the upper electrode 110, the photoelectric conversion film 112, the oxide semiconductor layer 140, and the insulating film 118 constitute a part of PD1 according to the present embodiment.

[0204] In addition, in the present embodiment, a lower electrode 116, a storage electrode 114, and a shielding electrode 108 are provided above the insulating film 118. Since the cross-section taken along the line a-a' is the same as the cross-sectional view of the pixel 100 according to the first embodiment shown above, its detailed description will be omitted here. Figure 15 the line a-a' is the same as the cross-sectional view of the pixel 100 according to the first embodiment shown above, so its detailed description will be omitted here. Figure 8 the cross-sectional view of the pixel 100 according to the first embodiment shown above, so its detailed description will be omitted here.

[0205] In addition, in the present embodiment, a multilayer wiring layer 120a is provided above the lower electrode 116, the storage electrode 114, and the shielding electrode 108. That is, in the stacked structure of the pixel 100, PD1 is provided between the multilayer wiring layer 120a and the semiconductor substrate 300a. The multilayer wiring layer 120a according to the present embodiment will be described below. In the following description, for easy understanding and for comparison with the multilayer wiring layer 120 according to the first embodiment, the stacked structure will be described from the lower side to the upper side of the multilayer wiring layer 120.

[0206] First, in the present embodiment, as Figure 15As shown, the driving lines 122 (specifically, the driving lines 122a, 122b, 122f, 122s and 122r) are arranged above the lower electrode 116, the storage electrode 114 and the shielding electrode 108, wherein the insulating film 130 is interposed between the driving lines 122 and the lower electrode 116, the storage electrode 114 and the shielding electrode 108. Figure 15 The cross section taken along the line b-b' is the same as that described above. Figure 9 The illustrated cross-sectional view of the pixel 100 according to the first embodiment is the same, and thus a detailed description thereof will be omitted here.

[0207] In addition, in this embodiment, Figure 15 As shown, the wiring 124 (specifically, the driving lines 124f, 124r and 124s, the power supply line 124vd, and the signal line 124vs) is arranged above the driving line 122, wherein the insulating film 130 is interposed between the wiring 124 and the driving line 122. Figure 15 The cross section taken along the line c-c' is the same as that described above. Figure 10 The illustrated cross-sectional view of the pixel 100 according to the first embodiment is the same, and thus a detailed description thereof will be omitted here.

[0208] In addition, in this embodiment, if Figure 15 As shown, the gate electrode 126 (specifically, the gate electrodes 126r, 126am, and 126s) is provided above the wiring 124, wherein the insulating film 130 is interposed between the gate electrode 126 and the wiring 124. Figure 15 The cross section taken along the line d-d' is the same as that described above. Figure 11 The illustrated cross-sectional view of the pixel 100 according to the first embodiment is the same, and thus a detailed description thereof will be omitted here.

[0209] In addition, in this embodiment, if Figure 15 As shown, the oxide semiconductor layer 142 is provided above the gate electrode 126, wherein the insulating film 132 is interposed between the oxide semiconductor layer 142 and the gate electrode 126. The oxide semiconductor layer 142 can be used as a pixel transistor (eg, an amplifier transistor TR 1 ) connected to the PD1. amp , transfer transistor TR trs , reset transistor TR rst and select transistor TR sel ) a common channel formation region (a portion facing each gate electrode 126) or a source / drain region (a portion connected to each driving line 124, etc.). In addition, in this embodiment, the insulating film 146 is provided over the oxide semiconductor layer 142.

[0210] That is, in this embodiment, compared with the above-described first embodiment, the positions of PD1 and the multilayer wiring layer 120 in the stacked structure of the pixel 100 can be inverted in the vertical direction. Further, in this embodiment, compared with the first embodiment above, the structural order in the multilayer wiring layer 120a can be inverted. However, even in this embodiment, similar to the first embodiment, a pixel 100 having pixel transistors (amplification transistor TR amp , selection transistor TR sel , and reset transistor TR rst ) and wirings can be provided. The pixel 100 can effectively output and transmit pixel signals by the charges generated in the photoelectric conversion film 112 while suppressing an increase in manufacturing cost.

[0211] Specifically, even in this embodiment, the channel formation regions of the pixel transistors (amplification transistor TR amp , selection transistor TR sel , and reset transistor TR rst ) connected to PD1 are also formed of an oxide semiconductor layer 142 capable of transmitting light, so that they can be stacked above PD2 and PD3. Further, also in this embodiment, by providing the drive lines 122a and 122b for driving the storage electrodes 114a and 114b and the drive lines 122r and 122s for driving the reset transistor TR rst etc. in the same layer, the number of layers in the stacked structure of the pixel 100 can be reduced. As a result, according to this embodiment, an increase in the manufacturing cost of the solid-state imaging device 1 including the pixel 100 can be suppressed. In addition, in this embodiment, compared with the case where pixel transistors are provided in the semiconductor substrate 300, the photoelectric conversion film 112 of PD1 and the pixel transistors of PD1 can be arranged closer to each other, and by forming the drive lines 122a, 122b, 122f, 122s, and 122r using a low-resistance wiring material, the driving speed of the pixel transistors and the storage electrodes 114a and 114b and the transmission speed of the charges generated in the photoelectric conversion film 112 can be increased.

[0212] <3.2 Manufacturing Method>

[0213] Next, a method of manufacturing the pixel 100 according to the second embodiment of the present disclosure will be described with reference to Figure 16 illustrated Figure 15 a cross-sectional view showing the method of manufacturing the pixel 100 according to the second embodiment of the present disclosure. Figure 16 is a cross-sectional view for explaining the method of manufacturing the pixel 100 according to the second embodiment of the present disclosure.

[0214] First, similar to the first embodiment, a semiconductor substrate 300a is prepared using an SOI substrate (not shown) and a support substrate (not shown), etc. On this semiconductor substrate 300a, PD2 and PD3, as well as corresponding pixel transistors, wirings, through electrodes, etc. are formed. In addition, a sealing film 204 is formed on the upper electrode 210 provided on the semiconductor substrate 300a. In this way, the semiconductor substrate 300a shown below Figure 16 can be obtained.

[0215] Next, an insulating film 146, an oxide semiconductor layer 142, and an insulating film 132 are sequentially stacked on another semiconductor substrate 300b (for example, an SOI substrate). Next, a gate electrode 126, a wiring 124, a driving line 122, a lower electrode 116, a storage electrode 114, and a shielding electrode 108 are formed on the insulating film 132. In addition, an insulating film 118, an oxide semiconductor layer 140, a photoelectric conversion film 112, an upper electrode 110, and a sealing film 144 are sequentially stacked on the lower electrode 116, the storage electrode 114, and the shielding electrode 108. In this way, the semiconductor substrate 300b shown above Figure 16 can be obtained. Since the formation details of each layer are the same as those of the first embodiment, the description thereof will be omitted here.

[0216] In addition, as Figure 16 shown, the semiconductor substrate 300a and the semiconductor substrate 300b are joined, so that the sealing film 204 and the sealing film 144 face each other. Note that when joining, the top surfaces of the sealing films 204 and 144 can be subjected to plasma treatment, or a thin silicon oxide film can be stacked on the sealing films 204 and 144 and heated. In addition, by removing the semiconductor substrate 300b, the pixel 100 according to the present embodiment shown Figure 15 can be obtained.

[0217] Incidentally, the photoelectric conversion films 112 and 212 are generally made of materials susceptible to heat. Therefore, in the present embodiment, by using the joining between the two semiconductor substrates 300a and 300b, the number of layers stacked on the photoelectric conversion films 112 and 212 can be further reduced. As a result, according to the present embodiment, since the number of times of applying heat to the photoelectric conversion films 112 and 212 during the formation of various layers can be reduced, the photoelectric conversion films 112 and 212 can be prevented from deteriorating due to heat.

[0218] 《4. Third Embodiment》

[0219] The solid-state imaging device 1 according to the embodiments of the present disclosure is generally applicable to electronic devices that use a solid-state imaging element for an image reading unit, such as: imaging devices, such as digital cameras or video cameras; mobile terminal devices having an imaging function; and copying machines that use a solid-state imaging element as an image reading unit. In addition, the embodiments of the present disclosure are applicable to robots, drones, automobiles, or medical devices (endoscopes), etc. that include the above-described imaging devices. Note that the solid-state imaging device 1 according to the present embodiment can be formed as a single chip and can be implemented in the form of a module having an imaging function, in which the imaging unit and the signal processing unit or the optical system are encapsulated together. Hereinafter, reference will be made to Figure 17 An example of an electronic device 700 including an imaging device 702 having the solid-state imaging device 1 according to the present embodiment will be described as a third embodiment of the present disclosure. Figure 17 FIG. is an explanatory diagram showing an example of an electronic device 700 including an imaging device 702 having a solid-state imaging device 1 according to the embodiments of the present disclosure.

[0220] As Figure 17 shown, the electronic device 700 includes an imaging device 702, an optical lens 710, a shutter mechanism 712, a drive circuit unit 714, and a signal processing circuit unit 716. The optical lens 710 focuses image light (incident light) from a subject onto the imaging surface of the imaging device 702. This enables signal charges to be stored in the solid-state imaging device 1 of the imaging device 702 for a certain period of time. The shutter mechanism 712 performs an opening / closing operation to control the light emission period and the light shielding period of the imaging device 702. The drive circuit unit 714 provides drive signals for controlling the signal transmission operation of the imaging device 702 or the shutter operation of the shutter mechanism 712, etc. That is, the imaging device 702 performs signal transmission based on the drive signals (timing signals) provided from the drive circuit unit 714. The signal processing circuit unit 716 performs various types of signal processing. For example, the signal processing circuit unit 716 outputs the video signal that has undergone signal processing to a storage medium (not shown) such as a memory, or outputs the signal to a display unit (not shown).

[0221] 《5. Fourth Embodiment》

[0222] <5.1 Embodiment>

[0223] Incidentally, in the pixel 100 according to the above-described embodiment of the present disclosure, since the PD2 generally has the property of being vulnerable to moisture and oxygen, a sealing film 204 is provided on the PD2 to protect the PD2. However, as described above, since the height (thickness) of the pixel 100 in the stacking direction increases due to the provision of the sealing film 204, crosstalk with an adjacent pixel 100 due to oblique incident light may easily occur. Therefore, in order to suppress the occurrence of crosstalk, it is conceivable to provide waveguides 402 and 404 for converging light in the insulating film 504 and the sealing film 204 above the substrate 500 (refer to Figure 18 ).

[0224] In addition, in the pixel 100 according to the above-described embodiment of the present disclosure, a plurality of pixel transistors including an oxide semiconductor layer 142 and a multilayer wiring layer 120 are provided, and a driving line 122 for driving these pixel transistors is provided. In addition, in order to ensure the degree of freedom in designing the pixel transistors, the driving line 122 needs to be multilayered. However, due to the multilayer structure of the driving line 122, similar to the above, since the height (thickness) of the pixel 100 in the stacking direction increases, crosstalk with an adjacent pixel 100 due to oblique incident light may easily occur. Therefore, in order to suppress the occurrence of such crosstalk, it is conceivable to provide a waveguide 400 for converging light in the multilayer wiring layer 120.

[0225] Therefore, reference will be made to Figures 18 to 21 describe the detailed stacking structure of the solid-state imaging device 1 according to the fourth embodiment of the present disclosure having the above waveguides 400, 402, and 404. Figure 18 is a part of a cross-sectional view of the pixel 100 (specifically, pixel 100a and 100b) according to the present embodiment. Specifically, Figure 18 mainly shows the portion between the PD2 and the PD1, in which the multilayer wiring layer 120 is inserted. In addition, Figure 19 is a cross-sectional view of the pixel 100 taken along the line f-f' of Figure 18 , Figure 20 is a cross-sectional view of the pixel 100 taken along the line e-e′ of Figure 18 , Figure 21 is a cross-sectional view of the pixel 100 taken along the line b-b′ of Figure 18 . Note that in the following description, the description of the points common to the above-described embodiments of the present disclosure will be omitted, and only the differences from the embodiments of the present disclosure will be described.

[0226] Specifically, in the present embodiment, as shown in Figure 18 and Figure 19As shown, in pixel 100, an insulating film 504 is stacked on a semiconductor substrate 500 made of silicon or the like, and a contact 502 made of a conductive film or the like and a waveguide 404 corresponding to pixels 100a and 100b are provided in the insulating film 504. For example, as Figure 19 shown, a plurality of waveguides 404 are arranged in the horizontal direction in the figure. In addition, in the present embodiment, for example, Si3N4 (refractive index of about 1.9) is preferably used as the material of the waveguide 404. In this way, light can be converged in the waveguide 404. However, in the present embodiment, there is no particular limitation on the material of the waveguide 404.

[0227] In addition, in the present embodiment, as Figure 18 and Figure 20 shown, pixel 100 has a lower electrode 216, a storage electrode 214, a shielding electrode 208, a photoelectric conversion film 212, and an upper electrode 210 provided as PD2. In addition, a sealing film 204 is provided above the upper electrode 210, and a waveguide 402 is provided in the sealing film 204 and corresponds to pixels 100a and 100b. For example, as Figure 19 shown, a plurality of waveguides 402 are arranged in the horizontal direction in the figure. In addition, in the present embodiment, for example, Si3N4 (refractive index of about 1.9) is preferably used as the material of the waveguide 402, and Al2O3 (refractive index of about 1.6) is preferably used as the material of the sealing film 204. In this way, light can be converged into the waveguide 402. In addition, in the present embodiment, there is no particular limitation on the materials of the sealing film 204 and the waveguide 402, but preferably, the difference in refractive index between the material of the waveguide 402 and the material of the sealing film 204 is about 0.2 or more. In this way, the light condensing efficiency of the waveguide 402 can be further improved.

[0228] In addition, as Figure 18 shown, even in the present embodiment, a multilayer wiring layer 120 including wirings and electrodes is provided above the insulating film 132. In addition, a lower electrode 116, a storage electrode 114, an insulating film 118, an oxide semiconductor layer 140, a photoelectric conversion film 112, and an upper electrode 110 for forming PD1 are provided above the multilayer wiring layer 120. More specifically, the storage electrodes 114a and 114b and the lower electrode 116 of PD1 are provided directly below the insulating film 118, and a waveguide 400 is provided directly below the storage electrodes 114a and 114b. For example, as Figure 21 shown, the waveguide 400 is symmetrically provided on the left and right sides of the figure with a driving line 122f interposed therebetween. In addition, the waveguide 400 can also be made of the same material as the waveguide 402. In this way, light can be converged in the waveguide 402.

[0229] Since the manufacturing method of the pixel 100 according to the present embodiment is the same as that of the pixel 100 according to the first embodiment of the present disclosure, the description thereof will be omitted here.

[0230] As described above, in the present embodiment, by providing waveguides 400, 402, and 404 for converging light in the insulating film 504, the multilayer wiring layer 120, and the sealing film 204, even when the height of the pixel 100 in the stacking direction increases, crosstalk with adjacent pixels 100 due to tilted incident light can be suppressed. The present embodiment is not limited to the case where all of the waveguides 400, 402, and 404 are provided, and a part of these waveguides may be provided.

[0231] <5.2 First Modified Example>

[0232] Note that the present embodiment is not limited to providing Figures 18 to 21 the waveguides 400, 402, and 404 shown, and internal lenses 600, 602, and 604 may be used instead of the waveguides 400, 402, and 404. The corresponding modified example as the first modified example of the present embodiment will be described using Figure 22 FIG. Figure 22 FIG. shows a part of a cross-sectional view of the pixel 100 according to the first modified example of the present embodiment.

[0233] As Figure 22 shown, in this modified example, internal lenses 600, 602, and 604 for condensing light are provided in the insulating film 504, the multilayer wiring layer 120, and the sealing film 204. In this way, according to this modified example, even when the height of the pixel 100 in the stacking direction increases, crosstalk with adjacent pixels 100 due to tilted incident light can be suppressed. The present modified example is not limited to the case where all of the internal lenses 600, 602, and 604 are provided, and a part of these internal lenses may be provided.

[0234] <5.3 Second Modified Example>

[0235] Furthermore, the above-described present embodiment is not limited to providing Figures 18 to 21 the waveguides 400, 402, and 404 shown, and barrier layers 800, 802, and 804 may be used instead of the waveguides 400, 402, and 404. The corresponding modified example as the second modified example of the present embodiment will be described using Figure 23 FIG. Figure 23 FIG. shows a part of a cross-sectional view of the pixel 100 according to the second modified example of the present embodiment.

[0236] As Figure 23As shown, in this modification example, barrier layers 800, 802, and 804 are provided in the insulating film 504, the multilayer wiring layer 120, and the sealing film 204. For example, when Al2O3 (refractive index of about 1.6) is used as the material of the sealing film 204 or the insulating film 504, the barrier layers 800, 802, and 804 are preferably made of SiO2 (refractive index of about 1.4). In this way, light can be focused. In addition, in this modification example, there is no particular limitation on the material of the barrier layers 800, 802, and 804, but preferably, the difference between the refractive index of the material of the barrier layers 800, 802, and 804 and the refractive index of the material of the sealing film 204 or the insulating film 504 is about 0.2 or more. In this way, the light condensing efficiency can be further improved. In addition, as the material of the barrier layers 800, 802, and 804, a metal material (Al, W, Ti, TiN, TiAl, Cu, Ta, TaN, Co, Ru, etc., or a material containing these elements) can be used. In this way, according to this modification example, even when the height of the pixel 100 in the stacking direction increases, crosstalk with adjacent pixels 100 caused by oblique incident light can be suppressed. This modification example is not limited to the case where all the barrier layers 800, 802, and 804 are provided, and a part of the barrier layers 800, 802, and 804 can be provided.

[0237] In addition, in the present disclosure, this embodiment and the first and second modification examples can be implemented in combination with each other. In addition, in the present disclosure, the positions where the waveguide, the internal lens, and the barrier layer are provided are not limited to the above positions, and the waveguide, the internal lens, and the barrier layer can be provided at other positions.

[0238] <<6. Application of the Endoscopic Surgery System>>

[0239] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0240] Figure 24 FIG. is an example showing a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (this technology) can be applied.

[0241] Figure 24 An aspect in which an operator (doctor) 11131 performs surgery on a patient 11132 on a hospital bed 11133 using the endoscopic surgery system 11000 is shown. As shown, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112; a support arm device 11120 for supporting the endoscope 11100; and a cart 11200 on which various devices for endoscopic surgery are installed.

[0242] The endoscope 11100 includes: a lens barrel 11101 having a region at a predetermined length from the tip inserted into the body cavity of a patient 11132; and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, an endoscope 11100 of a so-called rigid endoscope configured with a rigid lens barrel 11101 is shown. However, the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible lens barrel.

[0243] At the tip of the lens barrel 11101, an opening for mounting an objective lens is provided. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the lens barrel through an optical fiber extending within the lens barrel 11101 and irradiates an observation target in the body cavity of the patient 11132 through the above-mentioned objective lens. Note that the endoscope 11100 may be a direct-view endoscope, a perspective-view endoscope, or a side-view endoscope.

[0244] An optical system and an imaging element are provided inside the camera 11102, and the reflected light (observation light) from the observation target is converged onto the imaging element through this optical system. The observation light is subjected to photoelectric conversion by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image, is generated. This image signal is sent to the camera control unit (CCU) 11201 as raw data.

[0245] The CCU 11201 includes a central processing unit (CPU: central processing unit), a graphics processing unit (GPU: graphics processing unit), etc., and overall controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives the image signal from the camera 11102 and performs various image processing operations such as imaging processing (demosaicing processing) on this image signal for displaying an image based on this image signal.

[0246] Under the control of the CCU 11201, the display device 11202 displays an image based on the image signal (image processing has been performed on the image signal by the CCU 11201).

[0247] For example, the light source device 11203 includes a light source such as a light emitting diode (LED: light emitting diode), and provides irradiation light to the endoscope 11100 when imaging a surgical site or the like.

[0248] The input device 11204 is an input interface of the endoscopic surgical system 11000. A user can input various information and instructions into the endoscopic surgical system 11000 through the input device 11204. For example, the user inputs instructions or the like to change the imaging conditions (type of illumination light, magnification, focal length, etc.) of the endoscope 11100.

[0249] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing and cutting tissues, sealing blood vessels, etc. To ensure the field of view of the endoscope 11100 and the working space of the operator, the pneumoperitoneum device 11206 sends gas into the body cavity through the pneumoperitoneum tube 11111 to expand the body cavity of the patient 11132. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, images, and charts.

[0250] For example, the light source device 11203 that supplies illumination light to the endoscope 11100 when imaging the surgical site can be set by a white light source composed of an LED, a laser light source, or a combination of an LED and a laser light source. When the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203. In this case, the laser light from each of the RGB laser light sources is irradiated onto the observation object in a time-division manner, and the driving of the imaging element of the camera 11102 is controlled in synchronization with the irradiation timing. As a result, images corresponding to each of RGB can be captured in a time-division manner. According to this method, a color image can be obtained even when a color filter is not provided in the imaging element.

[0251] In addition, the driving of the light source device 11203 can be controlled so as to change the output light intensity at a predetermined time interval. Images are acquired in a time-division manner by controlling the driving of the imaging element of the camera 11102 in synchronization with the moment of changing the light intensity, and these images are synthesized, so that a high-dynamic-range image without so-called underexposure and overexposure can be generated.

[0252] In addition, the light source device 11203 can be configured to be capable of providing light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in human tissue, light in a narrower band region than the illumination light (i.e., white light) during conventional observation is irradiated, so as to perform so-called narrow-band imaging with high contrast for imaging predetermined tissues such as blood vessels on the surface layer of mucous membranes. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image by fluorescence generated by irradiating excitation light. In fluorescence observation, human tissue can be irradiated with excitation light, and fluorescence from the human tissue can be observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) can be locally injected into the human tissue, and the human tissue can be irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 can be configured to be capable of providing narrow-band light and / or excitation light corresponding to such special light observation.

[0253] Figure 25 is a block diagram showing Figure 24 an example of the functional configuration of the illustrated camera 11102 and CCU 11201.

[0254] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected via a transmission cable 11400.

[0255] The lens unit 11401 is an optical system provided at a portion connected to the lens barrel 11101. Observation light introduced from the tip of the lens barrel 11101 is guided to the camera 11102 and incident on the lens unit 11401. The lens unit 11401 is constituted by combining a plurality of lenses (including a zoom lens and a focusing lens).

[0256] The imaging unit 11402 is composed of imaging elements. The number of imaging elements constituting the imaging unit 11402 can be one (so-called single-board type) or multiple (so-called multi-board type). When the imaging unit 11402 is composed of multi-board type imaging elements, for example, image signals corresponding to each of RGB are generated by each imaging element, and a color image can be obtained by synthesizing these image signals. Alternatively, the imaging unit 11402 can be configured to have a pair of imaging elements for respectively acquiring a right-eye image signal and a left-eye image signal corresponding to three-dimensional (3D) display. By performing 3D display, the operator 11131 can more accurately grasp the depth of the biological tissue in the surgical site. When the imaging unit 11402 is composed of multi-board type imaging elements, a plurality of lens units 11401 are provided for each imaging element.

[0257] In addition, the imaging unit 11402 may not be provided in the camera 11102. For example, the imaging unit 11402 may be provided within the lens barrel 11101 and immediately behind the objective lens.

[0258] The drive unit 11403 is composed of an actuator, and under the control of the camera control unit 11405, the drive unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance. In this way, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0259] The communication unit 11404 is composed of a communication device for sending various information to the CCU 11201 and receiving various information from the CCU 11201. The communication unit 11404 sends the image signal obtained from the imaging unit 11402 as raw data to the CCU 11201 through the transmission cable 11400.

[0260] In addition, the communication unit 11404 receives a control signal for controlling the drive of the camera 11102 from the CCU 11201 and provides this control signal to the camera control unit 11405. For example, the above control signal includes information related to imaging conditions, such as information for specifying the frame rate of the captured image, information for specifying the exposure value during imaging, and / or information for specifying the magnification and focus of the captured image, etc.

[0261] Imaging conditions such as frame rate, exposure value, magnification, and focus as described above can be appropriately specified by the user, or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 has so-called auto exposure (AE), autofocus (AF), and auto white balance (AWB) functions.

[0262] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0263] The communication unit 11411 is composed of a communication device for sending various information to the camera 11102 and receiving various information from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 through the transmission cable 11400.

[0264] In addition, the communication unit 11411 sends a control signal for controlling the driving of the camera 11102 to the camera 11102. The above-mentioned image signal and the above-mentioned control signal can be transmitted through electrical communication, optical communication, etc.

[0265] The image processing unit 11412 performs various image processes on the image signal corresponding to the raw data transmitted from the camera 11102.

[0266] The control unit 11413 executes various controls related to imaging the surgical site, etc. through the endoscope 11100 and displaying the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102.

[0267] In addition, based on the image signal that has been processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display a captured image of the surgical site or the like. At this time, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific living parts, bleeding, and haze when using the energy treatment tool 11112 by detecting the shape, color, etc. of the edges of the objects included in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can use the recognition result to display various types of surgical assistance information on the image of the surgical site in a superimposed manner. By displaying the surgical assistance information in a superimposed manner and presenting the surgical assistance information to the operator 11131, the burden on the operator 11131 can be reduced, and the operator 11131 can perform the surgery reliably.

[0268] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 to each other is an electrical signal cable corresponding to electrical signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.

[0269] Here, in the illustrated example, communication is performed in a wired manner using the transmission cable 11400. However, communication between the camera 11102 and the CCU 11201 can also be performed in a wireless manner.

[0270] Examples of the endoscopic surgical system to which the technology according to the present disclosure can be applied have been described above. In the above configuration, the technology according to the present disclosure can be applied to, for example, the imaging unit 11402 of the camera 11102.

[0271] Although described here by taking the endoscopic surgical system as an example, the technology according to the present disclosure can also be applied to, for example, a microsurgical system or the like.

[0272] 《7. Application to Mobile Objects》

[0273] The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any of the following types of mobile objects, such as: cars, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, or robots.

[0274] Figure 26 It is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0275] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In Figure 26 In the example shown, the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio-visual output unit 12052, and a vehicle network interface (I / F) 12053 are shown.

[0276] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as devices such as a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a control device for a braking device for generating the braking force of the vehicle.

[0277] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 serves as the following devices: a keyless entry system; a smart key system; an automatic window device; or a control device for various lights such as headlights, taillights, brake lights, signals, or fog lights. In this case, the body system control unit 12020 can receive radio waves transmitted from a portable device that replaces the key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, automatic window device, and lights of the vehicle.

[0278] The external information detection unit 12030 detects the external information of the vehicle on which the vehicle control system 12000 is mounted. For example, a camera unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the camera unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the external information detection unit 12030 can perform object detection processing or distance detection processing on pedestrians, vehicles, obstacles, traffic signs, or letters on the road surface.

[0279] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The camera unit 12031 can output the electrical signal as an image or can output the electrical signal as distance measurement information. In addition, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0280] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the driver state detection unit 12041 for detecting the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera for photographing the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level based on the detection information input from the driver state detection unit 12041, or can determine whether the driver is sleeping.

[0281] The microcomputer 12051 is capable of calculating control target values for the driving force generating device, the steering mechanism, or the braking device based on the information outside and inside the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, and outputting control commands to the drive system control unit 12010. For example, the microcomputer 12051 is capable of performing cooperative control for implementing functions of an advanced driver assistance system (ADAS), and the functions of the advanced driver assistance system include: collision avoidance or impact mitigation of the vehicle, tracking based on the inter-vehicle distance, vehicle speed maintenance, collision warning of the vehicle, or lane departure warning of the vehicle.

[0282] In addition, the microcomputer 12051 is also capable of controlling the driving force generating device, the steering mechanism, or the braking device based on the information around the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, so as to perform cooperative control for autonomous driving that enables the vehicle to drive autonomously without depending on the driver's operation.

[0283] Furthermore, based on the external information of the vehicle acquired by the out-vehicle information detection unit 12030, the microcomputer 12051 is capable of outputting control commands to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights according to the positions of the vehicle in front or oncoming vehicles detected by the out-vehicle information detection unit 12030, and can perform coordinated control for anti-glare (for example, switching the high beam to the low beam).

[0284] The sound and image output unit 12052 sends output signals of at least one of sound and image to an output device, and the output device can provide information visually or auditorily to passengers in the vehicle or outside the vehicle. In Figure 26 the example, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 can include at least one of an on-board display and a head-up display.

[0285] Figure 27 This is a diagram showing an example of the installation position of the imaging unit 12031.

[0286] In Figure 27 this, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0287] For example, the imaging units 12101, 12102, 12103, 12104, and 12105 are set at positions including the front nose, rearview mirror, rear bumper, rear door, and the upper part of the windshield inside the vehicle of the vehicle 12100. The imaging unit 12101 set at the front nose and the imaging unit 12105 set at the upper part of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 set at the rearview mirror mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 set at the rear bumper or the rear door mainly acquires images behind the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used to detect the vehicle in front, pedestrians, obstacles, traffic lights, traffic signs, or lanes, etc.

[0288] Note that Figure 27 this shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 set at the front nose, the imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set at the rearview mirror, and the imaging range 12114 represents the imaging range of the imaging unit 12104 set at the rear bumper or the rear door. For example, by superimposing the image data acquired by the imaging units 12101 to 12104, a top-down view image of the vehicle 12100 when viewed from above is obtained.

[0289] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0290] For example, the microcomputer 12051 uses the distance information obtained from the imaging units 12101 to 12104 to determine the distance to the three-dimensional objects within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), so that the following three-dimensional objects can be extracted as the preceding vehicle: In particular, the three-dimensional object is closest to the vehicle 12100 on the driving road and travels at a predetermined speed (for example, greater than or equal to 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can preset the inter-vehicle distance to be ensured in front of the preceding vehicle and can execute automatic braking control (including following stop control) and automatic acceleration control (including following start control), etc. In this way, cooperative control for implementing autonomous driving such as autonomous driving that does not depend on the driver's operation can be executed.

[0291] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object based on the distance information obtained from the imaging units 12101 to 12104, extract other three-dimensional objects such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and utility poles, and use the extracted data to automatically avoid obstacles. For example, the microcomputer 12051 classifies the obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles that are difficult to visually identify. In addition, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. If the collision risk is higher than the set value and indicates the possibility of collision, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 or the display unit 12062, or execute forced deceleration or avoidance steering through the drive system control unit 12010 to assist driving to avoid collision.

[0292] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, the following process is performed to execute such pedestrian recognition: determining whether a person is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object; and extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 such that the display unit 12062 displays a rectangular outline line for emphasizing the identified pedestrian in a superimposed manner. In addition, the audio-visual output unit 12052 may control the display unit 12062 to cause the display unit 12062 to display an icon or the like for representing a pedestrian at a desired position.

[0293] Examples of the vehicle control system to which the technology according to the present disclosure can be applied have been described above. The technology according to the present disclosure is applicable to the imaging unit 12031 and the like in the above configuration.

[0294] <<8. Conclusion>>

[0295] As described above, according to an embodiment of the present disclosure, a pixel 100 having a pixel transistor (amplification transistor TR amp , selection transistor TR sel and reset transistor TR rst ) and wiring can be provided. While suppressing an increase in manufacturing cost, the pixel 100 can effectively output and transmit a pixel signal by charges generated by the photoelectric conversion film 112.

[0296] Note that in the above embodiment of the present disclosure, the case where it is applied to a back-illuminated CMOS image sensor structure has been described, but the embodiment of the present disclosure is not limited thereto and is applicable to other structures.

[0297] Note that in the above embodiment of the present disclosure, the pixel 100 in which the first conductivity type is P-type, the second conductivity type is N-type, and electrons are used as signal charges has been described, but the embodiment of the present disclosure is not limited to such an example. For example, the present embodiment is also applicable to a pixel 100 in which the first conductivity type is N-type, the second conductivity type is P-type, and holes are used as signal charges.

[0298] In addition, in the above-described embodiments of the present disclosure, the semiconductor substrate 300 may not be a silicon substrate and may be another substrate (e.g., a silicon-on-insulator (SOI) substrate or a SiGe substrate). Further, the semiconductor substrate 300 may include semiconductor structures formed on the above various substrates and the like.

[0299] In addition, in the above-described embodiments of the present disclosure and with reference to the accompanying drawings, various insulating films are shown in a simplified manner for ease of understanding. However, in reality, these insulating films may be laminated films composed of a plurality of different insulating materials, or may be laminated films formed through a plurality of different steps.

[0300] In addition, the solid-state imaging device 1 according to an embodiment of the present disclosure is not limited to a solid-state imaging device that detects the distribution of the incident light amount of visible light and forms an image. For example, the present embodiment is applicable to a solid-state imaging device that forms an image from an incident amount distribution (e.g., infrared rays, X-rays, or particles), or a solid-state imaging device (physical quantity distribution detection device) that detects the distribution of other physical quantities (e.g., pressure and capacitance) and forms an image, such as a fingerprint detection sensor.

[0301] "9. Supplementary"

[0302] As described above, the advantageous embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, but the technical scope of the present disclosure is not limited to the above examples. Obviously, various changes or corrections within the scope of the technical concept described in the appended claims can be conceived by those of ordinary skill in the technical field of the present disclosure, and it should be understood that such changes or corrections will naturally belong to the technical scope of the present disclosure.

[0303] In addition, the effects described in this specification are merely illustrative or exemplary and not restrictive. That is, in addition to or instead of the above effects, the technology according to the present disclosure can also exhibit other effects that are obvious to those skilled in the art from the description of this specification.

[0304] Note that the following configurations also belong to the technical scope of the present disclosure. (1)

[0306] A solid-state imaging element, comprising:

[0307] A semiconductor substrate;

[0308] A first photoelectric conversion unit disposed on the semiconductor substrate; and

[0309] A control unit disposed to be stacked with the first photoelectric conversion unit and including a plurality of pixel transistors for controlling the first photoelectric conversion unit, wherein

[0310] The first photoelectric conversion unit includes:

[0311] a second electrode

[0312] a first photoelectric conversion film, which is disposed above the second electrode and converts light into charges, and

[0313] a first electrode, which is disposed on the first photoelectric conversion film

[0314] the plurality of pixel transistors include an amplifying transistor that amplifies the charges and outputs the charges as pixel signals, and

[0315] a channel formation region of the amplifying transistor is formed of an oxide semiconductor layer. (2)

[0317] The solid-state imaging device according to (1), wherein

[0318] the plurality of pixel transistors further include:

[0319] a transfer transistor that transfers charges from the first photoelectric conversion unit, and

[0320] a channel formation region of the transfer transistor is formed of an oxide semiconductor layer. (3)

[0322] The solid-state imaging device according to (1) or (2), wherein

[0323] the plurality of pixel transistors further include:

[0324] a reset transistor that resets the stored charges; and

[0325] a selection transistor that outputs the pixel signal according to a selection signal, and

[0326] a channel formation region of at least one of the reset transistor and the selection transistor is formed of an oxide semiconductor layer. (4)

[0328] The solid-state imaging device according to any one of (1) to (3), wherein

[0329] the channel formation region of the amplifying transistor is formed of an oxide semiconductor layer that is common to the channel formation regions of at least one of the pixel transistors other than the amplifying transistor among the plurality of pixel transistors. (5)

[0331] The solid-state imaging device according to any one of (1) to (4), wherein the oxide semiconductor layer is disposed to be stacked with the control unit. (6)

[0333] The solid-state imaging device according to any one of (1) to (5), wherein the first photoelectric conversion film is formed of an organic photoelectric conversion film. (7)

[0335] The solid-state imaging device according to any one of (1) to (6), wherein the semiconductor substrate includes a second photoelectric conversion unit that converts light into electric charges. (8)

[0337] The solid-state imaging device according to (7), wherein the control unit is provided between the first photoelectric conversion unit and the semiconductor substrate. (9)

[0339] The solid-state imaging device according to (8) further includes a third photoelectric conversion unit that is provided between the control unit and the semiconductor substrate and converts light into electric charges. (10)

[0341] The solid-state imaging device according to (7), wherein the first photoelectric conversion unit is provided between the control unit and the semiconductor substrate. (11)

[0343] The solid-state imaging device according to (10) further includes a third photoelectric conversion unit that is provided between the first photoelectric conversion unit and the semiconductor substrate and converts light into electric charges. (12)

[0345] The solid-state imaging device according to (9) or (11), wherein the third photoelectric conversion unit includes a third photoelectric conversion film that converts light into electric charges, and the third photoelectric conversion film is formed of an organic photoelectric conversion film. (13)

[0347] The solid-state imaging device according to (1), wherein

[0348] the control unit includes:

[0349] a driving wiring layer having a plurality of driving lines for driving the plurality of pixel transistors;

[0350] a power signal wiring layer having a plurality of power supply lines for applying a power supply voltage to the plurality of pixel transistors and a plurality of signal lines for transmitting pixel signals; and

[0351] a gate electrode layer having a plurality of gate electrodes of the plurality of pixel transistors,

[0352] The driving wiring layer, the power signal wiring layer, and the gate electrode layer are respectively arranged to be stacked with the oxide semiconductor layer. (14)

[0354] The solid-state imaging device according to (13), wherein the driving line is formed of at least one of Cu, Al, W, Ti, TiN, Ta, and TaN. (15)

[0356] The solid-state imaging device according to (13) or (14), wherein at least one of the power line, the signal line, and the gate electrode is formed of a transparent conductive film. (16)

[0358] The solid-state imaging device according to any one of (13) to (15), wherein the wiring width of the signal line is larger than the wiring width of the driving line. (17)

[0360] The solid-state imaging device according to any one of (13) to (16), wherein the gate electrode layer further has a shielding electrode that surrounds the plurality of pixel transistors. (18)

[0362] The solid-state imaging device according to any one of (1) to (17), wherein the first photoelectric conversion unit further includes a storage control film that contacts the first photoelectric conversion film, and an insulating film is interposed between the storage control film and the first photoelectric conversion film. (19)

[0364] The solid-state imaging device according to any one of (1) to (7), wherein the first photoelectric conversion unit includes two pixel partitions that are line-symmetric when viewed from above the semiconductor substrate. (20)

[0366] A method for manufacturing a solid-state imaging device, comprising:

[0367] Forming an oxide semiconductor layer as a channel formation region of a pixel transistor above a semiconductor substrate;

[0368] Forming a gate electrode layer including a plurality of gate electrodes of a plurality of pixel transistors above the oxide semiconductor layer;

[0369] Forming a power signal wiring layer above the gate electrode layer, the power signal wiring layer including a plurality of power lines for applying a power voltage to the plurality of pixel transistors and a plurality of signal lines for transmitting pixel signals;

[0370] Above the power signal wiring layer, a driving wiring layer is formed, and the driving wiring layer includes a plurality of driving lines for driving the plurality of pixel transistors;

[0371] A second electrode is formed above the driving wiring layer;

[0372] A first photoelectric conversion film is formed above the second electrode; and

[0373] A first electrode is formed on the first photoelectric conversion film. (21)

[0375] The method for manufacturing a solid-state imaging device according to (20) further includes:

[0376] A first sealing film is formed on the first electrode; and

[0377] Another semiconductor substrate having a second photoelectric conversion unit and a second sealing film provided on the second photoelectric conversion unit is bonded to the semiconductor substrate such that the first sealing film and the second sealing film face each other.

[0378] List of reference numerals

[0379] 1 Solid-state imaging device

[0380] 10 Pixel array unit

[0381] 32 Vertical driving circuit unit

[0382] 34 Column signal processing circuit unit

[0383] 36 Horizontal driving circuit unit

[0384] 38 Output circuit unit

[0385] 40 Control circuit unit

[0386] 42 Pixel driving line

[0387] 44 Vertical signal line

[0388] 46 Horizontal signal line

[0389] 48 Input / output terminal

[0390] 70 Pixel transistor region

[0391] 80 Peripheral circuit unit

[0392] 100, 100a, 100b Pixel

[0393] 102, 102a, 102b On-chip lens

[0394] 104,144,204 Sealing film

[0395] 108,134,208 Shielding electrode

[0396] 110,210 Upper electrode

[0397] 112,212 Photoelectric conversion film

[0398] 114,114a,114b,214 Storage electrode

[0399] 116,216 Lower electrode

[0400] 118,130,132,146,218,324,504 Insulating film

[0401] 120 Multilayer wiring layer

[0402] 124,206,250,306 Wiring

[0403] 122,122a,122b,122f,122r,122s,124f,124r,124s Driving line

[0404] 124vd Power supply line

[0405] 124vs Signal line

[0406] 126,126am,126r,126s Gate electrode

[0407] 128,502 Contact

[0408] 140,142,240 Oxide semiconductor layer

[0409] 300,300a,300b,500 Semiconductor substrate

[0410] 302 Through electrode

[0411] 310 Electrode

[0412] 312a,312b Semiconductor region

[0413] 320 Isolation insulating film

[0414] 322a Source / drain region

[0415] 322b Floating diffusion unit

[0416] 400,402,404 Waveguide

[0417] 600,602,604 Internal lens

[0418] 800, 802, 804 Barrier layer

[0419] 700 Electronic device

[0420] 702 Imaging device

[0421] 710 Optical lens

[0422] 712 Shutter mechanism

[0423] 714 Driving circuit unit

[0424] 716 Signal processing circuit unit.

Claims

1. A solid-state imaging device, comprising: Semiconductor substrate; A first photoelectric conversion unit disposed on the semiconductor substrate; And A control unit disposed to be stacked with the first photoelectric conversion unit and including a plurality of pixel transistors for controlling the first photoelectric conversion unit, wherein, The first photoelectric conversion unit includes: A second electrode, A first photoelectric conversion film disposed above the second electrode and converting light into charges, and A first electrode disposed on the first photoelectric conversion film, The plurality of pixel transistors include an amplification transistor that amplifies the charges and outputs the charges as pixel signals, and A channel formation region of the amplification transistor is formed of an oxide semiconductor layer capable of transmitting light, Wherein, the semiconductor substrate includes a second photoelectric conversion unit that converts light into charges, Wherein, the control unit is disposed between the first photoelectric conversion unit and the semiconductor substrate, Wherein, the channel formation region of the amplification transistor is stacked above the second photoelectric conversion unit.

2. A solid-state imaging device, comprising: Semiconductor substrate; A first photoelectric conversion unit disposed on the semiconductor substrate; And A control unit disposed to be stacked with the first photoelectric conversion unit and including a plurality of pixel transistors for controlling the first photoelectric conversion unit, wherein, The first photoelectric conversion unit includes: A second electrode, A first photoelectric conversion film disposed above the second electrode and converting light into charges, and A first electrode disposed on the first photoelectric conversion film, The plurality of pixel transistors include an amplification transistor that amplifies the charges and outputs the charges as pixel signals, and A channel formation region of the amplification transistor is formed of an oxide semiconductor layer, Wherein, the semiconductor substrate includes a second photoelectric conversion unit that converts light into charges, Wherein, the first photoelectric conversion unit is disposed between the control unit and the semiconductor substrate.

3. The solid-state imaging device according to claim 1 or 2, wherein, The plurality of pixel transistors further include: A transfer transistor that transfers the charges from the first photoelectric conversion unit, and A channel formation region of the transfer transistor is formed of an oxide semiconductor layer.

4. The solid-state imaging device according to claim 1 or 2, wherein, The plurality of pixel transistors further include: A reset transistor that resets the stored charges; and A selection transistor that outputs the pixel signal according to a selection signal, and A channel formation region of at least one of the reset transistor and the selection transistor is formed of an oxide semiconductor layer.

5. The solid-state imaging device according to claim 1 or 2, wherein, The channel formation region of the amplification transistor is formed of an oxide semiconductor layer common to at least one of the pixel transistors other than the amplification transistor among the plurality of pixel transistors.

6. The solid-state imaging device according to claim 1 or 2, wherein, The oxide semiconductor layer is disposed to be stacked with the control unit.

7. The solid-state imaging device according to claim 1 or 2, wherein, The first photoelectric conversion film is formed of an organic photoelectric conversion film.

8. The solid-state imaging device according to claim 1, further comprising a third photoelectric conversion unit disposed between the control unit and the semiconductor substrate, and converting light into electric charges.

9. The solid-state imaging device according to claim 2, further comprising a third photoelectric conversion unit disposed between the first photoelectric conversion unit and the semiconductor substrate, and converting light into electric charges.

10. The solid-state imaging device according to claim 8, wherein, The third photoelectric conversion unit includes a third photoelectric conversion film that converts light into charges, and the third photoelectric conversion film is formed of an organic photoelectric conversion film.

11. The solid-state imaging device according to claim 1 or 2, wherein, The control unit includes: A driving wiring layer having a plurality of driving lines for driving the plurality of pixel transistors; A power signal wiring layer having a plurality of power lines for applying a power voltage to the plurality of pixel transistors and a plurality of signal lines for transmitting pixel signals; and A gate electrode layer having a plurality of gate electrodes of the plurality of pixel transistors, wherein the driving wiring layer, the power signal wiring layer, and the gate electrode layer are respectively arranged to be stacked with the oxide semiconductor layer.

12. The solid-state imaging device according to claim 11, wherein, The driving line is formed of at least one of Cu, Al, W, Ti, TiN, Ta, and TaN.

13. The solid-state imaging device according to claim 11, wherein, At least one of the power line, the signal line, and the gate electrode is formed of a transparent conductive film.

14. The solid-state imaging device according to claim 11, wherein, The wiring width of the signal line is greater than the wiring width of the driving line.

15. The solid-state imaging device according to claim 11, wherein, The gate electrode layer further has a shielding electrode surrounding the plurality of pixel transistors.

16. The solid-state imaging device according to claim 1 or 2, wherein, The first photoelectric conversion unit further includes a storage control film that contacts the first photoelectric conversion film via an insulating film, and the insulating film is interposed between the storage control film and the first photoelectric conversion film.

17. The solid-state imaging device according to claim 1 or 2, wherein, The first photoelectric conversion unit includes two pixel partitions, and when viewed from above the semiconductor substrate, the two pixel partitions are in a line-symmetric relationship.

18. A method for manufacturing a solid-state imaging device, comprising: Above the semiconductor substrate, an oxide semiconductor layer serving as a channel formation region of a pixel transistor is formed; Above the oxide semiconductor layer, a gate electrode layer including a plurality of gate electrodes of a plurality of pixel transistors is formed; Above the gate electrode layer, a power signal wiring layer is formed, and the power signal wiring layer includes a plurality of power lines for applying a power voltage to the plurality of pixel transistors and a plurality of signal lines for transmitting pixel signals; Above the power signal wiring layer, a driving wiring layer is formed, and the driving wiring layer includes a plurality of driving lines for driving the plurality of pixel transistors; A second electrode is formed above the driving wiring layer; A first photoelectric conversion film is formed above the second electrode; and A first electrode is formed on the first photoelectric conversion film, wherein the method further includes: forming a first sealing film on the first electrode; and bonding another semiconductor substrate having a second photoelectric conversion unit and a second sealing film provided on the second photoelectric conversion unit to the semiconductor substrate such that the first sealing film and the second sealing film face each other.

Images