Chip stacking semiconductor package and manufacturing method thereof

Abstract

A chip-stacked semiconductor package includes: a first chip, which includes a first detection pad and a second detection pad; a second chip, which is arranged on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium and a second medium, the first medium is arranged between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and the second medium is different from the first medium, and the second medium is arranged between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2019-0075789 filed on June 25, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present inventive concept relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a chip-stacked semiconductor package and a method of manufacturing the chip-stacked semiconductor package. Background Art

[0004] Chip-stacked semiconductor packages, which vertically stack multiple chips (semiconductor chips), are used in high-capacity, high-performance, and multifunctional electronic devices. During the in-line process of manufacturing a chip-stacked semiconductor package by stacking a second chip on a first chip, the stacking quality needs to be evaluated by measuring the stacking accuracy between the first and second chips or measuring or detecting the joint gap between the first and second chips. The reliability of the chip-stacked semiconductor package may depend on the stacking quality. Summary of the Invention

[0005] The present inventive concept provides a chip-stacked semiconductor package in which a stacking accuracy between a first chip and a second chip or a bonding gap between the first chip and the second chip can be measured.

[0006] The present inventive concept provides a method of manufacturing the aforementioned chip-stacked semiconductor package.

[0007] According to one aspect of the present disclosure, a chip-stacked semiconductor package is provided, comprising: a first chip including a first detection pad and a second detection pad; a second chip arranged on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium and a second medium, the first medium being arranged between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and the second medium being different from the first medium, and the second medium being arranged between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

[0008] According to another aspect of the present disclosure, a chip-stacked semiconductor package is provided, comprising: a first chip, comprising a first detection pad, a second detection pad, a first test terminal, and a second test terminal, the first test terminal being electrically connected to the first detection pad, and the second test terminal being electrically connected to the second detection pad; and a second chip, which is arranged on the first chip and has a gap between the first chip and the second chip, and the second chip comprises a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad, wherein the third detection pad overlaps with the first detection pad and is connected to the first detection pad through a medium, wherein the fourth detection pad is not connected to the second detection pad through the medium, wherein the fourth detection pad is electrically connected to the third detection pad via a conductive line, and wherein the first test terminal and the second test terminal are constructed to measure the capacitance between the second detection pad and the fourth detection pad.

[0009] According to another aspect of the present disclosure, a chip-stacked semiconductor package is provided, comprising: a first chip, comprising a first connecting member and a first chip pad, the first connecting member being respectively arranged on one surface of each of the through-silicon vias and electrically connected to the through-silicon vias, and the first chip pad being respectively located on the other surface of each of the through-silicon vias and electrically connected to the through-silicon vias; a second chip, which is located on the first chip and comprises a second connecting member electrically connected to the first chip pad, wherein the second connecting member comprises a bump and a second chip pad; and a sealant configured to seal a space between the second connecting members and between the first chip pads between the first chip and the second chip, wherein a first of the first chip pads forms a first detection pad, a second of the first chip pads forms a second detection pad, wherein a first of the second chip pads forms a third detection pad connected to the first detection pad, and a second of the second chip pads forms a fourth detection pad, wherein the fourth detection pad is not connected to the second detection pad, and wherein the fourth detection pad is electrically connected to the third detection pad via a conductive line.

[0010] According to another aspect of the present disclosure, a method for manufacturing a chip-stacked semiconductor package is provided, the method comprising: providing a first chip including a first detection pad, a second detection pad, a first test terminal, and a second test terminal, the first test terminal being electrically connected to the first detection pad, and the second test terminal being electrically connected to the second detection pad; stacking a second chip on the first chip with a gap between the first chip and the second chip, wherein the second chip includes a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; arranging the third detection pad to overlap with the first detection pad and connecting the first detection pad to the third detection pad through a first medium; providing a second medium between the fourth detection pad and the second detection pad, the second medium being different from the first medium; electrically connecting the fourth detection pad to the third detection pad via a conductive line; and measuring the capacitance between the second detection pad and the fourth detection pad by utilizing the first test terminal and the second test terminal.

[0011] According to another aspect of the present disclosure, a test device for testing a chip-stacked semiconductor package is provided, wherein the chip-stacked semiconductor package includes a first chip and a second chip, the first chip includes a first detection pad and a second detection pad, the second chip is stacked on the first chip, and there is a gap between the first chip and the second chip, and the second chip includes a third detection pad and a fourth detection pad, the third detection pad faces the first detection pad, and there is a first medium between the third detection pad and the first detection pad, the fourth detection pad faces the second detection pad, and there is a second medium between the fourth detection pad and the second detection pad, the test device includes: a memory that stores one or more instructions; and one or more processors that are constructed to execute the one or more instructions to: apply a first voltage to the first detection pad; measure a second voltage at the second detection pad, the second voltage corresponding to the first voltage propagated through the first detection pad, the third detection pad, the fourth detection pad, and the second detection pad; and obtain the capacitance between the second detection pad and the fourth detection pad based on the second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 and Figure 2 is a diagram for explaining a basic structure of a chip-stacked semiconductor package according to an embodiment of the present inventive concept, and a method of detecting stacking accuracy and a bonding gap between chips by using the basic structure;

[0014] Figure 3 Is used to explain the Figure 1 and Figure 2A diagram showing capacitance measurement of a chip-stacked semiconductor package;

[0015] Figures 4A to 4C Is used to explain Figure 1 and Figure 2 A plan view of the stacking accuracy of a chip-stacked semiconductor package;

[0016] Figures 5A to 5C Is used to explain Figure 1 and Figure 2 A cross-sectional view of a bonding gap of a chip stacked semiconductor package;

[0017] Figure 6 and Figure 7 is a layout diagram of a chip-stacked semiconductor package according to an embodiment of the inventive concept;

[0018] Figure 8 and Figure 9 is a layout diagram of a chip-stacked semiconductor package according to an embodiment of the inventive concept;

[0019] Figure 10A and Figure 10B is a plan view illustrating shapes and sizes of chip pads and inspection pads of a chip-stacked semiconductor package according to an embodiment of the inventive concept;

[0020] Figure 11 is a cross-sectional view of a chip-stacked semiconductor package according to an embodiment of the present inventive concept;

[0021] Figures 12A to 12G Is used to explain the manufacturing Figure 11 A cross-sectional view of a method for stacking chips in a semiconductor package;

[0022] Figure 13 and Figure 14 are cross-sectional views of semiconductor package systems each including a chip stacked semiconductor package according to an embodiment of the inventive concept;

[0023] Figure 15 and Figure 16 is a cross-sectional view of a chip-stacked semiconductor package according to an embodiment of the present inventive concept;

[0024] Figures 17A to 17G Is used to explain the manufacturing Figure 15 A cross-sectional view of a method for stacking chips in a semiconductor package; and

[0025] Figure 18 and Figure 19 is a cross-sectional view of a semiconductor package system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0026] The present invention will now be described more fully with reference to the accompanying drawings showing exemplary embodiments of the present invention. One embodiment may be implemented, or multiple embodiments may be combined and implemented. However, the present invention is not limited to these embodiments.

[0027] In the description herein, terms such as "first" and "second" are used to distinguish components and are not used to limit the components themselves or to indicate a specific order. In addition, descriptions such as being located "on," "top," "bottom," or "side" of a component indicate a relative positional relationship and do not indicate a specific situation such as being in direct contact with the component or being introduced at the interface between the other component and the component.

[0028] In addition, when one element is “coupled to” or “connected to” another element, the one element may be directly electrically or mechanically coupled to or directly electrically or mechanically connected to the other element, or a third element may be present between the one element and the other element.

[0029] Figure 1 and Figure 2 is a diagram for explaining a basic structure of a chip-stacked semiconductor package according to an embodiment of the inventive concept, and a method of detecting stacking accuracy and a bonding gap between chips by using the basic structure.

[0030] In detail, Figure 1 is a perspective view of a chip stacked semiconductor package CSP in which second chips 22 are stacked on first chips 12 , respectively. Figure 2 It is at A-A' along Figure 1 Cross-sectional view taken in the Y direction. Figure 1 and Figure 2 1 and 2 are diagrams for explaining detection of stacking accuracy and bonding gap between the first chip 12 and the second chip 22 by using the first inspection pad group MPD1 of the first chip 12 and the second inspection pad group MPD2 of the second chip 22 .

[0031] exist Figure 1 and Figure 2 , the X direction and the Y direction indicate horizontal directions parallel to respective surfaces of the first chip 12 and the second chip 22 , and the Z direction indicates a direction perpendicular to respective surfaces of the first chip 12 and the second chip 22 .

[0032] The first chip 12 may include a first chip region 13 and a first scribe region 15 surrounding the first chip region 13. According to an embodiment, the first scribe region 15 may be near the first chip region 13. According to an embodiment, the first scribe region 15 may be adjacent to the first chip region 13. According to an embodiment, the first scribe region 15 may be directly adjacent to the first chip region 13. For ease of explanation, Figure 1Only one first scribe line region 15 is shown. The first chip 12 may be a wafer-level chip or a chip-level chip. The first scribe line region 15 may be cut out from the final structure of the chip-stacked semiconductor package CSP, and thus the first scribe line region 15 may be partially or completely removed.

[0033] According to an embodiment, a plurality of first chip pads PD1 are formed in the first chip region 13. According to an embodiment, the first inspection pad group MPD1 may include one or more of the first chip pads PD1. That is, some of the first chip pads PD1 may constitute the first inspection pad group MPD1. The first inspection pad group MPD1 may include a first inspection pad 14 and a second inspection pad 16.

[0034] According to an embodiment, the first inspection pad 14 may be positioned adjacent to the second inspection pad 16. According to an embodiment, the planar shape of the first inspection pad 14 and the second inspection pad 16 may be circular. According to an embodiment, the radius of each of the first inspection pad 14 and the second inspection pad 16 may be 10 μm to 400 μm. According to an embodiment, although the planar size of the first inspection pad 14 and the second inspection pad 16 constituting the first inspection pad group MPD1 is the same as the planar size of each of the other first chip pads PD1 that are not part of the first inspection pad group MPD1, according to another embodiment, the planar size of the first inspection pad 14 and the second inspection pad 16 may be larger than the planar size of each of the other first chip pads PD1.

[0035] For example, when the radius of each of the other first chip pads PD1 is 10 μm to 20 μm, the radius of each of the first inspection pad 14 and the second inspection pad 16 may be 50 μm to 400 μm. Although the first chip pads PD1 are shown as being formed on the entire surface of the chip body layer, they may be formed on an edge portion or a central portion of the chip body layer.

[0036] The test terminal group TPD is formed on the first scribe area 15. The test terminal group TPD includes a first test terminal 17 and a second test terminal 19. The first test terminal 17 can be electrically connected to the first test pad 14 through a first conductive line 29a. The second test terminal 19 can be electrically connected to the second test pad 16 through a second conductive line 29e.

[0037] The first conductive line 29a and the second conductive line 29e may be wirings formed on the first chip 12. When the first scribe area 15 is cut during manufacturing, the first test terminal 17 and the second test terminal 19 may partially remain in the first scribe area 15 of the final structure of the chip-stacked semiconductor package CSP. In addition, when the first scribe area 15 is cut during manufacturing, the first conductive line 29a and the second conductive line 29e may remain in the first scribe area 15 of the final structure of the chip-stacked semiconductor package CSP.

[0038] The second chip 22 may be stacked on the first chip 12. The second chip 22 may include a second chip region 23. The second chip 22 may be a chip-level chip. A plurality of second chip pads PD2 are formed on the second chip region 23. According to an embodiment, the second test pad group MPD2 may include one or more of the second chip pads PD2. That is, some of the second chip pads PD2 constitute the second test pad group MPD2. The second test pad group MPD2 may include a third test pad 24 and a fourth test pad 26.

[0039] According to an embodiment, third inspection pad 24 may be positioned adjacent to fourth inspection pad 26. A planar shape of each of third inspection pad 24 and fourth inspection pad 26 may be circular. According to an embodiment, a radius of each of third inspection pad 24 and fourth inspection pad 26 may be 10 μm to 400 μm.

[0040] According to an embodiment, although the planar dimensions of the third inspection pad 24 and the fourth inspection pad 26 constituting the second inspection pad group MPD2 are the same as the planar dimensions of each of the other second chip pads PD2 that are not part of the second inspection pad group MPD2, according to another embodiment, the planar dimensions of the third inspection pad 24 and the fourth inspection pad 26 may be larger than the planar dimensions of each of the other second chip pads PD2. For example, when the radius of the other second chip pads PD2 is 10 μm to 20 μm, the radius of each of the third inspection pad 24 and the fourth inspection pad 26 may be 50 μm to 400 μm. Although the second chip pads PD2 are shown as being formed on the entire surface of the chip body layer, they may be formed on the edge portion or the central portion of the chip body layer. The third inspection pad 24 may be electrically connected to the fourth inspection pad 26 via a third conductive line 29 c. The third conductive line 29 c may be a wiring formed on the second chip 22.

[0041] The third and fourth detection pads 24 and 26 may face the first and second detection pads 14 and 16, respectively. A dielectric element 18 (ME) electrically and physically connecting the first and third detection pads 14 and 24 may be located between the first chip 12 and the second chip 22. The dielectric element 18 (ME) may be a bump, such as a solder bump. Thus, the first detection pads 14 of the first chip 12 and the third detection pads 24 of the second chip 22 may be electrically and physically connected to each other via the dielectric element 18 (ME) forming the fourth conductive line 29b.

[0042] According to an embodiment, a non-dielectric element 20 (NME) may be located between the first chip 12 and the second chip 22, such that the second detection pad 16 and the fourth detection pad 26 are not physically connected to each other. According to an embodiment, the non-dielectric element 20 (NME) may be a sealant (or encapsulant). Therefore, the second detection pad 16 of the first chip 12 and the fourth detection pad 26 of the second chip 22 are not physically connected to each other. However, the second detection pad 16 of the first chip 12 and the fourth detection pad 26 of the second chip 22 may be electrically connected via a fifth conductive line 29d based on a capacitive effect.

[0043] According to an embodiment, dielectric element 18 (ME) may include a material having high electrical conductivity, such as metal, to electrically connect first detection pad 14 of first chip 12 and third detection pad 24 of second chip 22. On the other hand, non-dielectric element 20 (NME) may include a material having low electrical conductivity, such as an insulator or a dielectric element, to generate a capacitive effect between the capacitive connection of second detection pad 16 of first chip 12 and fourth detection pad 26 of second chip 22.

[0044] The chip stacked semiconductor package CSP may inspect the stacking accuracy and the bonding gap between the first chip 12 and the second chip 22 by using the first inspection pad group MPD1 of the first chip 12 and the second inspection pad group MPD2 of the second chip 22 .

[0045] In detail, the chip stacked semiconductor package CSP can measure the capacitance between the second detection pad 16 and the fourth detection pad 26 by applying a voltage to the first test terminal 17 and the second test terminal 19 using the test equipment 28. For example, the test equipment 28 can apply a voltage to the first conductive line 29a, the fourth conductive line 29b, the third conductive line 29c, the fifth conductive line 29d, and the second conductive line 29e, thereby measuring the capacitance between the second detection pad 16 and the fourth detection pad 26.

[0046] According to an embodiment, a test device 28 measures a chip-stacked semiconductor package, the chip-stacked semiconductor package including a first chip and a second chip, the first chip having a first detection pad and a second detection pad, the second chip stacked on the first chip with a gap between the first and second chips, the second chip having a third detection pad and a fourth detection pad, the third detection pad facing the first detection pad and having a first dielectric between the third detection pad and the first detection pad, the fourth detection pad facing the second detection pad and having a second dielectric between the fourth detection pad and the second detection pad. The test device may include a memory and one or more processors, the memory storing one or more instructions, the one or more processors being configured to execute the one or more instructions to: apply a first voltage to the first detection pad; measure a second voltage at the second detection pad, the second voltage corresponding to the first voltage propagated through the first, third, fourth, and second detection pads; and obtain a capacitance between the second detection pad and the fourth detection pad based on the measured second voltage.

[0047] According to an embodiment, the one or more processors may be configured to obtain one of stacking accuracy and bonding gap information between the first chip and the second chip based on the measured capacitance. According to an embodiment, the one or more processors may be configured to: identify the overlapping area between the second inspection pad and the fourth inspection pad based on the measured capacitance; and obtain the stacking accuracy between the first chip and the second chip based on the overlapping area. According to an embodiment, the one or more processors may be configured to: identify the distance between the second inspection pad and the fourth inspection pad based on the measured capacitance; and obtain the bonding gap information between the first chip and the second chip based on the measured distance.

[0048] When measuring the capacitance between the second inspection pad 16 and the fourth inspection pad 26, the stacking accuracy between the first chip 12 and the second chip 22 can be detected based on the area of horizontal overlap between the first inspection pad 14 of the first chip 12 and the third inspection pad 24 of the second chip 22. Therefore, the chip stacked semiconductor package CSP according to the present invention can detect the stacking accuracy between the first chip 12 and the second chip 22 during the in-line manufacturing process without being affected by the process of cutting the second chip 22.

[0049] When the chip-stacked semiconductor package CSP according to the present invention measures the capacitance between the second inspection pad 16 and the fourth inspection pad 26, the chip-stacked semiconductor package CSP can detect the joint gap between the first chip 12 and the second chip 22. Therefore, the chip-stacked semiconductor package CSP according to the present invention can non-destructively measure and obtain the joint gap during an in-line manufacturing process. Detecting stacking accuracy and joint gaps through capacitance measurement in the chip-stacked semiconductor package CSP according to the present invention will be described in more detail later.

[0050] Figure 3 Is used to explain the Figure 1 and Figure 2 Diagram of the measured capacitance of a chip stacked semiconductor package (CSP).

[0051] In detail, Figure 3 in Figure 1 and Figure 2 The same reference numerals as in the drawings refer to the same elements. Figure 1 and Figure 2 The chip stacked semiconductor package CSP can measure capacitance between the second inspection pad 16 of the first chip 12 and the fourth inspection pad 26 of the second chip 22 , which are separated from each other by a gap d, by using a test device 28 .

[0052] The capacitance can be C=ε0*ε r *(A / d), where C may indicate capacitance, A may indicate the area of the second detection pad 16 or the fourth detection pad 26, d may indicate the distance between the second detection pad 16 and the fourth detection pad 26, ε0 may indicate the vacuum dielectric constant, and ε r The relative dielectric constant of the dielectric between the second detection pad 16 and the fourth detection pad 26 may be indicated.

[0053] Figure 1 and Figure 2 The chip stacked semiconductor package CSP may include second and fourth inspection pads 16 and 26 each having a circular planar shape. According to some embodiments, a radius of each of the second and fourth inspection pads 16 and 26 may be 10 μm to 400 μm.

[0054] For example, when the radius of each of the second detection pad 16 and the fourth detection pad 26 is 10 μm, the gap d between the second detection pad 16 and the fourth detection pad 26 is 8 μm, and the relative dielectric constant of the bottom filler, sealant or adhesive between the second detection pad 16 and the fourth detection pad 26 is 3.0, the capacitance C can be calculated as approximately 0.001 pF by using the following formula.

[0055] C=8.85*10 -12 *3*(π*(10*10 -6 ) 2 / (8*10 -6 ))

[0056] When the radius of each of the second detection pad 16 and the fourth detection pad 26 is 100 μm, the gap d between the second detection pad 16 and the fourth detection pad 26 is 8 μm, and the relative dielectric constant of the bottom filler, sealant or adhesive between the second detection pad 16 and the fourth detection pad 26 is 3.0, the capacitance C can be calculated as approximately 0.1 pF by using the following formula.

[0057] C=8.85*10 -12 *3*(π*(100*10 -6 ) 2 / (8*10 -6 ))

[0058] Figures 4A to 4C Is used to explain Figure 1 and Figure 2 A plan view of the stacking accuracy of a chip stacked semiconductor package CSP.

[0059] In detail, Figures 4A to 4C in Figure 1 and Figure 2 The same reference numerals as in the drawings refer to the same elements. Figures 4A to 4C Shown Figure 1 Each of the second inspection pad 16 of the first chip 12 and the fourth inspection pad 26 of the second chip 22 has a circular planar shape. Figures 4A to 4C A case is shown assuming that the gap between the second inspection pad 16 and the fourth inspection pad 26 is constant at 8 μm and the radius of each of the second inspection pad 16 and the fourth inspection pad 26 is 10 μm.

[0060] When the gap between the second detection pad 16 and the fourth detection pad 26 is constant and the capacitance between the second detection pad 16 and the fourth detection pad 26 is measured, the stacking accuracy can be calculated and evaluated by calculating the area where the second detection pad 16 and the fourth detection pad 26 overlap each other.

[0061] Figure 4AThe diagram shows a case where fourth detection pad 26 of second chip 22 is not stacked on second detection pad 16 of first chip 12. Therefore, there is no overlapping area between fourth detection pad 26 of second chip 22 and second detection pad 16 of first chip 12. In this case, the stacking accuracy, represented by the distance between center point O1 of second detection pad 16 and center point O2 of fourth detection pad 26, is no less than 20 μm, which is twice the radius r, and no capacitance is measured between second detection pad 16 and fourth detection pad 26.

[0062] Figure 4B The fourth detection pad 26 of the second chip 22 is precisely stacked on the second detection pad 16 of the first chip 12. Therefore, the two-dimensional overlapping area OLA1 is the same as the area of the second detection pad 16 or the fourth detection pad 26. In other words, the reference area of the horizontal overlap between the second detection pad 16 and the fourth detection pad 26 can be 100% of the area of the second detection pad 16 or the fourth detection pad 26. The reference area of the horizontal overlap between the second detection pad 16 and the fourth detection pad 26 can be π*r 2 (where r is the radius), which is 3.142r 2 .

[0063] exist Figure 4B In this case, since the center point O1 of the second inspection pad 16 and the center point O2 of the fourth inspection pad 26 are exactly the same as each other, the stacking accuracy expressed as the distance between the center point O1 of the second inspection pad 16 and the center point O2 of the fourth inspection pad 26 can be 0μm.

[0064] As mentioned above Figure 3 As described above, when the center point O1 of the second detection pad 16 and the center point O2 of the fourth detection pad 26 are exactly the same, the capacitance measured between the second detection pad 16 and the fourth detection pad 26 (that is, the reference capacitance (i.e., the upper reference capacitance)) can be approximately 0.001 pF. The reference capacitance can be used to detect the stacking accuracy between the second detection pad 16 and the fourth detection pad 26.

[0065] Figure 4C The fourth detection pad 26 of the second chip 22 partially overlaps the second detection pad 16 of the first chip 12 by a radius r. The two-dimensional overlapping area OLA2 of the fourth detection pad 26 stacked on the second detection pad 16 can be calculated as 2((π / 3)-(√3 / 4))*r 2 and can be 1.228r 2 . Figure 4C The two-dimensional overlapping area OLA2 (that is, the area OLA2 according to A-O1-B-O2-A) can be Figure 4BThe reference area is 39% of OLA1. Figure 4C In the example, the interior angle of A-O1-B can be 120°.

[0066] exist Figure 4C In the case of , the stacking accuracy expressed as the distance between the center point O1 of the second detection pad 16 and the center point O2 of the fourth detection pad 26 can be ±10 μm. Figure 3 As described, the capacitance measured between the second detection pad 16 and the fourth detection pad 26 may be 0.00039 pF (lower reference capacitance), which is 39% of the reference capacitance of 0.001 pF (upper reference capacitance).

[0067] When the two-dimensional overlapping area OLA2 of the fourth inspection pad 26 and the second inspection pad 16 is 39% to 100% of the reference area OLA1, the chip stacked semiconductor package CSP may provide good stacking accuracy, and thus the reliability of the chip stacked semiconductor package CSP may be high.

[0068] In this manner, the chip-stacked semiconductor package CSP according to the present invention can obtain the area of horizontal overlap between the second inspection pad 16 and the fourth inspection pad 26 based on the measured capacitance between the second inspection pad 16 and the fourth inspection pad 26. Furthermore, the stacking accuracy of the chip-stacked semiconductor package CSP can be determined and evaluated based on the measured capacitance between the second inspection pad 16 and the fourth inspection pad 26 or the horizontal overlap area between the second inspection pad 16 and the fourth inspection pad 26.

[0069] For example, when the radius of the second detection pad 16 or the fourth detection pad 26 is 10 μm to 400 μm, the area of the two-dimensional overlap between the fourth detection pad 26 and the second detection pad 16 may be 314 μm. 2 Up to 5024μm 2 (Reference Area) Therefore, when the area where the fourth inspection pads 26 two-dimensionally overlap with the second inspection pads 16 is 39% or more of the above-mentioned reference area, the stacking accuracy of the chip-stacked semiconductor package CSP can be evaluated as good.

[0070] Figures 5A to 5C Is used to explain Figure 1 and Figure 2 FIG. 5 is a cross-sectional view of a bonding gap of a chip stacked semiconductor package CSP. FIG.

[0071] In detail, Figures 5A to 5C in Figure 1 and Figure 2 The same reference numerals as in the drawings refer to the same elements. Figures 5A to 5C Shown Figure 1Each of the second inspection pad 16 of the first chip 12 and the fourth inspection pad 26 of the second chip 22 has a circular planar shape. Figures 5A to 5C The following situation is shown: assuming that the radius of each of the second detection pad 16 of the first chip 12 and the fourth detection pad 26 of the second chip 22 is 100 μm, assuming that the area of each of the second detection pad 16 and the fourth detection pad 26 is uniform, and the bonding gap between the second detection pad 16 and the fourth detection pad 26 is a reference bonding gap of, for example, 8 μm.

[0072] When the respective areas of the second inspection pad 16 and the fourth inspection pad 26 are uniform and the capacitance between the second inspection pad 16 and the fourth inspection pad 26 is measured, a bonding gap between the second inspection pad 16 and the fourth inspection pad 26 can be detected.

[0073] Reference Figure 5A When the bonding gap d1 between the second detection pad 16 of the first chip 12 and the fourth detection pad 26 of the second chip 22 is a reference bonding gap of 8 μm, for example, the reference capacitance between the second detection pad 16 and the fourth detection pad 26 may be 0.1 pF.

[0074] Reference Figure 5B , when the capacitance between the second detection pad 16 and the fourth detection pad 26 is 0.2 pF (which is 200% of the reference capacitance of 0.1 pF), the bonding gap d2 (lower reference bonding gap) between the second detection pad 16 and the fourth detection pad 26 can be 4 μm (which is 1 / 2 of the reference bonding gap).

[0075] Reference Figure 5C , when the capacitance between the second detection pad 16 and the fourth detection pad 26 is 0.067 pF (which is 67% of the reference capacitance of 0.1 pF), the bonding gap d3 (upper reference bonding gap) between the second detection pad 16 and the fourth detection pad 26 can be 12 μm (which is 3 / 2 of the reference bonding gap).

[0076] As such, the chip stacked semiconductor package CSP according to the inventive concept may detect the bonding gaps d1 , d2 , and d3 between the second and fourth inspection pads 16 and 26 due to the measured capacitances therebetween.

[0077] In addition, the chip stacked semiconductor package CSP according to the present inventive concept may obtain a bonding gap d1 between the second and fourth inspection pads 16 and 26 (which is a reference bonding gap d1 ) based on the measured reference capacitance between the second and fourth inspection pads 16 and 26 .

[0078] In other words, when the bonding gap between the second detection pad 16 of the first chip 12 and the fourth detection pad 26 of the second chip 22 is between d2 and d3 (i.e., between 1 / 2 and 3 / 2 of the reference bonding gap d1 between the second detection pad 16 and the fourth detection pad 26), the bonding gap of the chip stacked semiconductor package CSP can be evaluated as good.

[0079] Figure 6 and Figure 7 is a layout diagram of a chip-stacked semiconductor package CSP1 according to an embodiment of the inventive concept.

[0080] In detail, Figure 6 It may be a layout diagram of the first chip 32 of the chip stacked semiconductor package CSP1, Figure 7 Can be stackable Figure 6 The first chip 32 can be connected to the second chip 52 on the first chip 32. Figure 1 and Figure 2 The first chip 12 corresponds to the second chip 52. Figure 1 and Figure 2 The second chip 22 corresponds to the following. Figure 6 and Figure 7 With reference to the above Figure 1 and Figure 2 The description given is the same as the description given.

[0081] The first chip 32 may include a first chip region 33 and a first scribe region 35 surrounding the first chip region 33. The first scribe region 35 may be cut away from the final structure of the chip-stacked semiconductor package CSP1, and thus may be partially or completely removed.

[0082] A plurality of first chip pads PD1 are formed on edge portions of the first chip region 33. Some of the first chip pads PD1 constitute a plurality of first inspection pad groups MPD1a and MPD1b. The first inspection pad groups MPD1a and MPD1b may include first inspection pads 34 and 38 and second inspection pads 36 and 40.

[0083] The first inspection pad group MPD1a and MPD1b include a first sub-inspection pad group MPD1a and a second sub-inspection pad group MPD1b separated from each other. The first sub-inspection pad group MPD1a may include a first inspection pad 34 and a second inspection pad 36, and the second sub-inspection pad group MPD1b may include a first inspection pad 38 and a second inspection pad 40. The first sub-inspection pad group MPD1a can be used to detect stacking accuracy. The second sub-inspection pad group MPD1b can be used to detect bonding gaps.

[0084] A plurality of test terminal groups TPD1a and TPD1b are formed on the first scribe line area 35. The test terminal groups TPD1a and TPD1b include first test terminals 42 and 46 and second test terminals 44 and 48. The test terminal groups TPD1a and TPD1b include a first sub-test terminal group TPD1a and a second sub-test terminal group TPD1b separated from each other. The first sub-test terminal group TPD1a may include a first test terminal 42 and a second test terminal 44, and the second sub-test terminal group TPD1b may include a first test terminal 46 and a second test terminal 48.

[0085] The first sub-test pad group TPD1a can be used to detect stacking accuracy. The second sub-test pad group TPD1b can be used to detect joint gap. The first test terminals 42 and 46 can be electrically connected to the first detection pads 34 and 38 via conductive wires. The second test terminals 44 and 48 can be electrically connected to the second detection pads 36 and 40 via conductive wires.

[0086] The second chip 52 may be stacked on the first chip 32. The second chip 52 may include a second chip region 53 and a second scribe region 55. A plurality of second chip pads PD2 are formed on an edge portion of the second chip region 53. Some of the second chip pads PD2 constitute a plurality of second test pad groups MPD2a and MPD2b. The second test pad groups MPD2a and MPD2b may include third test pads 54 and 58 and fourth test pads 56 and 60.

[0087] The second inspection pad groups MPD2a and MPD2b include a third sub-inspection pad group MPD2a and a fourth sub-inspection pad group MPD2b that are separated from each other. The third sub-inspection pad group MPD2a may include a third inspection pad 54 and a fourth inspection pad 56, and the fourth sub-inspection pad group MPD2b may include a third inspection pad 58 and a fourth inspection pad 60. The third sub-inspection pad group MPD2a may be used to detect stacking accuracy. The fourth sub-inspection pad group MPD2b may be used to detect a joint gap.

[0088] The third detection pads 54 and 58 may be electrically connected to the fourth detection pads 56 and 60, respectively, via conductive lines. The third detection pads 54 and 58 and the fourth detection pads 56 and 60 may face the first detection pads 34 and 38 and the second detection pads 36 and 40, respectively. As described above, the first detection pads 34 and 38 may be electrically and physically connected to the third detection pads 54 and 58, respectively. The second detection pads 36 and 40 may not be physically connected to the fourth detection pads 56 and 60, respectively. According to an embodiment, the second detection pads 36 and 40 may be electrically connected to the fourth detection pads 56 and 60 through a capacitive effect.

[0089] Figure 8 and Figure 9 is a layout diagram of a chip-stacked semiconductor package CSP2 according to an embodiment of the inventive concept.

[0090] In detail, Figure 8 It may be a layout diagram of a first chip 62 of a chip stacked semiconductor package CSP2, Figure 9 Can be stackable Figure 8 The first chip 62 can be connected to the second chip 82 on the first chip 62. Figure 1 and Figure 2 The first chip 12 corresponds to the second chip 82. Figure 1 and Figure 2 The second chip 22 corresponds to the following. Figure 8 and Figure 9 With reference to the above Figure 1 and Figure 2 The description given is the same as the description given.

[0091] The first chip 62 may include a first chip region 63 and a first scribe region 65 surrounding the first chip region 63. The first scribe region 65 may be cut away from the final structure of the chip-stacked semiconductor package CSP2, and thus may be partially or completely removed.

[0092] A plurality of first chip pads PD1 are formed on the central portion of the first chip region 63. Some of the first chip pads PD1 constitute a plurality of first inspection pad groups MPD1a-1 and MPD1b-1. The first inspection pad groups MPD1a-1 and MPD1b-1 may include first inspection pads 64 and 68 and second inspection pads 66 and 70.

[0093] The first inspection pad group MPD1a-1 and MPD1b-1 include a first sub-inspection pad group MPD1a-1 and a second sub-inspection pad group MPD1b-1 separated from each other on both sides of the main layer. The first sub-inspection pad group MPD1a-1 can be used to inspect stacking accuracy. The second sub-inspection pad group MPD1b-1 can be used to inspect bonding gaps.

[0094] A plurality of test terminal groups TPD1a-1 and TPD1b-1 are formed on the first scribe area 65. The test terminal groups TPD1a-1 and TPD1b-1 include first test terminals 72 and 76, respectively, and second test terminals 74 and 78, respectively. The test terminal groups TPD1a-1 and TPD1b-1 include a first sub-test terminal group TPD1a-1 and a second sub-test terminal group TPD1b-1 separated from each other on both sides of the body layer.

[0095] The first sub-test pad group TPD1a-1 can be used to detect stacking accuracy. The second sub-test pad group TPD1b-1 can be used to detect joint gap. The first test terminals 72 and 76 can be electrically connected to the first detection pads 64 and 68 through conductive wires. The second test terminals 74 and 78 can be electrically connected to the second detection pads 66 and 70 through conductive wires.

[0096] The second chip 82 may be stacked on the first chip 62. The second chip 82 may include a second chip region 83 and a second scribe region 85. A plurality of second chip pads PD2 are formed on the central portion of the body layer above the second chip region 83. Some of the second chip pads PD2 constitute a plurality of second test pad groups MPD2a-1 and MPD2b-1. The second test pad groups MPD2a-1 and MPD2b-1 may include third test pads 84 and 88, respectively, and fourth test pads 86 and 90, respectively.

[0097] The second inspection pad groups MPD2a-1 and MPD2b-1 include a third sub-inspection pad group MPD2a-1 and a fourth sub-inspection pad group MPD2b-1 separated from each other. The third sub-inspection pad group MPD2a-1 can be used to inspect stacking accuracy. The fourth sub-inspection pad group MPD2b-1 can be used to inspect bonding gaps.

[0098] The third detection pads 84 and 88 may be electrically connected to the fourth detection pads 86 and 90, respectively, via conductive lines. The third detection pads 84 and 88 and the fourth detection pads 86 and 90 may face the first detection pads 64 and 68 and the second detection pads 66 and 70, respectively. As described above, the first detection pads 64 and 68 may be electrically and physically connected to the third detection pads 84 and 88, respectively. The second detection pads 66 and 70 may not be physically connected to the fourth detection pads 86 and 90, respectively. According to an embodiment, the second detection pads 66 and 70 may be electrically connected to the fourth detection pads 86 and 90 through a capacitive effect.

[0099] Figure 10A and Figure 10B is a plan view illustrating shapes and sizes of chip pads and inspection pads of a chip-stacked semiconductor package according to an embodiment of the inventive concept.

[0100] Figure 10A FIG2 shows the planar shapes of the chip pads PDa to PDe used in the semiconductor package of the chip stack according to the embodiment of the present invention. The chip pads PDa to PDe may correspond to the first chip pad PD1 and the second chip pad PD2 used in the first chip or the second chip. The chip pads PDa to PDe may correspond to the detection pads (e.g., Figure 1 and Figure 2The first detection pad 14, the second detection pad 16, the third detection pad 24 and the fourth detection pad 26 correspond to each other.

[0101] The planar shape of the chip pads PDa to PDe can be changed. The planar shape of the chip pads PDa to PDe can be polygonal instead of the circular shape described above. For example, the planar shape of the chip pads PDa to PDe can be a quadrilateral (PDa), a quadrilateral with rounded corners (PDb), a quadrilateral with cut corners (PDc), a hexagon (PDd), or an octagon (PDe).

[0102] Figure 10B FIG2 shows the planar dimensions of the chip pads PD3 and PD4 and the detection pads MP3 and MP4 used in the semiconductor package of the chip stack according to an embodiment of the present invention. The chip pads PD3 and PD4 may correspond to the first chip pad PD1 and the second chip pad PD2 used in the first chip or the second chip. The detection pads MP3 and MP4 may correspond to the detection pads (e.g., Figure 1 and Figure 2 The first detection pad 14, the second detection pad 16, the third detection pad 24 and the fourth detection pad 26 correspond to each other.

[0103] The planar shape of the chip pad PD3 and the detection pad MP3 can each be circular. The radius R1 and R2 of the chip pad PD3 and the detection pad MP3 can be different. For example, the radius R2 of the detection pad MP3 can be larger than the radius R1 of the chip pad PD3. In this case, capacitance measurement via the detection pad MP3 can be easily performed.

[0104] The planar shape of each of the chip pad PD4 and the detection pad MP4 can be a quadrilateral. The lengths L1 and L2 of one side of each of the chip pad PD4 and the detection pad MP4 can be different. For example, the length L2 of one side of the detection pad MP4 can be greater than the length L1 of one side of the chip pad PD4. In this case, capacitance measurement via the detection pad MP4 can be easily performed.

[0105] Figure 11 is a cross-sectional view of a chip-stacked semiconductor package 1000 ( CSP3 ) according to an embodiment of the inventive concept.

[0106] In detail, the chip stacked semiconductor package 1000 (CSP3) can be a package manufactured by chip on wafer (CoW) technology. The chip stacked semiconductor package 1000 may include a first chip 100, a second chip 200 and a sealant (or encapsulant) 330. The first chip 100 may include a body layer 110 (base wafer), a lower insulating layer 120, a through silicon via (TSV) 130, a first connecting member 140, a protective layer 160 and a first chip pad 170. According to an embodiment, the bump 144 is exposed through the bottom of the first chip 100, and the passivation layer 124 on the active surface of the first chip 100 is exposed. According to an embodiment, the lower insulating layer 120 may include a metal interlayer 122 and a passivation layer 124. According to an embodiment, the first connecting member 140 may include a bump pad 142 and a bump 144.

[0107] Similar to the first chip 100, the second chip 200 may include a body layer 210, a lower insulating layer 220, and a second connecting member 240. The second chip 200 may not include TSVs, and according to another embodiment, the second chip 200 may include TSVs. The active surface of the second chip 200 may be mounted on the inactive surface of the first chip 100, thereby forming a chip stack. The second connecting member 240 may be connected to the first chip pad 170 of the first chip 100. Therefore, the second chip 200 can be electrically connected to the TSV 130 of the first chip 100 via the second connecting member 240. Each second connecting member 240 may include a second chip pad 242 and a bump 244. According to an embodiment, the lower insulating layer 220 may include an intermetallic insulating layer 222 and a passivation layer 224.

[0108] The sealant 330 may fill the connection portion between the first chip 100 and the second chip 200, that is, the portion where the first chip pad 170 of the first chip 100 is connected to the second connection member 240. The sealant 330 may be formed from the underfill 310. The sealant 330 is formed to surround the two lateral surfaces (LS1 and LS2) of the second chip 200. Therefore, the sealant 330 formed on the two lateral surfaces of the second chip 200 and the sealant 330 formed in the connection portion between the first chip 100 and the second chip 200 may be formed from the same material.

[0109] The upper surface of the second chip 200 is exposed and not covered by the sealant 330. According to an embodiment, the two lateral surfaces of the first chip 100 are not covered by the sealant (or encapsulant) and are thus exposed. Therefore, when the chip stacked semiconductor package 1000 is mounted on a main chip or board substrate and is molded again, the additional molding material can smoothly combine and adhere to the upper surface of the second chip 200 or the lateral surfaces of the first chip 100.

[0110] The chip stacked semiconductor package 1000 (CSP3) may include the inspection pad group MPD as described above. The first chip pad 170 of the inspection pad group MPD may include a first inspection pad 170a and a second inspection pad 170b. The second chip pad 242 of the inspection pad group MPD may include a third inspection pad 242a and a fourth inspection pad 242b.

[0111] The first detection pad 170a and the third detection pad 242a are electrically and physically connected to each other by using the bump 244 as the dielectric element ME. The second detection pad 170b and the fourth detection pad 242b are not physically connected to each other by the sealant 330 as the non-dielectric element NME. The method of measuring capacitance by using the detection pad group MPD and detecting stacking accuracy and bonding gap based on the capacitance measurement has been described above, so the description of this method will be omitted.

[0112] Figures 12A to 12G Is used to explain the manufacturing Figure 11 A cross-sectional view of a method of stacking chips in a semiconductor package 1000 is provided. Figures 12A to 12G A method of manufacturing a chip-stacked semiconductor package 1000 by using CoW is explained.

[0113] Reference Figure 12A , a base wafer 10 including a plurality of first chips 100 having TSVs 130 formed therein is prepared. The base wafer 10 is completed by simultaneously forming the first chips 100 each including TSVs 130 on a wafer level. In the base wafer 10, the size (eg, length or width) of the chip region is represented by CR1.

[0114] The size (eg, length or width) of the scribe line region between the first chips 100 is represented by SR1. Figure 12A In the figure, for the convenience of explanation, three first chips 100 are shown on the base wafer 10, but dozens to hundreds of first chips 100 may be formed on the base wafer 10. As described above, Figure 1 Test terminal set TPD (for example, Figure 1 The first test terminal 17 and Figure 1 The second test terminal 19).

[0115] The base wafer 10 may include a body layer 110, a lower insulating layer 120, TSVs 130, a first connecting member 140, a protective layer 160, and a first chip pad 170. The body layer 110 may include a silicon substrate, an integrated circuit layer formed on the silicon substrate, and an interlayer insulating layer covering the integrated circuit layer. The lower insulating layer 120 may be formed below the body layer 110 and may include an intermetallic insulating layer 122 and a passivation layer 124. A multilayer wiring pattern may be formed within the intermetallic insulating layer 122.

[0116] The TSVs 130 may penetrate the body layer 110 and may be connected to the multi-layer wiring pattern of the lower insulating layer 120. Each first connection member 140 may include a bump pad 142 and a bump 144. The bump pad 142 may be formed of a conductive material on the passivation layer 124 and may be electrically connected to the multi-layer wiring pattern within the lower insulating layer 120. Therefore, the bump pad 142 may be electrically connected to the TSV 130 via the multi-layer wiring pattern. In other words, each first connection member 140 may be electrically connected to a corresponding one surface of each TSV 130.

[0117] Bump pad 142 can be formed of aluminum (Al), copper (Cu), etc., and can be formed by pulse plating or DC plating. However, bump pad 142 is not limited to the aforementioned materials or methods. Bump 144 can be formed on bump pad 142. Bump 144 can be formed of a conductive material such as copper (Cu), aluminum (Al), gold (Au) or solder. However, the material of bump 144 is not limited thereto. When bump 144 is formed of solder, bump 144 can be referred to as a solder bump.

[0118] The protective layer 160 may be formed on the upper surface of the main body layer 110 and may be formed of an insulating material to protect the main body layer 110 from external influences. The protective layer 160 may be formed of an oxide layer, a nitride layer, or a double layer formed of an oxide layer and a nitride layer. The protective layer 160 may be formed of an oxide layer (e.g., a silicon oxide (SiO2) layer) by high-density plasma chemical vapor deposition (HDP-CVD).

[0119] The first chip pad 170 may be formed on the protective layer 160 and may be electrically connected to the TSV 130. In other words, the first chip pad 170 may be formed on the other surface of the TSV 130 and may be electrically connected to the TSV 130. Like the bump pad 142, the first chip pad 170 may be formed of Al, Cu, or the like.

[0120] Reference Figure 12B, preparing a support carrier 800. An adhesive member 820 may be formed on the support carrier 800. The support carrier 800 may be formed of a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide (GaAs) substrate, a glass substrate, a plastic substrate, a ceramic substrate, or the like. According to this embodiment, the support carrier 800 may be formed of a silicon substrate or a glass substrate. The adhesive member 820 may be formed of, for example, a non-conductive film (NCF), an anisotropic conductive film (ACF), a UV film, an instant adhesive, a thermosetting adhesive, a laser-hardening adhesive, an ultrasonic-hardening adhesive, or a non-conductive paste (NCP).

[0121] The base wafer 10 is bonded to the support carrier 800 via the bonding member 820. The base wafer 10 may be attached to the support carrier 800 such that the first connection member 140 faces the support carrier 800. The support carrier 800 may be prepared before the base wafer 10 is prepared, or may be prepared after the base wafer 10 is prepared and before the base wafer 10 is attached to the support carrier 800.

[0122] Reference Figure 12C , prepare the second chip 200. Each second chip 200 may include a main layer 210, a lower insulating layer 220 and a second connecting member 240. Similar to the first chip 100, the main layer 210 may include a silicon substrate, an integrated circuit layer formed on the silicon substrate and an interlayer insulating layer covering the integrated circuit layer. The upper surface of the main layer 210 may be exposed to the outside. The upper surface of the main layer 210 may be the second surface of the silicon substrate, and the second surface of the silicon substrate faces the first surface of the silicon substrate on which the integrated circuit layer is formed. Therefore, the silicon in the silicon substrate may be exposed to the outside. In some cases, as in the first chip 100, a protective layer may be formed on the second surface of the silicon substrate.

[0123] The lower insulating layer 220 may be formed under the body layer 210 and may include an intermetallic insulating layer 222 and a passivation layer 224. A multi-layer wiring pattern may be formed within the intermetallic insulating layer 222.

[0124] Each second connection member 240 may include a second chip pad 242 and a bump 244. The second chip pad 242 may be formed of a conductive material on the passivation layer 224 and may be electrically connected to the multi-layer wiring pattern within the lower insulating layer 220. The second chip pad 242 may be formed of the same material as that used to form the bump pad 142 of the first connection member 140.

[0125] A bump 244 may be formed on the second chip pad 242. The bump 244 may be formed of a conductive material. Like the bump 144 of the first connection member 140, the bump 244 may be formed of copper (Cu), aluminum (Al), gold (Au), solder, or the like. However, the material of the bump 244 is not limited thereto. In contrast to the first chip 100, the second chip 200 may not include a TSV that penetrates the body layer 210.

[0126] The chip stack 1100 is formed by stacking each of the second chips 200 on the upper surface of each of the first chips 100. The chip stack 1100 can be formed by bonding the second connection members 240 of the second chips 200 to the first chip pads 170 of the first chip 100 through thermal compression. The second connection members 240 can be connected to the first chip pads 170 of the first chip 100. Therefore, the multi-layer wiring pattern of the second chip 200 can be electrically connected to the TSVs 130 of the first chip 100 via the second connection members 240.

[0127] When the second connection members 240 of the second chip 200 are positioned facing the first chip pads 170 of the first chip 100, the second chip 200 may be stacked on the first chip 100. The second chip 200 may be a chip of a different kind from the first chip 100. Alternatively, the second chip 200 may be a chip of the same kind as the first chip 100.

[0128] According to an embodiment, the Figure 12A The second chip 200 is obtained by using the same base wafer as the base wafer shown in FIG. 1 . In this case, TSVs may not be formed in the second chip 200. However, according to another embodiment, TSVs may be formed in the second chip 200. Therefore, the second chip 200 may be a chip separated and obtained from the same base wafer as the base wafer used for the first chip 100.

[0129] When the chip stack 1100 is formed by stacking the second chip 200 on the respective upper surfaces of the first chip 100, the test pad group MPD is formed as described above. When each test pad group MPD is formed, as described above, the first test pad 170a and the third test pad 242a are electrically and physically connected to each other by using the bump 244 as the dielectric element ME. The second test pad 170b and the fourth test pad 242b are not physically connected to each other via the non-dielectric element NME. The non-dielectric element NME may be a portion corresponding to a sealant formed later by an underfill or molding material.

[0130] After forming the chip stack 1100 by stacking the second chip 200 on the respective upper surfaces of the first chip 100, as described above, the capacitance between the second inspection pad 170b and the fourth inspection pad 242b can be measured using the test terminal located on the scribe line area of the first chip 100. The capacitance between the second inspection pad 170b and the fourth inspection pad 242b is measured online during the manufacturing process. Therefore, the stacking accuracy between the first chip 100 and the second chip 200 and the bonding gap between the first chip 100 and the second chip 200 can be tested.

[0131] Reference Figure 12D , the bottom filler 310 is formed to fill the connection portion between the first chip 100 and the second chip 200 of each chip stack 1100. The bottom filler 310 can constitute a non-dielectric unit NME. The bottom filler 310 can fill the connection portion between the first chip 100 and the second chip 200 (that is, the portion where the first chip pad 170 of the first chip 100 is connected to the second connection member 240). The bottom filler 310 can be formed of an underfill resin such as an epoxy resin, and the bottom filler 310 can include a silica filler, a flux, etc. The bottom filler 310 can be formed of a material different from the molding material to be formed later. However, the bottom filler 310 can be formed of the same material as the molding material.

[0132] The underfill 310 may fill only the connection portion between the first chip 100 and the second chip 200. Figure 12D As shown in FIG, the underfill 310 may surround the lateral surface of the second chip 200 while filling the connection portion between the first chip 100 and the second chip 200. The underfill process in this operation may be omitted if necessary.

[0133] In addition, the molding material 320 is formed to mold the chip stack 1100 attached to the support carrier 800. The molding material 320 can be formed of a polymer such as a resin. For example, the molding material 320 can be formed of an epoxy molding compound (EMC). Therefore, a sealant 330 including the bottom filler 310 and the molding material 320 that seal the chip stack 1100 is formed. The sealant 330 can seal the lateral surfaces or upper surfaces of the first chip 100 and the second chip 200 of each chip stack 1100. Due to the presence of the bottom filler 310, the molding material 320 can seal the lateral surfaces of the bottom filler 310.

[0134] The upper surface of the sealant 330 may be ground to expose the upper surface of the second chip 200 of each chip stack 1100. The upper surface of the sealant 330 may be located on the same plane as the upper surface of the second chip 200. When no TSV is formed in the second chip 200, the upper surface of the second chip 200 may be the second surface of the semiconductor substrate (i.e., silicon substrate) on which no integrated circuit layer is formed, and thus, the silicon of the second surface of the semiconductor substrate may be exposed to the outside.

[0135] When the upper surface of the chip stack 1100 (ie, the second chip 200 ) is exposed and a chip stacked semiconductor package to be completed later is mounted on a board substrate and molded, the molding material may be smoothly coupled and adhered to the upper surface of the second chip 200 .

[0136] Reference Figure 12E The first connection members 140 of the first chip 100 of the chip stack 1100 can be exposed to the outside by separating the support carrier 800 from the base wafer 10 and removing the adhesive member 820 from the base wafer 10 (constituting the body layer). Inspection pads including chip bonding pads can be formed on one surface of the first chip 100, and the first connection members 140 can be formed on the other surface of the first chip 100.

[0137] The support carrier 800 and the adhesive member 820 may be removed separately. In some cases, the support carrier 800 and the adhesive member 820 may be removed simultaneously. For example, when the support carrier 800 is formed of a transparent material (e.g., a glass substrate) and the adhesive member 820 is formed of a UV film, the support carrier 800 and the adhesive member 820 may be simultaneously separated from the base wafer 10 via UV irradiation.

[0138] Next, the base wafer 10 including the chip stack 1100 attached to the base wafer 10 is turned upside down, and then the support substrate 900 is attached to the base wafer 10. The support substrate 900 is attached to the second surface of the base wafer 10 facing the first surface of the base wafer 10 via the adhesive member 920, and the first connection member 140 of the first chip 100 is exposed via the first surface of the base wafer 10. The support substrate 900 can be formed by, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide (GaAs) substrate, a glass substrate, a plastic substrate, or a ceramic substrate. The adhesive member 920 can be formed by, for example, NCF, ACF, UV film, instant adhesive, thermosetting adhesive, laser hardening adhesive, ultrasonic hardening adhesive, or NCP. According to the present embodiment, the support substrate 900 can be formed by a glass substrate, and the adhesive member 920 can be formed by a UV film.

[0139] Reference Figure 12FEach chip stack 1100 undergoes an electrical die sorting (EDS) test by using a support substrate 900. The EDS test can be performed using a probe card 1400 or the like. The probe card 1400 may include a main body 1420 and terminal pins 1410. The terminal pins 1410 may be, for example, pogo pins. The pogo pins contact the corresponding first connection members 140 and apply an electrical signal to the first connection members 140, thereby enabling the EDS test to be performed.

[0140] In addition, during the EDS test, the capacitance between the second detection pad 170b and the fourth detection pad 242b can be measured using the first connection member 140. Because the first connection member 140 includes a bump pad 142 and a bump 144, the bump pad 142 and the bump 144 can be used as a test terminal. In other words, the bump pad 142 and the bump 144 included in the test terminal group TPD can be formed on the other surface of the first chip 100 and can include a first test terminal and a second test terminal. Therefore, the stacking accuracy between the first chip 100 and the second chip 200 and the bonding gap between the first chip 100 and the second chip 200 can be detected.

[0141] Through EDS testing or capacitance measurement, it is determined whether the chip stack 1100 is good or defective. In this way, a determination is made as to whether the chip stack 1100 is good or defective through EDS testing, and the chip stack 1100 determined to be defective is discarded. Therefore, the final chip stacked semiconductor package 1000 according to this embodiment is a package stacked with chips that have passed the EDS test. Therefore, the final chip stacked semiconductor package 1000 according to this embodiment can be referred to as a known good die stack (KGDS) package.

[0142] Reference Figure 12G The chip-stacked semiconductor package 1000 is obtained by sawing (cutting) the base wafer 10 and the sealant 330. The adhesive member 920 may be partially removed by sawing.

[0143] Next, the chip-stacked semiconductor package 1000 is completed by removing the support substrate 900 and the adhesive member 920. The support substrate 900 and the adhesive member 920 can be removed sequentially or simultaneously. After the chip-stacked semiconductor package 1000 is formed by dicing as described above, both lateral surfaces of the first chip 100 are exposed. Therefore, when the chip-stacked semiconductor package 1000 is mounted on a board substrate and molded again, additional molding material can smoothly couple and adhere to the lateral surfaces of the first chip 100.

[0144] Figure 13 and Figure 14 are cross-sectional views of semiconductor package systems 10000 and 10000 a , respectively including chip-stacked semiconductor packages according to embodiments of the inventive concept.

[0145] In detail, the semiconductor package systems 10000 and 10000a according to the embodiment may include a main chip 2000 and a chip-stacked semiconductor package 1000 and a main chip 2000 and a chip-stacked semiconductor package 1000a, respectively. The chip-stacked semiconductor package 1000 may be connected to the main chip 2000. Figure 11 The chip stacked semiconductor package 1000a may be the same as the chip stacked semiconductor package 1000 except that the second sealant 340 is formed to contact both lateral surfaces of the second chip 200. That is, in Figure 14 In the embodiment, the first sealant 330 is not formed to contact both lateral surfaces of the second chip 200. The chip stacked semiconductor packages 1000 and 1000a may each include a test pad group MPD. Therefore, the respective components of the chip stacked semiconductor packages 1000 and 1000a will not be described or will be briefly described.

[0146] Each of the chip-stacked semiconductor packages 1000 and 1000a is stacked on the main chip 2000. Each of the chip-stacked semiconductor packages 1000 and 1000a is sealed by a second sealant 340. The main chip 2000 may be larger than the first chip 100 and the second chip 200. Each of the chip-stacked semiconductor packages 1000 and 1000a may be mounted on the main chip 2000 via an adhesive member 2400. Therefore, the lower surface of the second sealant 340 may be bonded to a portion of the adhesive member 2400 located on the outside of the main chip 2000.

[0147] Similar to the memory chip, the master chip 2000 may include a body layer 2100, a lower insulating layer 2200, a passivation layer 2300, a TSV 2500, a third connection member 2600, a protective layer 2750, and a master chip pad 2700. The lower insulating layer 2200 and the passivation layer 2300 may include different integrated circuit layers and different multi-layer wiring patterns depending on the type of the master chip. The master chip 2000 may be a logic chip, for example, a central processing unit (CPU), a controller, or an application-specific integrated circuit (ASIC).

[0148] The number of TSVs 2500 and the number of main chip pads 2700 may be the same as the number of first connection members 140 of each of the first chips 100 of the chip-stacked semiconductor packages 1000 and 1000a, respectively stacked on the main chip 2000. In some cases, the number of TSVs 2500 and the number of main chip pads 2700 may be different from the number of first connection members 140. For example, more TSVs 2500 than first connection members 140 may be formed.

[0149] Each third connection member 2600 formed on the lower surface of the master chip 2000 may include a bump pad 2610 and a bump 2620. The number of third connection members 2600 may be less than the number of TSVs 2500. Therefore, a TSV 2500 without a corresponding third connection member 2600 may be connected to a third connection member 2600 already occupied by another TSV 2500 via a multi-layer wiring pattern.

[0150] Because the wiring formed on the board substrate on which the master chip 2000 is mounted is standardized, or because it is difficult to densify the wiring due to the physical properties (e.g., plasticity) of the board substrate, each of the third connection members 2600 formed on the master chip 2000 may be larger than each of the first connection members 140. For this reason, all TSVs 2500 may not correspond to all of the third connection members 2600, respectively.

[0151] Figure 15 and Figure 16 are cross-sectional views of chip-stacked semiconductor packages 1500 ( CSP4 ) and 1500 a ( CSP5 ) according to embodiments of the inventive concept.

[0152] In detail, the chip stacked semiconductor packages 1500 (CSP4) and 1500a (CSP5) can be packages manufactured by chip-on-chip (CoC). The chip stacked semiconductor packages 1500 and 1500a can include a first chip 100, a second chip 200 and a sealant 330a and a first chip 100, a second chip 200 and a sealant 330b, respectively. The first chip 100 can include a body layer 110, a lower insulating layer 120, TSVs 130, a first connecting member 140, a protective layer 160 and a first chip pad 170. The bump 144 is exposed through the bottom of the first chip 100, and the passivation layer 124 on the active surface of the first chip 100 is exposed.

[0153] Similar to the first chip 100, the second chip 200 may include a body layer 210, a lower insulating layer 220, and second connecting members 240. Each second connecting member 240 may include a second chip pad 242 and a bump 244. The second chip 200 may not include TSVs, or in some cases, may include TSVs. The active surface of the second chip 200 is mounted on the inactive surface of the first chip 100, thereby forming a chip stack, and the second connecting member 240 may be connected to the first chip pad 170 of the first chip 100. Therefore, the second chip 200 can be electrically connected to the TSVs 130 of the first chip 100 via the second connecting member 240.

[0154] The underfill 310a of the chip stacked semiconductor package 1500 (CSP4) may fill the connection portion between the first chip 100 and the second chip 200 (i.e., the portion where the first chip pad 170 of the first chip 100 is connected to the second connection member 240). Furthermore, the underfill 310a is formed to surround both lateral surfaces of the first chip 100. A molding material 320a is formed on the underfill 310a, and the underfill 310a and the molding material 320a constitute a sealant 330a.

[0155] The underfill 310b of the chip stacked semiconductor package 1500a (CSP5) can fill the connection portion between the first chip 100 and the second chip 200 (i.e., the portion where the first chip pad 170 of the first chip 100 is connected to the second connection member 240). A molding material 320b is formed on the underfill 310b, and the underfill 310b and the molding material 320b constitute a sealant 330b. The upper surfaces of the second chips 200 constituting the chip stacked semiconductor packages 1500 and 1500a are exposed and are not covered by the sealants 330a and 330b, respectively.

[0156] Each of the chip stacked semiconductor packages 1500 and 1500a may include the inspection pad group MPD as described above. Figure 11 The detection pad group MPD is described, so the description thereof will be omitted.

[0157] Figures 17A to 17G Is used to explain the manufacturing Figure 15 A cross-sectional view of a method of stacking chips in a semiconductor package 1500 is provided. Figures 17A to 17G A method of manufacturing a chip-stacked semiconductor package 1500 by using CoC is explained.

[0158] Reference Figure 17A, a base wafer 10 including a plurality of chips, a plurality of TSVs 130 being formed in each of the plurality of chips is prepared. The base wafer 10 bonded to the support substrate 900 via the bonding member 920 may be prepared.

[0159] The support substrate 900 may be formed of a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide (GaAs) substrate, a glass substrate, a plastic substrate, a ceramic substrate, etc. The adhesive member 920 may be, for example, an NCF, an ACF, an instant adhesive, a thermosetting adhesive, a laser hardening adhesive, an ultrasonic hardening adhesive, or an NCP. Figure 17A As shown in , the base wafer 10 may be bonded to the support substrate 900 such that the first connection members 140 face the support substrate 900. The base wafer 10 may be prepared by forming a plurality of chips each including TSVs on a wafer level.

[0160] Next, a plurality of chips are obtained by sawing the base wafer 10 along the scribe line regions. Each of the plurality of chips can be connected to Figure 15 The chip stack corresponds to the first chip 100 of the semiconductor package 1500. Therefore, for convenience of explanation, the chip obtained from the base wafer is hereinafter referred to as a "first chip" or "each first chip". Figure 17A , S1 indicates a cut portion obtained by sawing.

[0161] Sawing may be performed only on the base wafer 10, and may not be performed on the support substrate 900 existing below the base wafer 10. Figure 17A As shown in , a specific portion of the adhesive member 920 can be removed by sawing. After the first chip 100 is obtained from the base wafer 10, the support substrate 900 can be removed. When the support substrate 900 is being removed, the adhesive member 920 can be removed from the first chip 100, but the adhesive member 920 may not be removed from the first chip 100.

[0162] Reference Figure 17B , preparing a support carrier 800. An adhesive member 820 may be formed on the support carrier 800. The support carrier 800 may be formed of a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide (GaAs) substrate, a glass substrate, a plastic substrate, a ceramic substrate, or the like. According to this embodiment, the support carrier 800 may be formed of a silicon substrate or a glass substrate. The adhesive member 820 may be, for example, an NCF, an ACF, a UV film, an instant adhesive, a thermosetting adhesive, a laser-hardening adhesive, an ultrasonic-hardening adhesive, or an NCP.

[0163] Next, the first chips 100 are bonded to the support carrier 800 via the adhesive member 820. The first chips 100 may be attached to the support carrier 800 such that the first connection members 140 face the support carrier 800. Before bonding the first chips 100 to the support carrier 800, the adhesive members 820 bonded to the respective lower surfaces of the first chips 100 may be removed.

[0164] The first chips 100 may be arranged at intervals of a specific distance SP on the support substrate 800 and attached to the support substrate 800. According to embodiments, the specific distance SP may be predetermined. The predetermined distance SP may be appropriately determined in consideration of the size of the ultimately formed chip-stacked semiconductor package 1500.

[0165] Reference Figure 17C The chip stack 1100 is formed by stacking the second chip 200 on the upper surface of each first chip 100. The stacking may be performed by bonding the second connection members 240 of the second chip 200 to the first chip pads 170 of the first chip 100 by thermocompression.

[0166] The second chip 200 may also be obtained by dicing the base wafer, and TSVs may not be formed in the second chip 200. However, TSVs may be formed in the second chip 200. Therefore, the second chip 200 may be a chip separated and obtained from the same base wafer as that used for the first chip 100.

[0167] As mentioned above Figure 12C As described above, when the chip stack 1100 is formed by stacking the second chip 200 on the upper surface of each first chip 100, the test pad group MPD is formed. When each test pad group MPD is formed, as described above, the first test pad 170a and the third test pad 242a are electrically and physically connected to each other by using the bump 244 as the dielectric element ME. The second test pad 170b and the fourth test pad 242b are not physically connected to each other via the non-dielectric element NME. The non-dielectric element NME may be a portion corresponding to a sealant formed later by an underfill or a molding material.

[0168] After forming the chip stack 1100 by stacking the second chip 200 on the upper surface of each first chip 100, as described above, the capacitance between the second inspection pad 170b and the fourth inspection pad 242b can be measured using the test terminal located on the scribe line area of the first chip 100. The capacitance between the second inspection pad 170b and the fourth inspection pad 242b is measured online during the manufacturing process. Therefore, the stacking accuracy between the first chip 100 and the second chip 200 and the bonding gap between the first chip 100 and the second chip 200 can be tested.

[0169] Reference Figure 17D , the bottom filler 310a is formed to fill the connection portion between the first chip 100 and the second chip 200 of each chip stack 1100. The bottom filler 310a may constitute a non-dielectric unit NME. The bottom filler 310a may only fill the connection portion between the first chip 100 and the second chip 200. However, as Figure 17D As shown in FIG, the underfill 310 a may surround the lateral surface of the first chip 100 while filling the connection portion between the first chip 100 and the second chip 200 .

[0170] When the underfill 310a surrounds the first chip 100, the underfill 310a may be formed to be spaced a predetermined distance apart from an underfill surrounding the first chip 100 of another chip stack. However, the underfill 310a may be formed to overlap an adjacent underfill.

[0171] According to this embodiment, the bottom filler 310a may have a shape that widens downward, but the shape of the bottom filler 310a is not limited thereto and may be changed. For example, the bottom filler 310a may have a shape in which the upper and lower portions have almost the same size. The bottom filler process in this operation may be omitted.

[0172] Continuously, the molding material 320a is formed to mold the chip stack 1100 attached to the support carrier 800. The molding material 320a can be formed of a polymer such as a resin. For example, the molding material 320a can be formed of an epoxy molding compound (EMC). Therefore, a sealant 330a is formed that includes the bottom filler 310a and the molding material 320a and seals the chip stack 1100. The sealant 330a can seal the lateral surfaces or upper surfaces of the first chip 100 and the second chip 200 of each chip stack 1100. Due to the presence of the bottom filler 310a, the molding material 320a can seal the lateral surfaces of the bottom filler 310a.

[0173] The upper surface of the sealant 330a may be ground to expose the upper surface of the second chip 200 of each chip stack 1100. When no TSV is formed in the second chip 200, the upper surface of the second chip 200 may be the second surface of the semiconductor substrate having no integrated circuit layer thereon, and thus, silicon of the second surface of the semiconductor substrate may be exposed to the outside.

[0174] Reference Figure 17E, the support carrier 800 is separated from the chip stack 1100, and the adhesive member 820 is removed. After this separation and removal, the first connection member 140 of the first chip 100 of each chip stack 1100 can be exposed to the outside. The lower surface of the sealant 330a and the lower surface of the first chip 100 can form a horizontal plane, and therefore, the first connection member 140 of the first chip 100 can be exposed by protruding from the horizontal plane.

[0175] Next, the support substrate 950 is attached to the second surface of each chip stack 1100 via an adhesive member 952, that is, the second surface of each first chip 100 facing its first surface, and the first connection member 140 is exposed via the first surface. The support substrate 950 can be formed by, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide (GaAs) substrate, a glass substrate, a plastic substrate, or a ceramic substrate. The adhesive member 952 can be formed by, for example, NCF, ACF, UV film, instant adhesive, thermosetting adhesive, laser hardening adhesive, ultrasonic hardening adhesive, or NCP. According to the present embodiment, the support substrate 950 can be formed by a glass substrate and the adhesive member 920 can be formed by a UV film.

[0176] Reference Figure 17F Each chip stack 1100 undergoes an EDS test using the support substrate 950. The EDS test can be performed using a probe card 1400 or the like. The probe card 1400 may include a body portion 1420 and terminal pins 1410. The terminal pins 1410 may be, for example, spring pins. The spring pins contact the corresponding first connection members 140 and apply an electrical signal to the first connection members 140, thereby enabling the EDS test to be performed.

[0177] In addition, during the EDS test, the capacitance between the second inspection pad 170b and the fourth inspection pad 242b can be measured using the first connection member 140. Therefore, the stacking accuracy between the first chip 100 and the second chip 200 and the bonding gap between the first chip 100 and the second chip 200 can be tested.

[0178] Through EDS testing or capacitance measurement, it is determined whether the chip stack 1100 is good or defective. In this way, a determination is made as to whether the chip stack 1100 is good or defective through EDS testing, and the chip stack 1100 or semiconductor package 1000 determined to be defective is discarded. Therefore, the chip stacked semiconductor package 1500 according to this embodiment is a package in which chips that have passed the EDS test are stacked. Therefore, the chip stacked semiconductor package 1500 according to this embodiment can be referred to as a KGDS package.

[0179] Reference Figure 17GThe chip stacked semiconductor package 1500 is obtained by sawing the portion of the sealant 330a located between the chip stacks 1100. Sawing is performed only on the portion of the sealant 330a located between the chip stacks 1100. The adhesive member 952 may be partially removed by sawing. Figure 17G , S2 indicates a cut portion obtained by sawing.

[0180] Next, the chip-stacked semiconductor package 1500 is completed by removing the support substrate 950 and the adhesive member 952. The support substrate 950 and the adhesive member 952 may be removed sequentially or simultaneously.

[0181] Figure 18 and Figure 19 20000 and 20000 a are cross-sectional views of semiconductor package systems according to embodiments of the inventive concept.

[0182] In detail, the semiconductor package systems 20000 and 20000a according to the present embodiment may include a main chip 2000 and a chip-stacked semiconductor package 1500, and a main chip 2000 and a chip-stacked semiconductor package 1500a, respectively. The chip-stacked semiconductor package 1500 may be connected to the main chip 2000 and the chip-stacked semiconductor package 1500a. Figure 15 The chip-stacked semiconductor package 1500a may be the same as the chip-stacked semiconductor package 1500. The chip-stacked semiconductor package 1500a may be the same as the chip-stacked semiconductor package 1500, except that the encapsulant 330b including the molding material 320b is formed to contact both lateral surfaces of the first chip 100. Therefore, the respective components of the chip-stacked semiconductor packages 1500 and 1500a will not be described or will be briefly described.

[0183] Each of the chip-stacked semiconductor packages 1500 and 1500a is stacked on the main chip 2000. The chip-stacked semiconductor packages 1500 and 1500a are sealed by sealants 330a and 330b. The main chip 2000 may be larger than the first chip 100 and the second chip 200. Each of the chip-stacked semiconductor packages 1500 and 1500a may be mounted on the main chip 2000 via an adhesive member 2400. Therefore, the lower surface of each of the sealants 330a and 330b may be bonded to a portion of the adhesive member 2400 located on the outside of the main chip 2000.

[0184] Similar to a memory chip, the master chip 2000 may include a body layer 2100, a lower insulating layer 2200, a passivation layer 2300, a TSV 2500, a third connection member 2600, a protective layer 2750, and a master chip pad 2700. The lower insulating layer 2200 and the passivation layer 2300 may include different integrated circuit layers and different multi-layer wiring patterns depending on the type of the master chip. The master chip 2000 may be a logic chip, such as a CPU, a controller, or an ASIC.

[0185] The number of TSVs 2500 and the number of main chip pads 2700 may be the same as the number of first connection members 140 of each of the first chips 100 of the chip-stacked semiconductor packages 1500 and 1500a, respectively stacked on the main chip 2000. In some cases, the number of TSVs 2500 and the number of main chip pads 2700 may be different from the number of first connection members 140. For example, more TSVs 2500 than first connection members 140 may be formed.

[0186] Each of the third connection members 2600 formed on the lower surface of the master chip 2000 may include a bump pad 2610 and a bump 2620. The number of the third connection members 2600 may be less than the number of the TSVs 2500. Therefore, a TSV 2500 that does not have a corresponding third connection member 2600 may be connected to a third connection member 2600 already occupied by another TSV 2500 via a multi-layer wiring pattern.

[0187] Because the wiring formed on the board substrate on which the master chip 2000 is mounted is standardized, or because it is difficult to densify the wiring due to the physical properties (e.g., plasticity) of the board substrate, each of the third connection members 2600 formed on the master chip 2000 may be larger than each of the first connection members 140. For this reason, all TSVs 2500 may not correspond to all of the third connection members 2600, respectively.

[0188] Based on the overlap area between the detection pads of the first chip and the detection pads of the second chip obtained due to the measured capacitance between the detection pads of the first chip and the detection pads of the second chip, the chip-stacked semiconductor package according to the present invention measures the stacking accuracy between the first chip and the second chip. Therefore, the chip-stacked semiconductor package according to the present invention can detect the stacking accuracy online during the manufacturing process.

[0189] The chip-stacked semiconductor package according to the present invention detects the joint gap between the first and second chips by measuring the capacitance between the detection pads of the first chip and the detection pads of the second chip. Therefore, the chip-stacked semiconductor package according to the present invention can measure and obtain the joint gap non-destructively online during manufacturing.

[0190] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A chip stacked semiconductor package, comprising: A first chip comprising a first detection pad and a second detection pad; a second chip disposed on the first chip, the second chip comprising a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium and a second medium, wherein the first medium is disposed between the first detection pad and the third detection pad and is configured to electrically connect the first detection pad to the third detection pad; and a second medium different from the first medium, wherein the second medium is disposed between the second detection pad and the fourth detection pad and is configured to generate a capacitive effect between the second detection pad and the fourth detection pad.

2. The chip stacked semiconductor package according to claim 1, wherein: The first dielectric is a solder bump, and the second dielectric is an underfill or encapsulant.

3. The chip stacked semiconductor package according to claim 1, wherein: The third detection pad and the fourth detection pad are connected to each other via a conductive line in the second chip.

4. The chip stacked semiconductor package according to claim 1, wherein: The first chip includes: A chip area, wherein the first detection pad and the second detection pad are arranged on the chip area, a scribe line region adjacent to the chip region, and A plurality of conductive lines are formed on the scribe line region and are configured to electrically connect the first detection pad and the second detection pad.

5. The chip stacked semiconductor package according to claim 1, wherein: The first chip includes: A chip area, wherein the first detection pad and the second detection pad are arranged on the chip area, a scribe line region, which is adjacent to the chip region, a first test terminal electrically connected to the first inspection pad via a first conductive line formed on the scribe area, and A second test terminal is electrically connected to the second detection pad via a second conductive line formed on the scribe area.

6. The chip-stacked semiconductor package according to claim 1, wherein: The first chip further includes: a plurality of first chip pads, wherein a planar size of each of the first detection pad and the second detection pad is larger than a planar size of each of the plurality of first chip pads, and The second chip further includes: a plurality of second chip pads, wherein a planar size of each of the third inspection pad and the fourth inspection pad is larger than a planar size of each of the plurality of second chip pads.

7. The chip stacked semiconductor package according to claim 1, wherein: The horizontal overlapping area between the second inspection pad and the fourth inspection pad indicates stacking accuracy, and wherein the horizontal overlapping area between the second inspection pad and the fourth inspection pad is 39% to 100% of the area of the second inspection pad or the fourth inspection pad.

8. The chip stacked semiconductor package according to claim 1, wherein: The bonding gap between the first chip and the second chip is 1 / 2 to 3 / 2 of the reference bonding gap between the second detection pad and the fourth detection pad.

9. A chip-stacked semiconductor package, comprising: a first chip comprising a first detection pad, a second detection pad, a first test terminal, and a second test terminal, the first test terminal being electrically connected to the first detection pad, and the second test terminal being electrically connected to the second detection pad; as well as a second chip disposed on the first chip with a gap between the first chip and the second chip, wherein the second chip includes a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad, The third detection pad overlaps with the first detection pad and is connected to the first detection pad through a medium. wherein the fourth detection pad is not connected to the second detection pad through the medium, wherein the fourth detection pad is electrically connected to the third detection pad via a conductive line, and The first test terminal and the second test terminal are configured to measure capacitance between the second test pad and the fourth test pad.

10. The chip stacked semiconductor package according to claim 9, wherein: The first detection pad and the second detection pad constitute a first detection pad group, and the first detection pad group includes a first sub-detection pad group and a second sub-detection pad group separated from each other, and The third inspection pad and the fourth inspection pad constitute a second inspection pad group, and the second inspection pad group includes a third sub-inspection pad group and a fourth sub-inspection pad group that are separated from each other.

11. The chip stacked semiconductor package according to claim 9, wherein: The capacitance between the second detection pad and the fourth detection pad indicates a stacking accuracy based on a horizontal overlapping area between the second detection pad and the fourth detection pad, and the capacitance corresponding to the stacking accuracy is 39% to 100% of a reference capacitance.

12. The chip-stacked semiconductor package according to claim 9, wherein: The capacitance between the second detection pad and the fourth detection pad indicates a bonding gap between the first chip and the second chip, and the capacitance corresponding to the bonding gap is 67% to 200% of a reference capacitance.

13. A chip-stacked semiconductor package, comprising: a first chip including a first connecting member and a first chip pad, wherein the first connecting member is respectively disposed on one surface of each of the through-silicon vias and electrically connected to the through-silicon vias, and the first chip pad is respectively disposed on the other surface of each of the through-silicon vias and electrically connected to the through-silicon vias; a second chip located on the first chip and comprising a second connection member electrically connected to the first chip pad, wherein the second connection member comprises a bump and a second chip pad; and a sealant configured to seal a space between the second connection members and between the first chip pads between the first chip and the second chip, wherein a first one of the first chip pads forms a first detection pad, and a second one of the first chip pads forms a second detection pad, wherein the first of the second chip pads forms a third inspection pad connected to the first inspection pad, and the second of the second chip pads forms a fourth inspection pad, wherein the fourth detection pad is not connected to the second detection pad, and The fourth detection pad is electrically connected to the third detection pad via a conductive wire.

14. The chip stacked semiconductor package according to claim 13, wherein: The first connection member is formed of a test terminal electrically connected to the first detection pad and the second detection pad, and wherein the first connection member is configured to measure capacitance between the second detection pad and the fourth detection pad.

15. A method for manufacturing a chip-stacked semiconductor package, the method comprising: providing a first chip including a first detection pad, a second detection pad, a first test terminal, and a second test terminal, wherein the first test terminal is electrically connected to the first detection pad, and the second test terminal is electrically connected to the second detection pad; stacking a second chip on the first chip with a gap between the first chip and the second chip, wherein the second chip includes a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; Arranging the third detection pad to overlap with the first detection pad and electrically connecting the first detection pad to the third detection pad through a first medium; providing a second medium between the fourth detection pad and the second detection pad, wherein the second medium is different from the first medium and is configured to generate a capacitance effect between the second detection pad and the fourth detection pad; electrically connecting the fourth detection pad to the third detection pad via a conductive line; and The capacitance between the second detection pad and the fourth detection pad is measured by using the first test terminal and the second test terminal.

16. The method according to claim 15, further comprising: The stacking accuracy between the first chip and the second chip is obtained based on an overlapping area between the second detection pad and the fourth detection pad, which is calculated based on the measured capacitance.

17. The method according to claim 15, further comprising: Bonding gap information between the first chip and the second chip is obtained based on the measured capacitance.

18. The method according to claim 15, wherein A plurality of second chip pads are also provided on the second chip, and a planar size of the third inspection pad and the fourth inspection pad is set to be larger than a planar size of each of the plurality of second chip pads.

19. The method according to claim 15, wherein The first and second inspection pads are disposed adjacent to each other on one surface of the first chip, and the third and fourth inspection pads are disposed adjacent to each other on one surface of the second chip.

20. The method according to claim 15, wherein The first inspection pad and the second inspection pad are provided on one surface of the first chip, and the first test terminal and the second test terminal are provided on the other surface of the first chip.

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