Nonvolatile memory with read circuit operating at low voltage

Abstract

Various embodiments of the present application relate to a nonvolatile memory device having a read circuit that operates at a low voltage. The nonvolatile memory device includes a memory array, a read circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes a selectable bit line and a select switch. The read supply voltage generator includes a voltage regulation circuit and a pseudo column decoder, the pseudo column decoder being coupled to an output of the voltage regulation circuit and having electrical characteristics associated with a selected read path. The voltage regulation circuit is configured to receive a first electrical quantity associated with a desired voltage value on a selected bit line and a second electrical quantity associated with a desired current value for the selected bit line, and generate a regulated read supply voltage for the column decoder stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102019000010155, filed on June 26, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a nonvolatile memory device having a read circuit operating at a low voltage. Background Art

[0004] Recently, the use of memory devices manufactured in the back-end steps of the process (the storage elements of the memory device are obtained in the last layer of the device) has become very important because this allows simplifying the manufacturing process and thus reducing manufacturing costs, allowing obtaining embedded type memory devices that can be integrated with other circuits in the same die and can be manufactured using advanced CMOS technology.

[0005] In particular, back-end integration of non-volatile PCM devices is becoming increasingly important.

[0006] As is known, in PCM devices, the memory element is formed by a region of material that, when subjected to a sufficient current, is able to change its physical structure, transitioning from an amorphous phase to a crystalline phase, or vice versa, with a corresponding change in its ohmic resistance. This change in ohmic resistance is used to store digital data.

[0007] The two states of the memory element are referred to as a SET state and a RESET state, where the SET state is associated with a crystalline phase characterized by lower resistance (and therefore, higher current when the memory element is read at a constant voltage), and the RESET state is associated with an amorphous phase characterized by higher resistance (and therefore, lower current when the memory element is read at a constant voltage).

[0008] Currently manufactured embedded PCM devices have components and current paths compatible with a medium-valued supply voltage, such a supply voltage being generally equal to 1.8 V. However, recently, in view of the requirement for electronic devices and equipment to operate at increasingly lower voltages and / or to have increasingly higher autonomy, it is desirable to develop memory devices using components operating at low voltages (e.g., at 1.2 V). However, as will be described below with reference to Figure 1 and Figure 2 As discussed, this is not simple with the existing structure.

[0009] As is known and as Figure 1 The non-volatile memory device designated by 1 , here of the PCM type, schematically shown in FIG. 1 , essentially comprises a memory array 2 formed by a plurality of memory cells 3 , which are arranged in rows and columns and store corresponding data.

[0010] In the case of the PCM embodiment considered here, each memory cell 3 is formed by a PCM-type storage element 4, which is designed to store binary data, and a selection element 5, which is formed here by an NMOS transistor and is connected in series with the storage element 4. The selection elements 5 of the memory cells 3 arranged in the same row have gate terminals that are coupled together and to the same word line WL0, WL1, .... The selection elements 5 of the memory cells 3 arranged in the same column have respective first conductive terminals that are coupled to each other and, via the respective storage element 4, to the same local bit line LBL1, ..., LBLi, .... In addition, each selection element 5 has a second conductive terminal that is coupled to a reference potential line (e.g., ground).

[0011] The local bit lines LBL0, ..., LBLi, ... are coupled to a column decoder stage 6, shown in a simplified manner, which in turn is coupled to a bias and read circuit 7, of which only the voltage generation stage 11 and the sense amplifier stage 12 are shown schematically. The word lines WL0, WL1, ... are coupled to a schematically shown row decoder stage 8. In a known manner, the bias and read circuit 7, the column decoder stage 6, and the row decoder stage 8 enable selection of one or more memory cells 3 at a time based on a selection signal generated by a control unit 10.

[0012] exist Figure 1 In the example shown, the memory 1 has a hierarchical type bit line structure (in the simplified example, with two levels, but one or more levels can be envisaged), wherein the local bit lines LBL1, ..., LBLi, ... are coupled via first switches 13.0, 13.1, ... to global bit lines (also called master bit lines) MBL0, MBL1, ..., which in turn are coupled via second switches 14.0, 14.1, ... to the bias and read circuit 7. Figure 1 In the schematic representation of FIG, first switches 13.0, 13.1, ... (hereinafter also referred to as first switches 13), second switches 14.0, 14.1, ... (hereinafter also referred to as second switches 14) and global bit lines MBL0, MBL1, ... form a column decoder stage 6. The switches 13, 14 receive selection signals YO0, YO1, ..., YN <0> 、YN <1> ,…, these selection signals are collectively referred to as selection signal Y below.

[0013] The selection signals Y are logic signals which are generated by the control unit 10 and have a value which depends on the supply voltage which is provided by the voltage generation stage 11 and which is present in the control unit 10. Figure 1 It is called column decoding to read the supply voltage Vs.

[0014] In a manner known per se, the global bit lines MBL0, MBL1, . . . , the column decoder stage 6 and the local bit lines LBL1, . . . , LBLi form read paths 18 that can be activated individually or in parallel, each read path intended to create a conductive path between a memory cell 3 of the memory array 2 selected at a time and a sense amplifier stage 12. The sense amplifier stage 12 is generally of the differential type and is configured to compare the current(s) circulating in the selected memory cell(s) 3 with a reference current in order to determine the value of the stored data or data and to generate a digital read signal having one or more bits.

[0015] The task of the voltage generation stage 11 is to generate the voltages used by all other stages of the non-volatile memory device 1 during the various operating steps, and in particular the voltage generation stage 11 here has the task of generating the column decoding read supply voltage Vs mentioned above. In the following, then, reference will be made to Figure 2 Only the portion related to the generation of the column decoding read supply voltage Vs is described and discussed.

[0016] In particular, Figure 2 A read voltage generating circuit 15 is shown and the following description relates to the selection of a schematically shown single current path 18. However, it will be apparent to those skilled in the art that the discussion can be applied in a similar manner to the simultaneous selection and reading of multiple current paths 18.

[0017] exist Figure 2 , the column decoder stage 6 is represented by a single transistor 25 (the transistor 25 represents Figure 1 13, 14 and possibly other selection switches), the transistor 25 has a first terminal 25A connected to the local bit line LBLi, a control terminal 25B receiving a selection signal Y (which, as described, is typically formed from two or three hierarchical selection signals), and a second terminal 25C connected to the global bit line MBLi.

[0018] The read voltage generating circuit 15 uses a bandgap voltage Vbg generated by a bandgap circuit (not shown) and includes an operational amplifier 20 having a non-inverting input 20A, an inverting input 20B, and an output 20C. The non-inverting input 20A receives the bandgap voltage Vbg, the inverting input 20B is coupled to the ground line through a first resistor 23 and is coupled to the output 20C through a second resistor 24, and the output 20C is coupled to the control unit 10, and the output 20C provides the column decoding read supply voltage V S The control unit 10 then generates a voltage V S The same amplitude of the selection signal Y is used to select the read path 18 in the example considered.

[0019] The read voltage generating circuit 15 further comprises a cascode element 17 formed by MOS transistors arranged between the sense amplifier stage 12 and the column decoder stage 6. In particular, in the depicted representation with respect to a single current path 18, the cascode element 17 is coupled to the global bit line MBLi. Furthermore, as discussed below, the cascode element 17 receives a cascode control voltage V having an appropriate value at its gate terminal. C , the cascade control voltage V C The same is generated by the voltage generating stage 11 in a manner not shown.

[0020] In the read voltage generating circuit 15, resistors 23 and 24 define the column decoding read supply voltage V S , which enables safe control of the switches of the column decoder stage 6. In addition, the cascade element 17 regulates the voltage on the global bit line MBL (and thus the voltage on the read path 18) at a regulated and stable value to compensate for the variability of the electrical characteristics of the read path 18 in the actual memory device 1.

[0021] exist Figure 2 In the circuit, the column decoder reads the supply voltage V S The value of should be high enough to prevent the read path 18 from becoming resistive, while the cascade control voltage V C Limits and regulates the voltage on each selected memory cell 3. Therefore, the column decoder reads the supply voltage V S The value of is typically chosen high in order to take into account the variability of the electrical characteristics of the memory device 1 comprising the column decoder stage 6, and also to take into account variability related to the operating conditions, in particular the temperature.

[0022] Therefore, especially when using low voltage select devices and / or when the read path is not very resistive, the column decoding read supply voltage V S A high value of may result in a stress condition on the select device of the read path 18 towards the memory cell 3 . Summary of the Invention

[0023] The present disclosure relates to a nonvolatile memory device having a read circuit operating at a low voltage. Specific embodiments relate to a phase change memory (PCM) device, for example, an embedded type PCM device. The present disclosure is not limited to PCM devices.

[0024] Embodiments of the present invention provide a voltage generating circuit with improved performance.

[0025] In one embodiment, the memory device includes dedicated circuitry for regulating column decode voltages, the dedicated circuitry being capable of generating a voltage having a minimum value that allows a predefined value of voltage across a memory cell to be read when a predefined current flows in the read path. To this end, the regulation circuitry utilizes a dummy decode stage having the same electrical characteristics as the read path (or electrical characteristics that are in a predetermined and known ratio to the electrical characteristics of the read path) to adapt to the specific memory device and existing operating conditions, thereby compensating for inherent variability in the manufacturing process and operating conditions (e.g., operating temperature).

[0026] Therefore, it is no longer necessary to have cascaded devices in the read path, and, in a first approximation, the value of the generated supply voltage is the minimum value that enables correct reading of the memory cells. In this way, components designed to operate at low voltages can be used, and even if the components operate at medium supply voltages, stress conditions on components in the read path with characteristics that do not require high supply voltages can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order that the present invention may be better understood, embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0028] Figure 1 Schematically shows the structure of a known non-volatile memory device;

[0029] Figure 2 Shown in more detail Figure 1 a circuit diagram of some stages of a memory device;

[0030] Figure 3A A simplified circuit diagram showing a memory device having a voltage generation stage of the present invention;

[0031] Figure 3B Shown in detail Figure 3A A possible implementation of components of the voltage generating stage;

[0032] Figure 4 Another simplified circuit diagram of the memory device of the present invention is shown;

[0033] Figure 5A Shown Figure 3A or Figure 4 A possible implementation of the components of the level; and

[0034] Figure 5B Shown Figure 3A or Figure 4 Another possible embodiment of the components of the stage. DETAILED DESCRIPTION

[0035] Figure 3A Memory device 30 is shown. Memory device 30 is of non-volatile type, here of phase change type. Memory device 30 has Figure 1 The overall structure shown in FIG is similar to the overall structure shown in FIG, so some boxes are not shown, and other boxes are only shown schematically. For these parts, please refer to FIG. Figure 1 .

[0036] Figure 3A The memory device 30 shown in FIG. 3 includes a memory array 32 , a column decoder stage 36 , a sense amplifier stage 42 , a bias stage 37 , and a control unit 38 .

[0037] The memory array 32 is formed of a plurality of memory cells 33 (only one of these memory cells 33 is shown) that store corresponding data and have Figure 1 The structure of the memory cell 3. Figure 1 As in the example and in a manner not shown, the memory cells 33 are arranged in rows and columns. The memory cells 33 arranged in the same column are connected to each other and to the same bit line (only one common local bit line LBLi is shown). The bit lines are coupled to a column decoder stage 36.

[0038] In a manner not shown and with Figure 1 As in the example, the column decoder stage 36 may be of a hierarchical type and have Figure 1 , in which a local bit line (here, a universal local bit line LBLi) is coupled to a main bit line (only one universal main bit line MBLi is shown) via a switch (only one selection switch 43 is shown, which is coupled to the control unit 38 via a selection terminal 43A).

[0039] In a manner known per se and similar to that for Figure 1As described, during reading, the main bit line MBLi, the column decoder stage 36 and the local bit line LBLi form one or more read paths 48, which can be activated individually or in parallel and each of which is intended to create a conductive path between a memory cell 33 of the memory array 32 selected at a time and a sense amplifier stage 42. The sense amplifier stage 42 can be of the differential type for comparing the current circulating in the selected memory cell 33 with a reference current in order to determine the stored data value in a manner known per se and to generate a corresponding digital read signal.

[0040] The task of the bias stage 37 is to generate the voltages used by all other stages of the memory device 30 during the various operating steps. In particular, the bias stage 37 comprises a column decode voltage generation circuit 41 which is configured to generate (during a read step of the memory cell 33) a column decode read supply voltage V CDS , the control unit 38 generates a selection signal Y for the selection transistor of the column decoder stage 36 according to the cell 33 to be selected in the memory array 32. The selection signal Y has a voltage equal to the column decoder read supply voltage V CDS amplitude and has a logic value to select the desired read path or paths.

[0041] The column decoding voltage generating circuit 41 uses a reference voltage Vbg generated by a bandgap circuit (not shown) and includes an operational amplifier 50 having a non-inverting input 50A, an inverting input 50B, and an output 50C. The non-inverting input 50A receives the reference voltage Vbg; the inverting input 50B is coupled to a reference potential line 60 (ground) via a first resistor 51 having a resistance R1; the output 50C is coupled to the control unit 38, and the output 50C provides the column decoding voltage V CDS The voltage across the first resistor 51 is denoted hereinafter by V1 .

[0042] The column decoding voltage generating circuit 41 further includes a current mirror circuit 58 , a dummy column decoder 52 , and a second resistor 53 .

[0043] In detail, the current mirror circuit includes a first transistor 54 and a second transistor 55, both of which are PMOS transistors and have, for example, the same area and the same electrical characteristics. Alternatively, the two transistors 54 and 55 may have areas of a preset ratio so as to provide currents of a known preset ratio. The first transistor 54 is coupled to the power supply line V CC The second transistor 55 has a source terminal coupled to the power supply line VCC A source terminal of , a drain terminal coupled to the first intermediate node 56, and the gate terminal and the drain terminal are coupled together (diode connection).

[0044] The second resistor 53 is coupled between the ground line 60 and the second intermediate node 61 and has a resistance R2. The voltage across the second resistor 53 is hereinafter denoted by V2 and, as discussed in detail below, corresponds to the desired regulation value for the selected local bit line LBLi.

[0045] The pseudo column decoder 52 is formed by a plurality of switches corresponding to the switches present in the column decoder stage 36 on the read path 48, such that there is one switch for each decoding level of the column decoder stage 36. Figure 1 In the case of a hierarchical column decoder stage 36 with two switches formed by two decoding transistors similar to the switches 13 and 14, as in the example Figure 3B The details are shown in Figure 3A The stage in is formed by two dummy switches arranged in series. Here, the dummy column decoder 52 includes two dummy decoding transistors 57A, 57B, which are identical in number, structure and design electrical characteristics. Figure 1 The decoding switches 13 and 14 are similar.

[0046] Typically, the dummy decoding transistors 57A, 57B may be equal in number and structure to the decoding switches 13, 14, and may have a resistance that is in a well-defined ratio to the decoding switches 13, 14; for example, the dummy decoding transistors 57A, 57B may have twice the resistance of the decoding switches 13, 14, so that by conducting half the current, the dummy decoding transistors 57A, 57B have the same voltage drop as the decoding switches 13, 14; or the dummy decoding transistors 57A, 57B may have half the resistance of the decoding switches 13, 14, so that by conducting twice the current, the dummy decoding transistors 57A, 57B have the same voltage drop as the decoding switches 13, 14. Alternatively, the dummy decoding transistors 57A, 57B may have the same structure and resistance as the decoding switches 13, 14, but the number of dummy decoding transistors 57A, 57B is in a given ratio to the number of decoding switches 13, 14. For example, for each decoding switch 13, 14, two dummy decoding transistors may be provided to have twice the resistance; in this case, as explained below, the column decoding voltage generating circuit 41 is configured such that at the desired column voltage, the two dummy decoding transistors conduct half the current.

[0047] The dummy decode transistors 57A, 57B may be arranged in a die adjacent to the column decoder stage 36 in which the memory device 30 is integrated to share integration and operating conditions.

[0048] exist Figure 3B , the pseudo decoding transistors 57A, 57B are coupled between the first intermediate node 56 and the second intermediate node 61, the gate terminals of the pseudo decoding transistors 57A, 57B are coupled together and coupled to the output 50C of the operational amplifier 50, and receive the column decoding voltage V CDS .

[0049] In effect, current mirror circuit 58 forms a feedback circuit coupled between output 50C and inverting input 50B of operational amplifier 50 .

[0050] The column decoding voltage generating circuit 41 is configured to generate a column decoding read supply voltage V CDS The adjusted value of the local bit line LBLi is selected so that the voltage on the local bit line LBLi (at Figure 3A V b specified) is maintained at the set value.

[0051] For this purpose, when designing the memory, once the value of the resistor R2 and the value of the current I1 flowing through the first resistor 51 are combined, the value V2 on the second resistor 53 (the desired adjustment value for the selected local bit line LBLi - and the desired current value I1 flowing in the selected read path 48) is adjusted. R The resistance value of the first resistor 51 is derived from the fixed current value of the first resistor 51, which is associated with a specific operating condition of the memory cell, for example, the maximum value of the current drawn from the set memory cell is equal to the current value in the resistor 51 in a first approximation. Therefore, the column decoding read supply voltage V is verified in the design stage. CDS Compatible with switch 43 used.

[0052] As a measure to make the current value in resistor 51 equal (in a first approximation) to the desired current value I R Alternatively, by adjusting the size of the rest of the circuit (including the current mirror circuit 58, the pseudo column decoder 52, etc.) accordingly, the current I1 flowing through the first resistor 51 can be adjusted to the desired current I R With a preset ratio, for example, the desired current I R half or twice as much.

[0053] Furthermore, because the current mirror circuit 58 forces the current I2 flowing in the second resistor 53 to be equal to I1 (or in any case to be in a predetermined ratio to I1), the second resistor 53 reduces the value of the voltage V on the selected bit line LBLi to V because the electrical characteristics of the dummy column decoder 52 and the selected read path 48 are the same.b For example, when using a low voltage component (LV transistor, such as a 1.2V supply voltage V CC In the case of the memory device 30 obtained by operating the LV transistor, I R can be equal to 10μA, and the bit line voltage V b It may be between 400 mV and 600 mV, for example 600 mV.

[0054] In the column decoding voltage generating circuit 41 shown, the operational amplifier 50 automatically provides a bit line voltage V b The corresponding column decoder reads the supply voltage V CDS .

[0055] The column decode voltage generation circuit 41 adjusts itself to generate the minimum column decode read supply voltage V CDS , when the memory 30 has electrical characteristics different from the nominal design values, or when during operation, the circuit operates under conditions different from the initial conditions due to variability of external conditions such as temperature, the minimum column decoding reads the supply voltage V CDS The desired read voltage and current values ​​are also maintained on the selected read path.

[0056] In practice, for example, if the switches in the column decoder stage 36 (and therefore the switches 57A, 57B in the dummy column decoder 52, which are manufactured using the same technology and the same parameters and therefore presumably have the same electrical properties) tend to be switched at a preset bit line voltage V b If the operational amplifier 50 is conducting a higher current (e.g., when the temperature changes), the current I2 flowing through the second resistor 53 and the current I1 mirrored to the first resistor 51 by the current mirror circuit 58, as well as the voltage across the first resistor 51, also increase. The inverting input 50B of the operational amplifier 50 reaches a higher value than the non-inverting input 50A, and the operational amplifier 50 changes its operating point to reduce the column decoding voltage V CDS .

[0057] Figure 4 Shown Figure 3AA variation of memory device 30 is shown, designated here by 30'. Here, output 50C of operational amplifier 50 is connected to control unit 38 via output buffer 70. Depending on the requirements of column decoder stage 36, output buffer 70 can be formed from a standard voltage follower circuit with high current capacity. This solution is advantageous for memory devices 30' with very large column decoder stages 36 and multiple read paths 48 that are simultaneously active. In this case, output buffer 70 can provide the necessary current level and properly drive column decoder stage 36.

[0058] For the rest, Figure 4 The memory device 30' is connected to Figure 3A The memory device 30 is identical to the memory device 30 of FIG. 1 , so other stages and other components are designated by the same reference numerals and will not be described again.

[0059] Figure 5A A second resistor 53 is shown as one possible embodiment of a configurable resistive element. Specifically, the second resistor 53 is formed by a plurality of resistive elements 75 arranged in series between the second intermediate node 61 and the ground 60. The resistive elements 75 can have the same resistance, for example, R2 / N, where N is the number of resistive elements 75. Each node between two adjacent resistive elements 75 can be grounded via a corresponding controllable switch 76.

[0060] Each controllable switch 76 has a control terminal coupled to a logic unit (e.g., the control unit 38) that controls the closing of one of the controllable switches 76 based on the desired resistive value of the second resistor 53. Thus, the value of the resistance R2 of the second resistor 53 can be modified based on the effective electrical characteristics and / or the desired electrical characteristics of the component, for example during characterization and / or final testing of the memory device 30, 30′.

[0061] Alternatively, each resistive element 75 may be connected in parallel to a respective controllable switch 76. In this case, the resistance of each resistive element 75 may be different, for example in constant proportion to the resistance of an adjacent resistor.

[0062] According to another embodiment (in Figure 5B ), as shown in Figure 5B As shown in FIG, resistive elements 75 may be coupled in parallel via corresponding switches 76.

[0063] The first resistors 51 may have the same structure to provide wide variability of the current value I1 to be set.

[0064] From the above description, the advantages of the column decoding voltage generating circuit 41 described herein are apparent.

[0065] It is particularly important to emphasize that the adaptation of the operating point of the column decoding voltage generating circuit 41 can be achieved without inserting further cascade elements along the read path 48 of the selected cell, and that the column decoding voltage generating circuit 41 can therefore also be used in memory devices with a low supply voltage (e.g., equal to 1.2 V).

[0066] Furthermore, the absence of cascade elements directly on read path 48 enables faster read accessibility to memory array 32 .

[0067] For the memory device of the present invention, since there are no multiple cascade elements, one cascade element ( Figure 2 ), so the area of ​​the memory device 30 is reduced.

[0068] In addition, when the memory device 30 is capable of reading the supply voltage V with a column decode having a low value CDS When working, the column decoder reads the supply voltage V CDS The self-regulation allows avoiding stress on components of the memory device 30 even when the memory device 30 requires a higher column decode read supply voltage V CDS The ability to properly drive column decoder stage 36 is maintained even in this less common case.

[0069] The solution shown can also be advantageously applied to memory devices using medium supply voltages, with the above-mentioned advantages in terms of area, stress reduction and read speed.

[0070] Finally, it is obvious that modifications and variations may be made to the memory device described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.For example, the various embodiments described may be combined to provide further solutions.

Claims

1. A non-volatile memory device comprising: a memory array having a plurality of memory cells; Reading circuit; a column decoder stage coupled between the memory array and the read circuit, the column decoder stage comprising a plurality of selectable bit lines and a plurality of select switches, each switch being associated with a corresponding bit line, wherein the plurality of selectable bit lines and the plurality of select switches are configured to couple the memory cells to the read circuit when the selectable bit lines and the select switches are selected, thereby defining a selected read path; as well as a read supply voltage generator comprising a voltage regulation circuit and a dummy column decoder, the dummy column decoder being coupled to an output of the voltage regulation circuit and having electrical characteristics associated with the selected read path, wherein the voltage regulation circuit is configured to: receive a first electrical quantity associated with a desired voltage value on a selected selectable bit line and a second electrical quantity associated with a desired current value for the selected selectable bit line, and generate a regulated read supply voltage for the column decoder stage, wherein the regulated read supply voltage is usable to control the column decoder stage to provide the desired voltage value to the selected selectable bit line at the desired current value when the selectable bit line is selected; Wherein the voltage regulating circuit comprises an operational amplifier and a feedback circuit; wherein the operational amplifier has a first input, a second input, and an output; wherein the first input of the operational amplifier is configured to receive a reference electrical quantity; wherein the second input of the operational amplifier is coupled to the output of the operational amplifier through the feedback circuit, and the second input of the operational amplifier is configured to receive the second electrical quantity; and wherein an output of the operational amplifier is coupled to an output of the dummy column decoder and to an output of the read supply voltage generator; The system further includes: a voltage setting resistor coupled between the dummy column decoder and a reference potential line, the voltage setting resistor being configured to set the first electrical quantity; Also included: a current setting resistor coupled between the second input of the operational amplifier and a reference potential line, the current setting resistor being configured to generate the second electrical quantity; The feedback circuit includes a current mirror circuit. 2 . The nonvolatile memory device according to claim 1 , wherein the voltage setting resistor or the current setting resistor has an adjustable resistance.

3. The nonvolatile memory device of claim 2, wherein the voltage setting resistor or the current setting resistor comprises a plurality of selectable resistive elements that can be coupled together, each selectable resistive element having a corresponding connection switch.

4. The nonvolatile memory device of claim 1 , wherein the pseudo column decoder comprises: a first terminal coupled to the feedback circuit; a second terminal configured to receive the first electrical quantity; as well as A control terminal coupled to the output of the operational amplifier.

5. The nonvolatile memory device of claim 4 , wherein the column decoder stage has a number of decoding levels, and the dummy column decoder comprises a number of dummy decoding transistors connected in series, the number of the dummy decoding transistors being equal to the number of decoding levels of the column decoder stage. 6 . The nonvolatile memory device of claim 5 , wherein at least one of the dummy decoding transistors has a control terminal coupled to an output of the operational amplifier.

7. The nonvolatile memory device of claim 1, further comprising a current buffer coupled to an output of the voltage regulating circuit.

8. The nonvolatile memory device of claim 7, wherein the current buffer comprises a voltage follower circuit.

9. The nonvolatile memory device of claim 1, wherein each of the memory cells comprises a phase change memory cell.

10. A method for reading the memory device according to any one of claims 1 to 9, the method comprising: Selecting a bit line using a column decoder; coupling the memory cell to the read circuit via the selected bit line; obtaining a first electrical quantity associated with a desired voltage value on the selected bit line and a second electrical quantity associated with a desired current value for the selected bit line; generating a regulated read supply voltage by a voltage regulation circuit coupled to a dummy column decoder having electrical characteristics associated with a read path between the memory cell and the read circuit; as well as The regulated read supply voltage is provided to the column decoder.

11. The method of claim 10, wherein each of the memory arrays comprises a plurality of phase change memory cells, the memory cells being phase change memory cells.

12. A voltage generator circuit for use with a memory device, the circuit comprising: an operational amplifier having a first input, a second input, and an output, wherein the first input of the operational amplifier is coupled to receive a reference electrical quantity; a pseudo column decoder having a control input coupled to an output of the operational amplifier, wherein the pseudo column decoder is designed to have electrical characteristics associated with a column decoder stage of the memory device; a feedback circuit coupled between the second input of the operational amplifier and the current path of the pseudo column decoder, wherein the feedback circuit comprises a current mirror circuit; a voltage setting resistor coupled in series with the current path of the dummy column decoder between the dummy column decoder and a reference potential line; and A current setting resistor is coupled between the second input of the operational amplifier and the reference potential line. 13 . The circuit according to claim 12 , wherein the voltage setting resistor or the current setting resistor has an adjustable resistance.

14. The circuit of claim 13, wherein the voltage setting resistor or the current setting resistor comprises a plurality of selectable resistive elements that can be coupled together, each selectable resistive element having a corresponding connection switch.

15. The circuit of claim 12, wherein the pseudo column decoder is designed to have electrical characteristics associated with a selected read path between a selected memory cell and a read circuit of the memory device, the selected read path including a bit line selected by the column decoder stage.

16. The circuit of claim 12, wherein the dummy column decoder comprises a number of dummy decoding transistors connected in series, the number of dummy decoding transistors being equal to the number of decoding levels of the column decoder stage.

17. The circuit of claim 16, wherein at least one of the dummy decoding transistors has a control terminal coupled to an output of the operational amplifier.

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