Chip packaging structure forming method

Abstract

The embodiment of the present disclosure provides a method for forming a chip packaging structure. The method includes forming a guide hole structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer above a second surface of the first substrate. The method includes forming a first insulating layer above the barrier layer. The method includes forming a conductive pad above the first insulating layer and in a first opening, a second opening, and a third opening. The conductive pad extends continuously from the guide hole structure into the third opening. The method includes forming a conductive bump above the conductive pad in the third opening.

Description

Technical Field

[0001] The disclosed embodiments relate to a method for forming a chip packaging structure. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and using photolithography processes to pattern the various material layers to form circuit components and elements on the material layers.

[0003] Typically, dozens or hundreds of integrated circuits are manufactured on a single semiconductor wafer. The integrated circuits are sawn along the dicing lines to separate the dies. The individual dies are then packaged separately to form a package. Each package is bonded to a substrate. During the bonding process, the bonding stress between the package and the substrate reduces the yield of the bonding process. Therefore, improving the yield of the bonding process is a challenge. Summary of the invention

[0004] According to some embodiments, the present disclosure provides a method for forming a chip packaging structure. The method includes forming a guide hole structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer above a second surface of the first substrate. The barrier layer directly contacts the first substrate, and the barrier layer has a first opening exposing the guide hole structure. The method includes forming a first insulating layer above the barrier layer. The first insulating layer has a second opening and a third opening, the second opening is located above the first opening and exposes the guide hole structure, the third opening partially exposes the barrier layer, and the barrier layer is thinner than the first insulating layer. The method includes forming a conductive pad above the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad extends continuously from the guide hole structure to the third opening. The method includes forming a conductive bump above the conductive pad in the third opening.

[0005] According to some embodiments, the present disclosure provides a method for forming a chip packaging structure. The method includes forming a guide hole structure in a substrate. The method includes bonding a chip to a first surface of the substrate. The method includes forming a barrier layer above a second surface of the substrate, the barrier layer directly contacting the substrate. The method includes forming a first insulating layer partially above the barrier layer. The method includes forming a conductive pad above the first insulating layer, the conductive pad having a first portion and a second portion, the first portion passing through the barrier layer and the first insulating layer to connect to the guide hole structure, and the second portion passing through the first insulating layer and directly contacting the barrier layer. The method includes forming a second insulating layer above the first insulating layer and the conductive pad. The method includes forming a conductive bump above the second insulating layer, the first bottom of the conductive bump passing through the second insulating layer to connect to the second portion of the conductive pad.

[0006] According to some embodiments, the present disclosure provides a chip packaging structure. The chip packaging structure includes a first substrate. The chip packaging structure includes a guide hole structure that passes through the first substrate. The chip packaging structure includes a chip located above a first surface of the first substrate. The chip packaging structure includes a barrier layer located above a second surface of the first substrate, and the barrier layer directly contacts the first substrate. The chip packaging structure includes a first insulating layer located above the barrier layer. The chip packaging structure includes a conductive pad located above the first insulating layer, the conductive pad having a first portion and a second portion, the first portion passing through the barrier layer and the first insulating layer to connect the guide hole structure, and the second portion passing through the first insulating layer and directly contacting the barrier layer. The chip packaging structure includes a conductive bump located above the second portion of the conductive pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be described in detail with reference to the accompanying drawings of the specification. It should be noted that, in accordance with standard practice in the industry, various features are not shown in proportion and are only used for illustration. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0008] According to some embodiments, Figures 1A to 1H It is a cross-sectional view of various stages of the process used to form a chip packaging structure.

[0009] According to some embodiments, Figure 1E-1 yes Figure 1E A top view of a chip packaging structure.

[0010] According to some embodiments, Figure 1G-1 yes Figure 1G A top view of a chip packaging structure.

[0011] According to some embodiments, Figure 2 It is a cross-sectional view of the chip packaging structure.

[0012] According to some embodiments, FIG. 3A to FIG. 3C It is a cross-sectional view of various stages of the process used to form a chip packaging structure.

[0013] According to some embodiments, Figure 4A It is a cross-sectional view of the chip packaging structure.

[0014] According to some embodiments, Figure 4B yes Figure 4A A top view of a chip packaging structure.

[0015] Description of reference numerals:

[0016] 100,200,300,400,500,600: chip packaging structure

[0017] 110,210:Substrate

[0018] 111: Semiconductor substrate

[0019] 111a,111b: Surface

[0020] 112: Guide hole structure

[0021] 113,117: Barrier layer

[0022] 114: Redistribution Structure

[0023] 114a,118,212,230,310: Insulation layer

[0024] 114b,214: Line layer

[0025] 114c,216: Guide hole

[0026] 114d,167,218: Conductive pad

[0027] 115,132,180: Conductive bumps

[0028] 116,134: welding layer

[0029] 117a,118a,118b,164a,172,312: Open

[0030] 120: Chip

[0031] 122,152,180a: Top surface

[0032] 136,190a: Solder ball

[0033] 140,220: bottom filling layer

[0034] 150: Mold sealing layer

[0035] 162,320: Seed layer

[0036] 164: Mask layer

[0037] 166: Conductive layer

[0038] 167a: Part I

[0039] 167b: Part 2

[0040] 170: Mask layer

[0041] 182,322: Bottom

[0042] 190: Welding layer

[0043] D: Distance

[0044] G1: Clearance

[0045] SC: Cutting Road

[0046] V1: vertical direction

[0047] W1, W2, W3: Width DETAILED DESCRIPTION

[0048] Many different implementation methods or examples are disclosed below to implement the different features of the provided subject matter. The following describes specific embodiments of the components and their arrangements to illustrate the present disclosure. Of course, these embodiments are only for illustration and should not be used to limit the scope of the present disclosure. For example, it is mentioned in the specification that the first characteristic component is formed on the second characteristic component, which includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which there are other features between the first characteristic component and the second characteristic component, that is, the first characteristic component and the second characteristic component are not in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present disclosure and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0049] In addition, spatially related terms such as "below", "beneath", "down", "above", "upper" and similar terms may be used. These spatially related terms are for the convenience of describing the relationship between one (some) element or feature and another (some) element or feature in the diagram. These spatially related terms are intended to cover different orientations of the device including the feature. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used therein will also be interpreted according to the orientation after the rotation. It should be understood that additional operations can be provided before, during, and after the above method, and for other embodiments of the above method, some of the described operations can be replaced or removed.

[0050] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in the embodiments. For different embodiments, some of the stages described may be replaced or removed. Additional features may be added to the semiconductor device structure. For different embodiments, some of the functions described below may be replaced or removed. Although some embodiments are discussed by using operations performed in a specific order, the operations may be performed in other logical orders.

[0051] According to some embodiments, Figures 1A to 1H is a cross-sectional view of various stages of a process for forming a chip packaging structure. According to some embodiments, Figure 1AAs shown, a substrate 110 is provided. In some embodiments, the substrate 110 is an interposer wafer. According to some embodiments, the substrate 110 includes a semiconductor substrate 111, a via structure 112, a barrier layer 113 and a redistribution structure 114.

[0052] According to some embodiments, semiconductor substrate 111 has surfaces 111a and 111b. In some embodiments, semiconductor substrate 111 is made of an elemental semiconductor material including silicon or germanium in a single crystal, polycrystalline or amorphous structure.

[0053] In some other embodiments, the semiconductor substrate 111 is formed of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination thereof. The semiconductor substrate 111 may also include a multi-layer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0054] According to some embodiments, a via structure 112 is formed in the semiconductor substrate 111. The via structure 112 may extend from the surface 111a into the semiconductor substrate 111. According to some embodiments, a barrier layer 113 is formed over the semiconductor substrate 111. According to some embodiments, the barrier layer 113 is between the via structure 112 and the semiconductor substrate 111.

[0055] According to some embodiments, the barrier layer 113 is configured to prevent the material of the via structure 112 from diffusing into the semiconductor substrate 111. According to some embodiments, the barrier layer 113 is further configured to electrically insulate the via structure 112 from the semiconductor substrate 111.

[0056] According to some embodiments, the barrier layer 113 is made of a silicon-containing material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. or a combination thereof. In some other embodiments, the barrier layer 113 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS), etc.

[0057] The barrier layer 113 is formed by an oxidation process, a deposition process, a spin coating process or other suitable process. According to some embodiments, the deposition process includes a chemical vapor deposition (CVD) process, such as a flowable chemical vapor deposition (FCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, etc.

[0058] In some embodiments, substrate 110 is a device wafer including various device elements. In some embodiments, various device elements are formed in and / or above semiconductor substrate 111. For simplicity and clarity, device elements are not shown in the figure. Examples of various device elements include active devices, passive devices, other suitable elements or combinations thereof. Active devices may include transistors or diodes (not shown) formed at surface 111a. Passive devices include resistors, capacitors or other suitable passive devices.

[0059] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc. Various processes are performed to form various device elements, such as front-end-of-line (FEOL) semiconductor processes. The front-end-of-line semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0060] In some embodiments, isolation features (not shown) are formed in the semiconductor substrate 111. The isolation features are used to define the active region and electrically isolate various device elements formed in the active region. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0061] According to some embodiments, the redistribution structure 114 is formed over the semiconductor substrate 111. According to some embodiments, the redistribution structure 114 includes an insulating layer 114a, a wiring layer 114b, a guide hole 114c, and a conductive pad 114d. According to some embodiments, the insulating layer 114a is formed over the surface 111a. According to some embodiments, the wiring layer 114b is formed in the insulating layer 114a.

[0062] According to some embodiments, Figure 1A As shown, the vias 114c provide electrical connections between different circuit layers 114b, and between the circuit layer 114b and the conductive pad 114d. For simplicity, according to some embodiments, Figure 1A Only one wiring layer 114b is shown.

[0063] According to some embodiments, the via structure 112 is electrically connected to the conductive pad 114d through the circuit layer 114b and the via 114c. According to some embodiments, the conductive pad 114d is formed on the insulating layer 114a. According to some embodiments, the via structure 112, the circuit layer 114b, the via 114c, and the conductive pad 114d are formed of copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni) or other suitable materials.

[0064] According to some embodiments, Figure 1A As shown, conductive bumps 115 are formed on each conductive pad 114d. According to some embodiments, the conductive bumps 115 are formed of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni) or other suitable materials. According to some embodiments, as Figure 1A As shown, solder layers 116 are formed on each of the conductive bumps 115. According to some embodiments, the solder layers 116 are formed of a conductive material, such as tin (Sn) or other suitable materials.

[0065] According to some embodiments, Figure 1AAs shown, a chip 120 is provided. According to some embodiments, the chip 120 includes a system on chip (SoC). According to some embodiments, the chip 120 includes various device elements. In some embodiments, the various device elements are formed in the chip 120.

[0066] For simplicity and clarity, device elements are not shown in the figure. Examples of various device elements include active devices, passive devices, other suitable elements, or combinations thereof. Active devices may include transistors or diodes (not shown) formed on surface 111a. Passive devices include resistors, capacitors, or other suitable passive devices.

[0067] For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc. Various processes are performed to form various device elements, such as front-end-of-line (FEOL) semiconductor processes. The front-end-of-line semiconductor manufacturing processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0068] In some embodiments, isolation features (not shown) are formed in chip 120. The isolation features are used to define the active region and electrically isolate various device elements formed in the active region. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0069] According to some embodiments, Figure 1A As shown, conductive bumps 132 are formed above chip 120. According to some embodiments, as Figure 1AAs shown, solder layers 134 are formed respectively on the conductive bumps 132. According to some embodiments, the solder layers 134 are formed of a conductive material, such as tin (Sn) or other suitable materials.

[0070] According to some embodiments, Figure 1A and Figure 1B As shown, the chip 120 is disposed on the substrate 110. Thereafter, according to some embodiments, a reflow process is performed on the solder layers 134 and 116. According to some embodiments, after the reflow process, each solder layer 134 and the solder layer 116 below the solder layer 134 are melted and mixed together to form solder balls 136. Therefore, according to some embodiments, the chip 120 is bonded to the substrate 110 through the conductive bumps 132 and 115 and the solder balls 136.

[0071] According to some embodiments, Figure 1B As shown, an underfill layer 140 is formed in a gap G1 between the substrate 110 and the chip 120. According to some embodiments, the underfill layer 140 surrounds the conductive bumps 132 and 115, the solder balls 136, and the chip 120. According to some embodiments, the underfill layer 140 includes a polymer material (e.g., a molding compound material, epoxy, or resin).

[0072] According to some embodiments, Figure 1B As shown, a molding layer 150 is formed on the substrate 110. According to some embodiments, the molding layer 150 surrounds the chip 120, the bottom filling layer 140, the conductive bumps 132 and 115, and the solder balls 136. According to some embodiments, the molding layer 150 includes a polymer material (e.g., a molding compound material, an epoxy resin, or a resin). According to some embodiments, the step of forming the molding layer 150 includes forming a molding material layer on the substrate 110, the bottom filling layer 140, and the chip 120, and performing a planarization process on the molding material layer to remove the upper portion of the molding material layer until the top surface 122 of the chip 120 is exposed. According to some embodiments, the top surface 122 of the chip 120 and the top surface 152 of the molding layer 150 are substantially coplanar.

[0073] According to some embodiments, Figure 1C As shown, the lower portion of the semiconductor substrate 111 is removed. According to some embodiments, the removal process includes a chemical mechanical polishing (CMP) process. According to some embodiments, the via structure 112 and the barrier layer 113 are exposed after the removal process.

[0074] According to some embodiments, the via structure 112 and the barrier layer 113 pass through the semiconductor substrate 111. According to some embodiments, when the semiconductor substrate 111 is a silicon substrate, the via structure 112 is also called through-substratevias or through-silicon vias (TSV).

[0075] According to some embodiments, Figure 1D As shown, the semiconductor substrate 111 is turned upside down. According to some embodiments, Figure 1D As shown, a barrier layer 117 is formed above the surface 111b. According to some embodiments, the barrier layer 117 is configured to prevent the material of the wiring layer subsequently formed above the barrier layer 117 from diffusing into the semiconductor substrate 111. According to some embodiments, the barrier layer 117 is further configured to electrically insulate the wiring layer subsequently formed above the barrier layer 117 from the semiconductor substrate 111.

[0076] According to some embodiments, the barrier layer 117 directly contacts the semiconductor substrate 111. According to some embodiments, the barrier layer 117 has openings 117a. According to some embodiments, each opening 117a exposes the via structure 112 thereunder.

[0077] According to some embodiments, the barrier layer 117 is made of a silicon-containing material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. or a combination thereof. In some other embodiments, the barrier layer 113 is made of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethoxysilane (TEOS), etc.

[0078] The barrier layer 117 is formed using an oxidation process, a deposition process, a spin coating process, or other suitable processes. According to some embodiments, the deposition process includes a chemical vapor deposition (CVD) process, such as a flowable chemical vapor deposition (FCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, etc. According to some embodiments, the opening 117a is formed using a photolithography process and an etching process.

[0079] According to some embodiments, Figure 1E-1 yes Figure 1E A top view of a chip packaging structure. According to some embodiments, Figure 1E It is along Figure 1E-1 The cross-sectional view of the chip packaging structure is shown along the section line II'.

[0080] According to some embodiments, Figure 1E and Figure 1E-1As shown, an insulating layer 118 is formed on the barrier layer 117. According to some embodiments, the insulating layer 118 has openings 118a and 118b. According to some embodiments, each opening 118a is located above the opening 117a.

[0081] According to some embodiments, each opening 118a is connected to the opening 117a below. According to some embodiments, the openings 118a expose the underlying via structures 112. According to some embodiments, the openings 118a further expose the barrier layer 117 surrounding the via structures 112.

[0082] According to some embodiments, the opening 118b partially exposes the barrier layer 117 near the via structure 112. According to some embodiments, the insulating layer 118 is partially located between the openings 118a and 118b. According to some embodiments, the barrier layer 117 is thinner than the insulating layer 118. According to some embodiments, the hardness of the barrier layer 117 is greater than the hardness of the insulating layer 118.

[0083] According to some embodiments, the insulating layer 118 is made of a polymer material such as epoxy, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF film, etc. In some embodiments, the insulating layer 118 is formed of a photosensitive material and may undergo a chemical reaction when exposed to light.

[0084] In some embodiments, barrier layer 117 and insulating layer 118 are formed of different materials. According to some embodiments, insulating layer 118 is formed using a coating process, a lamination process, a chemical vapor deposition process, etc., or a combination thereof. According to some embodiments, openings 118a and 118b are formed using a photolithography process and an etching process.

[0085] Thereafter, according to some embodiments, as Figure 1E As shown, a seed layer 162 is formed over the barrier layer 117, the insulating layer 118, and the via structure 112. According to some embodiments, the seed layer 162 conformally covers the barrier layer 117, the insulating layer 118, and the via structure 112.

[0086] According to some embodiments, seed layer 162 directly contacts barrier layer 117, insulating layer 118, and via structure 112. According to some embodiments, the material of seed layer 162 includes titanium, copper, etc. According to some embodiments, seed layer 162 is formed using a physical vapor deposition (PVD) process, such as a sputtering process.

[0087] Thereafter, according to some embodiments, as Figure 1E and Figure 1E-1As shown, a mask layer 164 is formed over the seed layer 162. According to some embodiments, the mask layer 164 has openings 164a. According to some embodiments, each opening 164a exposes a portion of the seed layer 162 in the openings 117a, 118a, and 118b. According to some embodiments, the mask layer 164 is formed of a polymer material such as a photoresist material.

[0088] Thereafter, according to some embodiments, as Figure 1E and Figure 1E-1 As shown, a conductive layer 166 is formed in the opening 164a. According to some embodiments, the conductive layer 166 conformally covers the seed layer 162 exposed by the opening 164a. According to some embodiments, the conductive layer 166 is thicker than the seed layer 162. According to some embodiments, each conductive layer 166 is partially located in the openings 117a, 118a, and 118b below.

[0089] According to some embodiments, conductive layer 166 is formed of a metal material such as copper, aluminum, nickel, tungsten, titanium, etc. or a combination thereof. According to some embodiments, conductive layer 166 is formed using an electroplating process, an electroless plating process, etc.

[0090] Thereafter, according to some embodiments, as Figure 1E and Figure 1F As shown, the mask layer 164 is removed. According to some embodiments, the removal process includes an ashing process and / or a cleaning process. Thereafter, according to some embodiments, as Figure 1F As shown, the seed layer 162 previously located under the mask layer 164 is removed. According to some embodiments, the removal process includes an etching process, such as a wet etching process or a dry etching process.

[0091] According to some embodiments, Figure 1F As shown, after removing the seed layer 162 originally under the mask layer 164, each conductive layer 166 and the seed layer 162 remaining under the conductive layer 166 together form a conductive pad 167. According to some embodiments, each conductive pad 167 continuously extends from the underlying via structure 112 (or opening 117a) to the underlying opening 118b. According to some embodiments, as Figure 1F As shown, the conductive pad 167 has a W-shaped shape.

[0092] According to some embodiments, each conductive pad 167 has a first portion 167a and a second portion 167b. According to some embodiments, the first portion 167a passes through the barrier layer 117 and the insulating layer 118 to connect with the underlying via structure 112. According to some embodiments, the second portion 167b passes through the insulating layer 118.

[0093] According to some embodiments, the second portion 167b directly contacts the barrier layer 117. According to some embodiments, the insulating layer 118 is partially located between the first portion 167a and the second portion 167b. According to some embodiments, the insulating layer 118 separates the first portion 167a from the second portion 167b.

[0094] Thereafter, according to some embodiments, as Figure 1F As shown, a mask layer 170 is formed over the conductive pad 167 and the insulating layer 118. According to some embodiments, the mask layer 170 directly contacts the conductive pad 167 and the insulating layer 118.

[0095] According to some embodiments, mask layer 170 has openings 172 formed using appropriate photolithography and etching processes. According to some embodiments, each opening 172 partially exposes conductive pad 167 (or conductive layer 166) in opening 118b. According to some embodiments, mask layer 170 is formed of a polymer material, such as a photoresist material.

[0096] Thereafter, according to some embodiments, as Figure 1F As shown, conductive bumps 180 are formed in each opening 172. According to some embodiments, the conductive bumps 180 are directly located above the openings 118b. According to some embodiments, the conductive bumps 180 are directly located above the second portion 167b of the conductive pad 167. According to some embodiments, there is no seed layer between the conductive bumps 180 and the conductive pad 167 (or the conductive layer 166). According to some embodiments, the conductive bumps 180 are electrically connected to the via structure 112 through the conductive pad 167 below.

[0097] According to some embodiments, the conductive bump 180 is thicker than the conductive pad 167. According to some embodiments, the conductive bump 180 is in direct contact with the conductive pad 167 (or the conductive layer 166). In some embodiments, the bottom 182 of the conductive bump 180 is located in the opening 118b.

[0098] According to some embodiments, in the vertical direction V1 perpendicular to the surface 111b, the conductive bump 180 and the via structure 112 are misaligned. Therefore, according to some embodiments, during the subsequent bonding process, the bonding stress concentrated on the conductive bump 180 is not transferred to the via structure 112. According to some embodiments, the via structure 112 is thus prevented from being damaged by the bonding stress.

[0099] According to some embodiments, the conductive bump 180 is made of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or nickel (Ni). According to some embodiments, the conductive bump comprises a controlled collapse chip connector (C4) copper pillar bump. According to some embodiments, the conductive bump 180 is formed using a plating process such as an electroplating process.

[0100] Thereafter, according to some embodiments, as Figure 1F As shown, solder layers 190 are formed respectively over the conductive bumps 180. According to some embodiments, solder layers 190 are formed of tin (Sn), lead-free solder, or other suitable conductive materials having a melting point lower than that of the conductive bumps 180. According to some embodiments, solder layers 190 are formed using a plating process such as an electroplating process.

[0101] According to some embodiments, Figure 1G-1 yes Figure 1G A top view of a chip packaging structure. According to some embodiments, Figure 1G It is along Figure 1G-1 The cross-sectional view of the chip package structure 100 is shown along the section line II' in FIG. Figure 1G and Figure 1G-1 As shown, the mask layer 170 is removed. According to some embodiments, the removal process includes an ashing process and / or a cleaning process.

[0102] Thereafter, according to some embodiments, as Figure 1F and Figure 1G As shown, a reflow process is performed on the solder layer 190 to convert the solder layer 190 into solder balls 190a. Figure 1G As shown, according to some embodiments, a cutting process is performed to cut the substrate 110 and the encapsulation layer 150 along a predetermined cutting line SC, thereby forming a chip packaging structure 100. For simplicity, Figure 1G-1 Only one of the chip package structures 100 is shown.

[0103] According to some embodiments, Figure 1G As shown, the contact area between the conductive bump 180 and the conductive pad 167 is larger than the area of ​​the top surface 180a of the conductive bump 180. According to some embodiments, as Figure 1G-1 As shown, the width W1 of the conductive pad 167 is greater than the sum of the width W2 of the conductive bump 180 , the width W3 of the via structure 112 , and the distance D between the conductive bump 180 and the via structure 112 .

[0104] According to some embodiments, Figure 1H As shown in FIG. 1 , the chip package structure 100 is turned upside down. Figure 1HAs shown, according to some embodiments, the chip package structure 100 is bonded to the substrate 210 via solder balls 190 a .

[0105] According to some embodiments, during the bonding process, the bonding stress between the chip package structure 100 and the substrate 210 tends to be concentrated on the conductive bump 180. If the insulating layer 118 completely separates the conductive pad 167 under the conductive bump 180 from the barrier layer 117, the bonding stress concentrated on the conductive bump 180 may be transferred to the insulating layer 118 and may damage the insulating layer 118, which may reduce the yield of the bonding process.

[0106] According to some embodiments, since the conductive pad 167 under the conductive bump 180 directly contacts the barrier layer 117, the bonding stress concentrated on the conductive bump 180 is directly transferred to the barrier layer 117 and the semiconductor substrate 111. According to some embodiments, the bonding stress concentrated on the conductive bump 180 is prevented from damaging the insulating layer 118. According to some embodiments, since the barrier layer 117 is harder and thinner than the insulating layer 118, the barrier layer 117 can withstand the bonding stress concentrated on the conductive bump 180. According to some embodiments, the yield of the bonding process is improved.

[0107] In addition, according to some embodiments, since the conductive bump 180 is formed over the conductive pad 167 passing through the insulating layer 118, the coplanarity of the conductive bump 180 is not affected by the coplanarity of the insulating layer 118. Therefore, according to some embodiments, the coplanarity of the conductive bump 180 is improved. Therefore, according to some embodiments, the yield of the bonding process is improved.

[0108] In some embodiments, the ratio of the width W1 of the opening 118a to the width W2 of the conductive bump 180 is in a range of about 0.3 to about 1. In some embodiments, the ratio of the width W1 of the opening 118a to the width W2 of the conductive bump 180 is in a range of about 0.3 to about 0.8. If the ratio of the width W1 of the opening 118a to the width W2 of the conductive bump 180 is less than 0.3, the yield of the bonding process is slightly improved or not improved.

[0109] According to some embodiments, the substrate 210 includes an insulating layer 212, a wiring layer 214, a guide hole 216, and a conductive pad 218. According to some embodiments, the wiring layer 214 is formed in the insulating layer 212. According to some embodiments, the conductive pad 218 is formed above the insulating layer 212. According to some embodiments, the guide hole 216 provides electrical connection between different wiring layers 214 and between the wiring layer 214 and the conductive pad 218.

[0110] According to some embodiments, Figure 1HAs shown, an underfill layer 220 is formed between the substrates 110 and 210. In some embodiments, a portion of the underfill layer 220 is formed over the substrate 210 and surrounds the chip package structure 100. According to some embodiments, the underfill layer 220 is formed of an insulating material such as a polymer material. According to some embodiments, the chip package structure 200 is substantially formed in this step.

[0111] According to some embodiments, Figure 2 is a cross-sectional view of a chip packaging structure. According to some embodiments, Figure 2 As shown, in Figure 1F After the step of removing the mask layer 170 , an insulating layer 230 is then formed over the insulating layer 118 and the conductive pad 167 .

[0112] According to some embodiments, the insulating layer 230 covers the portion of the conductive pad 167 not covered by the conductive bump 180. According to some embodiments, the insulating layer 230 does not vertically overlap the conductive bump 180. According to some embodiments, the insulating layer 230 surrounds the conductive bump 180.

[0113] According to some embodiments, the insulating layer 230 is made of a polymer material such as epoxy, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF film, etc. In some embodiments, the insulating layer 230 is formed of a photosensitive material and may chemically react when exposed to light.

[0114] In some embodiments, the barrier layer 117 and the insulating layer 230 are made of different materials. According to some embodiments, the insulating layer 230 is formed using a dispensing process, a coating process, etc., or a combination thereof. According to some embodiments, as Figure 2 As shown, execute Figure 1G to Figure 1H The chip package structure 300 is formed by the steps of:

[0115] According to some embodiments, FIG. 3A to FIG. 3C is a cross-sectional view of various stages of a process for forming a chip packaging structure. According to some embodiments, Figure 3A As shown, in Figure 1E After the step of removing the mask layer 164, an insulating layer 310 is formed over the insulating layer 118 and the conductive pad 167. According to some embodiments, the insulating layer 310 has an opening 312. According to some embodiments, the opening 312 exposes the conductive pad 167 in the opening 118b of the insulating layer 118.

[0116] According to some embodiments, the insulating layer 310 is made of a polymer material such as epoxy resin, polyimide, polybenzoxazole (PBO), solder resist (SR), ABF film, etc. In some embodiments, the insulating layer 310 is formed of a photosensitive material and a chemical reaction may occur when exposed to light. In some embodiments, the barrier layer 117 and the insulating layer 310 are made of different materials.

[0117] According to some embodiments, the insulating layer 310 is formed using a coating process, a lamination process, a chemical vapor deposition process, or the like, or a combination thereof. According to some embodiments, the opening 312 is formed using a photolithography process and an etching process.

[0118] According to some embodiments, Figure 3A As shown, a seed layer 320 is formed over the insulating layer 310 and the conductive pad 167. In some embodiments, a bottom 322 of the seed layer 320 passes through the insulating layer 310 to conformally cover the second portion 167b of the conductive pad 167.

[0119] According to some embodiments, a bottom portion 322 of the seed layer 320 is partially located in the insulating layer 118. According to some embodiments, the seed layer 320 is formed of titanium, copper, etc. The material of the seed layer 320 may include other metals, such as silver, gold, aluminum, and combinations thereof.

[0120] Thereafter, according to some embodiments, as Figure 3A As shown, a mask layer 170 is formed over the seed layer 320. According to some embodiments, the mask layer 170 is in direct contact with the seed layer 320. According to some embodiments, the mask layer 170 has an opening 172. According to some embodiments, the opening 172 partially exposes the seed layer 320. According to some embodiments, the mask layer 170 is formed of a polymer material such as a photoresist material.

[0121] Thereafter, according to some embodiments, as Figure 3A As shown, conductive bumps 180 are formed in the openings 172 , respectively. According to some embodiments, the conductive bumps 180 are in direct contact with the seed layer 320 . According to some embodiments, the conductive bumps 180 are directly located above the openings 118 b . According to some embodiments, the conductive bumps 180 are directly located above the second portions 167 b of the conductive pads 167 .

[0122] According to some embodiments, the conductive bump 180 and the via structure 112 are offset in a vertical direction V1 perpendicular to the surface 111b. In some embodiments, according to some embodiments, the bottom 184 of the conductive bump 180 passes through the insulating layer 310. The insulating layer 310 is partially located between the conductive bump 180 and the conductive pad 167.

[0123] According to some embodiments, conductive bump 180 is formed of a conductive material such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or nickel (Ni). According to some embodiments, conductive bump 180 is formed using a plating process such as an electroplating process.

[0124] Thereafter, according to some embodiments, as Figure 3A As shown, solder layers 190 are formed respectively over the conductive bumps 180. According to some embodiments, solder layers 190 are formed of tin (Sn), lead-free solder, or other suitable conductive materials having a melting point lower than that of the conductive bumps 180. According to some embodiments, solder layers 190 are formed using a plating process such as an electroplating process.

[0125] According to some embodiments, Figure 3B As shown, the mask layer 170 is removed. According to some embodiments, the removal process includes an ashing process and / or a cleaning process. Thereafter, according to some embodiments, as Figure 3B As shown, the seed layer 320 initially located below the mask layer 170 is removed. According to some embodiments, the removal process includes an etching process such as a wet etching process or a dry etching process.

[0126] Thereafter, according to some embodiments, as Figure 3B As shown, a reflow process is performed on the solder layer 190 to convert the solder layer 190 into solder balls 190a. According to some embodiments, as Figure 3B As shown, a sawing process is performed to cut through the insulating layer 310 , the substrate 110 , and the molding layer 150 along predetermined sawing lines SC to form a chip package structure 400 .

[0127] According to some embodiments, the conductive bump 180 is electrically connected to the via structure 112 through the seed layer 320 and the underlying conductive pad 167. Figure 3C As shown, execute Figure 1H The chip package structure 500 is formed by performing the steps of:

[0128] According to some embodiments, Figure 4A is a cross-sectional view of a chip packaging structure 600. According to some embodiments, Figure 4B yes Figure 4A A top view of a chip package structure 600 is shown. According to some embodiments, Figure 4A It is along Figure 4B A cross-sectional view of the chip package structure 600 is shown along a cross-sectional line II′ in FIG.

[0129] According to some embodiments, Figure 4A and Figure 4B As shown, except that the conductive bump 180 overlaps with the guide hole structure 112 in the vertical direction, the chip package structure 600 is similar to Figure 3CA chip packaging structure 500 is provided.

[0130] The processes and materials used to form the chip package structures 300 , 500 , and 600 may be similar to or the same as the processes and materials used to form the above-described chip package structure 200 .

[0131] According to some embodiments, the present disclosure provides a chip packaging structure and a method for forming the same. This method (for forming a chip packaging structure) includes: forming a barrier layer and an insulating layer in sequence on a substrate, forming a conductive pad on the insulating layer, wherein the conductive pad has a first part and a second part, the first part passes through the barrier layer and the second insulating layer to connect with the guide hole structure in the substrate, and the second part passes through the insulating layer, and a conductive bump is formed on the second part. When a substrate is bonded to another substrate via a conductive bump, the bonding stress tends to be concentrated on the conductive bump. Since the second part passes through the insulating layer, the bonding stress concentrated on the conductive bump is directly transferred to the barrier layer and the substrate, but not to the insulating layer. Therefore, the insulating layer is protected from being damaged by the bonding stress. Therefore, the yield of the bonding process is improved.

[0132] According to some embodiments, the present disclosure provides a method for forming a chip packaging structure. The method includes forming a guide hole structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer above a second surface of the first substrate. The barrier layer directly contacts the first substrate, and the barrier layer has a first opening exposing the guide hole structure. The method includes forming a first insulating layer above the barrier layer. The first insulating layer has a second opening and a third opening, the second opening is located above the first opening and exposes the guide hole structure, the third opening partially exposes the barrier layer, and the barrier layer is thinner than the first insulating layer. The method includes forming a conductive pad above the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad extends continuously from the guide hole structure to the third opening. The method includes forming a conductive bump above the conductive pad in the third opening.

[0133] In some embodiments, the package structure forming method further includes bonding the first substrate to the second substrate through a conductive bump. In some embodiments, the conductive bump is thicker than the conductive pad, and the conductive bump directly contacts the conductive pad. In some embodiments, the bottom of the conductive bump is located in the third opening. In some embodiments, the second opening further exposes a portion of the barrier layer. In some embodiments, the conductive bump and the guide hole structure are misaligned in a vertical direction perpendicular to the second surface. In some embodiments, the chip package structure forming method further includes forming a second insulating layer above the first insulating layer and the conductive pad after forming the conductive bump above the conductive pad in the third opening, and the second insulating layer surrounds the conductive bump. In some embodiments, the first width of the conductive pad is greater than the sum of the second width of the conductive bump, the third width of the guide hole structure, and the distance between the conductive bump and the guide hole structure. In some embodiments, the operation of forming the conductive bump includes forming a mask layer above the conductive pad and the first insulating layer, the mask layer directly contacts the conductive pad and the first insulating layer, and the mask layer has a fourth opening, the fourth opening exposes the conductive pad located in the third opening, forms a conductive bump in the fourth opening, and removes the mask layer. In some embodiments, the barrier layer and the first insulating layer are formed of different materials.

[0134] According to some embodiments, the present disclosure provides a method for forming a chip packaging structure. The method includes forming a guide hole structure in a substrate. The method includes bonding a chip to a first surface of the substrate. The method includes forming a barrier layer above a second surface of the substrate, the barrier layer directly contacting the substrate. The method includes forming a first insulating layer partially above the barrier layer. The method includes forming a conductive pad above the first insulating layer, the conductive pad having a first portion and a second portion, the first portion passing through the barrier layer and the first insulating layer to connect to the guide hole structure, and the second portion passing through the first insulating layer and directly contacting the barrier layer. The method includes forming a second insulating layer above the first insulating layer and the conductive pad. The method includes forming a conductive bump above the second insulating layer, the first bottom of the conductive bump passing through the second insulating layer to connect to the second portion of the conductive pad.

[0135] In some embodiments, the chip packaging structure forming method further includes forming a seed layer above the second insulating layer before forming the conductive bump above the second insulating layer, the second bottom of the seed layer passes through the second insulating layer to conformally cover the second portion of the conductive pad, and the conductive bump is formed above the seed layer. In some embodiments, the second bottom of the seed layer is partially located in the first insulating layer. In some embodiments, the conductive pad has a W-shaped shape in a cross-sectional perspective. In some embodiments, the barrier layer is harder than the first insulating layer.

[0136] According to some embodiments, the present disclosure provides a chip packaging structure. The chip packaging structure includes a first substrate. The chip packaging structure includes a guide hole structure that passes through the first substrate. The chip packaging structure includes a chip located above a first surface of the first substrate. The chip packaging structure includes a barrier layer located above a second surface of the first substrate, and the barrier layer directly contacts the first substrate. The chip packaging structure includes a first insulating layer located above the barrier layer. The chip packaging structure includes a conductive pad located above the first insulating layer, the conductive pad having a first portion and a second portion, the first portion passing through the barrier layer and the first insulating layer to connect the guide hole structure, and the second portion passing through the first insulating layer and directly contacting the barrier layer. The chip packaging structure includes a conductive bump located above the second portion of the conductive pad.

[0137] In some embodiments, the conductive bump is thicker than the conductive pad, and the conductive bump directly contacts the conductive pad. In some embodiments, the contact area between the conductive bump and the conductive pad is greater than the area of ​​the top surface of the conductive bump. In some embodiments, the chip packaging structure further includes a second insulating layer located above the first insulating layer and the first portion of the conductive pad. In some embodiments, the chip packaging structure further includes a second insulating layer located above the first insulating layer and the conductive pad, the conductive bump passes through the second insulating layer to connect the conductive pad, and a portion of the second insulating layer is located between the conductive bump and the conductive pad.

[0138] The above content summarizes the features of many embodiments, so any technician in the relevant technical field can better understand the various aspects of the present disclosure. Any technician in the relevant technical field may have no difficulty in designing or modifying other processes and structures based on the present disclosure to achieve the same purpose and / or obtain the same advantages as the embodiments of the present disclosure. Any technician in the relevant technical field should also understand that different changes, substitutions and modifications are made without departing from the concept and scope of the present disclosure, and such equivalent creations do not exceed the concept and scope of the present disclosure.

Claims

1. A method for forming a chip packaging structure, comprising: forming a guide hole structure in a first substrate; Bonding a chip to a first surface of the first substrate; forming a barrier layer on a second surface of the first substrate, wherein the barrier layer directly contacts the first substrate and has a first opening exposing the guide hole structure; Forming a first insulating layer above the barrier layer, wherein the first insulating layer has a second opening and a third opening, the second opening is located above the first opening and exposes the guide hole structure, the third opening partially exposes the barrier layer, and the barrier layer is thinner than the first insulating layer; forming a conducting pad above the first insulating layer and in the first opening, the second opening, and the third opening, wherein the conducting pad continuously extends from the via structure to the third opening; as well as A conductive bump is formed above the conductive pad in the third opening.

2. The method for forming a chip packaging structure according to claim 1, further comprising: The first substrate is bonded to a second substrate through the conductive bump. 3 . The method for forming a chip package structure according to claim 1 , wherein the conductive bump is thicker than the conductive pad, and the conductive bump directly contacts the conductive pad. 4 . The chip package structure forming method according to claim 1 , wherein a bottom of the conductive bump is located in the third opening. 5 . The method for forming a chip package structure according to claim 1 , wherein the second opening further exposes a portion of the barrier layer. 6 . The method for forming a chip package structure according to claim 1 , wherein the conductive bump and the via structure are offset in a vertical direction perpendicular to the second surface.

7. The chip packaging structure forming method according to claim 1, further comprising: After forming the conductive bump above the conductive pad in the third opening, a second insulating layer is formed above the first insulating layer and the conductive pad, wherein the second insulating layer surrounds the conductive bump. 8 . The chip package structure forming method according to claim 1 , wherein a first width of the conductive pad is greater than a sum of a second width of the conductive bump, a third width of the via structure, and a distance between the conductive bump and the via structure.

9. The method for forming a chip package structure according to claim 1, wherein the operation of forming the conductive bump comprises: forming a mask layer above the conducting pad and the first insulating layer, wherein the mask layer directly contacts the conducting pad and the first insulating layer, and the mask layer has a fourth opening, and the fourth opening exposes the conducting pad located in the third opening; forming the conductive bump in the fourth opening; as well as Remove the mask layer. 10 . The method for forming a chip package structure according to claim 1 , wherein the barrier layer and the first insulating layer are formed of different materials.

11. A method for forming a chip packaging structure, comprising: forming a via structure in a substrate; bonding a chip to a first surface of the substrate; forming a barrier layer over a second surface of the substrate, wherein the barrier layer directly contacts the substrate; forming a first insulating layer partially over the barrier layer; forming a conducting pad on the first insulating layer, wherein the conducting pad has a first portion and a second portion, the first portion passes through the barrier layer and the first insulating layer to be connected to the via structure, and the second portion passes through the first insulating layer and directly contacts the barrier layer; forming a second insulating layer above the first insulating layer and the conducting pad; as well as A conductive bump is formed on the second insulating layer, wherein a first bottom of the conductive bump passes through the second insulating layer to connect the second portion of the conductive pad.

12. The method for forming a chip package structure according to claim 11, further comprising: Before forming the conductive bump over the second insulating layer, a seed layer is formed over the second insulating layer, wherein a second bottom of the seed layer passes through the second insulating layer to conformally cover the second portion of the conductive pad, and the conductive bump is formed over the seed layer. 13 . The method for forming a chip package structure according to claim 12 , wherein the second bottom portion of the seed layer is partially located in the first insulating layer. 14 . The method for forming a chip package structure according to claim 11 , wherein the conductive pad has a W-shaped shape in a cross-sectional view. 15 . The method for forming a chip package structure according to claim 11 , wherein the barrier layer is harder than the first insulating layer.

16. A chip packaging structure, comprising: a first substrate; A guide hole structure passing through the first substrate; A chip is located above a first surface of the first substrate; a barrier layer disposed over a second surface of the first substrate, wherein the barrier layer directly contacts the first substrate; a first insulating layer located above the barrier layer; a conducting pad located above the first insulating layer, wherein the conducting pad has a first portion and a second portion, the first portion passes through the barrier layer and the first insulating layer to connect the via structure, and the second portion passes through the first insulating layer and directly contacts the barrier layer; as well as A conductive bump is located above the second portion of the conductive pad. 17 . The chip package structure of claim 16 , wherein the conductive bump is thicker than the conductive pad, and the conductive bump directly contacts the conductive pad. 18 . The chip package structure according to claim 17 , wherein a contact area between the conductive bump and the conductive pad is larger than an area of ​​a top surface of the conductive bump.

19. The chip package structure according to claim 16, further comprising: A second insulating layer is located above the first insulating layer and the first portion of the conducting pad.

20. The chip packaging structure according to claim 16, further comprising: A second insulating layer is located above the first insulating layer and the conducting pad, wherein the conducting bump passes through the second insulating layer to connect to the conducting pad, and the second insulating layer is partially located between the conducting bump and the conducting pad.

21. A chip packaging structure, comprising: a first substrate; A guide hole structure passing through the first substrate; A chip is located above a first surface of the first substrate; a barrier layer disposed over a second surface of the first substrate, wherein the barrier layer directly contacts the first substrate; an insulating layer located above the barrier layer; a conductive pad, located above the insulating layer and passing through the insulating layer and the barrier layer to be connected to the via structure; as well as A conductive bump is located above the conductive pad, wherein in a top view of the conductive pad, the conductive bump and the guide hole structure, the conductive bump and the guide hole structure are separated from each other, and the conductive bump is electrically connected to the guide hole structure through the conductive pad.

22. The chip packaging structure of claim 21, wherein the conductive pad has a first portion and a second portion, the first portion passes through the barrier layer and the insulating layer to be connected to the via structure, the second portion passes through the insulating layer and directly contacts the barrier layer, and the conductive bump is located above the second portion. 23 . The chip package structure according to claim 22 , wherein a third portion of the insulating layer is located between the first portion and the second portion. 24 . The chip package structure according to claim 22 , wherein the second portion does not pass through the barrier layer. 25 . The chip package structure according to claim 21 , further comprising a second substrate, wherein the first substrate is bonded to the second substrate through the conductive bump. 26 . The chip package structure of claim 21 , wherein the conductive bump is thicker than the conductive pad, and the conductive bump directly contacts the conductive pad. 27 . The chip package structure of claim 21 , wherein a bottom of the conductive bump is embedded in the insulating layer and is located above the barrier layer. 28 . The chip package structure of claim 21 , wherein a first width of the conducting pad is greater than a sum of a second width of the conducting bump and a third width of the via structure. 29 . The chip package structure of claim 21 , wherein a first width of the conducting pad is greater than a sum of a second width of the conducting bump, a third width of the via structure, and a distance between the conducting bump and the via structure. 30 . The chip package structure according to claim 21 , wherein the barrier layer and the insulating layer are formed of different materials.

31. A chip packaging structure, comprising: a first substrate; A guide hole structure passing through the first substrate; A chip is located above a first surface of the first substrate; a barrier layer disposed over a second surface of the first substrate, wherein the barrier layer directly contacts the first substrate; an insulating layer located above the barrier layer; a conductive pad, located above the insulating layer and passing through the insulating layer and the barrier layer to connect the via structure; as well as A conductive bump is located above the conductive pad, wherein the conductive bump and the guide hole structure are offset in a vertical direction perpendicular to the second surface, and the conductive pad directly contacts the conductive bump and the guide hole structure.

32. A chip packaging structure as claimed in claim 31, wherein the conductive pad has a first portion and a second portion, the first portion passes through the barrier layer and the insulating layer to connect with the guide hole structure, the second portion passes through the insulating layer and directly contacts the barrier layer, and the conductive bump is located above the second portion. 33 . The chip packaging structure of claim 31 , wherein when viewed from a cross-sectional direction of the conducting pad, the conducting pad has a W-shaped shape. 34 . The chip package structure according to claim 33 , wherein the conducting pad directly contacts the insulating layer and the barrier layer. 35 . The chip package structure of claim 31 , wherein the barrier layer is harder than the insulating layer.

36. A chip packaging structure, comprising: a first substrate; A guide hole structure passing through the first substrate; A chip is located above a first surface of the first substrate; a barrier layer disposed over a second surface of the first substrate, wherein the barrier layer directly contacts the first substrate; a first insulating layer located above the barrier layer; a conductive pad, located above the insulating layer and passing through the insulating layer and the barrier layer to connect the via structure; a conductive bump located above the conductive pad; as well as A second insulating layer is located above the first insulating layer and the conducting pad, wherein a portion of the second insulating layer is embedded in the conducting pad above the via structure, and the conducting pad is partially located between the portion and the via structure. 37 . The chip package structure of claim 36 , wherein the portion of the second insulating layer and the via structure are arranged in a vertical direction perpendicular to the second surface. 38 . The chip package structure according to claim 36 , wherein the second insulating layer directly contacts the first insulating layer, the conductive pad, and the conductive bump.

39. The chip package structure according to claim 36, wherein the second insulating layer is partially located between the conductive bump and the conductive pad. 40 . The chip package structure according to claim 36 , wherein the conductive bump covers the portion of the second insulating layer.

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