Wafer, method for manufacturing the same, and semiconductor device

Abstract

The present disclosure relates to a wafer, a method for manufacturing the same, and a semiconductor device. The method for manufacturing the wafer includes: providing a wafer body, on which a dicing street for dicing is provided; forming a crack-stop silicon through-hole on a side portion of the dicing street, and a protective material is filled in the silicon through-hole. By providing crack-stop silicon through-holes filled with a protective material on both sides of the dicing street, when the wafer is diced, the cutting stress is prevented from damaging the die area. The crack-stop silicon through-holes can effectively reduce the width of the dicing street, which is beneficial to the miniaturization of the dicing street and improves the effective utilization rate of the wafer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a wafer, a method for manufacturing the same, and a semiconductor device. Background Art

[0002] With the development and progress of technology, the integration degree of integrated circuit chips is getting higher and higher. Single-layer chips can no longer meet the usage requirements, and the application of multi-layer stacked chips is becoming more and more extensive. Stacked chips are obtained by cutting multi-layer stacked wafers.

[0003] The multi-layer stacked wafer includes a die area and a dicing area. When dicing the dicing area, the die area may be damaged due to the influence of dicing stress and the like. In order to ensure that the die area is not damaged during dicing, a relatively large area of the dicing area is usually set. However, an overly large dicing area reduces the effective utilization rate of the wafer, thereby increasing the cost of the chip.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a wafer, a method for manufacturing the same, and a semiconductor device, so as to at least to some extent overcome the problem of low effective utilization rate of the wafer caused by the relatively large dicing area of the wafer in the related art.

[0006] According to a first aspect of the present disclosure, there is provided a method for manufacturing a wafer, the method for manufacturing a wafer including:

[0007] Providing a wafer body, on which a dicing lane for dicing is provided;

[0008] Forming a crack-stop silicon through-hole on a side portion of the dicing lane, and filling a protective material in the silicon through-hole.

[0009] According to an embodiment of the present disclosure, the forming a crack-stop silicon through-hole on a side portion of the dicing lane includes:

[0010] Forming a blind hole on a side portion of the dicing lane on a first surface of the wafer body;

[0011] Filling a protective material in the blind hole;

[0012] Thinning a second surface of the wafer body until the blind hole is exposed, the second surface being opposite to the first surface.

[0013] According to an embodiment of the present disclosure, the forming a crack-stop silicon through-hole on a side portion of the dicing lane includes:

[0014] A first anti-crack silicon through hole is formed at a side portion of a scribe line on a first wafer body;

[0015] A protective material is filled in the first anti-crack silicon through hole;

[0016] A second anti-crack silicon through hole is formed at a position corresponding to the scribe line side portion on the first anti-crack silicon through hole on a second wafer body, and the first wafer body and the second wafer body are stacked;

[0017] The protective material is filled in the second anti-crack silicon through hole.

[0018] According to an embodiment of the present disclosure, forming an anti-crack silicon through hole at a side portion of the scribe line includes:

[0019] Anti-crack silicon through holes are formed on both sides in the extending direction of the scribe line.

[0020] According to an embodiment of the present disclosure, the anti-crack silicon through hole includes continuously distributed silicon through holes or discretely distributed silicon through holes.

[0021] According to an embodiment of the present disclosure, multiple rows of anti-crack silicon through holes are formed on one side of the scribe line.

[0022] According to an embodiment of the present disclosure, the width of the anti-crack silicon through hole is 2 μm - 20 μm, and the depth of the anti-crack silicon through hole is 15 μm - 150 μm.

[0023] According to an embodiment of the present disclosure, the protective material includes one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate.

[0024] According to an embodiment of the present disclosure, an air gap hole is provided in the anti-crack silicon through hole.

[0025] According to a second aspect of the present disclosure, there is provided a wafer, the wafer including:

[0026] A wafer body, on which a scribe line for cutting is provided;

[0027] Anti-crack silicon through holes, provided at a side portion of the scribe line, and a protective material is filled in the anti-crack silicon through holes.

[0028] According to an embodiment of the present disclosure, the anti-crack silicon through holes are formed on both sides in the extending direction of the scribe line.

[0029] According to an embodiment of the present disclosure, the anti-crack silicon through hole includes continuously distributed silicon through holes or discretely distributed silicon through holes.

[0030] According to an embodiment of the present disclosure, multiple rows of crack-stop silicon vias are formed on one side of the dicing street.

[0031] According to an embodiment of the present disclosure, the width of the crack-stop silicon via is 2 μm - 20 μm, and the depth of the crack-stop silicon via is 15 μm - 150 μm.

[0032] According to an embodiment of the present disclosure, the protective material includes one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate.

[0033] According to an embodiment of the present disclosure, air gap holes are provided in the crack-stop silicon vias.

[0034] According to a third aspect of the present disclosure, a semiconductor device is provided, which includes multiple layers of the above-mentioned wafers stacked on top of each other.

[0035] The wafer manufacturing method provided by the present disclosure prevents the cutting stress from damaging the die area during wafer dicing by providing crack-stop silicon vias filled with a protective material on both sides of the dicing street. The crack-stop silicon vias can effectively reduce the width of the dicing street, which is beneficial to the miniaturization of the dicing street and improves the effective utilization rate of the wafer.

[0036] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0038] Figure 1 It is a flowchart of the first wafer manufacturing method provided for an exemplary embodiment of the present disclosure.

[0039] Figure 2 It is a flowchart of the second wafer manufacturing method provided for an exemplary embodiment of the present disclosure.

[0040] Figure 3 It is a flowchart of the third wafer manufacturing method provided for an exemplary embodiment of the present disclosure.

[0041] Figure 4 It is a top view schematic diagram of a wafer provided for an exemplary embodiment of the present disclosure.

[0042] Figure 5 A cross-sectional schematic diagram of a wafer provided by an exemplary embodiment of the present disclosure.

[0043] Figures 6 to 9 A process diagram for forming a crack-stop through-silicon via provided by an exemplary embodiment of the present disclosure.

[0044] Figures 10 to 11 Another process diagram for forming a crack-stop through-silicon via provided by an exemplary embodiment of the present disclosure.

[0045] Figure 12 A schematic diagram of the distribution of crack-stop through-silicon vias provided by an exemplary embodiment of the present disclosure.

[0046] Figure 13 A schematic diagram of a crack-stop through-silicon via provided by an exemplary embodiment of the present disclosure.

[0047] Figure 14 Another schematic diagram of the distribution of crack-stop through-silicon vias provided by an exemplary embodiment of the present disclosure.

[0048] In the figure:

[0049] 100, wafer body; 110, die; 120, saw street; 200, crack-stop through-silicon via; 210, blind hole; 230, first crack-stop through-silicon via; 240, second crack-stop through-silicon via; 250, air gap hole; 20, protective material layer; 300, first wafer body; 400, second wafer body. Detailed implementation manners

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted.

[0051] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0052] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and refer to the possibility of the existence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and do not limit the quantity of their objects.

[0053] In this exemplary embodiment, a wafer manufacturing method is first provided. As Figure 1 shown, the wafer manufacturing method may include the following steps:

[0054] Step S110: Provide a wafer body 100, on which a dicing street 120 for dicing is provided;

[0055] Step S120: Form a crack-stop silicon through-hole 200 on the side of the dicing street 120, and the through-hole is filled with a protective material.

[0056] In the wafer manufacturing method provided by the embodiments of the present disclosure, by providing crack-stop silicon through-holes 200 filled with a protective material on both sides of the dicing street 120, when the wafer is diced, the cutting stress is prevented from damaging the die area 110. Through the crack-stop silicon through-holes 200, the width of the dicing street 120 can be effectively reduced, which is beneficial to the miniaturization of the dicing street 120 and improves the effective utilization rate of the wafer.

[0057] In step S110, the wafer body 100 may be divided into a dicing street 120 and a die area 110. During dicing, the dicing blade acts on the dicing street 120, and the die area 110 is reserved. The wafer body 100 may include a silicon substrate such as a silicon epitaxial wafer or silicon-on-insulator, or may be a substrate of other semiconductor materials such as GaN. Moreover, the substrate may be an intrinsic semiconductor substrate, or an N-type doped or P-type doped semiconductor substrate, and the embodiments of the present disclosure do not limit this. A dielectric layer may be provided on the substrate, and the material of the dielectric layer may be one or more of silicon oxide, silicon nitride or silicon oxynitride. In specific implementation, the dielectric layer may be formed by methods such as chemical vapor deposition or atomic layer deposition. It can be understood that the dielectric layer may be a single insulating material layer, or may be a stack of multiple identical or different insulating material layers.

[0058] In a feasible implementation manner provided by the embodiments of the present disclosure, as Figure 2 shown, step S120 may include:

[0059] Step S210: Form a blind hole 210 on the side of the dicing street 120 on the first surface of the wafer body 100;

[0060] Step S220: Fill the blind hole 210 with a protective material;

[0061] Step S230: Thin the second surface of the wafer body 100 until the blind hole 210 is exposed. The second surface is opposite to the first surface.

[0062] In step S210, as Figure 6 shown, a blind hole 210 is formed on the side of the dicing channel 120 on the first surface of the wafer body 100. Among them, the blind hole 210 can be formed by dry etching, wet etching, laser etching or a combination of dry and wet etching. For example, dry etching can be reactive ion etching or inductively coupled plasma etching, and wet etching can be etching with hydrofluoric acid solution, buffered hydrofluoric acid etching solution or potassium hydroxide solution, TMAH solution. The blind hole 210 is located on the side of the dicing channel 120, and the cross-section of the blind hole 210 can be rectangular or trapezoidal.

[0063] It should be noted that the position of the blind hole 210 can be defined by photoresist. A photoresist is coated on the first surface of the wafer body 100, exposed through a corresponding mask plate, and the pattern of the mask plate is transferred to the photoresist layer; through development, the area to be opened with the crack stopping silicon through hole 200 is exposed on the photoresist layer; the blind hole 210 is formed by etching.

[0064] In step S220, as Figure 7 shown, a protective material can be filled in the blind hole 210. The protective material can be one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride and titanium nitride. At this time, an insulating layer can be formed on the wall of the blind hole 210 and the first surface of the wafer body 100 before filling the protective material. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition or thermal growth. The above conductive material is filled in the blind hole 210, for example, the above conductive material is filled in the blind hole 210 by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protection layer is electroplated and filled on the seed layer. During electroplating, a metal layer will be formed on the first surface of the wafer body 100, and this metal layer needs to be removed, for example, by etching or chemical mechanical polishing.

[0065] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition or thermal growth. At the same time, as Figure 7 shown, a protective material layer 20 will be formed on the first surface of the wafer body 100. At this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, as Figure 13 shown, air gap holes 250 can be provided between the protective materials filled in the blind hole 210.

[0066] In step S230, as Figure 9 shown, the second surface of the wafer body 100 is thinned until the blind hole 210 is exposed. The second surface of the wafer body 100 can be thinned by etching or chemical mechanical polishing, where the second surface of the wafer body 100 is opposite to the first surface. For example, if the first surface of the wafer body 100 is the back surface of the wafer body 100, then the second surface is the front surface of the wafer body 100.

[0067] In a feasible implementation provided by the embodiments of the present disclosure, as Figure 3 shown, step S120 may include:

[0068] Step S310, forming a first crack-stop silicon through-hole 230 on the side of the dicing street 120 on the first wafer body 300;

[0069] Step S320, filling a protective material in the first crack-stop silicon through-hole 230;

[0070] Step S330, forming a second crack-stop silicon through-hole 240 at a position corresponding to the side of the dicing street 120 on the second wafer body 400 and the first crack-stop silicon through-hole 230, where the first wafer body 300 and the second wafer body 400 are stacked;

[0071] Step S340, filling the protective material in the second crack-stop silicon through-hole 240.

[0072] In step S310, as Figure 10 shown, a first crack-stop silicon through-hole 230 can be formed on the side of the dicing street 120 on the first wafer body 300. In the case of multi-layer wafer stacking, by first forming blind holes 210 on each layer of wafer body, filling them, then thinning the wafer body 100, and then bonding multi-layer wafers, the process is complex. Therefore, a double-layer stacking structure can be formed first, and then crack-stop silicon through-holes are formed on each layer of wafer body 100 respectively, which can simplify the manufacturing process and improve production efficiency. For example, the stacking structure includes a first wafer body 300 and a second wafer body 400 stacked. A first crack-stop silicon through-hole 230 can be formed on the surface of the first wafer body 300 to expose the second wafer 400, and the first crack-stop silicon through-hole 230 is filled; then a second crack-stop silicon through-hole 240 is formed at a position corresponding to the surface of the second wafer body 400 and the first crack-stop silicon through-hole 230 to expose the first cut silicon through-hole 230, and the second cut silicon through-hole 240 is filled, omitting the thinning step and simplifying the manufacturing process.

[0073] Among them, the first crack-stopping silicon through hole 230 can be formed by dry etching, wet etching, laser etching or a combination of dry and wet etching. For example, dry etching can be reactive ion etching or inductively coupled plasma etching, and wet etching can be etching with hydrofluoric acid solution, buffered hydrofluoric acid etching solution, potassium hydroxide solution or TMAH solution. The first crack-stopping silicon through hole 230 is located on the side of the dicing street 120, and the cross-section of the first crack-stopping silicon through hole 230 can be rectangular or trapezoidal.

[0074] It should be noted that the position of the first crack-stopping silicon through hole 230 can be defined by photoresist. A photoresist is coated on the surface of the first wafer body 300 and exposed through a corresponding mask plate to transfer the pattern of the mask plate to the photoresist layer; through development, the area where the crack-stopping silicon through hole 200 is to be opened is exposed on the photoresist layer; the first crack-stopping silicon through hole 230 is formed by etching.

[0075] In step S320, a protective material can be filled in the first crack-stopping silicon through hole 230. The protective material can be one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride and titanium nitride. At this time, an insulating layer can be formed on the wall of the first crack-stopping silicon through hole 230 and the surface of the wafer body 100 before filling the protective material. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition or thermal growth. The above conductive material is filled in the first crack-stopping silicon through hole 230, for example, the above conductive material is filled in the first crack-stopping silicon through hole 230 by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protection layer is electroplated and filled on the seed layer. During the electroplating process, a metal layer will be formed on the surface of the wafer body 100, and this metal layer needs to be removed, for example, by etching or chemical mechanical polishing.

[0076] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition or thermal growth. At the same time, a protective material layer 20 will be formed on the surface of the first wafer body 300, and at this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, air gap holes 250 can be provided between the protective materials filled in the first crack-stopping silicon through hole 230.

[0077] In step S330, such as Figure 11As shown, a second crack stop silicon through hole 240 can be formed at a position corresponding to the side of the dicing street 120 and the first crack stop silicon through hole 230 on the second wafer body 400. Among them, the second crack stop silicon through hole 240 can be formed by dry etching, wet etching, laser etching or a combination of dry and wet etching. For example, dry etching can be reactive ion etching or inductively coupled plasma etching, and wet etching can be potassium hydroxide solution etching. The second crack stop silicon through hole 240 is located at the side of the dicing street 120, and the cross section of the second crack stop silicon through hole 240 can be rectangular or trapezoidal.

[0078] It should be noted that the position of the second crack stop silicon through hole 240 can be defined by photoresist. A photoresist is coated on the surface of the second wafer body 400 and exposed through a corresponding mask plate, and the pattern of the mask plate is transferred to the photoresist layer; through development, the area where the crack stop silicon through hole 200 is to be opened is exposed on the photoresist layer; the second crack stop silicon through hole 240 is formed by etching.

[0079] In step S340, the protective material is filled in the second crack stop silicon through hole 240. The protective material can be one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride and titanium nitride. At this time, an insulating layer can be formed on the wall of the second crack stop silicon through hole 240 and the surface of the wafer body 100 first when filling the protective material. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition or thermal growth. The above conductive material is filled in the second crack stop silicon through hole 240. For example, the above conductive material is filled in the second crack stop silicon through hole 240 by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protection layer is electroplated and filled on the seed layer. During electroplating, a metal layer will be formed on the surface of the wafer body 100, and this metal layer needs to be removed, for example, by etching or chemical mechanical polishing.

[0080] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition or thermal growth. At the same time, a protective material layer 20 will be formed on the surface of the second wafer body 400. At this time, the protective material layer 20 can be removed or not removed according to actual needs. Further, as Figure 13 shown, an air gap hole 250 can be provided between the protective materials filled in the second crack stop silicon through hole 240.

[0081] For a structure with more layers of wafer stacking, on the basis of the double-layer stacking structure in which the first crack stop silicon through hole 230 and the second crack stop silicon through hole 240 have been formed, each additional layer of wafer can be fabricated by the method of stacking first and then forming the crack stop silicon through hole, which can simplify the manufacturing process and improve production efficiency.

[0082] As Figure 12 shown, anti-crack silicon vias 200 are formed on both sides of the cutting lane 120 in the extending direction. Of course, in practical applications, anti-crack silicon vias 200 can also be provided on one side of the cutting lane 120, and the embodiments of the present disclosure are not limited thereto. The anti-crack silicon vias 200 include continuously distributed silicon vias or discretely distributed silicon vias. Multiple rows of anti-crack silicon vias 200 are formed on one side of the cutting lane 120. The width L of the anti-crack silicon vias 200 is 2 μm - 20 μm, and the depth S of the anti-crack silicon vias 200 is 15 μm - 150 μm. When there are multiple rows of anti-crack silicon vias 200 on one side of the cutting lane 120, the width of the entire silicon via region is 2 μm - 20 μm. The width of the anti-crack silicon vias 200 refers to the distance between two sidewalls of the anti-crack silicon vias 200 parallel to the cutting lane 120.

[0083] Among them, as Figure 14 shown, multiple rows of cutting silicon vias 200 can be provided on one side of the cutting lane 120, and the multiple rows of cutting silicon vias 200 can be arranged in parallel within the cutting lane 120, and the cutting stress is further relieved by the multiple rows of anti-crack silicon vias.

[0084] In the wafer manufacturing method provided by the embodiments of the present disclosure, by providing anti-crack silicon vias 200 filled with a protective material on both sides of the cutting lane 120, when the wafer is cut, the cutting stress is prevented from damaging the die area 110. The anti-crack silicon vias 200 can effectively reduce the width of the cutting lane 120, which is beneficial to the miniaturization of the cutting lane 120, improves the effective utilization rate of the wafer, and reduces the cost of the chip.

[0085] In this exemplary embodiment, a wafer is also provided. As Figure 4 shown, the wafer includes a wafer body 100 and anti-crack silicon vias 200. A cutting lane 120 for cutting is provided on the wafer body 100; the anti-crack silicon vias 200 are provided on the side of the cutting lane 120, and the anti-crack silicon vias 200 are filled with a protective material.

[0086] In the wafer provided by the embodiments of the present disclosure, by providing anti-crack silicon vias 200 filled with a protective material on both sides of the cutting lane 120, when the wafer is cut, the cutting stress is prevented from damaging the die area 110. The anti-crack silicon vias 200 can effectively reduce the width of the cutting lane 120, which is beneficial to the miniaturization of the cutting lane 120 and improves the effective utilization rate of the wafer.

[0087] The wafer body 100 can be divided into scribe lanes 120 and die areas 110. During dicing, the dicing blade acts on the scribe lanes 120, and the die areas 110 are reserved. The wafer body 100 can include a silicon substrate such as a silicon epitaxial wafer or silicon-on-insulator, or can be a substrate of other semiconductor materials such as GaN. Moreover, the substrate can be an intrinsic semiconductor substrate, or an N-type doped or P-type doped semiconductor substrate, which is not limited in the embodiments of the present disclosure. A dielectric layer can be provided on the substrate, and the material of the dielectric layer can be one or more of silicon oxide, silicon nitride, or silicon oxynitride. In specific implementation, the dielectric layer can be formed by methods such as chemical vapor deposition or atomic layer deposition. It can be understood that the dielectric layer can be a single layer of insulating material layer, or can be formed by laminating multiple layers of the same or different insulating material layers.

[0088] Stop crack silicon vias 200 are formed on both sides of the extending direction of the scribe lane 120. Of course, in practical applications, the stop crack silicon vias 200 can also be provided on one side of the scribe lane 120, and the embodiments of the present disclosure are not limited thereto. The stop crack silicon vias 200 include continuously distributed silicon vias or discretely distributed silicon vias. Multiple rows of stop crack silicon vias 200 are formed on one side of the scribe lane 120. The width L of the stop crack silicon vias 200 is 2 μm - 20 μm, and the depth S of the stop crack silicon vias 200 is 15 μm - 150 μm. When there are multiple rows of stop crack silicon vias 200 on one side of the scribe lane 120, the width of the entire area of the silicon vias is 2 μm - 20 μm. The width of the stop crack silicon vias 200 refers to the distance between two sidewalls of the stop crack silicon vias 200 parallel to the scribe lane 120.

[0089] The protective material can include one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate. Further, air gap holes 250 are provided in the stop crack silicon vias 200.

[0090] When the protective material is one or more of conductive materials such as copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, and titanium nitride, at this time, the stop crack silicon vias 200 can include an insulating layer and a protective material layer, and the insulating layer is located between the through holes on the wafer body 100 and the protective material. When filling the protective material, an insulating layer can be first formed on the through hole walls and the first surface of the wafer body 100. For example, the insulating layer can be formed by chemical vapor deposition, physical vapor deposition, or thermal growth. The above-mentioned conductive materials are filled into the through holes, for example, the above-mentioned conductive materials are filled into the through holes by electroplating. First, a seed layer is deposited on the insulating layer, and a metal protective layer is electroplated and filled on the seed layer.

[0091] When the filling material is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide, and tetraethyl orthosilicate, etc., the protective material can be filled by chemical vapor deposition, physical vapor deposition, or thermal growth. At the same time, a protective material layer 20 will be formed on the first surface of the wafer body 100. At this time, the protective material layer can be removed or not removed according to actual needs. Further, air gap holes 250 can be provided between the protective materials filled in the blind holes 210.

[0092] For the wafer provided by the embodiment of the present disclosure, by providing the crack-stop silicon vias 200 filled with the protective material on both sides of the scribe line 120, when the wafer is cut, the cutting stress can be prevented from damaging the die area 110. Through the crack-stop silicon vias 200, the width of the scribe line 120 can be effectively reduced, which is beneficial to the miniaturization of the scribe line 120, improves the effective utilization rate of the wafer, and reduces the chip cost.

[0093] In this exemplary embodiment, a semiconductor device is further provided. The semiconductor device includes multiple layers of the above-mentioned wafers stacked on top of each other. The crack-stop silicon vias 200 are provided on both sides of the scribe line 120 of each layer of wafer. The positions of the scribe lines 120 of the multiple layers of wafers correspond to each other. After the multiple layers of wafers are stacked, the projections of the scribe lines 120 of the multiple layers of wafers on any one layer of wafer coincide. Cut the wafer along the scribe line 120 to obtain multiple stacked dies.

[0094] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A wafer manufacturing method, characterized in that, the wafer manufacturing method includes: providing a first wafer body and a second wafer body which are stacked, and scribe lines for cutting are provided on the surfaces of the stacked first wafer body and the second wafer body; forming a crack stopping silicon through hole on the side of the scribe line, and the silicon through hole is filled with a protective material, wherein forming a crack stopping silicon through hole on the side of the scribe line includes: forming a first crack stopping silicon through hole in the first wafer body along the side of the scribe line, and the first crack stopping silicon through hole exposes the second wafer body; filling the first crack stopping silicon through hole with a protective material; forming a second crack stopping silicon through hole at a position corresponding to the first crack stopping silicon through hole on the second wafer body along the side of the scribe line, and the second crack stopping silicon through hole exposes the first crack stopping silicon through hole; filling the second crack stopping silicon through hole with the protective material; the first crack stopping silicon through hole and the second crack stopping silicon through hole form the crack stopping silicon through hole.

2. The wafer manufacturing method according to claim 1, characterized in that, forming a crack stopping silicon through hole on the side of the scribe line includes: forming the crack stopping silicon through holes on both sides in the extending direction of the scribe line.

3. The wafer manufacturing method according to claim 1, characterized in that, the crack stopping silicon through hole includes continuously distributed silicon through holes or discretely distributed silicon through holes.

4. The wafer manufacturing method according to claim 1, characterized in that, multiple rows of crack stopping silicon through holes are formed on one side of the scribe line.

5. The wafer manufacturing method according to claim 1, characterized in that, the width of the crack stopping silicon through hole is 2 micrometers - 20 micrometers, and the depth of the crack stopping silicon through hole is 15 micrometers - 150 micrometers.

6. The wafer manufacturing method according to claim 1, characterized in that, the protective material includes one or more of copper, tungsten, aluminum, tantalum, titanium, tantalum nitride, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, polyimide and tetraethyl orthosilicate.

7. The wafer manufacturing method according to claim 1, characterized in that, air gap holes are provided in the crack stopping silicon through hole.

8. A semiconductor device, characterized in that, it includes multiple wafers formed by the wafer manufacturing method according to any one of claims 1 - 7, and the multiple wafers are stacked.

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