High capacity semiconductor device including bifurcated memory module

Abstract

The present invention is entitled "High Capacity Semiconductor Device Including Bifurcated Memory Modules". The present invention discloses a semiconductor device comprising a stacked wafer of integrated memory modules. The semiconductor device of the present technology may include a plurality of memory array semiconductor wafers and a CMOS controller wafer, the plurality of memory array semiconductor wafers and the CMOS controller wafer working together as a single integrated flash memory semiconductor device. In an embodiment, the CMOS controller wafer may include a semiconductor die including an ASIC logic circuit integrated with a memory array logic circuit.

Description

Background Art

[0001] Strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, have become widely used to meet the growing demand for digital information storage and exchange. These memory devices are designed to be portable, versatile, and rugged. Their high reliability and large capacity make them ideal for use in a variety of electronic devices, including digital cameras, digital music players, video game consoles, PDAs, cellular phones, and solid-state drives.

[0002] Recently, ultra-high-density memory devices have been proposed that use a 3D stacked memory structure with strings of memory cells formed into layers. One such memory device is sometimes referred to as a bit-cost-scaling (BiCS) architecture. In addition to the layered memory cells, 3D memory devices also include logic circuitry for controlling the read / write operation of the memory cells. This logic circuitry is often fabricated using complementary metal-oxide-semiconductor (CMOS) technology and is typically formed beneath the stacked memory layers within a semiconductor wafer.

[0003] Currently, the use of flash memory devices as solid-state drives (SSDs) in data centers is a major initiative. As the number of memory layers in 3D memory structures increases to meet growing data center memory demands, positioning logic circuitry underneath the 3D memory cell structures becomes increasingly challenging. Furthermore, process parameters optimized for memory array formation may not be optimized for logic circuit formation. For example, utilizing heat to anneal 3D memory cell structures is known. While heat is beneficial for the memory cell structure, it can adversely affect the operation of the logic circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a flow chart for forming a first wafer including a controller die according to an embodiment of the present technology.

[0005] Figure 2 is a top view of a first major surface of a first semiconductor wafer including a controller die according to an embodiment of the present technology.

[0006] Figure 3 is a top view of a controller die of a first semiconductor wafer according to an embodiment of the present technology.

[0007] Figure 4 is a cross-sectional edge view of a controller die of a first semiconductor wafer in accordance with an embodiment of the present technology.

[0008] Figure 5 is a schematic block diagram of a controller die according to an embodiment of the present technology.

[0009] Figure 6 is a flow chart for forming a second wafer including memory array dies according to an embodiment of the present technology.

[0010] Figure 7 is a top view of a first major surface of a second semiconductor wafer including memory array dies according to an embodiment of the present technology.

[0011] Figure 8 is a top view of memory array dies of a second semiconductor wafer according to an embodiment of the present technology.

[0012] Figure 9 is a cross-sectional edge view of a memory array die of a second semiconductor wafer in accordance with an embodiment of the present technology.

[0013] Figure 10 is a flow chart for forming a semiconductor device according to an embodiment of the present technology.

[0014] Figure 11 is a perspective view of multiple stacked wafers forming an integrated wafer semiconductor device according to an embodiment of the present technology.

[0015] Figure 12 is an exploded cross-sectional edge view of a plurality of stacked semiconductor dies from a wafer forming an integrated wafer memory module in accordance with an embodiment of the present technology.

[0016] Figure 13 is a cross-sectional edge view of a memory module coupled to a semiconductor device of a host device in accordance with the present technology.

[0017] Figure 14 is a functional block diagram of a memory module according to an embodiment of the present technology.

[0018] Figure 15 is a perspective view of a plurality of stacked wafers forming a multi-channel integrated wafer semiconductor device according to an embodiment of the present technology.

[0019] Figure 16 is a functional block diagram of a multi-channel integrated wafer memory module according to an embodiment of the present technology. DETAILED DESCRIPTION

[0020] The technology of the present invention will now be described with reference to the accompanying drawings, which in an embodiment relate to a semiconductor device comprising wafers of stacked integrated memory modules. The semiconductor device of the technology of the present invention may include a plurality of memory array semiconductor wafers and a CMOS controller wafer, and the plurality of memory array semiconductor wafers and the CMOS controller wafer work together as a single integrated flash memory semiconductor device. In an embodiment, the CMOS controller wafer may include a semiconductor die that includes an ASIC logic circuit integrated with the memory array logic circuit. The ASIC logic circuit of the controller wafer die performs memory management and acts as an interface with a host device such as a server or host in a data center. The memory array logic circuit of the controller wafer die includes sensor amplifiers and peripheral functions, and acts as an interface with the memory array of the memory array wafer die.

[0021] The controller and memory array wafer dies may be formed with through-silicon vias (TSVs) so that once the controller and memory array wafers are stacked, the TSVs of the corresponding stacked semiconductor dies may be aligned and attached to one another, thereby electrically and mechanically connecting each semiconductor die in the corresponding wafers to form an integrated semiconductor device. Further details of the integrated semiconductor device and TSVs according to the present technology are provided below.

[0022] It should be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the present invention will be fully conveyed to those skilled in the art. In fact, the present invention is intended to cover alternatives, modifications, and equivalents of these embodiments, which are all included within the scope and spirit of the present invention as defined by the appended claims. In addition, in the following specific embodiments of the present invention, many specific details are provided to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without such specific details.

[0023] As used herein, the terms "top" and "bottom," "upper" and "lower," and "vertical" and "horizontal," and variations thereof, such as may be used herein by way of example and for illustrative purposes only, are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "approximately" mean that a specified dimension or parameter may vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ±2.5% of a given dimension.

[0024] Now refer to Figure 1 Flowchart and Figures 2 to 5FIG. 5 illustrates an embodiment of a first semiconductor wafer including a controller semiconductor die. In step 50, the first semiconductor wafer 100 may be processed into a plurality of first semiconductor dies 102, such as Figures 2 to 4 As shown. These first semiconductor dies 102 may also be referred to herein as controller dies 102, and the first wafer 100 may also be referred to herein as controller wafer 100. The first semiconductor wafer 100 may initially be an ingot of wafer material, which may be single crystal silicon grown according to a Czochralski (CZ) or float zone (FZ) process. However, in other embodiments, the first wafer 100 may be formed of other materials and by other processes.

[0025] The controller wafer 100 may be cut from an ingot and have a first major planar surface 104 and a second major planar surface 107 ( Figure 4 ) are polished on both to provide a smooth surface. The first major surface 104 may undergo various processing steps to separate the wafer 100 into respective first semiconductor die 102 and to form integrated circuits of the respective first semiconductor die 102 on and / or in the first major surface 104.

[0026] Specifically, in step 50, first semiconductor die 102 may be processed in embodiments to include ASIC logic circuitry 112 and memory array logic circuitry 114 formed in a dielectric substrate including layer 116, as shown. Figure 4 shown. Figure 4 A cross section of a single die 102 is shown that is representative of all the dies 102 on the first wafer 100. Figure 5 ASIC logic 112 and memory array logic 114 are described in more detail, but generally speaking, ASIC logic 112 performs memory management and acts as an interface to control data exchange with a host device. Memory array logic 114 includes sensor amplifiers (SA) and peripheral (peri) circuits that act as switching mode interface circuits to decode bit lines / word lines to a buffer and then transfer data between the memory array (described below) and ASIC logic 112. In an embodiment, ASIC logic 112 may be fabricated above memory array logic 114 in a layer of wafer 100 (from Figure 4 1 . Logic circuits 112, 114 may be fabricated using CMOS technology, but in alternative embodiments, the logic circuits may be fabricated using other technologies. In alternative embodiments, as described below, controller semiconductor die 102 may include other and / or additional integrated circuits.

[0027] In step 52, multiple layers of metal interconnects and vias 120 may be formed in and through the layers of semiconductor die 102. These metal interconnects and vias 120 may electrically couple ASIC logic circuitry 112 and memory array logic circuitry 114. These metal interconnects and vias 120 may also include a pattern of through-silicon vias (TSVs) 120a extending between the top major planar surface 104 and the bottom major planar surface 107 of the first wafer 100.

[0028] The TSVs 120a can be formed by etching holes through the first semiconductor die 102 in the finished pattern of the TSVs 120a. These holes can then be lined with a diffusion barrier. A seed layer can then be deposited by PVD or CVD, but in other embodiments can be deposited by other techniques. The seed layer can be formed of copper, aluminum, tin, nickel, gold, alloys thereof, or other materials. A conductive material can then be electroplated onto the seed layer. The conductive material can include copper, but other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, alloys thereof, or combinations thereof can also be used.

[0029] A passivation layer 128 may be formed on top of the dielectric film layer 116. In step 54, a bonding pad 108 coupled to the TSV 120a may be formed on the passivation layer 128. Figure 3 and Figure 4 ). A passivation layer 128 may be etched over TSV 120a, and a bond pad 108 may be formed over liner 106. As is known in the art, bond pad 108 may be formed of, for example, copper, aluminum, and alloys thereof, and liner 106 may be formed of, for example, a titanium / titanium nitride stack (such as, for example, Ti / TiN / Ti), although these materials may differ in other embodiments. Bond pad 108 and liner 106 together may have a thickness of 720 nm, although this thickness may be greater or less in other embodiments.

[0030] In step 56, the controller wafer 100 may be thinned in a back grinding process to define a second major planar (inactive) surface 107 of the wafer 100. In step 58, a redistribution layer (RDL) 130 may be formed on the second major planar surface 107, such as Figure 4As shown. RDL 130 can electrically connect selected bonding pads 108 and TSVs 120a to a pattern of microbumps 132 distributed on RDL 130. Microbumps 132 can be Cu, AgSn, or other metals that can be bonded between two wafers. The height of microbumps 132 can be approximately 1 μm to 50 μm, but this height can be thinner or thicker than the height in other embodiments. Metal interconnects 120 including TSVs 120a can be used to transmit signals and current between die bonding pads 108 and ASIC logic circuitry 112 and between memory array logic circuitry 114 and microbumps 132.

[0031] Figure 2 The number and pattern of semiconductor dies 102 shown on wafer 100 are exemplary only. In other embodiments, wafer 100 may include more first semiconductor dies 102 and may include different patterns. Similarly, Figure 3 and Figure 4 includes a pattern of bonding pads 108 on one semiconductor die 102 surrounding the periphery of the semiconductor die 102. However, in other embodiments, Figure 3 and Figure 4 The pattern of the bonding pads 108 on the first semiconductor die 102 and the number of the bonding pads 108 may vary.

[0032] Figure 5 1 is a block diagram showing more details of the ASIC logic circuit 112 and the memory array logic circuit 114 on the controller die 102. The ASIC logic circuit 112 includes a host interface 142 that connects to and communicates with the host device 300 ( Figure 13In one embodiment, the host interface 142 provides a PCIe interface. Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 142 is also connected to the network-on-chip (NOC) 134. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communications and brings significant improvements compared to conventional bus and crossbar switch interconnects. Compared to other designs, the NOC improves the scalability of system-on-chip (SoC) and the efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high level of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to grow, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 134 are the processor 136, ECC engine 138, memory interface 140, and DRAM controller 144. The DRAM controller 144 is used to operate and communicate with a local high-speed volatile memory 146 (eg, DRAM). In other embodiments, the local high-speed volatile memory 146 may be an SRAM or other type of volatile memory.

[0033] ECC engine 138 performs error correction services. For example, ECC engine 138 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, ECC engine 138 is a circuit programmed by software. For example, ECC engine 138 can be a programmable processor. In other embodiments, ECC engine 138 is a custom, dedicated hardware circuit without any software. In another embodiment, the functions of ECC engine 138 are implemented by processor 136.

[0034] The processor 136 performs various memory operations. For example, the memory array module (MM) is a module / process running on the processor 136 for performing programming, erasing, reading, and memory management processes. The read calibration manager (RC) is a module / process running on the processor 136 for performing read calibration processes. In one embodiment, the read calibration manager (RC) is implemented as part of the ECC engine 138. The error indication manager (IOE) is a module / process running on the processor 136 for calculating error indications, which are used to calibrate read reference levels. In one embodiment, the error indication manager (IOE) is implemented as part of the ECC engine 138 or as part of the read calibration manager (RC).

[0035] In one embodiment, the processor 136 is programmed by firmware, such that the read calibration manager (RC) and the error indication manager (IOE) are firmware / software. In other embodiments, the processor 136 is a custom and dedicated hardware circuit without any software. The processor 136 (alone or in conjunction with the ECC engine 138) can perform recalibration of the read reference level to determine an updated read reference level, including dynamically and adaptively selecting a test read reference level for sensing sample data.

[0036] The processor 136 also implements the Translation Module (TM) as a software / firmware process or dedicated hardware circuit. In many systems, non-volatile memory is addressed within the memory system using physical addresses associated with one or more memory dies, as described below. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the memory system can freely store data between locations on one or more memory dies.

[0037] The memory interface 140 communicates with the memory array logic 114. The memory array 212 on the second die 202 (described below) can be controlled by the memory array logic 114 on the first die 102. The memory array logic 114 can have circuitry for accessing, controlling, and driving the memory elements of the memory array to implement functions such as programming and reading. The memory array logic 114 cooperates with the read / write circuits 168 to perform memory operations on the memory array. The read / write circuits 168 can include multiple sense blocks (sense circuits) that allow pages of memory cells from the memory array dies on the memory wafer (described below) to be read or programmed in parallel.

[0038] In one embodiment, logic circuit 114 may include a state machine 152, an address decoder 154, and a power control module 156. State machine 152 provides chip-level control of memory operations. Storage area 153 may be provided for operating memory array 212, such as programming parameters of different rows or other groups of memory cells. These programming parameters may include bit line voltages and verify voltages.

[0039] The address decoder 154 provides an address interface between the address interface used by the host device or ASIC logic circuit 112 and the hardware address used by decoders 163 and 166. The power control module 156 controls the power and voltage provided to the word lines and bit lines during memory operations. The power control module may include drivers for the word line layer in a 3D configuration, source side select gates, drain side select gates, and source lines. The source side select gate is the gate transistor at the source end of the NAND string, and the drain side select gate is the transistor at the drain end of the NAND string.

[0040] According to aspects of the present technology, the aforementioned ASIC logic circuitry 112 and memory array logic circuitry 114 are integrated into a single semiconductor die 102, and the memory array 212 (described below) is separated into its own chip. However, it should be understood that some of the aforementioned functions of the ASIC logic circuitry 112 and memory array logic circuitry 114 can be offloaded to the memory array semiconductor die. In further embodiments, additional components and functions can be added to the controller die 102.

[0041] The second semiconductor wafer 200 may be processed into a plurality of second semiconductor dies 202 before, after, or in parallel with forming the controller semiconductor die on the first wafer 100. Figure 6 Flowchart and Figures 7 to 9 The diagram of FIG. 1 illustrates the fabrication and operation of semiconductor die 202 on wafer 200 .

[0042] Figure 7 1 shows a top view of a second semiconductor wafer 200. The second semiconductor wafer 200 may initially be a single crystal silicon ingot grown according to a CZ, FZ or other process. The second semiconductor wafer 200 may have a first main surface 204 and a second main surface 207 ( Figure 9 ) to provide a smooth surface. The first major surface 204 may undergo various processing steps to separate the second wafer 200 into respective second semiconductor die 202 and to form integrated circuits of the respective second semiconductor die 202 on and / or in the first major surface 204. These second semiconductor die 202 may also be referred to herein as memory array dies 202, and the second wafer 200 may also be referred to herein as a memory array wafer 200.

[0043] In one embodiment, memory array die 202 may be processed in step 60 to include a memory array 212 formed in a dielectric substrate including layers 224 and 226, such as Figure 9 shown. Figure 9 A cross-section of a single die 202 is shown, representing all of the die 202 on wafer 200. Further details of memory array 212 are provided below, but generally speaking, memory array 212 can be formed as a 3D stacked memory structure having strings of memory cells formed as layers. However, it should be understood that second semiconductor die 202 can be processed to include integrated circuits other than 3D stacked memory structures.

[0044] In step 62, multiple layers of metal interconnects and vias 220 may be formed in and through the layers of semiconductor die 202. These metal interconnects and vias 220 may include a pattern of TSVs 220a extending between the top major planar surface 204 and the bottom major planar surface 207 of the second wafer 200.

[0045] As in wafer 100, TSVs 220a in wafer 200 can be formed by etching holes through second semiconductor die 202 in the pattern of completed TSVs 220a. These holes can then be lined with a barrier, and a seed layer can be deposited. A conductive material can then be electroplated onto the seed layer. The conductive material can include copper, but other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, alloys thereof, or combinations thereof can also be used.

[0046] A passivation layer 228 may be formed on top of the dielectric film layer 226. In step 64, a bonding pad 208 coupled to the TSV 220a may be formed through the passivation layer 228. Figure 8 and Figure 9 ). A passivation layer 228 may be etched over TSV 220a, and a bond pad 208 may be formed over liner 206. As with pad 108 described above, bond pad 208 may be formed of, for example, copper, aluminum, and alloys thereof, and liner 206 may be formed of, for example, a titanium / titanium nitride stack (such as, for example, Ti / TiN / Ti), although these materials may differ in other embodiments. Bond pad 208 and liner 206 together may have a thickness of 720 nm, although this thickness may be greater or less in other embodiments.

[0047] In step 66, the memory array wafer 200 may be thinned in a back grinding process to define a second major planar (inactive) surface 207 of the wafer 200. In step 68, a redistribution layer (RDL) 230 may be formed on the second major planar surface 207, such as Figure 9 The RDL 230 can electrically connect selected bond pads 208 and TSVs 220a to a pattern of microbumps 232 distributed on the RDL 230. The metal interconnects 220 including the TSVs 220a can be used to transmit signals and current between the memory array 212, the die bond pads 208, and the microbumps 232.

[0048] Figure 7 The number and pattern of semiconductor dies 202 shown on wafer 200 are exemplary only. In other embodiments, wafer 200 may include more memory array semiconductor dies 202 and may include different patterns. Similarly, Figure 8 and Figure 9includes a pattern of bond pads 208 on one of the semiconductor dies 202 around the periphery of the semiconductor die 202. However, in other embodiments, Figure 8 and Figure 9 The pattern of the bonding pads 208 on the second semiconductor die 202 and the number of the bonding pads 208 may vary.

[0049] The die 202 of the memory array wafer 200 may each include a memory structure of memory cells, such as an array of memory cells. The array 212 of memory cells ( Figure 9 ) can be passed through the word line through the row decoder 163 ( Figure 5 ) and are addressed from the controller die 102 on the controller wafer 100 via the column decoder 166 via the bit lines. The multiple memory elements in the memory array can be configured so that they are connected in series or so that each element can be addressed individually. By way of non-limiting example, a flash memory system (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of series-connected transistors including a memory cell and a select gate transistor.

[0050] A NAND memory array can be configured so that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements of a memory array can be configured so that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements can be configured in other ways.

[0051] The memory array 212 can be two-dimensional (2D) or three-dimensional (3D). The memory array 212 can include an array of one or more memory elements (also referred to as memory cells). A 3D memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y, and z directions, where the z direction is substantially perpendicular to the major planar surfaces 204, 207 of the memory array die 102, and the x and y directions are substantially parallel to the major planar surfaces 204, 207 of the memory array die 102).

[0052] According to aspects of the present technology, one or more memory array wafers 200 can be stacked with the controller wafer 100 to form a semiconductor device. Figure 10 Flowchart and Figures 11 to 16 The structure and manufacture of such semiconductor devices are explained in the following diagram.

[0053] In step 70, the first memory array wafer 200 may be mounted on a temporary carrier, such as Figure 11 and12 A temporary carrier 250 is shown. The temporary carrier 250 can be, for example, metal, glass, or silicon. The bottom wafer 200 can be adhered to the temporary carrier 250 using a temporary adhesive 252, which can be a laser / UV release film, a heat release film, or a mechanical release film to allow for easy removal, as described below.

[0054] In an embodiment, the first memory array wafer 200 may be the only memory array wafer used in the semiconductor device. However, in other embodiments, additional memory array wafers 200 may be stacked on the bottom wafer 200 in step 72. In an embodiment, there may be n total memory array wafers, where n = 1, 2, 4, 8, 16, 32, or another number of wafers. The memory array wafers 200 may be aligned and stacked with each other so that the microbumps 232 of one wafer are mounted on top of the bond pads 208 of the next lower wafer.

[0055] After stacking a desired number of memory array wafers 200 on a temporary carrier, the controller wafer 100 may be mounted on the topmost memory array wafer in step 74 to form a semiconductor device 260, such as Figure 11 shown. Figure 11 The number of memory wafers 200 in FIG. 1 is exemplary only and may vary as described above.

[0056] The controller wafer 100 may be aligned with and stacked on the topmost memory array wafer 200 such that the microbumps 132 of the controller wafer 100 are mounted on top of the bond pads 208 of the topmost memory array wafer 200. Once all wafers 100, 200 have been mounted on the temporary carrier 250, the semiconductor device 260 may be heated in step 76 to reflow the microbumps 132, 232 to secure the wafers and electrical connections in place.

[0057] The wafers 100 , 200 are stacked in such a manner that a column of memory array dies 202 are aligned with each other and with the controller die 102 above the column, which serves as a controller for the memory array dies 202 in the column. Figure 11 A dashed box 262 is shown surrounding a column of memory array die 202 and controller die 102. Each such column of memory array die 202 and its associated controller die 102 may be referred to herein as a memory module 264. Figure 12 Shown is an exploded cross-sectional edge view of a single memory module 264 from wafers 100, 200 of semiconductor devices 260. As used herein, a semiconductor device may be a single memory module 264, or the semiconductor device may be the memory array wafer 200 and the controller wafer 100 all together.

[0058] Once the wafers 100, 200 are mounted on the carrier 250 and attached in step 76, any spaces between the wafers may be underfilled with epoxy or other resin or polymer in step 80. The underfill material may be applied as a liquid and then allowed to harden into a solid layer. This underfill step protects the electrical connections between the wafers and also secures the die in the memory module columns to each other. Various materials may be used as the underfill material, but in one embodiment, the underfill material may be Hysol epoxy resin from Henkel Corporation, which has offices in California, USA. In other embodiments, the underfill step 80 may be omitted.

[0059] Next, step 82 is performed, in which the semiconductor device 260 on the carrier 250 is encapsulated in an enclosure such as a molding compound. The molding compound may include, for example, a solid epoxy resin, a phenolic resin, fused silica, crystalline silica, carbon black, and / or a metal hydroxide. Such molding compounds are available from, for example, Sumitomo Corporation and Nitto Denko Corporation, both of which are headquartered in Japan. Other molding compounds from other manufacturers are contemplated. The molding compound may be applied by an FFT (free flow thin) process or by other known processes, including by transfer molding or injection molding techniques. In other embodiments, the enclosure may be formed of other materials and formed around the semiconductor device 260 on the carrier 250 in other ways. In other embodiments, the encapsulation step 82 may be omitted.

[0060] In step 84, carrier 250 may be removed by dissolving temporary adhesive 252. Temporary adhesive 252 may be dissolved using heat, mechanical force, chemicals, laser or UV light, and / or by other methods.

[0061] In step 86, solder balls 266 may be attached to pads 108 on the upper surface of wafer 100, as shown. Figure 13 shown. Figure 13 A single memory module 264 including solder balls 266 is shown, but solder balls 266 may be provided on the die bond pads 108 of all dies on the top surface of the controller wafer 100. The solder balls 266 may be used to electrically and mechanically couple the semiconductor device 260 to a host device 300. The host device 300 may be, for example, a printed circuit board coupled to a server or host computer within a data center. It should be understood that in alternative embodiments, the host device 300 may be other devices.

[0062] In one embodiment, the semiconductor device 260 is formed from an entire wafer to provide a high-capacity storage device, such as for use in a data center or other high-capacity applications. In another embodiment, the wafer 100, 200 of the semiconductor device 260 can be cut to provide individual memory modules 264. As described above, each such memory module 264 can include an array of one or more memory array dies 202 and a controller die 102 encapsulated in a mold compound. Solder balls 266 can be provided on the die bond pads 108 of the controller die 102 to allow the individual memory modules 264 to be attached to a host device such as a printed circuit board. The semiconductor device 260 can be cut into the individual memory modules 264 by, for example, a laser or a saw blade.

[0063] Figure 14 2 is a functional block diagram of a single memory module 264 from semiconductor device 260. As shown, each controller die 102 in wafer 100 controls a column of n memory array dies 202 in wafer 200. Logic circuitry 114 that controls the operation of memory array dies 202 is integrated within controller die 102 along with logic circuitry 112 that interfaces with host device 300.

[0064] Figures 11 to 14 A single channel memory module 264 is shown in which the controller die 102 controls a single rank of memory die 202 . Figure 15 and Figure 16 An alternative embodiment of a semiconductor device 260 including a four-channel memory module 264 is shown. Figure 15 As shown in the view of wafers 100, 200 in FIG, the controller wafer 100 in this embodiment may include fewer controller dies 102 than memory array dies 202 in each wafer 200. In this example, a single controller die 102 may control four columns of memory array dies 202, as shown by dashed box 272.

[0065] like Figure 16 As shown in the functional block diagram of FIG, the memory array die 202 on the wafer 200 can be the same as the memory array die described above. However, in this embodiment, the controller die 102 of each channel memory module 264 can have a separate memory array logic circuit 114 for each channel. A single ASIC logic circuit 112 can interact with each memory array logic circuit 114 and can interact with the host device 300 as described above. In another embodiment, each memory module 264 can be an n-channel device, where the controller die 102 includes n memory array logic circuits 114 for controlling n columns of memory array die 202.

[0066] In the above embodiment, the controller wafer 100 is mounted on top of the wafer stack of semiconductor devices 260. However, in other embodiments, the controller wafer 100 may be located elsewhere in the wafer stack, such as, for example, at the bottom of the stack.

[0067] In summary, examples of the present technology relate to a semiconductor device configured to operate with a host device, the semiconductor device comprising: a first semiconductor die, the first semiconductor die comprising: an ASIC logic circuit configured to interact with the host device, and a memory array logic circuit configured to interact with a memory array; and a group of one or more second semiconductor dies coupled to the first semiconductor die, the group of one or more second semiconductor dies comprising a memory array configured to interact with the memory array logic circuit of the first semiconductor die.

[0068] In another example, the present technology relates to a semiconductor device configured to operate with a host device, the semiconductor device comprising: a first wafer comprising at least one of logic circuitry for interacting with the host device and logic circuitry for interacting with a memory array; and a plurality of second wafers physically and electrically coupled to the first wafer, the plurality of second wafers comprising a plurality of memory arrays.

[0069] In another example, the present technology relates to a semiconductor device configured to operate with a host device, the semiconductor device comprising: a controller wafer, the controller wafer comprising a plurality of controller semiconductor dies, each of the plurality of controller semiconductor dies comprising: an ASIC logic circuit for interacting with the host device, a memory array logic circuit for interacting with a memory array; and a plurality of memory array wafers physically and electrically coupled to the first wafer, the plurality of memory array wafers each comprising a plurality of memory array semiconductor dies having a memory array.

[0070] In another example, the technology of the present invention relates to a semiconductor device configured to operate with a host device, the semiconductor device comprising: a first semiconductor die, the first semiconductor die including: a host interface circuit logic device for interacting with the host device, and a memory array circuit logic device for interacting with a memory array device; and a group of one or more second semiconductor dies coupled to the first semiconductor die, the group of one or more second semiconductor dies including a memory array device for storing data, the memory array device interacting with the memory array logic circuit of the first semiconductor die.

[0071] The above specific embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments have been selected to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments with various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A semiconductor device configured to operate with a host device, the semiconductor device comprising: A first semiconductor die having a major surface and comprising: an ASIC logic circuit configured to interact with the host device, the ASIC logic circuit being disposed at a first height along an axis perpendicular to the major surface within the first semiconductor die, and a memory array logic circuit configured to interact with a memory array, the memory array logic circuit being disposed at a second height along the axis perpendicular to the major surface within the first semiconductor die, the second height being different from the first height; and A set of one or more second semiconductor dies coupled to the first semiconductor die along the axis perpendicular to the major surface, the set of one or more second semiconductor dies comprising the memory array configured to interact with the memory array logic circuitry of the first semiconductor die.

2. The semiconductor device of claim 1 , wherein the first semiconductor die is part of a first wafer and the group of one or more second semiconductor die is part of one or more second wafers, wherein the first wafer and the group of one or more second wafers are stacked on each other.

3. The semiconductor device of claim 1 , wherein the first semiconductor die is part of a first wafer and the group of one or more second semiconductor die is part of one or more second wafers, wherein the first wafer and the group of one or more second wafers are stacked on each other, and the first semiconductor die and the group of one or more second semiconductor die are aligned in a row with each other in the stacked wafers. 4 . The semiconductor device according to claim 1 , wherein the semiconductor device is a single-channel device.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a multi-channel device. 6 . The semiconductor device of claim 5 , wherein the first semiconductor die comprises memory array logic circuitry for each channel of the plurality of channels. 7 . The semiconductor device of claim 1 , wherein the first die and the set of one or more second dies are electrically coupled through through silicon vias in the first die and the set of one or more second dies.

8. A semiconductor device according to claim 1, wherein the first semiconductor die includes a group of bonding pads on a first surface configured to cooperate with contacts of the host device, and a group of conductive bumps on a second surface configured to cooperate with contacts of a memory array die of the group of one or more memory array dies. 9 . The semiconductor device of claim 1 , wherein the set of one or more second semiconductor dies comprises a three-dimensional stacked memory structure having memory cell strings formed as layers.

10. A semiconductor device configured to operate with a host device, the semiconductor device comprising: a first wafer, the first wafer comprising a main surface and at least one of a logic circuit for interacting with the host device and a logic circuit for interacting with a memory array, the logic circuit for interacting with the host device being disposed at a first height along an axis perpendicular to the main surface within the first wafer, and the logic circuit for interacting with the memory array being disposed at a second height along the axis perpendicular to the main surface within the first wafer, the second height being different from the first height; and A plurality of second wafers are physically and electrically coupled to the first wafer along the axis perpendicular to the major surface, the plurality of second wafers comprising a plurality of memory arrays. 11 . The semiconductor device of claim 10 , wherein the first wafer includes a logic circuit for interacting with the host device and a logic circuit for interacting with a memory array. 12 . The semiconductor device of claim 10 , wherein the first wafer comprises a first semiconductor die comprising a logic circuit for interacting with the host device and a logic circuit for interacting with a memory array. 13 . The semiconductor device of claim 12 , wherein the plurality of second wafers comprises a plurality of second semiconductor dies, each of the plurality of second semiconductor dies comprising a memory array. 14 . The semiconductor device of claim 12 , wherein the first semiconductor die and a plurality of second semiconductor dies are stacked in a column with each other. 15 . The semiconductor device of claim 10 , wherein the first wafer and the plurality of second wafers are stacked on top of each other to form a stack of wafers. The semiconductor device of claim 15 , wherein the first wafer is on top of the stack of wafers. 17 . The semiconductor device of claim 15 , wherein the first wafer comprises a plurality of first semiconductor dies, and the plurality of second wafers each comprises a plurality of second semiconductor dies, wherein a first die of the plurality of first dies controls a group of second dies of the plurality of second dies. 18 . The semiconductor device of claim 15 , wherein a group of second dies controlled by a first die are mounted in a column below the first die.

19. A semiconductor device configured to operate with a host device, the semiconductor device comprising: A controller wafer comprising a main surface and a plurality of controller semiconductor dies, each of the plurality of controller semiconductor dies comprising: An ASIC logic circuit for interacting with the host device, the ASIC logic circuit being disposed at a first height along an axis perpendicular to the major surface within the controller wafer a memory array logic circuit for interacting with a memory array, the memory array logic circuit being disposed at a second height along the axis perpendicular to the major surface within the controller wafer, the second height being different from the first height; and A plurality of memory array wafers are physically and electrically coupled to the first wafer along the axis perpendicular to the major surface, the plurality of memory array wafers each including a plurality of memory array semiconductor dies having a memory array.

20. The semiconductor device of claim 19, wherein the plurality of memory array wafers are stacked on top of each other to form a stack of wafers, wherein the memory array semiconductor dies of the respective memory array wafers are physically and electrically bonded to each other in columns. 21 . The semiconductor device of claim 20 , wherein the controller wafer is stacked on an upper surface of an uppermost memory array wafer in the stack of wafers.

22. The semiconductor device of claim 20, wherein a controller semiconductor die of the plurality of controller semiconductor dies is physically and electrically coupled to a column of memory array semiconductor dies, the controller semiconductor die controlling the column of memory array semiconductor dies.

23. The semiconductor device of claim 19, further comprising a plurality of bonding pads on a surface of the controller wafer, and a plurality of solder balls on the plurality of bonding pads, the plurality of solder balls being configured to electrically and physically couple the semiconductor device to the host device.

24. The semiconductor device of claim 19, wherein the ASIC logic circuit in each controller die is fabricated in a first layer of each controller die, and the memory array logic circuit is fabricated in a second layer of each controller die that is different from the first layer.

25. A semiconductor device configured to operate with a host device, the semiconductor device comprising: A first semiconductor die having a major surface and comprising: a host interface circuit logic device for interacting with a host device, the host interface circuit logic device being disposed at a first height along an axis perpendicular to the major surface within the first semiconductor die, and a memory array circuit logic device for interacting with a memory array device, the memory array circuit logic device being disposed at a second height along the axis perpendicular to the major surface within the first semiconductor die, the second height being different from the first height; and A group of one or more second semiconductor dies coupled to the first semiconductor die along the axis perpendicular to the main surface, the group of one or more second semiconductor dies including the memory array device for storing data, the memory array device interacting with the memory array logic circuit of the first semiconductor die.

Images