Semiconductor device and method of manufacturing a semiconductor device

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern.

Description

Technical Field

[0001] Embodiments relate to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0002] As a scaling technology for increasing the density of a semiconductor device, a multi-gate transistor in which a fin-shaped silicon body or a nanowire-shaped silicon body is formed on a substrate and a gate is formed on a surface of the silicon body may be considered.

[0003] Multi-gate transistors can use three-dimensional (3D) channels and can facilitate the scaling of multi-gate transistors. The current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0004] An embodiment can be implemented by providing a semiconductor device comprising: a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer comprising a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and comprising a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern.

[0005] An embodiment can be achieved by providing a semiconductor device comprising: a lower semiconductor layer on a substrate, the lower semiconductor layer comprising a first material; a stacked structure on the lower semiconductor layer, the stacked structure comprising a conductive pattern and an upper semiconductor layer on the conductive pattern, the upper semiconductor layer comprising a second material different from the first material; and a source / drain region on the lower semiconductor layer, the source / drain region being connected to the upper semiconductor layer.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: a silicon substrate; a buried insulating layer on the silicon substrate, the buried insulating layer comprising an oxide; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer comprising a recess; a first silicon channel pattern spaced apart from the lower semiconductor layer; a second silicon channel pattern on the first silicon channel pattern; a gate electrode on the lower semiconductor layer, the gate electrode surrounding at least a portion of the first silicon channel pattern and the second silicon channel pattern; and a source / drain region connected to the first silicon channel pattern and the second silicon channel pattern and filling at least a portion of the recess, wherein the lower semiconductor layer comprises a material different from a material of the first silicon channel pattern and the second silicon channel pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0009] Figures 2 to 9 Shown is a method of manufacturing a device according to some embodiments. Figure 1 Schematic cross-sectional views of stages in a method of manufacturing a semiconductor device.

[0010] Figure 10 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0011] Figure 11 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0012] Figure 12 and Figure 13 Shown is a method of manufacturing a device according to some embodiments. Figure 11 Schematic cross-sectional views of stages in a method of manufacturing a semiconductor device.

[0013] Figure 14 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0014] Figure 1 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0015] Reference Figure 1 According to some embodiments, a semiconductor device may include: a substrate 100; a buried insulating layer 110 on the substrate 100; a lower semiconductor layer 200 on the buried insulating layer 110; and a conductive pattern 400, a first channel pattern 320_1, a second channel pattern 320_2, a third channel pattern 320_3, a gate spacer 108, a capping pattern 350, and a plurality of contacts 800 on the lower semiconductor layer 200. The conductive pattern 400 may include a gate electrode 330 and a gate insulating layer 220. In one implementation, as shown in FIG. Figure 1 As shown, three of the plurality of channel patterns 320_1, 320_2, and 320_3 and three of the plurality of conductive patterns 400 may be included (e.g., stacked in the thickness direction of the substrate 100). In one implementation, the first channel pattern 320_1, the second channel pattern 320_2, and the third channel pattern 320_3 may be collectively referred to as the plurality of channel patterns 320_1, 320_2, and 320_3.

[0016] The substrate 100 may be, for example, a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. As used herein, the term "or" is not exclusive; for example, "A or B" includes A, B, or A and B. In one implementation, the substrate 100 may include an epitaxial layer formed on a base substrate.

[0017] In one implementation, the buried insulating layer 110 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. To simplify the description, the case where the buried insulating layer 110 is made of silicon oxide will be described as an example.

[0018] For example, the substrate 100 and the buried insulating layer 110 on the substrate 100 may be silicon-on-insulator (SOI). In one implementation, the buried insulating layer 110 may be a buried oxide (BOX) layer of the SOI substrate 100 or a buried oxide (BOX) layer on the SOI substrate 100.

[0019] The lower semiconductor layer 200 may be on the buried insulating layer 110. The lower semiconductor layer 200 may be formed of or include, for example, silicon germanium (SiGe). In the process of manufacturing a semiconductor device according to some embodiments, the thickness of the silicon germanium may be increased to help reduce the possibility of an unetched phenomenon occurring when forming a source / drain recess or to prevent an unetched phenomenon from occurring when forming a source / drain recess. The silicon germanium may be the same material as the sacrificial layer formed during the semiconductor manufacturing process, and when the sacrificial layer is removed, the silicon germanium constituting the lower semiconductor layer 200 may also be partially removed. For example, according to the method of manufacturing a semiconductor device, the thickness of the lower semiconductor layer 200 remaining in the semiconductor device after manufacturing may be thin, thereby suppressing the leakage current of the semiconductor device according to some embodiments and also reducing the leakage capacitance.

[0020] The conductive pattern 400 may be on the lower semiconductor layer 200. The conductive pattern 400 may include a gate electrode 330. In one embodiment, the gate electrode 330 may include, for example, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, or Al. In one embodiment, the gate electrode 330 may be formed of, for example, Si, SiGe, or a nonmetal. In one embodiment, the gate electrode 330 may be formed, for example, by a replacement process.

[0021] The conductive pattern 400 may further include a gate insulating layer 220 surrounding the gate electrode 330. In one embodiment, the gate insulating layer 220 may have a shape that surrounds every surface of the gate electrode except the upper surface of the uppermost gate electrode 330 (for example, except the surface of the gate electrode 330 facing away from the substrate 100 and on the far side of the substrate 100). The gate insulating layer 220 may include a high dielectric material having a higher dielectric constant than that of the silicon oxide layer. In one embodiment, the high dielectric material may include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0022] A stack structure 500 including an upper semiconductor layer (eg, channel pattern) may be on the lower semiconductor layer 200. In the stack structure 500 including the upper semiconductor layer, a plurality of channel patterns 320_1, 320_2, and 320_3 and gate electrodes 330 surrounded by gate insulating layers 220 may be alternately stacked.

[0023] In one implementation, the plurality of channel patterns 320_1 , 320_2 , and 320_3 may include, for example, silicon (Si) or germanium (Ge) as an elemental semiconductor material. In one implementation, the plurality of channel patterns 320_1 , 320_2 , and 320_3 may include a compound semiconductor, for example, a Group IV-IV compound semiconductor or a Group III-V compound semiconductor.

[0024] For example, when the plurality of channel patterns 320_1, 320_2, and 320_3 include a Group IV-IV compound semiconductor, the plurality of channel patterns 320_1, 320_2, and 320_3 may include a binary compound or a ternary compound including at least two elements of, for example, carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or include the above compounds doped with a Group IV element. For example, when the plurality of channel patterns 320_1, 320_2, and 320_3 include a Group III-V compound semiconductor, the plurality of channel patterns 320_1, 320_2, and 320_3 may include a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a Group III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a Group V element.

[0025] The capping pattern 350 may be on upper surfaces of the gate electrode 330 and the gate insulating layer 220. The capping pattern 350 may include an insulating material.

[0026] In one implementation, the cover pattern may be omitted.

[0027] The gate spacer 108 may be on both side surfaces of the gate insulating layer 220 and the capping pattern 350. For example, the gate insulating layer 220, the gate electrode 330, and the capping pattern 350 may fill a trench formed by an inner sidewall of the gate spacer 108.

[0028] In one implementation, the gate spacer 108 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), or a combination thereof.

[0029] The source / drain regions 700 may be connected to the lower semiconductor layer 200 and the stacked structure 500 including the conductive pattern 400 and the upper semiconductor layer. In one embodiment, the source / drain regions 700 may have a maximum width in the first direction (X direction) that is smaller than the maximum width in the second direction (Y direction). The sidewalls of the source / drain regions 700 may have a curved shape, and when the plurality of channel patterns 320_1, 320_2, and 320_3 are PMOS silicon channel patterns, channel mobility may be improved by applying stress to the plurality of channel patterns 320_1, 320_2, and 320_3.

[0030] A silicide layer 900 may be on the source / drain regions 700 , and a plurality of contacts 800 may be on the silicide layer 900 .

[0031] According to some embodiments, the lower semiconductor layer 200 of the semiconductor device may have a first thickness D1 (in the second direction Y), which may be smaller than a second thickness D2 and a third thickness D3 described below. For example, the area where the semiconductor device (e.g., the lower semiconductor layer 200) interfaces with the source / drain may be minimized, thereby reducing leakage current or leakage capacitance in an off state.

[0032] In one implementation, when manufacturing a semiconductor device according to some embodiments, the lower semiconductor layer 200 may be formed to have a second thickness D2, which may be relatively thick (e.g., compared to the first thickness D1). For example, when forming a recess for forming the source / drain region 700, the lowermost surface (in the -Y direction) of the source / drain region 700 may be prevented from passing through the lower semiconductor layer 200 and reaching the buried insulating layer 110, and an etching phenomenon in which the source / drain region 700 is formed but does not reach the lower semiconductor layer 200 may also be prevented.

[0033] In an implementation, when measured in the Y direction, the thickness D1 of the lower semiconductor layer 200 may be smaller than the thicknesses of the channel patterns 320_1 , 320_2 , and 320_3 .

[0034] Figures 2 to 9Shown is a method of manufacturing a device according to some embodiments. Figure 1 Schematic cross-sectional views of stages in a method of manufacturing a semiconductor device. In the following description, redundant descriptions may be omitted.

[0035] Reference Figure 2 , the lower semiconductor layer 200 may be formed on the buried insulating layer 110 on the substrate 100. A first preliminary stacked structure 300_1 (wherein the sacrificial layer 210 and the first channel pattern 320_1 are sequentially stacked) may be formed on the lower semiconductor layer 200. A second preliminary stacked structure 300_2 (wherein the sacrificial layer 210 and the second channel pattern 320_2 are sequentially stacked) may be formed on the first preliminary stacked structure 300_1. A third preliminary stacked structure 300_3 (wherein the sacrificial layer 210 and the third channel pattern 320_3 are sequentially stacked) may be formed on the second preliminary stacked structure 300_2. In one implementation, each of the preliminary stacked structures 300_1, 300_2, and 300_3 may further include a sacrificial layer 210 and a channel pattern.

[0036] Each of the sacrificial layers 210 may comprise the same material. The sacrificial layers 210 and the plurality of channel patterns 320_1, 320_2, and 320_3 may comprise different materials. In one implementation, each sacrificial layer 210 may have a third thickness D3 in the Y direction, which is the thickness direction of the substrate. In one implementation, each sacrificial layer 210 may have a different thickness. The following describes a case where each sacrificial layer 210 has the same third thickness D3.

[0037] In one implementation, each of the sacrificial layers 210 may include silicon germanium. In addition, the plurality of channel patterns 320_1 , 320_2 , and 320_3 may include a material having an etch selectivity with respect to the sacrificial layer 210 .

[0038] In one embodiment, the plurality of channel patterns 320_1, 320_2, and 320_3 may include a material that can be used as a channel region of a transistor. For example, in the case of a PMOS transistor, the plurality of channel patterns 320_1, 320_2, and 320_3 may include a material having high hole mobility, and in the case of an NMOS transistor, the plurality of channel patterns 320_1, 320_2, and 320_3 may include a material having high electron mobility. Hereinafter, it will be described that the plurality of channel patterns 320_1, 320_2, and 320_3 include silicon.

[0039] When each of the plurality of channel patterns 320_1 , 320_2 , and 320_3 includes silicon, they may be described as a plurality of silicon channel patterns.

[0040] The lower semiconductor layer 200 on the buried insulating layer 110 may have a second thickness D2 in the Y direction, which is the thickness direction of the substrate 100. The second thickness D2 may be greater than Figure 1 The first thickness D1 of the lower semiconductor layer 200 (for example, the thickness of the lower semiconductor layer 200 in the Y direction in the final manufactured device) can be greater than the third thickness D3. In one embodiment, the second thickness D2 can be equal to the third thickness D3.

[0041] In one implementation, the buried insulating layer 110 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof.

[0042] The lower semiconductor layer 200 may include silicon germanium in the same manner as the sacrificial layer 210. For example, in a process for manufacturing a semiconductor device according to some embodiments, the second thickness D2 of the lower semiconductor layer 200 may be adjusted to help prevent an unetched phenomenon when forming source / drain recesses.

[0043] In one implementation, the lower semiconductor layer 200 may include silicon germanium in the same manner as the sacrificial layer 210, and when the sacrificial layer 210 is removed as described below, the lower semiconductor layer 200 may also be partially removed, so that the lower semiconductor layer 200 of the semiconductor device according to some embodiments may be formed to have a first thickness D1 that is less than the initial second thickness D2.

[0044] For example, the first thickness D1 of the lower semiconductor layer 200 of the semiconductor device according to some embodiments may be less than the second thickness D2 (eg, intermediate thickness) during the process of manufacturing the semiconductor device according to some embodiments, thereby reducing the influence of leakage current or leakage capacitance in the off state.

[0045] The first ratio or concentration of germanium in the silicon germanium of the lower semiconductor layer 200 may be less than the second ratio or concentration of germanium in the silicon germanium of the sacrificial layer 210. In the process of removing the sacrificial layer 210, the removal rate may vary depending on the ratio of germanium in the silicon germanium. For example, the smaller the ratio of germanium in the silicon germanium, the faster the removal rate. For example, if the ratio of germanium in the lower semiconductor layer 200 is less than the ratio of germanium in the sacrificial layer 210, then in the process of removing the sacrificial layer 210, the lower semiconductor layer 200 can be removed faster than the sacrificial layer 210, which will be described below.

[0046] For example, by reducing the proportion of germanium in the lower semiconductor layer 200, the second thickness D2 of the lower semiconductor layer 200 can be further increased. For example, the non-etching phenomenon that occurs during the process of manufacturing the semiconductor device according to some embodiments can be suppressed, and the lower semiconductor layer 200 can also be removed more quickly during the removal of the sacrificial layer 210. For example, the first thickness D1 of the lower semiconductor layer 200 of the semiconductor device according to some embodiments can be reduced, thereby suppressing leakage current or leakage capacitance in the off state of the semiconductor device according to some embodiments.

[0047] By using the mask pattern on the third preliminary stacked structure 300_3, a sacrificial gate 104 and a mask pattern 106 on the sacrificial gate 104 may be formed. The sacrificial gate 104 may include, for example, polysilicon or amorphous silicon.

[0048] Then, refer to Figure 3 The gate spacer 108 may be conformally formed to cover the upper surface of the third preliminary stacked structure 300_3 , the side surfaces of the sacrificial gate 104 , and the upper and side surfaces of the mask pattern 106 .

[0049] In one implementation, the gate spacer 108 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), or a combination thereof.

[0050] Then, refer to Figure 4 , the gate spacer 108 may be etched to form a source / drain recess R1 exposing at least a portion of the lower semiconductor layer 200 .

[0051] In a method of manufacturing a semiconductor device according to some embodiments, the second thickness D2 of the lower semiconductor layer 200 may be selected so that an unetching phenomenon does not occur when forming the source / drain recesses R1 .

[0052] For example, the lower semiconductor layer 200 having a sufficiently thick second thickness D2 can help prevent the lowermost surface of the source / drain recess R1 from passing through the lower semiconductor layer 200 in the -Y direction and reaching the buried insulating layer 110. It can also prevent an unetched phenomenon in which the lower semiconductor layer 200 is not etched at all.

[0053] A side surface of the source / drain recess R1 may have a curved shape, which may increase stress when the plurality of channel patterns 320_1 , 320_2 , and 320_3 are P-type silicon patterns, thereby further improving mobility of charges in the channel.

[0054] In the method of manufacturing a semiconductor device according to some embodiments, the side surface of the source / drain recess R1 may have a shape other than a curved shape. In one implementation, the lowermost surface of the source / drain recess R1 may be at a suitable position within the lower semiconductor layer 200 .

[0055] Then, refer to Figure 5 The source / drain region 700 may be formed in the source / drain recess R1 by an epitaxial process. The uppermost surface of the source / drain region 700 (e.g., on the far side of the substrate 100) may be higher in the Y direction than the uppermost surface of the third channel pattern 320_3 of the third preliminary stacked structure 300_3 (e.g., farther from the substrate in the Y direction).

[0056] Then, refer to Figure 6 , an interlayer insulating layer 225 may be formed to cover the source / drain regions 700 , the gate spacers 108 , and the mask pattern 106 . Figure 6 A state is shown in which the upper surfaces of the interlayer insulating layer 225 , the gate spacer 108 , and the mask pattern 106 are planarized by a chemical mechanical polishing (CMP) process after the interlayer insulating layer 225 is formed.

[0057] The interlayer insulating layer 225 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material having a lower dielectric constant than silicon oxide. In one embodiment, the low dielectric constant material may include, for example, flowable oxide (FOX), Tonen Silazane (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), parylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material, or a combination thereof.

[0058] Then, refer to Figure 7 , the sacrificial layer 210 can be removed. For reference, Figure 7 In the embodiment, for convenience of description in the method of manufacturing a semiconductor device according to some embodiments, the second thickness D2 of the lower semiconductor layer 200 is maintained.

[0059] In the method of manufacturing a semiconductor device according to some embodiments, the proportion of germanium in the lower semiconductor layer 200 may be smaller than the proportion of germanium in the sacrificial layer 210, and when the sacrificial layer 210 is removed, the lower semiconductor layer 200 may be removed faster. For example, the thickness of the lower semiconductor layer 200 may be reduced from the (intermediate) second thickness D2 to Figure 8 The (final) first thickness D1.

[0060] According to some embodiments, the thickness and the germanium ratio of the lower semiconductor layer 200 can be adjusted or selected according to the semiconductor device. For example, in order to form a thick lower semiconductor layer 200 during the process of manufacturing a semiconductor device according to some embodiments and ultimately form a lower semiconductor layer 200 having a very thin first thickness D1 in the semiconductor device according to some embodiments formed according to the manufacturing method, the semiconductor device according to some embodiments can be manufactured by reducing the germanium ratio in the lower semiconductor layer 200 so that the second thickness D2 of the lower semiconductor layer 200 formed in the initial step of the method of manufacturing a semiconductor device according to some embodiments becomes thicker.

[0061] Then, refer to Figure 8 At the location where the sacrificial layer has been removed, the gate insulating layer 220 may be formed along the sidewall of the space where the sacrificial layer has been removed. Then, by filling the gate insulating layer 220 with a conductive material, the gate electrode 330 may be formed.

[0062] In the semiconductor device according to the method of manufacturing the semiconductor device according to some embodiments, the lower semiconductor layer 200 may be partially removed at a high rate during removal of the sacrificial layer, and thus the first thickness D1 may be made smaller than the second thickness D2.

[0063] Then, refer to Figure 9 After removing the sacrificial gate 104 and the mask pattern 106, another gate insulating layer 220 may be formed along the sidewalls of the trench formed in the gate spacer 108. Then, another gate electrode 330 may be formed by filling a conductive material in the gate insulating layer 220. A capping pattern 350 may be formed on the upper surface of the gate electrode 330 and the surface of the gate insulating layer 220.

[0064] Refer again Figure 1 ,exist Figure 9 After the process, by removing the interlayer insulating layer 225, a silicide layer 900 may be formed on the source / drain region 700, and a plurality of contacts 800 may be formed on the silicide layer 900. For example, the plurality of contacts 800 may transmit electrical signals to the source / drain region 700.

[0065] Figure 10 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown. In the following description, redundant description may be omitted.

[0066] Reference Figure 10The lower semiconductor layer 200 may include a first sub-semiconductor layer 201 and a second sub-semiconductor layer 202. The first sub-semiconductor layer 201 may have a first-first thickness D1_1, and the second sub-semiconductor layer 202 may have a first-second thickness D1_2. In one implementation, the first-first thickness D1_1 and the first-second thickness D1_2 may be different thicknesses.

[0067] In the semiconductor device according to some embodiments, the first sub-semiconductor layer 201 of the lower semiconductor layer 200 may include silicon, and the second sub-semiconductor layer 202 of the lower semiconductor layer 200 may include silicon germanium.

[0068] For example, the first thickness of the lower semiconductor layer 200 can be adjusted by respectively adjusting the first-first thickness D1_1 of the first sub-semiconductor layer 201 and the first-second thickness D1_2 of the second sub-semiconductor layer 202. For example, by adjusting the proportion of germanium included in the second sub-semiconductor layer 202, the rate of removing the second sub-semiconductor layer 202 of the lower semiconductor layer 200 when removing the sacrificial layer can be adjusted.

[0069] Apart from Figure 2 In addition to the lower semiconductor layer 200 including the first sub-semiconductor layer 201 and the second sub-semiconductor layer 202, the manufacturing method according to some embodiments is as follows: Figure 10 The method of the semiconductor device is similar, and repeated description thereof is omitted.

[0070] Figure 11 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0071] According to some embodiments Figure 1 The semiconductor devices are different. Figure 11 The semiconductor device may further include an inner spacer 308 between the gate insulating layer 220 and the source / drain regions 700. For example, the inner spacer 308 may be on a side surface of the gate insulating layer 220 surrounding the gate electrode 330 between the source / drain regions 700.

[0072] The inner spacer 308 may include, for example, a low-k material, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbon nitride (SiOCN), or a combination thereof. The low-k material may be a material having a lower dielectric constant than silicon oxide.

[0073] Figure 12 and Figure 13 Shown is a method of manufacturing a device according to some embodiments. Figure 11 Schematic cross-sectional views of stages in a method of manufacturing a semiconductor device.

[0074] Manufacturing according to some embodiments Figure 11 Some intermediate steps of the method of semiconductor device Figures 2 to 4 The steps are the same as those described in Figure 4 Step after step.

[0075] Reference Figure 12 , portions of the sacrificial layer 210 exposed by the source / drain recesses R1 may be etched. For example, the sacrificial layer 210 may be etched by a selective etching process.

[0076] Through the etching process of the sacrificial layer 210 , the inner spacer recess SR may be formed such that a sidewall of the sacrificial layer 210 is more recessed than a sidewall (eg, in the X direction) of each of the plurality of channel patterns 320_1 , 320_2 , and 320_3 exposed by the source / drain recess R1 .

[0077] Then, refer to Figure 13 , inner spacers 308 may be formed along sidewalls exposed by the source / drain recesses R1 , and then, remaining portions (except for the inner spacers 308 formed between the plurality of channel patterns 320_1 , 320_2 , and 320_3 ) may be removed.

[0078] Next steps and Figures 5 to 9 The steps are the same as Figure 9 After the steps of Figure 11 The process of the semiconductor device is also similar, and its description is omitted.

[0079] Figure 14 A schematic cross-sectional view of a semiconductor device according to some embodiments is shown.

[0080] Reference Figure 14 ,and Figure 1 Unlike the semiconductor device of FIG. 1 , the lower semiconductor layer 200 may include a first sub-semiconductor layer 201 and a second sub-semiconductor layer 202, and the semiconductor device may include an inner spacer 308. The features of the lower semiconductor layer 200 including the first sub-semiconductor layer 201 and the second sub-semiconductor layer 202 are similar to those of FIG. Figure 10 The features of the semiconductor device including the inner spacer 308 are similar to Figure 11 The features of the semiconductor device, description of which is omitted.

[0081] In summary and review, semiconductor devices are becoming smaller and higher in performance. For example, small structural differences in transistors included in a semiconductor device can have a large impact on the performance of the semiconductor device. To meet performance requirements, silicon-on-insulator (SOI) substrates can be used.

[0082] To form a transistor structure on an SOI substrate, a silicon (Si) layer may be formed on a buried insulating layer forming the SOI substrate. If the thickness of the silicon layer on the buried insulating layer is too thin, when forming source / drain recesses in the process of manufacturing the semiconductor device, an unetched phenomenon may occur due to a lack of margin. If the thickness of the silicon layer on the buried insulating layer is too thick, the leakage current of the semiconductor device may increase.

[0083] One or more embodiments may include forming a silicon germanium (SiGe) layer instead of a silicon layer on the buried insulating layer to increase the margin by forming a thick silicon germanium layer during the process of manufacturing the semiconductor device, and to reduce the leakage current of the semiconductor device by maintaining a thin thickness of the silicon germanium layer after manufacturing the semiconductor device.

[0084] One or more embodiments may provide a semiconductor device having improved product reliability.

[0085] One or more embodiments may provide a method for manufacturing a semiconductor device having improved product reliability.

[0086] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0087] Korean Patent Application No. 10-2019-0076005, entitled “Semiconductor Device and Method of Manufacturing Semiconductor Device,” filed on June 26, 2019, in the Korean Intellectual Property Office is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a buried insulating layer on the substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer on the first sub-semiconductor layer, the second sub-semiconductor layer comprising a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and comprising a second material different from the first material, the second material having an etching selectivity with respect to the first material; a gate electrode surrounding at least a portion of the channel pattern; as well as a source / drain region on the lower semiconductor layer, the source / drain region being connected to the channel pattern, wherein the lower semiconductor layer includes source / drain recesses, and A portion of the source / drain region fills the source / drain recess.

2. The semiconductor device according to claim 1, wherein: The first material includes silicon germanium (SiGe), and The thickness of the lower semiconductor layer is smaller than the thickness of the channel pattern when measured in the same direction. 3 . The semiconductor device of claim 1 , wherein the first material comprises silicon germanium, and the second material comprises silicon.

4. The semiconductor device according to claim 1, wherein: The first semiconductor sub-layer includes silicon, and The first material in the second sub-semiconductor layer includes silicon germanium.

5. The semiconductor device according to claim 1, wherein A side surface of the source / drain region has a curved shape. 6 . The semiconductor device according to claim 1 , further comprising an inner spacer on a sidewall of the gate electrode.

7. A semiconductor device comprising: a lower semiconductor layer on a substrate, the lower semiconductor layer comprising a first sub-semiconductor layer and a second sub-semiconductor layer on the first sub-semiconductor layer, the second sub-semiconductor layer comprising a first material; a stacked structure on the lower semiconductor layer, the stacked structure comprising a conductive pattern and an upper semiconductor layer on the conductive pattern, the upper semiconductor layer comprising a second material different from the first material, the second material having an etching selectivity relative to the first material; as well as A source / drain region directly contacts the lower semiconductor layer, the source / drain region being connected to the upper semiconductor layer. 8 . The semiconductor device of claim 7 , wherein the conductive pattern comprises a gate electrode surrounding at least a portion of the upper semiconductor layer.

9. The semiconductor device according to claim 7, further comprising a buried insulating layer on the substrate, wherein: The first material includes silicon germanium, and The second material includes silicon.

10. The semiconductor device according to claim 7, wherein: The first semiconductor sub-layer includes silicon, and The first material in the second sub-semiconductor layer includes silicon germanium. 11 . The semiconductor device according to claim 10 , wherein a side surface of the source / drain region has a curved shape. 12 . The semiconductor device according to claim 7 , further comprising inner spacers on sidewalls of the stack structure.

13. A semiconductor device comprising: Silicon substrate; a buried insulating layer on the silicon substrate, the buried insulating layer comprising oxide; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer comprising a recess; a first silicon channel pattern spaced apart from the lower semiconductor layer; a second silicon channel pattern on the first silicon channel pattern; a gate electrode on the lower semiconductor layer, the gate electrode surrounding at least a portion of the first silicon channel pattern and the second silicon channel pattern; as well as a source / drain region connected to the first silicon channel pattern and the second silicon channel pattern and filling at least a portion of the recess, wherein the lower semiconductor layer includes a material different from that of the first silicon channel pattern and the second silicon channel pattern, The lower semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer on the first sub-semiconductor layer, The first sub-semiconductor layer includes silicon, The second sub-semiconductor layer includes silicon germanium.

14. The semiconductor device according to claim 13, wherein: The lower semiconductor layer includes silicon germanium, and The thickness of the lower semiconductor layer is smaller than the thickness of the first and second silicon channel patterns when measured in the same direction.

15. The semiconductor device according to claim 13, further comprising an inner spacer on the gate electrode.

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