Comparator with negative capacitance compensation

Abstract

This invention provides a high-speed comparator circuit. The circuit includes an amplifier section, a latch section, and a negative capacitor section. The amplifier section includes an input terminal coupled to receive an analog signal and an output terminal. The latch section is coupled to the amplifier section. The latch section is configured to provide a digital value at the output terminal based on the analog signal. The negative capacitor section is coupled to the output terminal. The negative capacitor section is configured to eliminate parasitic capacitance coupled to the first output terminal.

Description

Technical Field

[0001] This disclosure relates generally to electronic circuits, and more specifically to a comparator with negative capacitance compensation. Background Art

[0002] Today, many integrated circuits (ICs) and system-on-chip (SoC) devices are used in applications such as analog and digital radio, base stations, and radar, requiring high-speed, high-precision, high-linearity, and high-bandwidth analog-to-digital converters (ADCs). Because the trigonometric integrator (TRIC) modulator meets many of these challenging requirements, it is considered a suitable architecture for these ADCs. However, TLC modulators have limitations when operating at the extremely high frequencies required by these applications (e.g., greater than 5 GHz). Summary of the Invention

[0003] According to one aspect of the present invention, a circuit is provided, comprising:

[0004] The amplifier section has a first input terminal coupled to receive a first analog signal and a first output terminal;

[0005] A latch section coupled to the amplifier section, the latch section being configured to provide a digital value at the first output based on the first analog signal; and

[0006] The negative capacitance portion coupled to the first output terminal is configured to eliminate parasitic capacitance coupled to the first output terminal.

[0007] According to one or more embodiments, the negative capacitance portion further includes: a first transistor having a first power supply electrode coupled to the first output terminal; a second transistor having a first power supply electrode coupled to a control electrode of the first transistor and a control electrode coupled to the first output terminal; and a capacitor having a first end coupled to a second power supply electrode of the first transistor and a second end coupled to a second power supply electrode of the second transistor.

[0008] According to one or more embodiments, the capacitor has a capacitance value approximately equal to that of the parasitic capacitance coupled to the first output terminal.

[0009] According to one or more embodiments, the negative capacitance portion further includes: a first current source having a first end coupled to a first voltage supply terminal and a second end coupled to a second power supply electrode of the first transistor; and a second current source having a first end coupled to the first voltage supply terminal and a second end coupled to a second power supply electrode of the second transistor.

[0010] According to one or more embodiments, the amplifier section further includes: a first transistor having a first power supply electrode, a second power supply electrode coupled to a second output terminal, and a control electrode coupled to receive the first analog signal; and a second transistor having a first power supply electrode coupled to the first power supply electrode of the first transistor, a second power supply electrode coupled to the first output terminal, and a control electrode coupled to receive a second analog signal, wherein the first analog signal and the second analog signal together include a differential signal.

[0011] According to one or more embodiments, the amplifier portion further includes a first current source having a first end coupled to a first voltage supply terminal and a second end coupled to the first power supply electrode of the first transistor and the second transistor.

[0012] According to one or more embodiments, the latch portion further includes: a third transistor having a first power supply electrode coupled to the second power supply electrode of the first transistor at the second output terminal, a second power supply electrode coupled to the second voltage supply terminal, and a control electrode coupled to the second power supply electrode of the second transistor at the first output terminal; and a fourth transistor having a first power supply electrode coupled to the second power supply electrode of the second transistor, a second power supply electrode coupled to the second voltage supply terminal, and a control electrode coupled to the second power supply electrode of the first transistor.

[0013] According to one or more embodiments, a first digital-to-analog converter (DAC) is further included, the first DAC having an input coupled to the first output, and the output of the DAC being coupled to provide a second analog signal representing the digital value.

[0014] According to one or more embodiments, a summing circuit is further included, the summing circuit having a first input terminal coupled to receive an input signal, a second input terminal for receiving the second analog signal, and an output terminal coupled to provide a first differential signal generated by subtracting the second analog signal from the input signal.

[0015] According to a second aspect of the present invention, a circuit is provided, comprising: an amplifier portion having a first input terminal coupled to receive a first analog signal and a first output terminal, the amplifier portion being coupled between a first voltage supply terminal and the first output terminal; a latch portion coupled to the amplifier portion at the first output terminal, the latch portion being configured to provide a digital value based on the first analog signal; and a negative capacitance portion coupled to the amplifier portion and the latch portion at the first output terminal, the negative capacitance portion being configured to eliminate parasitic capacitance coupled to the first output terminal.

[0016] According to one or more embodiments, the negative capacitance portion further includes: a first transistor coupled between the first voltage supply terminal and the first output terminal, the first transistor having a first power supply electrode coupled to the first output terminal; a second transistor having a first power supply electrode coupled to a control electrode of the first transistor and a control electrode coupled to the first power supply electrode of the first transistor; and a capacitor having a first end coupled to a second power supply electrode of the first transistor and a second end coupled to a second power supply electrode of the second transistor, the capacitor having a capacitance value approximately equal to the parasitic capacitance coupled to the first output terminal.

[0017] According to one or more embodiments, the negative capacitance portion further includes: a first current source having a first end coupled to the first voltage supply terminal and a second end coupled to the second power supply electrode of the first transistor; and a second current source having a first end coupled to the first voltage supply terminal and a second end coupled to the second power supply electrode of the second transistor.

[0018] According to one or more embodiments, the amplifier section further includes: a third current source coupled to the first voltage supply terminal; a third transistor having a first power supply electrode coupled to the third current source and a control electrode coupled to receive the first analog signal; and a fourth transistor having a first power supply electrode coupled to the first current source, a second power supply electrode coupled to the first output terminal, and a control electrode coupled to receive a second analog signal, the first analog signal and the second analog signal together comprising a differential signal.

[0019] According to one or more embodiments, the third current source is configured to supply a current amount that is approximately equal to the sum of the currents supplied by the first current source and the second current source.

[0020] According to one or more embodiments, a first digital-to-analog converter (DAC) is further included, the first DAC having an input coupled to the first output, and the output of the DAC being coupled to provide a second analog signal representing the digital value.

[0021] According to one or more embodiments, a summing circuit is further included, the summing circuit having a first input terminal coupled to receive an input signal, a second input terminal for receiving the second analog signal, and an output terminal coupled to the first input terminal of the amplifier section.

[0022] According to one or more embodiments, the summing circuit is configured to provide a first differential signal at the output, the first differential signal being generated by subtracting the second analog signal from the input signal.

[0023] According to a third aspect of the present invention, a circuit is provided, comprising: an amplifier section, the amplifier section including: a first transistor having a first power supply electrode, a second power supply electrode coupled to a first output terminal, and a control electrode coupled to receive a first analog signal; and a second transistor having a first power supply electrode coupled to the first power supply electrode of the first transistor, a second power supply electrode coupled to a second output terminal, and a control electrode coupled to receive a second analog signal, the first analog signal and the second analog signal together comprising a differential signal; and a latch section coupled to the amplifier section, the latch section including: a third transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to receive a second analog signal. The first output terminal includes a control electrode, a fourth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to the second output terminal; and a negative capacitor portion coupled to the amplifier portion and the latch portion, the negative capacitor portion including: a fifth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to the second output terminal, a sixth transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to the first output terminal, and a capacitor having a first end coupled to the second power supply electrode of the first transistor and a second end coupled to the second power supply electrode of the second transistor.

[0024] According to one or more embodiments, the capacitor has a capacitance value that is approximately equal to the parasitic capacitance coupled to the first output terminal or the second output terminal.

[0025] According to one or more embodiments, the device further includes: a seventh transistor having a first power supply electrode coupled to the second output and a control electrode coupled to receive a control signal; and an eighth transistor having a first power supply electrode coupled to the first output and a control electrode coupled to receive the control signal; wherein the control signal in the first logic state causes the seventh transistor and the eighth transistor to conduct and resets the latch portion. Attached Figure Description

[0026] This invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements shown in the drawings are not necessarily drawn to scale for simplicity and clarity.

[0027] Figure 1 An example trigonometric integral modulator according to an embodiment is shown in simplified block diagram form.

[0028] Figure 2 The simplified schematic diagram illustrates the components included in the embodiment. Figure 1 An example implementation of the comparator in the quantizer 108.

[0029] Figure 3 The following is illustrated in the form of a graph: [The text then lists the components included in the embodiment]. Figure 1 Example simulation results of the comparator in quantizer 108. Detailed Implementation

[0030] A high-speed comparator is provided, comprising a negative capacitor circuit system. By incorporating the negative capacitor circuit system to eliminate the comparator's output parasitic capacitance, a shorter latch access time is achieved. With a shorter latch access time, the comparator can be configured to operate at a higher frequency. Processing samples with a comparator operating at a higher frequency enables a higher throughput.

[0031] Figure 1 An example trigonometric modulator 100 according to an embodiment is shown in simplified block diagram form. Modulator 100 includes an input terminal labeled IN for receiving a differential input signal and an output terminal labeled OUT for providing a digital differential output signal corresponding to the sampled analog signal. In this example, modulator 100 includes summing circuits 102 and 106, a loop filter circuit (LF) 104, a quantizer circuit 108, and digital-to-analog converter (DAC) circuits 110 and 112. In this embodiment, quantizer 108 may be implemented as a single-bit quantizer and is therefore referred to as a comparator coupled to a memory element. The memory element is configured and arranged to store the comparator's output data, which can then be processed by the DAC circuits 110 and 112.

[0032] The first summing circuit 102 includes a first input coupled to receive an analog signal (e.g., a differential signal) and an output coupled to the input of a loop filter 104 at node D1. The output of the loop filter 104 is coupled to the first input of a second summing circuit 106 at node FD1, and the output of the second summing circuit 106 is coupled to the input of a quantizer 108 at node D2. The output of the quantizer 108 is coupled to the inputs of DACs 110 and 112 and provides an OUT digital value corresponding to the sampled analog signal. The output of DAC 110 is coupled to the second input of the summing circuit 102 at node A1, and the output of DAC 112 is coupled to the second input of the summing circuit 106 at node A2. The first feedback loop includes DAC 110 and summing circuit 102, and the second feedback loop includes DAC 112 and summing circuit 106.

[0033] In this embodiment, summing circuit 102 generates a first differential signal D1 by subtracting the analog output signal A1 of DAC 110 from the analog input signal IN. Analog signal A1 corresponds to the digital value OUT received at the input of DAC 110. Loop filter 104 generates a filtered signal FD1 based on the received first differential signal D1. Summing circuit 106 generates a second differential signal D2 by subtracting the analog output signal A2 of DAC 112 from the received signal FD1. Analog signal A2 corresponds to the digital value OUT received at the input of DAC 112. In this embodiment, DAC 112 is included to form a loop delay (ELD) compensation path to further stabilize the overall feedback loop. Quantizer 108 generates the digital value OUT based on the received signal D2. In this embodiment, the digital value OUT comprises a complementary digital signal pair, each signal in the complementary digital signal pair being either logic high (e.g., logic 1) or logic low (e.g., logic 0), and DACs 110 and 112 can be characterized as a single-bit DAC.

[0034] Figure 2A simplified schematic diagram illustrates an example implementation of a comparator 200 included in a quantizer 108 of a modulator 100 according to an embodiment. In this embodiment, the comparator 200 can be characterized as a differential single-bit comparator with integrated latch circuitry (e.g., memory elements). The comparator 200 includes inputs for receiving differential signals, labeled VP and VN; an input for receiving a control clock signal, labeled CLK; a first output for providing a digital signal corresponding to the received differential signal, labeled OUTP; and a second output for providing a complementary (e.g., opposite) digital signal corresponding to the received differential signal, labeled OUTN. In this example, the comparator 200 includes an amplifier section formed by P-channel transistors 202 to 204 and a current source 218, a latch and reset section formed by N-channel transistors 206 to 212, and a negative capacitance section formed by P-channel transistors 224 to 226, a capacitor 228, and current sources 220 to 222. Capacitors 214 to 216 represent parasitic capacitances coupled to the OUTN and OUTP output terminals.

[0035] The amplifier section includes transistors 202 to 204 and a current source 218. The amplifier section is coupled to receive differential signals at the control electrodes of transistors 202 and 204, respectively. A first power supply electrode of transistor 202 is coupled at a node labeled N1 to a first power supply electrode of transistor 204 and a first terminal of current source 218. A second power supply electrode of transistor 202 is coupled to an output terminal OUTN, and a second power supply electrode of transistor 204 is coupled to an output terminal OUTP. A second terminal of current source 218 is coupled to a first voltage supply terminal labeled VDD. In this embodiment, current source 218 is configured to provide a current I1. In this embodiment, the VDD supply terminal supplies a normal operating voltage, and transistors 202 and 204 are formed to have approximately similar size parameters (e.g., width and length values) to each other.

[0036] The latch and reset section includes transistors 206 through 212 and is coupled to the amplifier section at outputs OUTN and OUTP. In this embodiment, transistors 206 and 208 are cross-coupled and configured to form a latch circuit, wherein transistors 206 and 208 have approximately similar size parameters to each other. A first power supply electrode of transistor 206 is coupled to output OUTN, a control electrode of transistor 206 is coupled to output OUTP, and a second power supply electrode of transistor 206 is coupled to a second voltage supply terminal labeled GND. In this embodiment, the GND supply terminal supplies a ground voltage (e.g., 0 volts). A first power supply electrode of transistor 208 is coupled to output OUTP, a control electrode of transistor 208 is coupled to output OUTN, and a second power supply electrode of transistor 208 is coupled to the GND supply terminal.

[0037] In this embodiment, transistors 210 and 212 are configured to form a reset circuit, so that a first state of the CLK control signal (e.g., logic high) resets the latch circuit. A first power supply electrode of transistor 210 is coupled to the output terminal OUTN, a control electrode of transistor 210 is coupled to receive the CLK control signal, and a second power supply electrode of transistor 210 is coupled to the GND supply terminal. A first power supply electrode of transistor 212 is coupled to the output terminal OUTP, a control electrode of transistor 212 is coupled to receive the CLK control signal, and a second power supply electrode of transistor 212 is coupled to the GND supply terminal. In this embodiment, when the CLK control signal is in a second state (e.g., logic low), the reset circuit is inactive, allowing the latch circuit to sense a voltage difference (e.g., across output terminals OUTN and OUTP) and latch accordingly.

[0038] Capacitors 214 and 216 are shown for illustrative purposes, depicting parasitic capacitances coupled to the OUTN and OUTP output terminals. A first terminal of capacitor 214 is coupled to the OUTN output terminal, a first terminal of capacitor 216 is coupled to the OUTP output terminal, and a second terminal of both capacitors 214 and 216 is coupled to the GND supply terminal. In this embodiment, capacitors 214 and 216 have approximately similar capacitance values ​​to each other.

[0039] The negative capacitance portion is coupled to the amplifier and latch portions at outputs OUTN and OUTP. The negative capacitance portion is configured to substantially eliminate parasitic capacitance coupled to outputs OUTN and OUTP. The negative capacitance portion includes transistors 224 and 226, capacitor 228, and current sources 220 and 222. In this embodiment, transistors 224 and 226 are configured in a cross-coupled arrangement, wherein transistors 224 and 226 have approximately similar size parameters to each other. The first power supply electrode of transistor 224 is coupled to output OUTP, the control electrode of transistor 224 is coupled to output OUTN, and the second power supply electrode of transistor 224 is coupled to the first terminal of capacitor 228 and the first terminal of current source 220 at node N2. The first power supply electrode of transistor 226 is coupled to output OUTN, the control electrode of transistor 226 is coupled to output OUTP, and the second power supply electrode of transistor 226 is coupled to the second terminal of capacitor 228 and the first terminal of current source 222 at node N3. The second terminals of current source 220 and current source 222 are coupled to the VDD supply terminal. In this embodiment, current source 220 is configured to provide a current I2 that is approximately half the current I1, and current source 222 is configured to provide a current I3 that is approximately equal to the current I2. In this embodiment, capacitor 228 is configured to have a capacitance that is approximately equal to the parasitic capacitance coupled to each of the output terminals OUTN and OUTP.

[0040] Figure 3 Example simulation results of the comparator 200 included in the quantizer 108 of the modulator 100 according to an embodiment are shown in graph form. Graph 300 includes the timing of the CLK control signal and the simulated response waveforms of the corresponding differential output signals OUT (e.g., OUTN and OUTP). The CLK and OUT waveforms with time values ​​in nanoseconds (ns) on the X-axis and voltage values ​​in volts (V) on the Y-axis are shown. The CLK waveform includes signal transitions 302 to 306, which depict the operational phases of the quantizer 108 (e.g., latching and reset). The OUT waveform includes a first differential waveform formed by signals 308 and 310 and a second differential waveform formed by (dashed) signals 312 and 314, which depict the simulation results of the comparator 200 during normal operation. In this example, the first differential waveform depicts the first simulation result of comparator 200 without using a negative capacitor circuit system, and the second differential waveform depicts the second simulation result that covers the first simulation result of comparator 200, demonstrating the desired access time improvement achieved by using a negative capacitor circuit system.

[0041] At time t1, when the CLK control signal transitions from logic high (302) to logic low, comparator 200 enters the latching phase. Subsequently, the voltage difference across the differential inputs (e.g., VP, VN) of comparator 200 causes the latching section to begin latching.

[0042] At time t2, signals 312 and 314 of the second differential waveform have reached predetermined thresholds representing the corresponding logic high and logic low values. Arrow 318 indicates the access time of comparator 200 using a negative capacitor circuit system from time t1 to time t2.

[0043] At time t3, signals 308 and 310 of the first differential waveform have reached predetermined thresholds representing the corresponding logic high and logic low values. Arrow 316 indicates the access time of comparator 200 from time t1 to time t3 without using the negative capacitor circuit system. As depicted in this example, the access time of comparator 200 using the negative capacitor circuit system is significantly shorter (e.g., ~20%). Because of the shorter access time, comparator 200 can operate at a significantly higher frequency.

[0044] In this example, the latching phase ends and the reset phase begins when the CLK control signal transitions from logic low (304) to logic high at approximately 1.2 ns. When the CLK control signal transitions from logic low (306), comparator 200 re-enters the latching phase. In this example, the CLK control signal is shown as a 50% duty cycle signal. In some embodiments, the CLK control signal may be configured to have a duty cycle of less than 50%, and in other embodiments, the CLK control signal may be configured to have a duty cycle of greater than 50%.

[0045] A circuit is provided comprising an amplifier section having a first input coupled to receive a first analog signal and a first output; a latch section coupled to the amplifier section, the latch section being configured to provide a digital value at the first output based on the first analog signal; and a negative capacitor section coupled to the first output, the negative capacitor section being configured to eliminate parasitic capacitance coupled to the first output. The negative capacitor section may further include a first transistor having a first power supply electrode coupled to the first output; a second transistor having a first power supply electrode coupled to a control electrode of the first transistor and a control electrode coupled to the first output; and a capacitor having a first end coupled to a second power supply electrode of the first transistor and a second end coupled to a second power supply electrode of the second transistor. The capacitor may have a capacitance value approximately equal to the parasitic capacitance coupled to the first output. The negative capacitor section may further include a first current source having a first end coupled to a first voltage supply and a second end coupled to the second power supply electrode of the first transistor; and a second current source having a first end coupled to the first voltage supply and a second end coupled to the second power supply electrode of the second transistor. The amplifier section may further include a first transistor having a first power supply electrode, a second power supply electrode coupled to a second output terminal, and a control electrode coupled to receive the first analog signal; and a second transistor having a first power supply electrode coupled to the first power supply electrode of the first transistor, a second power supply electrode coupled to the first output terminal, and a control electrode coupled to receive a second analog signal, wherein the first analog signal and the second analog signal together comprise a differential signal. The amplifier section may further include a first current source having a first terminal coupled to a first voltage supply terminal and a second terminal coupled to the first power supply electrodes of the first transistor and the second transistor. The latch section may further include a third transistor having a first power supply electrode coupled to the second power supply electrode of the first transistor at the second output terminal, a second power supply electrode coupled to a second voltage supply terminal, and a control electrode coupled to the second power supply electrode of the second transistor at the first output terminal; and a fourth transistor having a first power supply electrode coupled to the second power supply electrode of the second transistor, a second power supply electrode coupled to the second voltage supply terminal, and a control electrode coupled to the second power supply electrode of the first transistor. The circuit may further include a first digital-to-analog converter (DAC) having an input coupled to the first output, and the output of the DAC being coupled to provide a second analog signal representing the digital value.The circuit may further include a summing circuit having a first input terminal coupled to receive an input signal, a second input terminal for receiving the second analog signal, and an output terminal coupled to provide a first differential signal generated by subtracting the second analog signal from the input signal.

[0046] In another embodiment, a circuit is provided, the circuit including an amplifier section having a first input coupled to receive a first analog signal and a first output, the amplifier section being coupled between a first voltage supply and the first output; a latch section coupled to the amplifier section at the first output, the latch section being configured to provide a digital value based on the first analog signal; and a negative capacitance section coupled to the amplifier section and the latch section at the first output, the negative capacitance section being configured to eliminate parasitic capacitance coupled to the first output. The negative capacitance section may further include a first transistor coupled between the first voltage supply and the first output, the first transistor having a first power supply electrode coupled to the first output; a second transistor having a first power supply electrode coupled to a control electrode of the first transistor and a control electrode coupled to the first power supply electrode of the first transistor; and a capacitor having a first end coupled to a second power supply electrode of the first transistor and a second end coupled to a second power supply electrode of the second transistor, the capacitor having a capacitance value substantially equal to the parasitic capacitance coupled to the first output. The negative capacitor section may further include a first current source having a first terminal coupled to the first voltage supply terminal and a second terminal coupled to the second power supply electrode of the first transistor; and a second current source having a first terminal coupled to the first voltage supply terminal and a second terminal coupled to the second power supply electrode of the second transistor. The amplifier section may further include a third current source coupled to the first voltage supply terminal; a third transistor having a first power supply electrode coupled to the third current source and a control electrode coupled to receive the first analog signal; and a fourth transistor having a first power supply electrode coupled to the first current source, a second power supply electrode coupled to the first output terminal, and a control electrode coupled to receive a second analog signal, the first analog signal and the second analog signal together comprising a differential signal. The third current source may be configured to supply a current amount approximately equal to the sum of the currents supplied by the first current source and the second current source. The circuit may further include a first digital-to-analog converter (DAC) having an input terminal coupled to the first output terminal, and an output terminal coupled to provide a second analog signal representing the digital value. The circuit may further include a summing circuit having a first input terminal coupled to receive an input signal, a second input terminal for receiving the second analog signal, and an output terminal coupled to the first input terminal of the amplifier section. The summing circuit may be configured to provide a first differential signal at the output terminal, the first differential signal being generated by subtracting the second analog signal from the input signal.

[0047] In another embodiment, a circuit is provided, the circuit including an amplifier section, the amplifier section including: a first transistor having a first power supply electrode, a second power supply electrode coupled to a first output terminal, and a control electrode coupled to receive a first analog signal; and a second transistor having a first power supply electrode coupled to the first power supply electrode of the first transistor, a second power supply electrode coupled to a second output terminal, and a control electrode coupled to receive a second analog signal, the first analog signal and the second analog signal together including a differential signal; and a latch section coupled to the amplifier section, the latch section including: a third transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to receive a second analog signal. The circuit includes a control electrode at the first output terminal, a fourth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to the second output terminal, and a negative capacitor portion coupled to the amplifier portion and the latch portion, the negative capacitor portion comprising: a fifth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to the second output terminal, a sixth transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to the first output terminal, and a capacitor having a first end coupled to a second power supply electrode of the first transistor and a second end coupled to a second power supply electrode of the second transistor. The capacitor may have a capacitance value approximately equal to the parasitic capacitance coupled to the first output terminal or the second output terminal. The circuit may further include a seventh transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to receive a control signal; and an eighth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to receive the control signal, wherein the control signal in a first logic state causes the seventh and eighth transistors to conduct and resets the latch portion.

[0048] It should now be understood that quantizers configured to eliminate output parasitic capacitance are available. By incorporating a negative capacitance circuit system to eliminate the quantizer's output parasitic capacitance, shorter latch access times are achieved. With shorter latch access times, the quantizer can be configured to operate at higher frequencies. Processing samples with a quantizer operating at higher frequencies allows for higher throughput.

[0049] Because the devices implementing this invention consist mostly of electronic components and circuits known to those skilled in the art, the circuit details will not be explained to any extent greater than that shown above as necessary, in order to understand and comprehend the basic concepts of this invention and not to obscure or distract from the teachings of this invention.

[0050] Although the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention. Any benefit, advantage, or solution to the problem described herein with reference to specific embodiments is not intended to be construed as a critical, necessary, or essential component or element of any or all claims.

[0051] The term “coupling” as used in this article is not intended to be limited to direct coupling or mechanical coupling.

[0052] Furthermore, as used herein, the term "a" is defined as one or more. And, introductory phrases used in the claims, such as "at least one" and "one or more," should not be construed as implying that any additional claim element introduced by the indefinite article "a" limits any particular claim containing such an introduced claim element to an invention containing only one of that element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a." The same applies to the use of definite articles.

[0053] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of such elements.

Claims

1. A circuit, characterized in that, include: An amplifier section coupled to a first current source, the amplifier section having a first input coupled to receive a first analog signal and a first output, wherein the first current source is configured to generate a first current; A latch section coupled to the amplifier section, the latch section being configured to provide a digital value at the first output based on the first analog signal; as well as A negative capacitor portion coupled to the first output terminal and a second current source, wherein the negative capacitor portion is configured to eliminate parasitic capacitance coupled to the first output terminal, and the second current source is configured to generate a second current that is substantially half of the first current. and A first digital-to-analog converter (DAC) has an input coupled to the first output, and the output of the first DAC is coupled to provide a second analog signal representing the digital value.

2. The circuit according to claim 1, characterized in that, The negative capacitance portion further includes: A first transistor, the first transistor having a first power supply electrode coupled to the first output terminal; A second transistor, the second transistor having a first power supply electrode coupled to the control electrode of the first transistor and a control electrode coupled to the first output terminal; and A capacitor having a first end coupled to a second power supply electrode of the first transistor and a second end coupled to a second power supply electrode of the second transistor.

3. The circuit according to claim 2, characterized in that, The capacitor has a capacitance value approximately equal to that of the parasitic capacitance coupled to the first output terminal.

4. The circuit according to claim 2, characterized in that, The negative capacitance portion further includes: A first current source, the first current source having a first terminal coupled to a first voltage supply terminal and a second terminal coupled to the second power supply electrode of the first transistor; and The second current source has a first end coupled to the first voltage supply terminal and a second end coupled to the second power supply electrode of the second transistor.

5. The circuit according to claim 1, characterized in that, The amplifier section further includes: A first transistor, the first transistor having a first power supply electrode, a second power supply electrode coupled to a second output terminal, and a control electrode coupled to receive the first analog signal; and The second transistor has a first power supply electrode coupled to the first power supply electrode of the first transistor, a second power supply electrode coupled to the first output terminal, and a control electrode coupled to receive a second analog signal, the first analog signal and the second analog signal together comprising a differential signal.

6. The circuit according to claim 5, characterized in that, The amplifier section further includes a first current source having a first end coupled to a first voltage supply terminal and a second end coupled to the first power supply electrode of the first transistor and the second transistor.

7. The circuit according to claim 5, characterized in that, The latch portion further includes: A third transistor, the third transistor having a first power supply electrode coupled to the second power supply electrode of the first transistor at the second output terminal, a second power supply electrode coupled to the second voltage supply terminal, and a control electrode coupled to the second power supply electrode of the second transistor at the first output terminal; and A fourth transistor having a first power supply electrode coupled to the second power supply electrode of the second transistor, a second power supply electrode coupled to the second voltage supply terminal, and a control electrode coupled to the second power supply electrode of the first transistor.

8. A circuit, characterized in that, include: An amplifier section coupled to a first current source, the amplifier section having a first input terminal coupled to receive a first analog signal and a first output terminal, the amplifier section being coupled between a first voltage supply terminal and the first output terminal, wherein the first current source is configured to generate a first current; A latch section is coupled to the first output terminal of the amplifier section, the latch section being configured to provide a digital value based on the first analog signal; as well as A negative capacitor portion coupled to the amplifier portion and the latch portion and a second current source are provided at the first output terminal. The negative capacitor portion is configured to eliminate parasitic capacitance coupled to the first output terminal, and the second current source is configured to generate a second current that is substantially half of the first current. and A first digital-to-analog converter (DAC) has an input coupled to the first output, and the output of the first DAC is coupled to provide a second analog signal representing the digital value.

9. A circuit, characterized in that, include: An amplifier section coupled to a first current source, the amplifier section comprising: A first transistor, the first transistor having a first power supply electrode, a second power supply electrode coupled to a first output terminal, and a control electrode coupled to receive a first analog signal; and The second transistor has a first power supply electrode coupled to the first power supply electrode of the first transistor, a second power supply electrode coupled to the second output terminal, and a control electrode coupled to receive a second analog signal, wherein the first analog signal and the second analog signal together include a differential signal. A latch section coupled to the amplifier section, the latch section comprising: A third transistor, the third transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to the first output terminal, and A fourth transistor, the fourth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to the second output terminal; and A negative capacitor portion coupled to the amplifier section and the latch section, and a second current source, wherein the second current source is configured to generate a second current substantially half that of the first current, the negative capacitor portion comprising: A fifth transistor, the fifth transistor having a first power supply electrode coupled to the first output terminal and a control electrode coupled to the second output terminal, A sixth transistor, the sixth transistor having a first power supply electrode coupled to the second output terminal and a control electrode coupled to the first output terminal, and A capacitor having a first terminal coupled to a second power supply electrode of the first transistor and a second terminal coupled to a second power supply electrode of the second transistor; and A first digital-to-analog converter (DAC) has an input coupled to a first output, and the output of the first DAC is coupled to provide a second analog signal representing a digital value, the digital value being provided by a latch portion based on the first analog signal at the first output.

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