Semiconductor device including gate layer and vertical structure

Abstract

A semiconductor device includes: vertical structures on a substrate; and an interlayer insulating layer and a gate layer on the substrate, wherein the gate layer is sequentially stacked in a memory cell array region and extends into an extension region, the gate layer has a pad region in the extension region in a stepped structure, a surface of a first vertical structure faces the gate layer, a surface of a second vertical structure faces at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than an upper surface of the first core pattern.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2019-0081435, entitled "Semiconductor Device Including Gate Layer and Vertical Structure and Method of Forming the Same", filed with the Korean Intellectual Property Office on July 5, 2019, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a semiconductor device including a gate layer and a vertical structure, and a method of forming the semiconductor device. Background Technology

[0004] To enhance the price competitiveness of products, the integration density of semiconductor devices can be increased. To further increase the integration density of semiconductor devices, three-dimensional rather than two-dimensional arrangements of memory cells have been considered. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising: a first vertical structure on a substrate; a second vertical structure on a substrate; and an interlayer insulating layer and a gate layer alternately stacked on the substrate, wherein the gate layers are sequentially stacked in a memory cell array region of the substrate and extend into an extension region of the substrate adjacent to the memory cell array region of the substrate, the gate layers having pad regions arranged in a stepped structure in the extension region, side surfaces of the first vertical structure facing the gate layers in the memory cell array region, side surfaces of the second vertical structure facing at least one gate layer in the extension region, the first vertical structure comprising a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and a pad pattern on an upper surface of the first core pattern, the second vertical structure comprising a second core pattern and a second semiconductor layer on a side surface of the second core pattern, the first core pattern and the second core pattern each comprising an insulating material, and the upper surface of the second semiconductor layer and the upper surface of the second core pattern being farther from the substrate than the upper surface of the first core pattern.

[0006] Embodiments can be realized by providing a semiconductor device including a stack structure on a substrate, the stack structure including a plurality of gate layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a cover structure on the stack structure; an upper insulating layer on the cover structure; a first vertical structure penetrating a first region of the stack structure and extending into the cover structure; a second vertical structure penetrating a second region of the stack structure and extending into the cover structure, the second region of the stack structure being adjacent to the first region of the stack structure; and a contact plug penetrating the upper insulating layer, wherein the first vertical structure includes a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and a pad pattern on an upper surface of the first core pattern, the second vertical structure includes a second core pattern and a second semiconductor layer on a side surface of the second core pattern, the pad pattern is electrically connected to the contact plug, and the upper insulating layer is in contact with the second semiconductor layer and the second core pattern.

[0007] Embodiments can be realized by providing a semiconductor device including a stack structure on a substrate, the stack structure including a stack region and a staircase region adjacent to the stack region; a cover structure on the stack structure; a first vertical structure penetrating the stack region of the stack structure and extending into the cover structure; a second vertical structure penetrating the staircase region of the stack structure and extending into the cover structure; an upper insulating layer on the cover structure, the first vertical structure, and the second vertical structure; and a bit line contact plug penetrating the upper insulating layer and electrically connected to the first vertical structure, wherein the first vertical structure includes a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and a pad pattern on an upper surface of the first core pattern, the pad pattern is in contact with the bit line contact plug, the second vertical structure includes a second core pattern and a second semiconductor layer on a side surface of the second core pattern, the first core pattern and the second core pattern each include an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than an upper surface of the first core pattern.

[0008] Embodiments can be realized by providing a method of forming a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating layers and preliminary gate layers; forming a first cover pattern and a mask layer sequentially stacked on the mold structure; patterning the mold structure to form a staircase structure in a region adjacent to the first cover pattern; forming a second cover pattern such that the second cover pattern covers the staircase structure; forming a plurality of holes including a first hole penetrating the mask layer, the first cover pattern, and the mold structure and a second hole penetrating the second cover pattern and the mold structure; performing an annealing process to discharge a gas in the interlayer insulating layers, the first cover pattern, and the second cover pattern; and forming vertical structures in the plurality of holes.

[0009] The first coverage pattern, the second coverage pattern, and the interlayer insulation layer can be formed of silicon oxide, and the mask layer can be formed of an insulating material different from silicon oxide. The mask layer can be removed while the vertical structures are formed in the plurality of holes.

[0010] The method can further include, after the mask layer is removed while the vertical structures are formed in the plurality of holes, forming an upper insulation layer on the first coverage pattern and the second coverage pattern, forming a separation trench that penetrates the upper insulation layer, the first coverage pattern, the second coverage pattern, and the mold structure, removing the preliminary gate layer exposed by the separation trench to form a space, forming a gate layer in the space, forming a separation structure that fills the separation trench, and forming a contact plug that penetrates the upper insulation layer.

[0011] The vertical structures can include first vertical structures in the first holes and second vertical structures in the second holes. The first vertical structures can include first semiconductor layers on inner surfaces of the first holes, first core patterns that fill portions of the first holes in which the first semiconductor layers are formed, and pad patterns on the first core patterns. The second vertical structures can include second semiconductor layers on inner surfaces of the second holes and second core patterns that fill the second holes in which the second semiconductor layers are formed.

[0012] The upper insulation layer can be in contact with the second semiconductor layers and the second core patterns, and the contact plug can be electrically connected to the pad patterns. BRIEF DESCRIPTION OF DRAWINGS

[0013] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, of which:

[0014] Figure 1 A plan view of a semiconductor device according to an example embodiment is illustrated;

[0015] Figures 2A-2C A cross-sectional view of a semiconductor device according to an example embodiment is illustrated;

[0016] Figure 3 A partially enlarged cross-sectional view of a semiconductor device according to a modified embodiment is illustrated;

[0017] Figure 4A A partially enlarged cross-sectional view of a semiconductor device according to a modified embodiment is illustrated;

[0018] Figure 4B A partially enlarged cross-sectional view of a semiconductor device according to a modified embodiment is illustrated;

[0019] Figure 5A A partially enlarged cross-sectional view of a semiconductor device according to a modified embodiment is illustrated;

[0020] Figure 5BA partial enlarged cross-sectional view of a semiconductor device according to a modified embodiment is shown.

[0021] Figure 6 A cross-sectional view of a semiconductor device according to a modified embodiment is shown.

[0022] Figures 7A-13B Cross-sectional views of some stages in a method of forming a semiconductor device according to an example embodiment are shown. DETAILED DESCRIPTION

[0023] Hereinafter, a semiconductor device according to an example embodiment will be described with reference to Figure 1 and Figures 2A-2C A semiconductor device according to an example embodiment will be described. Figure 1 Plan views of some components are shown to describe a semiconductor device according to an example embodiment. Figure 2A Cross-sectional views of regions taken along Figure 1 lines I-I’ of FIG. 1A are shown to describe a semiconductor device according to an example embodiment. Figure 2B Cross-sectional views of regions taken along Figure 1 lines II-II’ of FIG. 1A are shown to illustrate a semiconductor device according to an example embodiment. Figure 2C Cross-sectional views of regions taken along Figure 1 lines III-III’ and IV-IV’ of FIG. 1A are shown to describe a semiconductor device according to an example embodiment.

[0024] With reference to Figure 1 and Figures 2A-2C , a semiconductor device 1 according to an example embodiment can include a substrate 3, a stack structure 115s, cover structures 42 and 58, and a plurality of vertical structures 96. The substrate 3 can include a semiconductor substrate 3.

[0025] The stack structure 115s can be on the substrate 3. The stack structure 115s can include a first stack group 115s1 on the substrate 3 and a second stack group 115s2 on the first stack group 115s1.

[0026] The stack structure 115s can be on a memory cell array region MA of the substrate 3 and can extend into an extension region EA of the substrate 3 adjacent to the memory cell array region MA. The stack structure 115s can include interlayer insulating layers and gate layers alternately and repeatedly (e.g., in a vertical direction Z) stacked. For example, the first stack group 115s1 can include first interlayer insulating layers 8 and first gate layers 112g1 alternately and repeatedly stacked, and the second stack group 115s2 can include second interlayer insulating layers 29 and second gate layers 112g2 alternately and repeatedly stacked. The first gate layers 112g1 and the second gate layers 112g2 can be substantially parallel to an upper surface 3s (e.g., a plane defined by a first direction X and a second direction Y) of the substrate 3.

[0027] The first stack group 115s1 can further include an intermediate interlayer insulating layer 12 on the uppermost first gate layer 112g1 (e.g., the first gate layer 112g1 farthest from the substrate 3 in the vertical direction Z) of the first gate layers 112g1. The intermediate interlayer insulating layer 12 can be between the uppermost first gate layer 112g1 and the lowermost second interlayer insulating layer 29 (e.g., the second interlayer insulating layer 29 closest to the substrate 3 in the vertical direction Z) of the second interlayer insulating layers 29.

[0028] The stack structure 115s can include a first region 115A and a second region 115B adjacent to the first region 115A. The first region 115A of the stack structure 115s can be on the memory cell array region MA of the substrate 3, and the second region 115B of the stack structure 115s can be on the extension region EA of the substrate 3. The first region 115A of the stack structure 115s can be referred to as a “stack region,” and the second region 115B of the stack structure 115s can be referred to as a “stair region.”

[0029] The first gate layers 112g1 can be stacked apart from each other in the vertical direction Z in the first region 115A and can extend from the first region 115A into the second region 115B. The vertical direction Z can be a direction perpendicular to an upper surface of the substrate 3 (e.g., perpendicular to the first direction X and the second direction Y). The first gate layers 112g1 can include a first gate pad region 112p1 in a stair structure in the second region 115B.

[0030] The second gate layers 112g2 can be stacked apart from each other in the vertical direction Z in the first region 115A and can extend from the first region 115A into the second region 115B. The second gate layers 112g2 can include a second gate pad region 112p2 in a stair structure in the second region 115B of the stack structure 115s.

[0031] The cover structures 42 and 58 can be on the substrate 3. In one embodiment, the cover structures 42 and 58, the first interlayer insulating layer 8, and the second interlayer insulating layer 29 can be formed of silicon oxide in which a gas is removed or reduced by an annealing process. For example, a semiconductor device 1 capable of improving integration density and reducing defects can be provided.

[0032] The cover structures 42 and 58 can include a first cover pattern 42 (on the first region 115A of the stack structure 115s) and a second cover pattern 58 (adjacent to the first cover pattern 42 and on the second region 115B of the stack structure 115s).

[0033] The first coverage pattern 42 can include the first lower coverage layer 34 and a first upper coverage layer 40 on the first lower coverage layer 34. A thickness (e.g., in the vertical direction Z) of the first upper coverage layer 40 can be greater than a thickness of the first lower coverage layer 34.

[0034] The second coverage pattern 58 can include a second lower coverage layer 15 and a second upper coverage layer 56 on the second lower coverage layer 15. An upper surface of the second lower coverage layer 15 can be substantially coplanar with an upper surface of the first stack group 115s1.

[0035] The second lower coverage layer 15 can cover the first gate pad region 112p1 of the first stack group 115s1.

[0036] The second upper coverage layer 56 can be on the second lower coverage layer 15 and can cover the second gate pad region 112p2 of the second stack group 115s2. The second upper coverage layer 56 and the first coverage pattern 42 can have side surfaces facing each other.

[0037] In one embodiment, an upper surface (e.g., a surface facing away from the substrate 3 in the vertical direction Z) of the second upper coverage layer 56 and an upper surface of the first upper coverage layer 40 can be substantially coplanar with each other.

[0038] The plurality of vertical structures 96 can be in the holes 18 and 61 (e.g., see Figure 3 ) that penetrate the coverage structures 42 and 58 and the stack structure 115s. For example, the plurality of vertical structures 96 can penetrate the coverage structures 42 and 58 and the stack structure 115s. Upper surfaces of the plurality of vertical structures 96 can be substantially coplanar with each other. The plurality of vertical structures 96 can have substantially the same width (e.g., in the first direction X and / or the second direction Y).

[0039] The plurality of vertical structures 96 can include a first vertical structure 96a and a second vertical structure 96b.

[0040] The first vertical structure 96a can penetrate the first region 115A of the stack structure 115s and extend into the first coverage pattern 42. The first vertical structure 96a can penetrate the first coverage pattern 42. The second vertical structure 96b can penetrate the second region 115B of the stack structure 115s and can extend into the second coverage pattern 58. The second vertical structure 96b can penetrate the second coverage pattern 58. Side surfaces of the first vertical structure 96a can face the first gate layer 112g1 and the second gate layer 112g2 in the memory cell array region MA. Side surfaces of the second vertical structure 96b can face at least one of the first gate layer 112g1 and the second gate layer 112g2 in the extension region EA.

[0041] The first vertical structure 96a can include the first core pattern 82a and a pad pattern 93 on an upper surface of the first core pattern 82a. The second vertical structure 96b can include the second core pattern 82b.

[0042] The first core pattern 82a and the second core pattern 82b can include an insulating material. The first core pattern 82a and the second core pattern 82b can be formed of the same material, e.g., silicon oxide. An upper surface of the second core pattern 82b can be higher (e.g., further from the substrate 3 in the vertical direction Z) than an upper surface of the first core pattern 82a. An upper surface of the pad pattern 93 can be substantially coplanar with the upper surface of the second core pattern 82b.

[0043] In an embodiment, the first vertical structure 96a can further include a first semiconductor layer 79a on a side surface of the first core pattern 82a, and the second vertical structure 96b can further include a second semiconductor layer 79b on a side surface of the second core pattern 82b.

[0044] In an embodiment, the first vertical structure 96a can further include a first dielectric structure 70a on an outer side surface of the first semiconductor layer 79a, and the second vertical structure 96b can further include a second dielectric structure 70b on an outer side surface of the second semiconductor layer 79b.

[0045] In an embodiment, the plurality of vertical structures 96 can penetrate the stack structure 115s and can extend into the substrate 3.

[0046] The first gate layer 112g1 and the second gate layer 112g2 can each have a side surface facing the first vertical structure 96a. The first gate layer 112g1 and the second gate layer 112g2 can each have a side surface in contact with the first vertical structure 96a.

[0047] A portion of the first gate layer 112g1 and the second gate layer 112g2 can have a side surface in contact with the second vertical structure 96b, and another portion of the first gate layer 112g1 and the second gate layer 112g2 can be spaced apart from the second vertical structure 96b.

[0048] The semiconductor device 1 according to the example embodiment can further include an upper insulating structure 128 on the cover structures 42 and 58. The upper insulating structure 128 can include a first upper insulating layer 102, a second upper insulating layer 121, and a third upper insulating layer 127 stacked in order.

[0049] The semiconductor device 1 according to the example embodiment can further include a bit line contact plug 130 penetrating the upper insulating structure 128 and electrically connected to the pad pattern 93 of the first vertical structure 96a. The semiconductor device 1 according to the example embodiment can further include a bit line 136 on the bit line contact plug 130.

[0050] The semiconductor device 1 according to the example embodiment can further include a gate contact plug 124 sequentially penetrating the second upper insulating layer 121, the first upper insulating layer 102, and the second cap pattern 58 and electrically connected to the first gate pad region 112p1 and the second gate pad region 112p2.

[0051] The semiconductor device 1 according to the example embodiment can further include an upper contact plug 133 penetrating the third upper insulating layer 127 and electrically connected to the gate contact plug 124. The semiconductor device 1 according to the example embodiment can further include a gate interconnect 139 on the upper contact plug 133.

[0052] In an implementation, the semiconductor device 1 can further include a separation structure 118 penetrating the first upper insulating layer 102, the cap structures 42 and 58, and the stack structure 115s. The separation structure 118 can extend in the first direction X (e.g., longitudinally). The first direction X can be a direction parallel to the upper surface 3s of the substrate 3. An upper surface of the separation structure 118 can be at a higher height (e.g., further away in the vertical direction Z from the substrate 3) than an upper surface of the vertical structure 96.

[0053] The separation structure 118 can include first separation structures 118a, second separation structures 118b (between the first separation structures 118a), and third separation structures 118c (between the first separation structures 118a and end-to-end facing any of the second separation structures 118b). In the first direction X, a length of each of the first separation structures 118a can be greater than a length of each of the second separation structures 118b. The third separation structures 118c can be in the first region 115A of the stack structure 115s and can extend into the second region 115B, and the second separation structures 118b can be in the second region 115B of the stack structure 115s.

[0054] In an implementation, the separation structure 118 can be formed of an insulating material. In an implementation, the separation structure 118 can include an insulating material and a conductive material. In an implementation, each of the separation structures 118 can include a layer of the conductive material and a layer of the insulating material on side surfaces of the layer of the conductive material.

[0055] The semiconductor device 1 according to the example embodiment can further include an insulating pattern 37 that penetrates at least the uppermost second gate layer 112g2 of the second gate layers 112g2. In one implementation, the insulating pattern 37 can also penetrate the second gate layer 112g2 immediately below the uppermost second gate layer 112g2, and can extend in the vertical direction Z to also penetrate the uppermost second gate layer 112g2. The insulating pattern 37 can be in the form of a line pattern extending longitudinally in the first direction X, and can be between the first partition structure 118a and the third partition structure 118c. The width of each partition structure 118 in the second direction Y can be greater than the width of the insulating pattern 37 in the second direction Y. The second direction Y can be parallel to the upper surface 3s of the substrate 3, and can be perpendicular to the first direction X.

[0056] Hereinafter, the example of the stack structure 115s and the vertical structure 96 will be described with reference to Figure 3 FIGS. 1A and 1B. Figure 3 FIGS. 2A and 2B show partial enlarged cross-sectional views of the “A” portion and the “B” portion of FIGS. 1A and 1B, respectively. Figure 2C

[0057] In one implementation, with reference to Figure 3 , the first gate layer 112g1 and the second gate layer 112g2 can each include a first layer 113a and a second layer 113b. The second layer 113b can extend between the first layer 113a and the vertical structure 96 while covering the lower surface and the upper surface of the first layer 113a.

[0058] In one implementation, the first layer 113a can include a first conductive material (e.g., tungsten (W), etc.), and the second layer 113b can include a second conductive material different from the first conductive material (e.g., titanium nitride (TiN), tungsten nitride (WN), etc.).

[0059] In one implementation, the first layer 113a can include a conductive material (e.g., TiN, W, etc.), and the second layer 113b can include a dielectric material. The dielectric material of the second layer 113b can be a high-k dielectric such as aluminum oxide (AlO).

[0060] As described above, the vertical structure 96 can include a first vertical structure 96a and a second vertical structure 96b, the first vertical structure 96a can include the first dielectric structure 70a, the first semiconductor layer 79a, the first core pattern 82a, and the pad pattern 93, and the second vertical structure 96b can include the second dielectric structure 70b, the second semiconductor layer 79b, and the second core pattern 82b.

[0061] In one implementation, the first semiconductor layer 79a can cover the side surface of the first core pattern 82a, and can extend in the vertical direction Z to cover the side surface of the pad pattern 93. ​

[0062] In an embodiment, the upper surface of the first semiconductor layer 79a can be substantially coplanar with the upper surface of the pad pattern 93.

[0063] In an embodiment, the upper surface of the second semiconductor layer 79b can be substantially coplanar with the upper surface of the pad pattern 93.

[0064] In an embodiment, the upper surface of the second core pattern 82b can be substantially coplanar with the upper surface of the pad pattern 93.

[0065] In an embodiment, the upper surface of the first dielectric structure 70a, the upper surface of the first semiconductor layer 79a, and the upper surface of the pad pattern 93 can be substantially coplanar with each other.

[0066] In an embodiment, the upper surface of the second dielectric structure 70b, the upper surface of the second semiconductor layer 79b, and the upper surface of the second core pattern 82b can be substantially coplanar with each other.

[0067] The upper surface of the second semiconductor layer 79b and the upper surface of the second core pattern 82b can be higher than the upper surface of the first core pattern 82a of the first vertical structure 96a. The “height” can be a height based on a distance from the upper surface of the substrate 3 in the vertical direction Z.

[0068] In an embodiment, the width (e.g., in the second direction Y) of the pad pattern 93 can be greater than the width of the first core pattern 82a. The first semiconductor layer 79a can include a first portion 79a_1 and a second portion 79a_2, the thickness (e.g., in the second direction Y) of the second portion 79a_2 being less than the thickness of the first portion 79a_1. The first portion 79a_1 of the first semiconductor layer 79a can cover the side surface of the first core pattern 82a, and the second portion 79a_2 of the first semiconductor layer 79a can cover the side surface of the pad pattern 93. The second portion 79a_2 of the first semiconductor layer 79a can be between the pad pattern 93 and the first dielectric structure 70a (e.g., in the second direction Y). The width (e.g., in the second direction Y) of the pad pattern 93 can be greater than the width of the second core pattern 82b. The thickness (e.g., in the second direction Y) of the second portion 79a_2 of the first semiconductor layer 79a can be less than the thickness of the second semiconductor layer 79b at the same height as the second portion 79a_2 of the first semiconductor layer 79a.

[0069] In one implementation, the first dielectric structure 70a and the second dielectric structure 70b can include the same layers of material. For example, the first dielectric structure 70a and the second dielectric structure 70b can each include a first dielectric layer 72, a second dielectric layer 76, and a data storage layer 74 between the first dielectric layer 72 and the second dielectric layer 76. The first dielectric layer 72 can be a first gate dielectric layer, and the second dielectric layer can be a second gate dielectric layer.

[0070] The second dielectric layer 76 of the first dielectric structure 70a can be between the data storage layer 74 and the first semiconductor layer 79a, and the second dielectric layer 76 of the second dielectric structure 70b can be between the data storage layer 74 and the second semiconductor layer 79b.

[0071] In one implementation, the first gate layer 112gl can include a single or multiple first lower gate layers and a multiple first upper gate layers on the single or multiple first lower gate layers. The second gate layer 112g2 can include a multiple second lower gate layers and a single or multiple second upper gate layers on the second lower gate layers.

[0072] In the first gate layer 112gl and the second gate layer 112g2, the multiple first upper gate layers and the multiple second lower gate layers can include word lines. At least one of the single or multiple first lower gate layers can be a lower select gate line, and at least one of the single or multiple second upper gate layers can be an upper select gate line.

[0073] In one implementation, the data storage layer 74 of the first vertical structure 96a can include an area in a semiconductor device (e.g., a vertical NAND flash device) that is capable of storing data. For example, the data storage layer 74 of the first vertical structure 96a can be an area between a gate layer of a word line and the first semiconductor layer 79a in the first gate layer 112gl and the second gate layer 112g2 can be an area that is capable of storing data.

[0074] In one implementation, the first semiconductor layer 79a of the first vertical structure 96a can be a channel layer or a channel region of a vertical NAND flash device.

[0075] In one embodiment, each vertical structure 96 may include a lower vertical structure 96_L and an upper vertical structure 96_U on the lower vertical structure 96_L. For example, the first vertical structure 96a and the second vertical structure 96b may each include a lower vertical structure 96_L and an upper vertical structure 96_U. The lower vertical structure 96_L of each of the first vertical structure 96a and the second vertical structure 96b may penetrate the first stack group 115s1. The upper vertical structure 96_U of each of the first vertical structure 96a and the second vertical structure 96b may penetrate the second stack group 115s2. The width (e.g., in the second direction Y) of the upper region of the lower vertical structure 96_L (e.g., in the region adjacent to the upper vertical structure 96_U) may be greater than the width of the lower region of the upper vertical structure 96_U adjacent to the lower vertical structure 96_L.

[0076] The first upper insulating layer 102 can cover the entire upper surface of the second vertical structure 96b. The first upper insulating layer 102 can contact the upper surface of the second dielectric structure 70b, the upper surface of the second semiconductor layer 79b, and the upper surface of the second core pattern 82b of the second vertical structure 96b.

[0077] In one embodiment, the width of the first vertical structure 96a may be less than or greater than the width of the bit line contact plug 130. The bit line contact plug 130 may be electrically connected to the pad pattern 93 of the first vertical structure 96a. The pad pattern 93 may be formed of doped silicon. A portion of the upper surface of the first vertical structure 96a may be in contact with the first upper insulating layer 102.

[0078] Next, refer to Figure 4A , Figure 4B , Figure 5A and Figure 5B Describe various modifications to the semiconductor device based on the example. Figure 4A , Figure 4B , Figure 5A and Figure 5B Each showed Figure 2C A partially enlarged cross-sectional view of sections "A" and "B". In the following description, the focus will be on the modified components described above, while other components will be directly referenced or not described further.

[0079] In the following text, reference will be made to Figure 4A Describe the pad pattern ( Figure 3 93) and the first semiconductor layer ( Figure 3 Example of modification of 79a).

[0080] In one implementation, reference Figure 4AThe width of the pad pattern 193a can be greater than the width of the first core pattern 82a. The upper surface of the first semiconductor layer 179a can be in contact with the lower surface of the pad pattern 193a. The lower surface of the pad pattern 193a can be in contact with the upper surface of the first semiconductor layer 179a and the upper surface of the first core pattern 82a. The upper surface of the second semiconductor layer 79b can be coplanar with the upper surface of the pad pattern 193a and can be higher than the upper surface of the first semiconductor layer 179a.

[0081] Hereinafter, a modification example of the pad pattern (93) and the first semiconductor layer (79a) will be described with reference to Figure 4B Figure 3 Figure 3

[0082] In one embodiment, with reference to Figure 4B The pad pattern 193b can include a first portion 193b_1 on the first core pattern 82a and a second portion 193b_2 extending from the first portion 193b_1 in a direction toward the substrate 3 (e.g., in the vertical direction Z) to be in contact with the upper side surface of the first core pattern 82a.

[0083] The first semiconductor layer 179b can be in contact with the second portion 193b_2 of the pad pattern 193b. The upper surface of the first semiconductor layer 179b can be lower than the upper surface of the first core pattern 82a. For example, the distance between the upper surface of the first semiconductor layer 179b and the upper surface of the substrate 3 in the vertical direction Z can be shorter than the distance between the upper surface of the first core pattern 82a and the upper surface of the substrate 3 in the vertical direction Z.

[0084] Hereinafter, a modification example of the first dielectric structure (70a), the second dielectric structure (70b), the first gate layer (112g1), and the second gate layer (112g2) will be described with reference to Figure 5A Figure 3 Figure 3 Figure 3 Figure 3

[0085] In one embodiment, with reference to Figure 5A The side surface of the first gate layer 112g1’ can be further recessed than the side surface of the first interlayer insulating layer 8. The side surface of the second gate layer 112g2’ can be further recessed than the side surface of the second interlayer insulating layer 29.

[0086] ​​​​​​​​The first dielectric structure 270a and the second dielectric structure 270b each can include a first dielectric layer 272, a second dielectric layer 276, and a data storage pattern 274 between the first dielectric layer 272 and the second dielectric layer 276. The first dielectric structure 270a can be on an outer side surface of the first semiconductor layer 79a, and the second dielectric structure 270b can be on an outer side surface of the second semiconductor layer 79b. The data storage patterns 274 can be spaced apart from each other in the vertical direction Z, between one first dielectric layer 272 and one second dielectric layer 276.

[0087] The data storage patterns 274 can face the first gate layer 112g1' and the second gate layer 112g2'. In one embodiment, the data storage patterns 274 facing the first gate layer 112g1' can be between the first interlayer insulating layers 8, and the data storage patterns 274 facing the second gate layer 112g2' can be provided between the second interlayer insulating layers 29.

[0088] The data storage patterns 274 of the first gate layer 112g1' and the second gate layer 112g2' facing among the first gate layer 112g1' and the second gate layer 112g2' of the first vertical structure 96a can be word lines. The data storage patterns 274 can be regions of the memory device capable of storing data.

[0089] Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described. Figure 5B A modification example of the semiconductor device 1 according to the example embodiment will be described.

[0090] In one embodiment, with reference to Figure 5B , the semiconductor device can further include a horizontal connection pattern 145 between the stack structure 115s and the substrate 3. For example, the horizontal connection pattern 145 can be between the lowermost first interlayer insulating layer 8 and the substrate 3.

[0091] The vertical structure 96' can penetrate the cover structures 42 and 58, the stack structure 115s, and the horizontal connection pattern 145, and can extend into the substrate 3.

[0092] The vertical structure 96' can include a first vertical structure 96a' at a position corresponding to the above-described first vertical structure 96a and a second vertical structure 96b' at a position corresponding to the above-described second vertical structure 96b. Figure 3 Figure 3 The first vertical structure 96a' can include the above-described first core pattern 82a, the pad pattern 93, and the first semiconductor layer 79a, and the second vertical structure 96b' can include the above-described second core pattern 82b and the second semiconductor layer 79b.

[0093] The first vertical structure 96a' can include the above-described first core pattern 82a, the pad pattern 93, and the first semiconductor layer 79a, and the second vertical structure 96b' can include the above-described second core pattern 82b and the second semiconductor layer 79b.

[0094] ​The first vertical structure 96a' can include a first dielectric structure 370a covering the outer side surface of the first semiconductor layer 79a and covering the lower surface of the first semiconductor layer 79a. The second vertical structure 96b' can include a second dielectric structure 370b covering the outer side surface of the second semiconductor layer 79b and covering the lower surface of the second semiconductor layer 79b.

[0095] The horizontal connection pattern 145 can include a first horizontal connection pattern 145a and a second horizontal connection pattern 145b on the first horizontal connection pattern 145a. The first horizontal connection pattern 145a can be formed of silicon. The second horizontal connection pattern 145b can be formed of silicon. The first horizontal connection pattern 145a and the second horizontal connection pattern 145b can be formed of doped polysilicon. In one embodiment, the first horizontal connection pattern 145a and the second horizontal connection pattern 145b can be formed of polysilicon having N-type conductivity. In one embodiment, at least one of the first horizontal connection pattern 145a and the second horizontal connection pattern 145b can include a metal (e.g., tungsten (W), etc.) or a metal nitride (e.g., tungsten nitride (WN), titanium nitride (TiN), etc.). The horizontal connection pattern 145 can be in contact with the substrate 3.

[0096] In a region adjacent to the first vertical structure 96a', the first horizontal connection pattern 145a can be in contact with the first semiconductor layer 79a, and the second horizontal connection pattern 145b can be spaced apart from the first semiconductor layer 79a.

[0097] In a region adjacent to the second vertical structure 96b', the first horizontal connection pattern 145a can be in contact with the second semiconductor layer 79b, and the second horizontal connection pattern 145b can be spaced apart from the second semiconductor layer 79b.

[0098] The first horizontal connection pattern 145a can include a portion 145e1 extending from a portion in contact with the first semiconductor layer 79a to a portion between the second horizontal connection pattern 145b and the first semiconductor layer 79a, and a portion 145e2 extending from a portion in contact with the first semiconductor layer 79a to a portion between the substrate 3 and the first semiconductor layer 79a. Similarly, the first horizontal connection pattern 145a can include a portion 145e1 extending from a portion in contact with the second semiconductor layer 79b to a portion between the second horizontal connection pattern 145b and the second semiconductor layer 79b, and a portion 145e2 extending from a portion in contact with the second semiconductor layer 79b to a portion between the substrate 3 and the second semiconductor layer 79b.

[0099] The lengths (e.g., in the vertical direction Z) of the respective portions 145e1 and 145e2 of the first horizontal connection pattern 145a can be smaller than the thickness (e.g., in the vertical direction Z) of the second horizontal connection pattern 145b.

[0100] Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figure 6 Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figure 6 A cross-sectional view of a region taken along Figure 1 a III-III' line is shown.

[0101] In one embodiment, with reference to Figure 6 , the substrate 3a can include a lower substrate 303, an upper substrate 309 on the lower substrate 303, and a peripheral circuit region 306 between the lower substrate 303 and the upper substrate 309. The lower substrate 303 can be a semiconductor substrate. The upper substrate 309 can include a semiconductor material and / or a conductive material.

[0102] The peripheral circuit region 306 can include a peripheral circuit pattern 306a and a peripheral insulating layer 306b covering the peripheral circuit pattern 306a.

[0103] In this modification example, the semiconductor device can include a horizontal connection pattern 145 and a vertical structure 96', which are substantially the same as described with reference to Figure 5B Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to

[0104] The partition structure 118 can be in contact with the horizontal connection pattern 145. In one embodiment, the partition structure 118 can penetrate the horizontal connection pattern 145, and can extend into the upper substrate 309 of the substrate 3a.

[0105] Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figure 1 and Figures 7A-13B Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figures 7A-13B Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figure 7A , 8A , 9A, 10A, 11A, 12A, and 13A are cross-sectional views of a region taken along Figure 1 a I-I' line, Figure 7B , 8B , 9B, 10B, 11B, 12B, and 13B are cross-sectional views of a region taken along Figure 1 a III-III' line and a IV-IV' line. Figures 7A-13B Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figure 1 , Figures 2A-2C and Figure 3 Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to

[0106] Hereinafter, a modification example of the semiconductor device 1 according to the example embodiment will be described with reference to Figure 1 , Figure 7A and Figure 7B A first mold structure 6 can be formed on a substrate 3. The substrate 3 can include a semiconductor substrate.

[0107] Forming the first mold structure 6 can include forming first interlayer insulating layers 8 and first preliminary gate layers 10 that are alternately and repeatedly stacked on the substrate 3, forming an intermediate interlayer insulating layer 12 on the uppermost first preliminary gate layer 10, and patterning the first interlayer insulating layers 8, the first preliminary gate layers 10, and the intermediate interlayer insulating layer 12 to form a stepped structure. The first interlayer insulating layers 8 can be formed of an insulating material such as silicon oxide.

[0108] In one embodiment, the first preliminary gate layers 10 can be formed of a material different from that of the first interlayer insulating layers 8, for example, silicon nitride.

[0109] In one embodiment, the first preliminary gate layers 10 can be formed of polysilicon.

[0110] An insulating material layer can be formed on the substrate 3 to cover the first mold structure 6. The insulating material layer can be planarized to form a second lower cover layer 15. An upper surface of the second lower cover layer 15 and an upper surface of the first mold structure 6 can be substantially coplanar with each other.

[0111] A lower hole 18 can be formed on the substrate 3. A portion of the lower hole 18 can penetrate the first mold structure 6, and a remaining portion of the lower hole 18 can penetrate the second lower cover layer 15 and the first mold structure 6.

[0112] In one embodiment, the lower hole 18 can expose the substrate 3. In one embodiment, the lower hole 18 can extend into the substrate 3.

[0113] A first annealing process 21 can be performed to outwardly expel gas (for example, hydrogen) in the first interlayer insulating layers 8 and the second lower cover layer 15 from the first interlayer insulating layers 8 and the second lower cover layer 15 and to remove the expelled gas. The gas in the first interlayer insulating layers 8 can be outwardly expelled through sidewalls of the lower hole 18, and the gas in the second lower cover layer 15 can be outwardly expelled through the sidewalls of the lower hole 18 and an upper surface of the second lower cover layer 15.

[0114] The first interlayer insulating layers 8 and the second lower cover layer 15 can be formed of silicon oxide, and the first annealing process 21 can be performed at a temperature of about 600 degrees Celsius or more.

[0115] Referring to Figure 1 , Figure 8A and Figure 8B , a lower gap fill pattern can be formed to fill the lower hole 18. The lower gap fill pattern can be formed of silicon.

[0116] A second mold structure 27 can be formed on the first mold structure 6 and the second lower cover layer 15. The second mold structure 27 can include second interlayer insulating layers 29 and second preliminary gate layers 31 that are alternately and repeatedly stacked.

[0117] The second interlayer insulating layer 29 can be formed of the same material as the first interlayer insulating layer 8, and the second preliminary gate layer 31 can be formed of the same material as the first preliminary gate layer 10.

[0118] The first lower cap layer 34 can be formed on the second mold structure 27.

[0119] The first lower cap layer 34 can be formed of silicon oxide.

[0120] An insulating pattern 37 can be formed to penetrate the first lower cap layer 34 and extend downward to penetrate the uppermost preliminary gate layer and the next uppermost preliminary gate layer among the second preliminary gate layers 31. The insulating pattern 37 can be formed of silicon oxide.

[0121] A plurality of layers can be formed on the first lower cap layer 34, and the plurality of layers and the first lower cap layer 34 can be patterned to form a first upper cap layer 40 on the first lower cap layer 34 and a mask pattern on the first upper cap layer. The mask pattern can include a first mask layer 47 and a second mask layer 49 sequentially stacked.

[0122] In one embodiment, the first mask layer 47 can include silicon nitride, and the second mask layer 49 can include silicon oxide.

[0123] In one embodiment, the first lower cap layer 34 and the first upper cap layer 40 can constitute a first cap pattern 42.

[0124] The second mold structure 27 can be patterned to form a stepped structure. The stepped structure of the second mold structure 27 can be formed on the first mold structure 6.

[0125] An insulating material layer can be formed on the substrate having the second mold structure 27, the first mask layer 47, and the second mask layer 49. The insulating material layer can be planarized downward to a top surface of the second mask layer 49 to form a second upper cap layer 56. The second upper cap layer 56 can cover the stepped structure of the second mold structure 27 and the second lower cap layer 15.

[0126] In one embodiment, the second lower cap layer 15 and the second upper cap layer 56 can constitute a second cap pattern 58.

[0127] In one embodiment, the first cap pattern 42 and the second cap pattern 58 can constitute cap structures 42 and 58.

[0128] An upper hole 61 can be formed to penetrate the second mask layer 49, the first mask layer 47, and the cap structures 42 and 58 and expose the lower gap fill pattern. The lower gap fill pattern exposed by the upper hole 61 can be removed.

[0129] The lower holes 18 and the upper holes 61 can constitute the holes 18 and 61.

[0130] The second annealing process 64 can be performed so that the gas in the first interlayer insulating layer 8, the second interlayer insulating layer 29, and the first cover pattern 42 is discharged outward through the side surfaces of the holes 18 and 61, and the gas in the second cover pattern 58 can be discharged outward through the side surfaces of the holes 18 and 61 and the upper surface of the second cover pattern 58.

[0131] The first interlayer insulating layer 8, the second interlayer insulating layer 29, the first cover pattern 42, and the second cover pattern 58 can be formed of silicon oxide. The second annealing process 64 can be performed at a temperature of, for example, 600 degrees Celsius or higher at which the gas such as hydrogen in the silicon oxide can be discharged.

[0132] Referring to Figure 1 , Figure 9A and Figure 9B , the preliminary vertical structures 67 can be formed in the holes 18 and 61.

[0133] In forming the preliminary vertical structures 67, a plurality of layers can be formed to fill the holes 18 and 61 and to cover the second mask layer 49, and the plurality of layers can be planarized to form the preliminary vertical structures 67 defined in the holes 18 and 61 while exposing the first mask layer 47.

[0134] Forming the preliminary vertical structures 67 can include forming dielectric structures 70a and 70b on the sidewalls of the holes 18 and 61, forming semiconductor layers 79a and 79b to cover the dielectric structures 70a and 70b in the holes 18 and 61 and to cover the lower surfaces of the holes 18 and 61, and forming core patterns 82a and 82b to fill other portions of the holes 18 and 61.

[0135] In one embodiment, the preliminary vertical structures 67 can include first preliminary vertical structures 67a and second preliminary vertical structures 67b. The first preliminary vertical structures 67a can penetrate the first cover pattern 42, the second mold structure 27, and the first mold structure 6. A plurality of the second preliminary vertical structures 67b can be provided. One portion of the second preliminary vertical structures 67b can penetrate the second upper cover layer 56, the second mold structure 27, and the first mold structure 6, and another portion of the second preliminary vertical structures 67b can penetrate the second upper cover layer 56, the second lower cover layer 15, and the first mold structure 6.

[0136] Referring to Figure 1 , Figure 10A and Figure 10B , a mask pattern 85 can be formed to cover the second preliminary vertical structures 67b in the preliminary vertical structures 67 and to expose the first preliminary vertical structures 67a. The mask pattern 85 can be a photoresist pattern.

[0137] A portion of the first core pattern 82a in the first pre-vertical structure 67a can be etched to form a recessed area 88. In one embodiment, the first core pattern 82a in the first pre-vertical structure 67a can be recessed from the upper surface of the first mask layer 47 to a position between the upper and lower surfaces of the first overlay pattern 42.

[0138] refer to Figure 1 , Figure 11A and Figure 11B It can remove the mask pattern. Figure 10A and Figure 10B (85).

[0139] A pad material layer 91 can be formed to fill the recessed area 88 in the first pre-constructed vertical structure 67a and cover the first mask layer 47 and the second upper cover layer 56. The pad material layer 91 can be formed of polysilicon.

[0140] refer to Figure 1 , Figure 12A and Figure 12B The pad pattern 93 can be formed in the recessed area 88 within the first pre-vertical structure 67a while planarizing the pad material layer 91. The pre-vertical structure 67 can be formed as a vertical structure 96 with reduced height.

[0141] The first pre-constructed vertical structure 67a can be formed as a first vertical structure 96a including a pad pattern 93. The first mask layer 47 can be removed while forming the pad pattern 93, and the second upper cover layer 56 of the second cover pattern 58 can be formed with its upper surface coplanar with the upper surface of the first cover pattern 42.

[0142] While forming the pad pattern 93, the second preliminary vertical structure 67b can be formed as a second vertical structure 96b. The upper surface of the second vertical structure 96b can be substantially coplanar with the upper surface of the first vertical structure 96a. In one embodiment, the first vertical structure 96a and the second vertical structure 96b can be formed with, as shown in the reference... Figure 3 The same structure as described above.

[0143] refer to Figure 1 , Figure 13A and Figure 13B A first upper insulating layer 102 can be formed on the covering structures 42 and 58. The first upper insulating layer 102 can contact the upper surface of the first vertical structure 96a and the upper surface of the second vertical structure 96b.

[0144] A dividing groove 105 can be formed to penetrate the first upper insulating layer 102, the covering structures 42 and 58, the first mold structure 6, and the second mold structure 27.

[0145] The separation trench 105 can expose the first preliminary gate layer 10 and the second preliminary gate layer 31.

[0146] Then, the first preliminary gate layer 10 and the second preliminary gate layer 31 can be removed, thereby forming spaces 108a and 108b to expose side surfaces of the vertical structures 96. The spaces 108a and 108b can include a first space 108a formed due to the removal of the first preliminary gate layer 10 and a second space 108b formed due to the removal of the second preliminary gate layer 31.

[0147] Returning Figure 1 , Figure 2A , Figure 2B and Figure 2C A first gate layer 112g1 can be formed to fill the first space 108a formed due to the removal of the first preliminary gate layer 10, and a second gate layer 112g2 can be formed to fill the second space 108b formed due to the removal of the second preliminary gate layer 31. The first gate layer 112g1 and the second gate layer 112g2 can be formed simultaneously.

[0148] A separation structure 118 can be formed to fill the separation trench 105. A second upper insulating layer 121 can be formed on the first upper insulating layer 102. A gate contact plug 124 can be formed to penetrate the second upper insulating layer 121, the first upper insulating layer 102, and the second overlay pattern 58 and to be electrically connected to a first gate pad region 112p1 of the first gate layer 112g1 and a second gate pad region 112p2 of the second gate layer 112g2.

[0149] A third upper insulating layer 127 can be formed on the second upper insulating layer 121.

[0150] A bit line contact plug 130 can be formed to penetrate the third upper insulating layer 127, the second upper insulating layer 121, and the first upper insulating layer 102 and to be electrically connected to the pad pattern 93. An upper contact plug 133 can be formed to penetrate the third upper insulating layer 127 and to be electrically connected to the gate contact plug 124. A bit line 136 can be formed on the third upper insulating layer 127 to be electrically connected to the bit line contact plug 130. A gate interconnection 139 can be formed on the third upper insulating layer 127 to be electrically connected to the upper contact plug 133.

[0151] As described above, example embodiments can provide a semiconductor device formation method that can expel gas in a material layer that can be formed of silicon oxide using an annealing process. This annealing process can be used to prevent semiconductor device defects that can otherwise be caused by gas in a material layer that can be formed of silicon oxide. Furthermore, this annealing process can help prevent or significantly reduce the occurrence of defects even when the thickness of the material layer that can be formed of silicon oxide is reduced. As a result, the integration density of the semiconductor device can be improved.

[0152] One or more embodiments can provide a semiconductor device and a formation method thereof that can improve integration density.

[0153] Example embodiments have been disclosed herein and, although a particular terminology is employed, such terminology is used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, attributes and / or benefits can be utilized in combinations other than the specific embodiments described, and other variations of these specific embodiments can be utilized, without departing from the spirit and scope of the present disclosure. It is, therefore, contemplated that the application in its broadest scope can be carried out other than as specifically described.

Claims

1. A semiconductor device comprising: a first vertical structure on a memory cell array region of a substrate; a second vertical structure on an extension region of the substrate adjacent to the memory cell array region; a stack structure including alternatingly repeating interlayer insulating layers and gate layers stacked on the substrate; an upper insulating layer on the stack structure; a bit line on the upper insulating layer, wherein the bit line vertically overlaps the first vertical structure and does not vertically overlap the second vertical structure; and a contact plug penetrating the upper insulating layer and electrically connected to a pad pattern and the bit line, wherein: the gate layers are sequentially stacked in the memory cell array region and extend into the extension region, the gate layers have a pad region arranged to have a stepped structure in the extension region, a side surface of the first vertical structure faces the gate layers in the memory cell array region, a side surface of the second vertical structure faces at least one of the gate layers in the extension region, the first vertical structure includes a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and the pad pattern on an upper surface of the first core pattern, the second vertical structure includes a second core pattern and a second semiconductor layer on a side surface of the second core pattern, the first core pattern and the second core pattern each include an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern is from the substrate, wherein the semiconductor device further comprises: a horizontal connection pattern between the stack structure and the substrate; and a partition structure penetrating the stack structure, wherein: the horizontal connection pattern is spaced apart from a lowermost one of the gate layers, the horizontal connection pattern is in contact with the first semiconductor layer of the first vertical structure; the substrate includes a lower substrate, an upper substrate on the lower substrate, and a peripheral circuit region between the lower substrate and the upper substrate, the horizontal connection pattern is between the upper substrate and the stack structure, a portion of the partition structure is in contact with the horizontal connection pattern, and an upper surface of the partition structure is at a higher level than upper surfaces of the first vertical structure and the second vertical structure.

2. The semiconductor device of claim 1, wherein, The upper insulating layer covers an entire upper surface of the second vertical structure.

3. The semiconductor device of claim 2, wherein: a width of the contact plug is smaller than a width of an upper surface of the first vertical structure, and the upper insulating layer covers a portion of the upper surface of the first vertical structure.

4. The semiconductor device of claim 1, wherein, The upper surface of the second semiconductor layer and the upper surface of the second core pattern are coplanar with each other.

5. The semiconductor device of claim 1, wherein, An upper surface of the pad pattern is coplanar with the upper surface of the second core pattern.

6. The semiconductor device of claim 1, wherein: the first semiconductor layer extends to a side surface of the pad pattern, and an upper surface of the first semiconductor layer is coplanar with an upper surface of the pad pattern.

7. The semiconductor device of claim 1, wherein, A width of the pad pattern is greater than a width of the first core pattern.

8. The semiconductor device of claim 1, wherein, A width of the pad pattern is greater than a width of the second core pattern.

9. The semiconductor device of claim 1, wherein: The first semiconductor layer includes: a first portion covering a side surface of the first core pattern; and a second portion covering a side surface of the pad pattern, and a thickness of the second portion of the first semiconductor layer is less than a thickness of the first portion of the first semiconductor layer.

10. The semiconductor device of claim 9, wherein, A thickness of the second portion of the first semiconductor layer is less than a thickness of the second semiconductor layer at a same height as the second portion of the first semiconductor layer.

11. A semiconductor device, comprising: a stack structure on a substrate, the stack structure including a plurality of gate layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a cover structure on the stack structure; an upper insulating layer on the cover structure; a first vertical structure penetrating a first region of the stack structure and extending into the cover structure; a second vertical structure penetrating a second region of the stack structure and extending into the cover structure, the second region of the stack structure being adjacent to the first region of the stack structure; a bit line on the upper insulating layer, wherein the bit line vertically overlaps the first vertical structure and does not vertically overlap the second vertical structure; and a contact plug penetrating the upper insulating layer, wherein: the first vertical structure includes a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and a pad pattern on an upper surface of the first core pattern, the second vertical structure includes a second core pattern and a second semiconductor layer on a side surface of the second core pattern, the upper insulating layer is in contact with the second semiconductor layer and the second core pattern, the contact plug is electrically connected to the pad pattern and the bit line, and wherein an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern is from the substrate, wherein the semiconductor device further comprises: a horizontal connection pattern between the stack structure and the substrate; and a separation structure penetrating the stack structure, wherein: the stack structure further includes a plurality of interlayer insulating layers, the plurality of interlayer insulating layers and the plurality of gate layers are alternately and repeatedly stacked, the horizontal connection pattern is spaced apart from a lowermost gate layer of the plurality of gate layers, the horizontal connection pattern is in contact with the first semiconductor layer of the first vertical structure; the substrate includes a lower substrate, an upper substrate on the lower substrate, and a peripheral circuit region between the lower substrate and the upper substrate, the horizontal connection pattern is between the upper substrate and the stack structure, a portion of the separation structure is in contact with the horizontal connection pattern, and an upper surface of the separation structure is at a higher height than upper surfaces of the first vertical structure and the second vertical structure.

12. The semiconductor device of claim 11, wherein: the plurality of gate layers are sequentially stacked in the vertical direction in the first region of the stack structure, and the second region of the stack structure is adjacent to the first region of the stack structure. The plurality of gate layers have gate pad regions extending from the first region of the stack structure to the second region of the stack structure to have a staircase structure in the second region of the stack structure.

13. The semiconductor device of claim 11, wherein: The first vertical structure further includes a first dielectric structure, The second vertical structure further includes a second dielectric structure, At least a portion of the first semiconductor layer is between the first dielectric structure and the first core pattern, and At least a portion of the second semiconductor layer is between the second dielectric structure and the second core pattern.

14. The semiconductor device of claim 13, wherein, The first and second dielectric structures each include a first gate dielectric layer, a second gate dielectric layer, and a data storage layer between the first and second gate dielectric layers.

15. The semiconductor device of claim 13, wherein, The first and second dielectric structures each include a first gate dielectric layer, a second gate dielectric layer, and a data storage pattern between the first and second gate dielectric layers, and The data storage patterns are spaced apart from each other in the vertical direction.

16. The semiconductor device of claim 11, wherein: The first vertical structure includes a first lower vertical structure and a first upper vertical structure on the first lower vertical structure, The second vertical structure includes a second lower vertical structure and a second upper vertical structure on the second lower vertical structure, A width of an upper region of the first lower vertical structure adjacent to the first upper vertical structure is greater than a width of a lower region of the first upper vertical structure adjacent to the first lower vertical structure, and A width of an upper region of the second lower vertical structure adjacent to the second upper vertical structure is greater than a width of a lower region of the second upper vertical structure adjacent to the second lower vertical structure.

17. A semiconductor device, comprising: a stack structure on a substrate, the stack structure including a stack region and a staircase region adjacent to the stack region; a cap structure on the stack structure; a first vertical structure penetrating the stack region of the stack structure and extending into the cap structure; a second vertical structure penetrating the staircase region of the stack structure and extending into the cap structure; an upper insulating layer on the cap structure, the first vertical structure, and the second vertical structure; a bit line on the upper insulating layer, wherein the bit line vertically overlaps the first vertical structure and does not vertically overlap the second vertical structure; and a bit line contact plug penetrating the upper insulating layer and electrically connected to the first vertical structure and the bit line, wherein: The first vertical structure includes a first core pattern, a first semiconductor layer on a side surface of the first core pattern, and a pad pattern on an upper surface of the first core pattern, The pad pattern is in contact with the bit line contact plug, The second vertical structure includes a second core pattern and a second semiconductor layer on a side surface of the second core pattern, The first and second core patterns each include an insulating material, and The first and second core patterns each include an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern is from the substrate, wherein the semiconductor device further comprises: a horizontal connection pattern between the stack structure and the substrate; and a separation structure that penetrates the stack structure, the substrate comprises a lower substrate, an upper substrate on the lower substrate, and a peripheral circuit region between the lower substrate and the upper substrate, the horizontal connection pattern is between the upper substrate and the stack structure, a portion of the separation structure is in contact with the horizontal connection pattern, the first vertical structure and the second vertical structure each extend downward, penetrating the stack structure, to penetrate the horizontal connection pattern, the first semiconductor layer and the second semiconductor layer are each in contact with the horizontal connection pattern, and an upper surface of the separation structure is at a higher level than upper surfaces of the first vertical structure and the second vertical structure.

18. The semiconductor device of claim 17, further comprising: a first gate contact plug; and a second gate contact plug, wherein: the first vertical structure further comprises a first dielectric structure, the second vertical structure further comprises a second dielectric structure, at least a portion of the first semiconductor layer is between the first dielectric structure and the first core pattern, at least a portion of the second semiconductor layer is between the second dielectric structure and the second core pattern, the stack structure comprises a first stack group and a second stack group on the first stack group, the first stack group comprises a plurality of interlayer insulating layers and a plurality of first gate layers that are alternately and repeatedly stacked, the plurality of first gate layers comprises, in the staircase region, a first gate pad region having a staircase structure, the first gate contact plug is in contact with the first gate pad region and extends upward to penetrate the cap structure, the second stack group comprises a plurality of interlayer insulating layers and a plurality of second gate layers that are alternately and repeatedly stacked, the plurality of second gate layers comprises, in the staircase region, a second gate pad region having a staircase structure, the second gate contact plug is in contact with the second gate pad region and extends upward to penetrate the cap structure; the first vertical structure comprises a first lower vertical structure and a first upper vertical structure on the first lower vertical structure, the second vertical structure comprises a second lower vertical structure and a second upper vertical structure on the second lower vertical structure, an upper surface of the second lower vertical structure is at a same level as an upper surface of the first lower vertical structure, the first lower vertical structure penetrates the first stack group of the stack region of the stack structure, the first upper vertical structure penetrates the second stack group of the stack region of the stack structure and extends into the cap structure, a width of an upper region of the first lower vertical structure is greater than a width of a lower region of the first upper vertical structure, the upper region of the first lower vertical structure is adjacent to the lower region of the first upper vertical structure, a width of an upper region of the second lower vertical structure is greater than a width of a lower region of the second upper vertical structure, and The upper region of the second lower vertical structure is adjacent to the lower region of the second upper vertical structure.

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