Magnetoresistive random access memory device and its manufacturing method

Abstract

A magnetoresistive random access memory (MRAM) device and a method for manufacturing the same are provided. The device includes: a substrate; a memory cell including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern located on a sidewall of the memory cell; a via located on the memory cell and in contact with the upper electrode; and wiring located on the via and in contact with the via, wherein a central portion of the upper electrode protrudes from the remainder of the upper electrode in a vertical direction substantially perpendicular to the upper surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2019-0080642, filed on July 4, 2019 with the Korean Intellectual Property Office and entitled “Magnetoresistive Random Access Device and Method of Manufacturing the Same”, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a magnetoresistive random access memory (MRAM) device and a method of manufacturing the same. Background Technology

[0004] In a method for manufacturing an MRAM device, after forming an upper electrode on a lower electrode layer and a magnetic tunnel junction (MTJ) structure layer sequentially stacked on a substrate, an ion beam etching (IBE) process using the upper electrode as an etching mask can be performed on the lower electrode layer and the MTJ structure layer in a diagonal direction (e.g., not perpendicular to the upper surface of the substrate) to form the lower electrode and the MTJ structure. Summary of the Invention

[0005] An embodiment can be implemented by providing a magnetoresistive random access memory (MRAM) device, the MRAM device comprising: a substrate; a memory cell including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern located on a sidewall of the memory cell; a via located on the memory cell and in contact with the upper electrode; and wiring located on the via and in contact with the via, wherein a central portion of the upper electrode protrudes from the remainder of the upper electrode in a vertical direction substantially perpendicular to the upper surface of the substrate.

[0006] An embodiment can be implemented by providing a magnetoresistive random access memory (MRAM) device, the MRAM device comprising: a substrate; a memory cell including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern located on a sidewall of the memory cell; a via located on the memory cell and contacting each of the upper electrode and the passivation pattern; and wiring located on the via and electrically connected to the via, wherein the upper electrode includes a first portion, a second portion, and a third portion sequentially stacked and integrally formed, and the width of the second portion of the upper electrode decreases by an amount greater than the width of the first portion of the upper electrode and the width of the third portion of the upper electrode decreases by the same amount along the vertical direction substantially perpendicular to the upper surface of the substrate.

[0007] An embodiment can be implemented by providing a magnetoresistive random access memory (MRAM) device, the MRAM device comprising: a substrate; a memory cell including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern located on a sidewall of the memory cell; a via located on the memory cell and in contact with the upper electrode; and wiring located on the via and electrically connected to the via, wherein the upper electrode includes: a first portion having a sidewall with a constant slope; a second portion having a sidewall with a varying slope; and a third portion projecting from the second portion in a vertical direction substantially perpendicular to the upper surface of the substrate, and the lower surface of the via having a concave shape in the vertical direction at a portion in contact with the third portion of the upper electrode.

[0008] An embodiment can be implemented by providing a method for manufacturing a magnetoresistive random access memory (MRAM) device, the method comprising: sequentially forming a lower electrode layer, a magnetic tunnel junction (MTJ) structure layer, and an upper electrode layer on a substrate; forming a mask on the upper electrode layer; performing a first etching process on the upper electrode layer using the mask to form a preliminary upper electrode; performing a second etching process on the mask remaining on the preliminary upper electrode to reduce the width of the mask; and performing a third etching process using the remaining mask having the reduced width to partially remove the upper portion of the preliminary upper electrode to form the upper electrode.

[0009] An embodiment can be implemented by providing a method for manufacturing a magnetoresistive random access memory (MRAM) device, the method comprising: sequentially forming a lower electrode layer, a magnetic tunnel junction (MTJ) structure layer, and an upper electrode layer on a substrate; forming a sacrificial pattern on the upper electrode layer such that the sacrificial pattern includes an opening; forming a mask filling the opening, and then removing the sacrificial pattern; etching the upper electrode layer using the mask to form an upper electrode; etching the mask remaining on the upper electrode to reduce the width of the mask; partially removing the upper portion of the upper electrode using the mask with the reduced width; etching the lower electrode layer and the MTJ structure layer using the upper electrode with the partially removed upper portion as an etching mask to form the lower electrode and the MTJ structure; forming a via contacting the upper surface of the upper electrode; and forming wiring contacting the via. Attached Figure Description

[0010] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figures 1 to 10 Cross-sectional views of various stages in a method for manufacturing an MRAM device according to an example embodiment are shown.

[0012] Figures 11 to 15 A cross-sectional view of an MRAM device according to an example embodiment is shown. Detailed Implementation

[0013] Figures 1 to 10 Cross-sectional views of various stages in a method for manufacturing an MRAM device according to an example embodiment are shown.

[0014] Reference Figure 1 A first insulating intermediate layer 110 may be formed on the substrate 100, and a contact plug 120 may be formed to extend through the first insulating intermediate layer 110 and contact the upper surface of the substrate 100.

[0015] Substrate 100 may include semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, or GaSb. In an example embodiment, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0016] In one embodiment, various structures such as word lines, transistors, diodes, source / drain layers, contact plugs, vias, wiring, etc., can be formed on the substrate 100.

[0017] A first insulating interlayer 110 may be formed on the substrate 100 to cover various structures. The first insulating interlayer 110 may include an oxide such as silicon oxide.

[0018] The contact plug 120 can be formed by forming a first opening extending through the first insulating interlayer 110 and exposing the upper surface of the substrate 100, forming a conductive layer on the substrate 100 and the first insulating interlayer 110 to fill the first opening, and planarizing the upper portion of the conductive layer until the upper surface of the first insulating interlayer 110 can be exposed. The conductive layer may include a metal (e.g., tungsten, titanium, tantalum, etc.), a metal nitride (e.g., tungsten nitride, titanium nitride, or tantalum nitride), or polycrystalline silicon doped with impurities.

[0019] Subsequently, a lower electrode layer 130, a magnetic tunnel junction (MTJ) structure layer 170, an upper electrode layer 180, an etch stop layer 190, a sacrificial layer 200, and a first mask layer 210 can be sequentially formed on the first insulating intermediate layer and the contact plug 120. In one embodiment, the MTJ structure layer 170 may include a fixed layer 140, a tunnel barrier layer 150, and a free layer 160.

[0020] The lower electrode layer 130 and the upper electrode layer 180 may include metal or metal nitride.

[0021] In one embodiment, a barrier layer may be further formed on the lower electrode layer 130 to help reduce or prevent abnormal growth of the metal included in the fixing layer 140. The barrier layer may include an amorphous metal or a metal nitride, such as tantalum, tantalum nitride, titanium, titanium nitride, etc.

[0022] In one embodiment, the fixing layer 140 may include a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, and an upper ferromagnetic layer.

[0023] The fixed layer 140 may include, for example, FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2, FeF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, or Cr. The lower and upper ferromagnetic layers may include, for example, Fe, Ni, or Co. The antiferromagnetic coupling spacer layer may include, for example, Ru, Ir, or Rh.

[0024] The tunnel barrier layer 150 may include, for example, aluminum oxide or magnesium oxide, and the free layer 160 may include, for example, Fe, Ni or Co.

[0025] The etch stop layer 190 may include a nitride such as silicon nitride, and the sacrificial layer 200 may include, for example, a spin-on hard mask (SOH), and the first mask layer 210 may include an oxide such as silicon oxide.

[0026] Reference Figure 2After forming the first mask 215 by performing a photolithography process using a photoresist pattern on the first mask layer 210, a first etching process using the first mask 215 as an etching mask can be performed to etch the sacrificial layer below the first mask 215, and a sacrificial pattern 205 (including a second opening 220 that partially exposes the upper surface of the etch stop layer 190) can be formed.

[0027] In one embodiment, the upper surface of the etch stop layer 190 exposed by the second opening 220 may also be partially etched, but the upper electrode layer 180 may not be etched because the upper electrode layer 180 is protected by the etch stop layer 190.

[0028] The first mask 215 retained on the sacrificial pattern 205 after the first etching process can be removed.

[0029] Reference Figure 3 After forming a second mask layer on the exposed upper surface of the etch stop layer 190 and the sacrificial pattern 205 to fully fill the second opening 220, the second mask layer can be planarized until the upper surface of the sacrificial pattern 205 is exposed to form the second mask 230, and the sacrificial pattern 205 can be removed after the planarization process. For example, the remaining portion of the upper surface of the etch stop layer 190 can be exposed (e.g., except for the portion on which the second mask 230 is formed or covered).

[0030] In one embodiment, a plurality of second masks 230 may be formed along a horizontal direction substantially parallel to the upper surface of the substrate 100, and each second mask 230 may have a columnar shape extending in a vertical direction substantially perpendicular to the upper surface of the substrate 100.

[0031] In one embodiment, the second mask 230 may have a flat upper surface. In another embodiment, the second mask 230 may also have an upper surface with a concave or convex central portion.

[0032] In one implementation, the planarization process can be performed using a chemical mechanical polishing process or an etch-back process.

[0033] Reference Figure 4 The etch stop layer 190 and the upper electrode layer 180 can be sequentially patterned by using a second etch process with the second mask 230 as the etch mask, and a sequentially stacked initial upper electrode 185 and etch stop pattern 195 can be formed on the MTJ structure layer 170.

[0034] The second etching process may include a dry etching process and may be performed until the upper surface of the MTJ structure layer 170 is exposed.

[0035] Reference Figure 5After forming the second insulating intermediate layer 240 to cover the sidewalls of the initial upper electrode 185, the sidewalls of the etch stop pattern 195, and the sidewalls and upper surface of the second mask 230, the upper portion of the second insulating intermediate layer 240 can be removed until the sidewalls of the etch stop pattern 195 are exposed. For example, the sidewalls and upper surface of the second mask 230 can be exposed. The upper portion of the second insulating intermediate layer 240 can be removed by, for example, a CMP process and / or an etch-back process.

[0036] In one implementation, such as Figure 5 As shown, when the upper portion of the second insulating intermediate layer 240 is removed, all portions of the sidewalls of the etch stop pattern 195 can be exposed. In one embodiment, only the upper portion of the sidewalls of the etch stop pattern 195 can be exposed, and the lower portion of the sidewalls of the etch stop pattern 195 can be left unexposed.

[0037] Reference Figure 6 A third etching process can be performed to partially remove the exposed sidewalls of the second mask 230 and reduce the width of the second mask 230.

[0038] The third etching process may include wet etching.

[0039] The etch stop pattern 195 can also be partially removed, and the initial upper electrode 185 can still be protected by the etch stop pattern 195 (e.g., the remainder of the etch stop pattern 195).

[0040] In one embodiment, the reduced width of the second mask 230 may be smaller than the width of the initial upper electrode 185 (e.g., as measured in a horizontal direction parallel to the top surface of the substrate 100). In one embodiment, the etch stop pattern 195 may have a width that increases from its top side or upper surface (e.g., away from the substrate 100) toward its bottom side or lower surface (e.g., close to the substrate 100). In one embodiment, the upper surface of the etch stop pattern 195 may have substantially the same width as the lower surface of the second mask 230 (e.g., a reduced width), and the lower surface of the etch stop pattern 195 may have substantially the same width as the upper surface of the initial upper electrode 185. For example, the etch stop pattern 195 may have a trapezoidal cross-sectional shape.

[0041] In one embodiment, the second mask 230 with a reduced width may have sidewalls substantially perpendicular to or perpendicular to the upper surface of the substrate 100, and may have a flat upper surface. In another embodiment, the second mask 230 with a reduced width may have sidewalls not perpendicular to the upper surface of the substrate 100, or may have a concave or convex upper surface.

[0042] Reference Figure 7A fourth etching process can be performed using a second mask 230 (with a reduced width) as an etching mask to remove the etching stop pattern 195 and partially remove the upper part of the initial upper electrode 185, thereby forming the upper electrode 187.

[0043] A fourth etching process can be performed to partially remove the upper edge region of the initial upper electrode 185 without removing the lower part of the initial upper electrode 185. For example, the upper electrode 187 formed by partially removing the initial upper electrode 187 can have a shape in which its central portion protrudes vertically from the rest.

[0044] In one embodiment, the central portion of the upper electrode 187 with a protruding shape may have sidewalls substantially perpendicular to the upper surface of the substrate 100, and may have a flat upper surface. In another embodiment, the central portion of the upper electrode 187 with a protruding shape may have sidewalls that are not perpendicular to but inclined relative to the upper surface of the substrate 100, and may also have a concave or convex upper surface.

[0045] The fourth etching process may include dry etching.

[0046] Reference Figure 8 The free layer 160, tunnel barrier layer 150, fixed layer 140, and lower electrode layer 130 can be sequentially patterned using a fifth etching process that uses the upper electrode 187 as an etching mask to form a memory cell comprising a lower electrode 135, a fixed layer pattern 145, a tunnel barrier pattern 155, a free layer pattern 165, and an upper electrode 187 sequentially stacked on the contact plug 120. The fixed layer pattern 145, tunnel barrier pattern 155, and free layer pattern 165 can form an MTJ structure 175.

[0047] The fifth etching process may include a dry etching process, such as an ion beam etching (IBE) process. The IBE process may be performed multiple times in a diagonal direction (e.g., not perpendicular to the upper surface of the substrate 100), and the IBE process may be performed using an etching gas including fluorine-containing gas and ammonia (NH3) gas, as well as oxygen to suppress the consumption of the upper electrode 187 as a reactive gas.

[0048] In one embodiment, the dry etching process can be performed, for example, by a triple IBE process, and the triple IBE process can be performed at angles of 65°, 35° and 35° relative to the upper surface of the substrate 100, respectively.

[0049] When performing a dry etching process, the upper part of the first insulating intermediate layer 110 can also be partially removed, and the first insulating intermediate layer 110 can have a concave upper surface.

[0050] The upper electrode 187 may include a lower portion 187a, a central or intermediate portion 187b, and a protruding portion 187c, which are integrally formed and sequentially stacked along a vertical direction. For example, the upper electrode 187 may have an integral shape in which the central portion protrudes from or relative to the remaining portions in a vertical direction. The lower portion 187a, the intermediate portion 187b, and the protruding portion 187c of the upper electrode 187 may be referred to as the first portion 187a, the second portion 187b, and the third portion 187c of the upper electrode 187, respectively.

[0051] In one embodiment, the sidewall of the lower portion 187a of the upper electrode 187 may have a constant slope (e.g., it may be flat), the sidewall of the middle portion 187b of the upper electrode 187 may have a slope that gradually decreases towards the top (e.g., away from the substrate 100, such that the sidewall of the middle portion 187b may be curved), and the sidewall of the protruding portion 187c of the upper electrode 187 may have a slope greater than that of the sidewall of the adjacent middle portion 187b. In one embodiment, the sidewall of the protruding portion 187c of the upper electrode 187 may have a constant slope (e.g., it may be flat), and at least a portion (e.g., the lower portion) of the sidewall of the protruding portion 187c of the upper electrode 187 (e.g., near the substrate 100) may be substantially perpendicular to the upper surface of the substrate 100.

[0052] In one embodiment, the lower portion 187a of the upper electrode 187 may have a width that gradually decreases toward the top (e.g., in the direction away from the substrate 100), such that the lower portion 187a may have a slightly tapered shape; the middle portion 187b of the upper electrode 187 may have a width that decreases sharply in the direction away from the substrate 100, such that the middle portion 187b may have a rounded corner shape; and the protruding portion 187c of the upper electrode 187 may have a width that decreases in the direction away from the substrate 100. In one embodiment, the protruding portion 187c of the upper electrode 187 may have a constant width in the direction away from the substrate 100.

[0053] In one embodiment, at least the central region of the upper surface of the protrusion 187c of the upper electrode 187 may be flat, and the edge region of its upper surface may be rounded.

[0054] The lower portion 187a, the middle portion 187b, and the protruding portion 187c of the upper electrode 187 can have different thicknesses in the vertical direction. For example, the lower portion 187a can have the largest thickness, the middle portion 187b can have the smallest thickness, and the protruding portion 187c can have a thickness smaller than that of the lower portion 187a and larger than that of the middle portion 187b.

[0055] As described above, even if the upper electrode 187 is formed to have a large thickness (e.g., in the vertical direction), the upper portion of the upper electrode 187 (e.g., the protruding portion 187c of the upper electrode 187) can have a reduced width, so that ions implanted by the IBE process are not blocked by the upper electrode 187. For example, the lower electrode layer 130 and the MTJ structure layer 170 can be effectively patterned without being affected by the adjacent upper electrode 187.

[0056] The lower part 187a, the middle part 187b, and the protruding part 187c of the upper electrode 187 can have various thicknesses, which will be described below.

[0057] In one implementation, such as Figure 8 As shown, the lower surface of the memory cell can have a larger area than the upper surface of the contact plug 120. In one embodiment, the lower surface of the memory cell can have a substantially the same area as the upper surface of the contact plug 120. In one embodiment, conductive pads can be further formed between the contact plug 120 and the memory cell.

[0058] Reference Figure 9 A passivation layer 250 can be formed on the first insulating intermediate layer 110 to cover the memory cell, and a third insulating intermediate layer 260 can be formed on the passivation layer 250.

[0059] Each of the passivation layer 250 and the third insulating intermediate layer 260 can be formed by, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), etc.

[0060] The passivation layer 250 may include a nitride such as silicon nitride, and the third insulating intermediate layer 260 may include an oxide such as silicon oxide.

[0061] Reference Figure 10 After forming a trench 267 extending through the upper portion of the third insulating intermediate layer 260 and a via 265 connected thereto and exposing a portion of the passivation layer 250, the exposed portion of the passivation layer 250 can be removed to expose the upper electrode 187, and vias 270 and wirings 280 can be formed to fill the via 265 and trench 267, respectively. The vias 270 and wirings 280 can be stacked sequentially and can together form a wiring structure 290.

[0062] In one embodiment, trench 267 can be formed by performing a dry etching process using a first etching mask to remove the upper portion of the third insulating intermediate layer 260. Via 265, connected to trench 267 and exposing a portion of the passivation layer 250 on the memory cell, can be formed by performing a dry etching process using a second etching mask. The exposed portion of the passivation layer 250 can be removed by performing a wet etching process. In another embodiment, the exposed portion of the passivation layer 250 can also be removed by performing a dry etching process. For example, the passivation layer 250 can be transformed into a passivation pattern 255.

[0063] A barrier layer can be formed on the upper surface of the exposed upper electrode 187, the upper surface of the passivation pattern 255, the sidewall of the via 265, the lower surface and sidewall of the trench 267, and the upper surface of the third insulating intermediate layer 260. A metal layer can be formed on the barrier layer to fill the via 265 and the trench 267. The metal layer and the barrier layer can be planarized until the upper surface of the third insulating intermediate layer 260 can be exposed to form a passage 270 and wiring 280, both of which include the barrier pattern and the metal pattern.

[0064] In one implementation, each planarization process can be performed using CMP and / or etch-back processes.

[0065] The barrier layer may include metal nitrides such as tantalum nitride and titanium nitride, or metals such as tantalum and titanium, and the metal layer may include metals such as tungsten, copper, and aluminum.

[0066] The passage 270 can at least contact the middle portion 187b and the protruding portion 187c of the upper electrode 187, and can also contact the uppermost surface of the passivation pattern 255 adjacent to the lower portion 187a of the upper electrode 187. In one embodiment, the lower surface of the passage 270 can have an uneven shape, in which the central region is concave in the vertical direction and the edge regions are convex in the vertical direction. In one embodiment, the lowermost surface of the passage 270 can be at a height higher than or equal to the upper end of the lower portion 187a of the upper electrode 187.

[0067] In one embodiment, the sidewalls of the passage 270 may have varying slopes, for example, they may not be perpendicular to the upper surface of the substrate 100, and the width of the passage 270 may decrease as it approaches the uppermost surface of the passivation pattern 255 (e.g., toward the substrate 100).

[0068] The MRAM device can be manufactured by performing the above-described process. In one embodiment, the MRAM device may include multiple memory cells, and the wiring structure 290 may be configured to connect to the multiple memory cells. In this case, the wiring structure 290 can be used as a bit line of the MRAM device.

[0069] As described above, even if the upper electrode 187 is formed with a large thickness (e.g., in the vertical direction), the lower electrode 135 and the MTJ structure 175 can still be formed effectively, and sufficient distance can be ensured between the memory cell and the wiring structure 290 in the vertical direction. For example, the electrical short circuit and magnetic field immunity of the memory cell and the wiring structure 290 can be minimized, and the electrical characteristics of the MRAM device can be improved.

[0070] Figures 11 to 15 A cross-sectional view of an MRAM device according to an example embodiment is shown. Except for the shape of the upper electrode 187 and the shape of the passage 270 thereon, these MRAM devices are similar to... Figure 10 The MRAM devices described herein are substantially the same or similar. Therefore, the same reference numerals refer to the same elements, and their repeated detailed descriptions may be omitted here.

[0071] Reference Figure 11 The protruding portion 187c of the upper electrode 187 may have a sidewall substantially perpendicular to the upper surface of the substrate 100, and may have a generally flat upper surface. The middle portion 187b of the upper electrode 187 may also have a sidewall substantially perpendicular to the upper surface of the substrate 100, and may have a generally flat upper surface.

[0072] In one embodiment, the width of the upper electrode 187 can decrease progressively upwards from the lower portion 187a and the middle portion 187b. In another embodiment, the width of the upper electrode 187 can decrease rapidly towards the lower surface of the protrusion 187c (e.g., the width of the protrusion 187c can decrease discontinuously, in a stepped manner relative to the widths of the lower portion 187a and the middle portion 187b). For example, the vertical reduction in the width of the middle portion 187b of the upper electrode 187 can be greater than the vertical reduction in the width of the lower portion 187a and the protrusion 187c of the upper electrode 187. The upper electrode 187 can have a relatively constant width vertically from the protrusion 187c to the top.

[0073] Reference Figure 10 and Figure 11 The upper electrode 187 may have a maximum thickness T1 at the lower portion 187a and a minimum thickness T2 at the middle portion 187b. The protruding portion 187c of the upper electrode 187 may have a thickness T3 that is less than the thickness T1 of the lower portion 187a and greater than the thickness T2 of the middle portion 187b.

[0074] Reference Figure 12The upper electrode 187 may have a maximum thickness T1 at the lower portion 187a and a minimum thickness T3 at the protruding portion 187c. The middle portion 187b of the upper electrode 187 may have a thickness T2 that is less than the thickness T1 of the lower portion 187a and greater than the thickness T3 of the protruding portion 187c.

[0075] Additionally, refer to Figures 10 to 12 The thickness T1 of the lower part 187a of the upper electrode 187 can be less than the sum of the thickness T2 of the middle part 187b and the thickness T3 of the protruding part 187c.

[0076] In one embodiment, the passage 270 may contact each of the protrusion 187c and the intermediate portion 187b of the upper electrode 187, but may not contact the lower portion 187a of the upper electrode 187.

[0077] Reference Figure 13 The upper electrode 187 may have a maximum thickness T3 at the protruding portion 187c and a minimum thickness T1 at the lower portion 187a. The middle portion 187b of the upper electrode 187 may have a thickness T2 that is less than the thickness T3 of the protruding portion 187c and greater than the thickness T1 of the lower portion 187a.

[0078] In one embodiment, the passage 270 may contact each of the protrusion 187c and the intermediate portion 187b of the upper electrode 187, but may not contact the lower portion 187a of the upper electrode 187, and may also not contact a portion of the sidewall of the intermediate portion 187b.

[0079] Reference Figure 14 The passage 270 may only contact the protruding portion 187c of the upper electrode 187, and may not contact the middle portion 187b or the lower portion 187a of the upper electrode 187.

[0080] Reference Figure 15 The passage 270 can contact the protruding portion 187c, the middle portion 187b, and a portion of the lower portion 187a of the upper electrode 187. In one embodiment, the passage 270 may not cover all portions of the sidewall of the lower portion 187a of the upper electrode 187.

[0081] Reference Figure 14 and Figure 15 The upper electrode 187 may have a maximum thickness T1 at the lower portion 187a and a minimum thickness T2 at the middle portion 187b. The protruding portion 187c of the upper electrode 187 may have a thickness T3 that is less than the thickness T1 of the lower portion 187a and greater than the thickness T2 of the middle portion 187b.

[0082] By summarizing and reviewing, it can be found that increasing the thickness of the top electrode can help improve the electrical properties of the MRAM device. Ions implanted diagonally via subsequent IBE processes may be blocked by the increased thickness of the top electrode. For example, other top electrodes adjacent to the top electrode, as well as the lower electrode layer and MTJ structure layer below each of these other top electrodes, may not be properly patterned.

[0083] One or more embodiments may provide an MRAM device with improved characteristics.

[0084] An MRAM device according to an example embodiment may include a lower electrode layer, an MTJ structure, and an upper electrode sequentially stacked on a substrate, the upper electrode having a shape such that a central portion protrudes further than an edge portion in a vertical direction perpendicular to the upper surface of the substrate.

[0085] For example, even if the upper electrode has a relatively large thickness, at least the central portion of the upper electrode can have a reduced width compared to the edge portion of the upper electrode, so that ions implanted by the subsequent IBE process can not be blocked by the upper electrode and other upper electrodes adjacent to it, and the lower electrode layer and MTJ structure layer below each other upper electrode can be effectively patterned.

[0086] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art that, at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A magnetoresistive random access memory device, comprising: Substrate; A storage cell comprising a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked on a substrate, the upper electrode comprising a lower portion, a middle portion, and a protruding portion sequentially stacked in a direction substantially perpendicular to the upper surface of the substrate; Passivation pattern, the passivation pattern being located on the sidewall of the storage cell; A pathway, the pathway being located on the storage cell and in contact with the upper electrode; and The wiring is located on and in contact with the path. The central portion of the upper electrode protrudes from the rest of the upper electrode in the vertical direction. The thickness of the protruding portion of the upper electrode in the vertical direction is greater than the thickness of the middle portion of the upper electrode in the vertical direction, and The middle portion has a convex shape with rounded corners.

2. The magnetoresistive random access memory device according to claim 1, wherein: The lower sidewall has a constant slope, the middle sidewall has a slope that decreases from the lower portion toward the protruding portion, and the slope of the sidewall of the protruding portion is greater than the slope of the sidewall of the adjacent middle portion.

3. The magnetoresistive random access memory device according to claim 2, wherein, The decrease in width of the middle portion of the upper electrode along the vertical direction is greater than the decrease in width of the lower portion of the upper electrode and the protruding portion of the upper electrode along the vertical direction.

4. The magnetoresistive random access memory device according to claim 2, wherein, The protruding portion of the upper electrode has an upper surface that is at least flat in the central part.

5. The magnetoresistive random access memory device according to claim 2, wherein, The protruding portion of the upper electrode has a rounded upper surface.

6. The magnetoresistive random access memory device according to claim 2, wherein, The thickness of the protruding portion of the upper electrode in the vertical direction is greater than the thickness of the lower portion of the upper electrode in the vertical direction.

7. The magnetoresistive random access memory device according to claim 2, wherein, The thickness of the protruding portion of the upper electrode in the vertical direction is less than the thickness of the lower portion of the upper electrode in the vertical direction.

8. The magnetoresistive random access memory device according to claim 2, wherein, The thickness of the middle portion of the upper electrode in the vertical direction is less than the thickness of the lower portion of the upper electrode in the vertical direction.

9. The magnetoresistive random access memory device according to claim 1, wherein, The passage contacts the uppermost surface of the passivation pattern.

10. The magnetoresistive random access memory device according to claim 1, wherein, The passivation pattern has a uniform thickness and includes silicon nitride.

11. The magnetoresistive random access memory device according to claim 1, wherein, The passage has a lower surface, wherein: The central portion of the lower surface is concave in the vertical direction, and The edge portion of the lower surface is convex in the vertical direction.

12. The magnetoresistive random access memory device according to claim 1, wherein, The height of the lowest surface of the passage is higher than or equal to the height of the upper surface of the lower part of the upper electrode.

13. A magnetoresistive random access memory device, comprising: Substrate; A storage cell, the storage cell comprising a lower electrode, a magnetic tunnel junction structure and an upper electrode sequentially stacked on the substrate; Passivation pattern, the passivation pattern being located on the sidewall of the storage cell; A pathway, the pathway being located on the memory cell and contacting each of the upper electrode and the passivation pattern; and Wiring, the wiring being located on the path and electrically connected to the path. in: The upper electrode comprises a first part, a second part, and a third part that are sequentially stacked and integrally formed. The decrease in width of the second portion of the upper electrode along a vertical direction substantially perpendicular to the upper surface of the substrate is greater than the decrease in width of the first portion of the upper electrode and the decrease in width of the third portion of the upper electrode along the vertical direction. The first portion of the upper electrode has a first thickness in the vertical direction. The second portion of the upper electrode has a second thickness in the vertical direction. The third portion of the upper electrode has a third thickness in the vertical direction. The first thickness is greater than each of the second thickness and the third thickness, and The second part has a convex shape with rounded corners.

14. The magnetoresistive random access memory device according to claim 13, wherein, The width of each of the first and second portions of the upper electrode decreases away from the substrate along the vertical direction.

15. The magnetoresistive random access memory device according to claim 13, wherein, The width of the third portion of the upper electrode decreases away from the substrate along the vertical direction.

16. The magnetoresistive random access memory device according to claim 13, wherein, The width of the third portion of the upper electrode remains constant along the vertical direction away from the substrate.

17. The magnetoresistive random access memory device according to claim 13, wherein, The first thickness is less than the sum of the second thickness and the third thickness.

18. The magnetoresistive random access memory device according to claim 13, wherein, The passage contacts the second and third portions of the upper electrode, but not the first portion of the upper electrode.

19. A magnetoresistive random access memory device, comprising: Substrate; A storage cell, the storage cell comprising a lower electrode, a magnetic tunnel junction structure and an upper electrode sequentially stacked on the substrate; Passivation pattern, the passivation pattern being located on the sidewall of the storage cell; A pathway, the pathway being located on the storage cell and in contact with the upper electrode; and Wiring, the wiring being located on the path and electrically connected to the path. in: The upper electrode includes: a first portion having sidewalls with a constant slope; a second portion having sidewalls with varying slopes; and a third portion protruding from the second portion in a direction substantially perpendicular to the upper surface of the substrate. The lower surface of the passage has a concave shape in the vertical direction at the portion that contacts the third portion of the upper electrode, and The width of the upper electrode decreases discontinuously and in a stepped manner from the third part to the second part.

20. The magnetoresistive random access memory device according to claim 19, wherein, The sidewall of the third portion of the upper electrode has a slope that decreases as it moves away from the substrate along the vertical direction.

21. The magnetoresistive random access memory device according to claim 19, wherein, The third portion of the upper electrode has a sidewall perpendicular to the upper surface of the substrate.

22. A method for manufacturing a magnetoresistive random access memory device, the method comprising: A lower electrode layer, a magnetic tunnel junction structure layer, and an upper electrode layer are sequentially formed on a substrate; A mask is formed on the upper electrode layer; A first etching process using the mask is performed on the upper electrode layer to form a preliminary upper electrode; A second etching process is performed on the mask remaining on the initial upper electrode to reduce the width of the mask; and The upper electrode is formed by performing a third etching process using a remaining mask with a reduced width to partially remove the upper portion of the initial upper electrode, such that the upper electrode comprises a lower portion, a middle portion, and a protruding portion sequentially stacked along a vertical direction substantially perpendicular to the upper surface of the substrate. in: The central portion of the protruding part of the upper electrode protrudes from the middle portion of the upper electrode in the vertical direction. The thickness of the protruding portion of the upper electrode in the vertical direction is greater than the thickness of the middle portion of the upper electrode in the vertical direction, and The middle portion has a convex shape with rounded corners.

23. The method according to claim 22, wherein, The mask comprises silicon oxide.

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