Method and system for controlling switches of a DC-to-DC converter

Abstract

According to one embodiment, a system and method for controlling a DC-to-DC converter includes a primary full bridge coupled to a secondary full bridge via a transformer. After a startup time period, an electronic data processor controls the converter to effectively operate in a first control mode, a second control mode, or a third control mode, wherein the first control mode comprises a phase-shifted mode, the second control mode comprises a triangular waveform control mode, and the third control mode comprises a trapezoidal waveform control mode. The electronic data processor determines a maximum target power range and a transition power level threshold for each control mode.

Description

Technical Field

[0001] The present disclosure relates to a method and system for controlling switches of a DC-to-DC converter. Background Art

[0002] In some prior art techniques, a DC-to-DC converter is used to interface with or convert a DC bus voltage between a first voltage level and a second voltage level of a direct current (DC) voltage. For example, a primary full bridge is coupled to a secondary full bridge via a transformer, wherein the primary full bridge is associated with an energy storage device at a first voltage level and the secondary full bridge is associated with a load at a second voltage level. If the switches in the primary full bridge or the secondary full bridge are operated in a phase-shift modulation mode, the possible soft switching states are limited, such that the switches tend to generate more heat than in a triangular waveform modulation mode. Although the triangular waveform modulation mode has more possible soft switching states, the triangular waveform modulation mode may only have a limited operating range. Therefore, there is a need for a method and system for controlling efficient switching of a DC-to-DC converter that generates less heat energy than a system operating primarily in a phase-shift modulation mode. Summary of the Invention

[0003] According to one embodiment, a system and method for controlling a DC-to-DC converter includes a primary full bridge coupled to a secondary full bridge via a transformer. After a startup time period, an electronic data processor controls the converter to effectively operate in a first control mode, a second control mode, or a third control mode for each of a series of time intervals. For example, the first control mode includes a phase-shift mode; the second control mode includes a triangular waveform control mode; and the third control mode includes a trapezoidal waveform control mode. The electronic data processor determines a maximum target power range and a transition power level threshold for each control mode. The electronic data processor estimates the transition power level threshold for one or more corresponding control modes based on the following applied to corresponding equations: (a) reference loss data stored in a data storage device, the reference loss data being based on predetermined or simulated converter switching losses and conduction losses associated with different control modes; and / or (b) measurements of observed primary and observed secondary voltages (e.g., AC voltages at transformer winding terminals, or DC voltages at DC input and output terminals of the converter). An electronic data processor manages transitions in or between control modes based on the maximum target power range and the estimated power level threshold, wherein the control modes apply time-synchronized control signals to respective control terminals of primary switches in the primary full bridge and secondary switches in the secondary full bridge. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A is a schematic diagram of one embodiment of a DC-to-DC converter including a primary full bridge coupled to a secondary full bridge via a transformer.

[0005] Figure 1B is a schematic diagram of another embodiment of a DC-to-DC converter including a primary full bridge coupled to a secondary full bridge via a transformer.

[0006] Figure 2A is the drain-source voltage (V DS ) and drain current (I D ) is an exemplary graph.

[0007] Figure 2B is the drain-source voltage of the switch during the soft turn-on time window and the soft turn-off time window (V DS ) and drain current (I D ) is an exemplary graph.

[0008] Figure 3 is the associated primary voltage, secondary voltage, inductor voltage, and inductor current for the converter assembly operating in a first mode (e.g., phase-shifted mode) and a possible gate input voltage (e.g., V GS ) or an exemplary graph of base input voltage versus time.

[0009] Figure 4A are exemplary graphs of possible primary and secondary voltages versus time for a fixed duty cycle modulation or duty cycle (eg, as observed at a transformer winding).

[0010] Figure 4B are exemplary graphs of possible primary and secondary voltages versus time for variable duty cycle modulation or duty cycle (eg, as observed at a transformer winding).

[0011] Figure 5 is the associated primary voltage, secondary voltage, inductor voltage, and inductor current for the converter assembly operating in the second mode (e.g., triangle waveform control mode), and possible gate input voltages (e.g., V GS ) or an exemplary graph of base input voltage versus time.

[0012] Figure 6 are the associated primary voltage, secondary voltage, inductor voltage, and inductor current for the converter assembly operating in the third mode (e.g., trapezoidal waveform control mode), and possible gate input voltages (e.g., V GS ) or an exemplary graph of base input voltage versus time.

[0013] Figure 7is an exemplary graph of operating modes relating efficiency and power delivered to the load. DETAILED DESCRIPTION

[0014] In any of the above-referenced figures in this document, any arrows or lines connecting any blocks, components, modules, multiplexers, sensors, switches, diodes, memories, data storage devices, data processors, electronic components, oscillators, or other electronic or software modules may include one or more of the following items: physical paths of electrical signals, physical paths of electromagnetic signals, logical paths of data, one or more data buses, circuit board traces, transmission lines; links, calls, communications, or data messages between software modules, programs, data, or components; or the sending or receiving of data messages, software instructions, modules, subroutines, or components.

[0015] In one embodiment, the systems and methods disclosed herein may include computer-implemented systems, methods, or converters in which one or more data processors process, store, retrieve, and otherwise manipulate data via a data bus and one or more data storage devices (e.g., data storage devices or memories) as described herein and in the accompanying drawings. As used herein, "configured to, adapted for, or arranged to" means that the data processor, converter, or controller is programmed with appropriate software instructions, software modules, executable code, databases, and / or necessary data to perform any referenced function, mathematical operation, logical operation, calculation, determination, process, method, algorithm, subroutine, or program associated with one or more blocks set forth in any other drawings in this disclosure. Alternatively, separately or cumulatively from the above definitions, "configured to, adapted for, or arranged to" may mean that the converter includes one or more components described herein as software modules, equivalent electronic hardware modules, or both, to perform any referenced function, logical operation, mathematical operation, calculation, determination, process, method, algorithm, subroutine, or program.

[0016] Figure 1A FIG1 is a schematic diagram of an embodiment of a direct current to direct current converter 11 (DC to DC converter), which includes a primary full bridge 10 coupled to a secondary full bridge 12 via a transformer 14. The primary full bridge 10 includes a first pair 50 of primary switches and a second pair 52 of primary switches. The first pair 50 of primary switches are coupled between direct current (DC) primary terminals 84 (e.g., input terminals) of the primary full bridge 10; the second pair 52 of primary switches 58 are coupled between the DC primary terminals 84 (e.g., input terminals) of the primary full bridge 10.

[0017] In one embodiment, the DC-to-DC converter 11 comprises a single-phase dual active bridge DC-to-DC converter having a DC primary terminal 84 (e.g., a DC input terminal) at the primary full bridge 10 and a DC secondary terminal 86 (e.g., a DC output terminal) at the secondary full bridge 12, wherein the DC-to-DC converter can operate unidirectionally or bidirectionally.

[0018] Each pair of primary switches 58 includes a low-side switch 62 and a high-side switch 64. Similarly, each pair of secondary switches 60 includes a low-side switch 62 and a high-side switch 64. Each switch (58, 60) has a switch terminal 68 that is controlled by a control terminal 70. For example, if the switch is a field effect transistor such as a metal oxide semiconductor field effect transistor (MOSFET), the switch terminal 68 includes a source terminal and a drain terminal and the control terminal 70 includes a gate terminal. In one configuration, for each pair of primary switches 58, the switch terminal 68 of the low-side switch 62 is coupled in series to the switch terminal 68 of the high-side switch 64 across the DC primary terminal 84. Figure 1A As shown, each switch has a protection diode 66 coupled in parallel to the switch terminal 68 of the corresponding switch. In one embodiment, the switches (58, 60) may include silicon carbide field effect transistors or other semiconductor devices.

[0019] In the primary full bridge 10, the switch terminals 68 of the first pair 50 of low-side switches 62 and high-side switches 64 are coupled together at a first node 72 or first junction associated with the primary AC electrical signal. In the primary full bridge 10, the switch terminals 68 of the second pair 52 of low-side switches 62 and high-side switches 64 are coupled together at a second node 74 or second junction associated with the primary AC electrical signal.

[0020] The secondary full bridge 12 includes a third pair 54 of switches (e.g., secondary switches 60) and a fourth pair 56 of switches (e.g., secondary switches 60) coupled between the DC secondary ends 86 (e.g., the output ends) of the secondary full bridge 12. The third pair 54 of switches (e.g., secondary switches 60) are coupled between the DC secondary ends (e.g., the output ends) of the secondary full bridge 12; the fourth pair 56 of switches (e.g., secondary switches 60) are coupled between the DC secondary ends 86 (e.g., the output ends) of the secondary full bridge 12.

[0021] Each pair of secondary switches 60 includes a low-side switch 62 and a high-side switch 64. Each secondary switch 60 has a switch terminal 68 controlled by a control terminal 70. For example, if the switches are field effect transistors such as metal oxide semiconductor field effect transistors (MOSFETs), the switch terminal 68 includes a source terminal and a drain terminal and the control terminal 70 includes a gate terminal. Figure 1A As shown, each secondary switch 60 has a protection diode 66 coupled in parallel to a switch terminal 68 of the corresponding switch.

[0022] In the DC-to-DC converter 11 in an exemplary configuration, each diode 66 facilitates dissipation of current associated with the corresponding switch (58, 60) to which the diode 66 is coupled in parallel to reduce a transient voltage across the switch (e.g., during a previous turn-off, previous deactivation, or previous dead time of the switch in preparation) to facilitate the next turn-on of the switch or the next activation of the switch (58, 60). In one embodiment, the protection diode 66 may be composed of a gallium nitride diode or other semiconductor material.

[0023] In the secondary full bridge 12, the switch ends 68 of the third pair 54 of low-side switches 62 and high-side switches 64 are coupled together at a third node 76 or third junction associated with the secondary AC electrical signal. In the secondary full bridge 12, the switch ends 68 of the fourth pair 56 of low-side switches 62 and high-side switches 64 are coupled together at a fourth node 78 or fourth junction associated with the secondary AC electrical signal.

[0024] In one embodiment, the transformer 14 is coupled between the primary full bridge 10 and the secondary full bridge 12. For example, the primary winding 80 of the transformer 14 is coupled to the first node 72 (e.g., the first output terminal) of the first pair 50 of primary switches 58 and the second node 74 (e.g., the second output terminal) of the second pair 52 of primary switches 58. Similarly, the secondary winding 82 of the transformer 14 is coupled to the third node 76 (e.g., the third output terminal) of the third pair 54 of switches (e.g., the secondary switches 60) and the fourth node 78 (e.g., the fourth output terminal) of the fourth pair 56 of switches (e.g., the secondary switches 60).

[0025] The transformer 14 has a primary winding 80 and a secondary winding 82, where the transformer 14 ratio (n) represents the voltage ratio between the primary and secondary ends. For example, the primary winding 80 ratio may represent the relative number of turns (n) of the primary winding 80 and the secondary winding 82. The voltage ratio or winding ratio may depend on the winding configuration, the conductor configuration, and the configuration of any core (e.g., a ferromagnetic core, a ferrite core, or an iron core).

[0026] An energy source 22 (e.g., a battery, a capacitor, or a generator output) is coupled to a direct current (DC) primary terminal 84 (e.g., an input terminal). A load 24 is configured to be coupled to a direct current (DC) secondary terminal 86 (e.g., an output terminal). However, the DC-to-DC converter 11, including the primary full bridge 10, the secondary full bridge 12, and the transformer 14, can operate bidirectionally, for example, transferring power in either direction between the DC primary terminal 84 and the DC secondary terminal 86. In one direction, the energy source 22 at the DC primary terminal 84 can power the load 24 at the DC secondary terminal 86. However, in the opposite direction, the load 24 at the DC secondary terminal 86 can provide excess or transient energy to the DC primary terminal 84 to charge the energy source 22. As shown, a capacitor, such as the primary capacitor 18, is positioned across the DC primary terminal 84, and a secondary capacitor 20 is positioned across the DC secondary terminal 86, where the primary capacitor 18 and the secondary capacitor 20 are used for filtering (e.g., to reduce noise such as current ripple or voltage ripple in the DC voltage).

[0027] In some embodiments, the DC primary 84 is configured to operate at a different voltage level than the DC secondary 86. In other embodiments, the DC primary 84 and DC secondary voltage levels may have variable voltage levels that can dynamically fluctuate with the load 24 or operating conditions for various time intervals (e.g., sampling times of the DC voltage observed at the DC primary input and DC secondary output of the converter). For example, the DC primary 84 operates at a higher voltage level or a higher voltage range (e.g., approximately 400 VDC to approximately 800 VDC) than the lower voltage level or lower voltage range (e.g., approximately 12 VDC to approximately 400 VDC) of the DC secondary 86. Thus, because the transformer blocks DC energy from passing between the transformer primary and transformer secondary, the electronic components or DC-to-DC converter 11 support vehicles with different DC bus levels isolated from each other.

[0028] In one embodiment, the electronic data processor 32 (e.g., the electronic controller 38) is configured to provide time-synchronized control signals to the control terminals 70 of the primary switch 58 and the secondary switch 60 to control the converter 11 to operate efficiently in the first control mode 26, the second control mode 28, or the third control mode 30. Figure 7 ), wherein the first control mode 26 comprises a phase-shift mode, the second control mode 28 comprises a triangular waveform control mode, and wherein the third control mode 30 comprises a trapezoidal waveform control mode.

[0029] In one embodiment, the electronic controller 38 includes an electronic data processor 32, a data storage device 40, and one or more data ports 42 coupled to or in communication with a data bus 44. The electronic data processor 32, the data storage device 40, and the one or more data ports 42 can communicate data messages with each other via the data bus 44.

[0030] The electronic data processor 32 may include a microcontroller, a microprocessor, a programmable logic array, a logic device, an arithmetic logic unit, a digital signal processor, an application specific integrated circuit, or another device for processing or manipulating data. The data storage device 40 may include an electronic memory, a non-volatile random access memory, a magnetic storage device, an optical storage device, or another device for storing, retrieving, and managing data, files, data structures, or data records. The data port 42 may include an input / output port, a data transceiver, a wired transceiver, a wireless transceiver, a buffer memory, or a combination of the foregoing.

[0031] The electronic data processor 32 or its data port 42 is connected to or in communication with the control terminals 70 of the switches (e.g., primary switch 58 and secondary switch 60) of the primary full-bridge 10 and the secondary full-bridge 12. Thus, the electronic controller 38 can control the timing and operation of each switch, such as activation time, deactivation time, biasing, and other aspects. In one embodiment, the electronic controller 38 or electronic data processor 32 uses a fixed switching frequency (e.g., within an operating range of the switching frequency) of the fundamental frequency of the switches for multiple or all modulation modes, such as the first mode, the second mode, and the third mode. Furthermore, the switches can operate at the same or substantially similar fixed duty cycle (e.g., 50% duty cycle with a tolerance of ±10%) for multiple or all modulation modes, such as the first mode, the second mode, and the third mode. In some configurations, the peak amplitude and duration of the gate signals of the high-side switch 64 and the low-side switch 62 of any pair or phase are approximately equal or substantially comparable. In one configuration, the electronic data processor 32 or electronic controller 38 is configured to determine a maximum target power range 34 and a transition power level threshold for each control mode.

[0032] In one embodiment, the electronic data processor 32 or the electronic controller 38 is configured to perform one or more of the following: (a) determining one or more transition power level thresholds during operation; (b) selecting an optimal control mode among the control modes to reduce or minimize switching losses; and (c) selecting an optical control mode among the control modes to provide maximum soft switching of the primary and secondary switches. For example, the upper limit of the maximum target power range 34 is equal to, proportional to, or comparable to the transfer power equation corresponding to the corresponding control mode. Although the DC primary terminal 84 (e.g., the DC primary bus) and the DC secondary terminal 86 (e.g., the DC secondary bus) have fixed voltage levels, the primary voltage (V1) at (or across) the transformer primary winding 80 or the secondary voltage (V2) at (or across) the transformer secondary winding 82, or both, may vary.

[0033] In one embodiment, the first voltage sensor 46 (e.g., a primary voltage sensor) is configured to measure a primary voltage (e.g., an RMS voltage, a peak voltage, or other AC voltage measurement) and the second voltage sensor 48 (e.g., a secondary voltage sensor) is configured to: (a) measure observed primary and secondary voltages (e.g., an RMS voltage, a peak voltage, or other AC voltage measurement); and (b) provide the measured observed voltage readings of the primary and secondary voltages (e.g., at the transformer ends of the primary and secondary windings) to the electronic controller 38 via one or more data ports 42. In another embodiment, the first voltage sensor 46 and the second voltage sensor 48 may measure one or more of the following: an AC voltage level, a RMS voltage level, or rectified AC (e.g., via a half-wave or full-wave bridge rectifier) ​​at one or more transformer windings (80, 82). Furthermore, the electronic controller 38 or the electronic data processor 32 is configured to estimate the DC primary voltage at the DC primary input 84 and the DC secondary voltage at the DC secondary output 86 of the converter 11 based on the measurements, or may control the switches in an initialization mode or a test mode to facilitate direct measurement of the primary voltage at the DC primary input 84 and the secondary voltage at the DC secondary output 86 of the converter.

[0034] Alternatively, (eg, during initialization mode or operation mode) the first voltage sensor 146 ( Figure 1B ) and the second voltage sensor 148 ( Figure 1B) is configured to: (a) measure the primary voltage at the DC primary input 84 and the secondary voltage at the DC secondary output 86 of the converter 11; and (b) provide the measurements to the electronic controller 38 via the one or more data ports 42. Thus, the observed primary voltage and the observed secondary voltage may be applied to or applied to one or more transmission power equations that are applied to the respective control modes to estimate the maximum transmission power for the respective control modes; thereby, establishing a limit (e.g., an upper limit) for the respective operating range or the respective operating region for each respective control mode.

[0035] like Figure 7 As shown, the upper limit of a control mode can be established to coexist with the lower limit of an adjacent control mode. For example, the upper limit of the transition power threshold 36 of the second mode 28 (e.g., the triangular waveform control mode) is coexistent with the lower limit of the same transition power threshold 36 of the third control mode 30 (e.g., the trapezoidal waveform control mode); and the upper limit of the transition power threshold 136 of the third control mode 30 is coexistent with the lower limit of the same transition power threshold 136 of the first control mode 26.

[0036] In one embodiment, the electronic controller 38 is configured to estimate (e.g., at runtime or online) one or more transition power level thresholds (36, 136) based on reference loss data (e.g., thermal energy loss data) stored in the data storage device 40, either cumulatively or independently of the transfer power equations for the respective modes. For example, the reference loss data is based on predetermined or simulated (e.g., offline) DC-to-DC converter model switching losses and conduction losses associated with the different control modes. The electronic data processor 32 or the electronic controller 38 is configured to manage transitions between or within the control modes based on the maximum target power range 34 and the estimated transition power thresholds (e.g., transition levels).

[0037] Figure 1A Similar to Figure 1B , the difference is Figure 1A The first voltage sensor 46 and the second voltage sensor 48 are composed of Figure 1B The first voltage sensor 146 and the second voltage sensor 148 may be replaced by the first voltage sensor 146 and the second voltage sensor 148. For example, the readings of the first voltage sensor 146 and the second voltage sensor 148 may be applied to the equations described herein for determining the DC primary voltage (V1) at terminal 84 or the DC secondary voltage (V2) at terminal 86. In alternative embodiments, if the DC primary voltage (V1) is fixed within a certain tolerance or is regulated within a certain tolerance, then the first voltage sensor 146 or the second voltage sensor 148 may be omitted, and if the DC secondary voltage (V2) is fixed within a certain tolerance or is regulated within a certain tolerance, then the second voltage sensor 148 may be omitted.

[0038] Figure 2Ais an exemplary graph of potential drain-source voltage (or collector-emitter voltage) and drain current (or base current) of the switch during turn-on and turn-off according to possible hard switching events associated with switching losses (e.g., lower efficiency of the DC to DC converter 11) or heat. Figure 2A In FIG. 2 , the vertical axis indicates the signal magnitude 205 and the horizontal axis indicates the time 206. The drain-source voltage 201 (V DS ) is the voltage measured across or between the switch terminals 68 (e.g., drain and source, or collector and emitter) of the switch. The drain current 202 (I D ).

[0039] During the conduction window 203 or switch enable period, the Figure 2A The left-hand diagonal hatched triangular area 207 in FIG. indicates potential switching losses. During the cutoff window 204 , or when the switch is deactivated, potential switching losses are indicated by the right-hand diagonal hatched area 207 . Losses associated with potential hard switching events generally increase with increasing switching frequency and voltage (e.g., drain-source voltage of the switch). While hard switching events can occur in any switching mode, they are more likely to occur in the first control mode 26 or phase-shifted operating mode of the switches of the DC-DC converter 11.

[0040] Figure 2B is the drain-source voltage (V DS )201 and drain current (I D )312 is an exemplary graph. Figure 2B In FIG. 2 , the vertical axis indicates the signal magnitude 205 and the horizontal axis indicates the time 206. The drain-source voltage 201 (V DS ) is the voltage measured across or between the switch terminals 68 (e.g., drain and source, or collector and emitter) of the switch. The drain current 312 (I D ), wherein the drain current 312 has a peak magnitude 314 between the soft turn-on window 303 and the soft turn-off window 304, and a bow shape or a sudden drop from the peak magnitude to avoid the drain current 312 flowing during the soft turn-on window 303 and the soft turn-off window 304.

[0041] During the soft turn-on window 303 or switch enable period, if there is no overlap between the drain-source voltage 201 and the drain current 312, then Figure 2B The left zero voltage turn-on region in indicates possible soft switching. During the soft turn-off window 304 or switch deactivation period, if there is no overlap between the drain-source voltage 201 and the drain current 312, the right zero current turn-off region indicates possible switching losses. In other words, during Figure 2B During a possible soft switching event, the switch has a zero drain-source voltage 201 or a near-zero drain-source voltage 201 to minimize losses. Furthermore, the soft switching event is associated with one or more of the following: (a) potentially increased efficiency of the DC-to-DC converter 11 and potentially increased power density; (b) potentially reduced electromagnetic radiation or interference generated by the switch; and (c) potentially longer lifetime of the switch (e.g., semiconductor switch) associated with reduced thermal stress; and therefore, potentially longer lifetime of the DC-to-DC converter 11.

[0042] Figure 3 is the associated primary voltage 307 (V pri ), secondary voltage 308(V sec ), inductor voltage 309(V L ) and the inductor current 310 (I L ), and possible gate input voltages (V GS ) or an exemplary graph of base input voltage versus time. In one embodiment, the AC primary voltage (V pri ) and secondary voltage (V sec ) are proportional to or derivative of the primary input voltage (V1) and the secondary output voltage (V2), respectively.

[0043] In the first control mode 26 or phase-shift mode, the DC-to-DC converter 11 can operate at any power level equal to or lower than its maximum operating power level. Although soft switching events, such as zero voltage switching (ZVS) or zero current switching (ZCS), can be achieved in the first control mode 26, the soft switching events depend on the load 24 and its electrical characteristics (e.g., resistance, reluctance, inductance, and capacitance) and / or the relative values ​​of the first current (I1) in the primary winding 80 and the second current (I2) in the primary winding 80.

[0044] The currents flowing through the primary winding 80 and the secondary winding 82 of the transformer 14 have waveforms of the same shape, but with different magnitudes. The current levels (I1 and I2) determine the soft switching event. For example, when I1>0 and I2>0, both the primary and secondary switches are turned on / off with ZVS. When I1<0 and I2>0, only the primary switch is turned on / off with ZVS. The voltage 309 (V L ) is the voltage across inductor 16 (L), which in some embodiments can be estimated according to the following equation:

[0045] V L =V pri -nVsec , where V L is the voltage across the inductor 16 or the model inductance of the primary winding 80 of the transformer 14; V pri is the primary voltage across the primary winding 80 of the transformer and the inductor 16, V sec is the secondary voltage across the secondary winding 82 of the transformer 14 , and n is the turns ratio of the primary winding 80 to the secondary winding 82 .

[0046] The inductor current 310 (I L ) can be estimated according to the following equation:

[0047] Where V L is the voltage across the inductor 16 or the model inductance of the primary winding 80 of the transformer 14; where I L is the current flowing through inductor 16 , where L is the inductance value of inductor 16 , and where t is the time associated with charging or discharging inductor 16 .

[0048] Whenever possible, in the first control mode 26, the controller 38 may control the primary current and the secondary current (which may be cumulative or secondary applied) according to various examples to achieve a soft switching state. In the first example, the load 24 may at least partially affect or cause the first current level 311 (I1) and the second current level 313 in the primary winding 80 of the transformer. Figure 3 In the middle, the current is 310 (I L ) is the current flowing through the inductor 16 or the model inductance associated with the primary winding 80 of the transformer 14.

[0049] In a second example, in the first control mode 26, if the drain current 202 (I ) is low during the on-state (e.g., the on-window 203) or the off-state (e.g., the off-window 204) of the switch due to a load inductive current in a winding of the inductive transformer 14 (e.g., I 1 or I 2 in the primary winding 80) and / or due to the load 24 having an inductive characteristic, the drain current 202 (I ) is low during the on-state (e.g., the on-window 203) or the off-state (e.g., the off-window 204) of the switch. D ) is greater than zero, a hard switching event may occur (e.g., during the first control mode 26). For example, the load inductive current has a current waveform I L , where I1 and I2 are the same current waveform I L (eg, two points in the inductor 16 or transformer primary side current waveform).

[0050] In a third example, in the first control mode 26, if the first current level (I1) is greater than zero and if the second current level (I2) is less than zero, a hard switching event (e.g., non-ZVS) may occur in the primary switch 58 of the primary full bridge 10. In a fourth example, in the first control mode 26, if the first current level (I1) is less than zero and if the second current level (I2) is greater than zero, a hard switching event (e.g., non-ZVS) may occur in the secondary switch 60 of the secondary full bridge 12. In a fifth example, in the first control mode 26, if both the first current level (I1) and the second current level (I2) are greater than zero, a soft switching event (e.g., ZVS) may occur.

[0051] In the first control mode 26, the drain-source voltage (V DS ) to support ZVS during the soft turn-on window 303 of any switch in the first control mode 26. However, in the first control mode 26, if the switch is turned off or disabled, the turn-off window 204 is a hard switching event.

[0052] In the first control mode 26 , the maximum achievable power transfer is achieved when the phase offset between the primary full bridge 10 and the secondary full bridge 12 is approximately 180 degrees according to the following equation:

[0053]

[0054] Where n is the transformation ratio between the primary winding 80 and the secondary winding 82 of the transformer 14; V1 is the DC voltage input to the primary full bridge 10 at the DC primary terminal 84 (e.g., the input voltage provided by the energy source 22); V2 is the output DC voltage of the secondary full bridge 12 associated with the DC secondary terminal 86; f s is the switching frequency of the switches ( 58 , 60 ); and L is the transformer inductance modeled as the model inductor 16 in series with the primary winding 80 of the transformer 14 .

[0055] In the first control mode 26, the phase offset Φ between the primary full bridge 10 and the secondary full bridge 12 (e.g., between switch S1 and switch S5) is variable and adjusted based on the required transfer power of the DC-to-DC converter 11 according to the following equation:

[0056]

[0057] Where n is the transformation ratio between the primary winding 80 and the secondary winding 82 of the transformer 14, V1 is the DC voltage input to the primary full bridge 10 at the DC primary terminal 84 (e.g., the input voltage provided by the energy source 22); V2 is the output DC voltage of the secondary full bridge 12 associated with the DC secondary terminal 86; fs is the switching frequency of the switches, L is the inductance modeled as the model inductor 16 in series with the primary winding 80 of the transformer 14 , and P is the transferred power of the DC-to-DC converter 11 .

[0058] Reference Figure 1A and Figure 3 In the first control mode 26, the primary switches 58 include a first pair 50 (S1, S2) of switches for the first phase (e.g., the first leg) and a second pair 52 (S3, S4) of switches for the second phase (e.g., the second leg). Figure 3 As shown, in the first control mode 26, the high-side switches 64 (S1) of the first pair 50 have a complementary phase offset (e.g., approximately 180 degrees offset) relative to the high-side switches 64 (S3) of the second pair 52; the low-side switches (S2) of the first pair 50 have a complementary phase offset (e.g., approximately 180 degrees offset) relative to the low-side switches 62 (S4) of the second pair 52. Similarly, in the first control mode 26, the secondary switches 60 include a third pair 54 (S5, S6) of switches for the third phase (e.g., the third leg) and a fourth pair 56 (S7, S8) of switches for the fourth phase (e.g., the fourth leg). Figure 3 As shown, in the first control mode 26, the high-side switches 64 (S5) of the third pair 54 have a complementary phase offset (e.g., approximately 180 degrees offset) relative to the high-side switches 64 (S7) of the fourth pair 56; and the low-side switches (S6) of the third pair 54 have a complementary phase offset (e.g., approximately 180 degrees offset) relative to the low-side switches 62 (S8) of the fourth pair 56.

[0059] In addition Figure 3 In FIG, primary switches 58 include a first pair 50 of switches for the first phase and a second pair 52 of switches for the second phase. In a first control mode 26, within each of the first and second pairs 50 and 52 of primary switches, the high-side switch 64 has a complementary phase offset and approximately a 50% duty cycle relative to the low-side switch 62. A 50% duty cycle means that either the low-side switch 62 or the high-side switch 64 within a pair is active or conducting approximately half the time, where approximately means a tolerance of ±10% on the 50% duty cycle. Similarly, secondary switches 60 include a third pair 54 of switches for the third phase and a fourth pair 56 of switches for the fourth phase. In a first control mode 26, within each of the third and fourth pairs 54 and 56 of primary switches 58, the high-side switch 64 has a complementary phase offset and approximately a 50% duty cycle relative to the low-side switch 62.

[0060] Figure 3The top four graphs show a plurality of control signals applied to the control terminals 70 of the switches (58, 60) in the DC to DC converter 11. The second to last graph (305) shows the corresponding primary voltage 307 (V pri ) ) and the secondary voltage 308 (V sec The last or bottom graph (306) shows the inductor 16 (L lk ) of the inductor voltage 309(V L ) and the inductor current 310 (I L ) or the inductance associated with the primary winding of transformer 14. Figure 3 All of the graphs of have a common time scale along each horizontal axis 300 and individual signal magnitudes for each signal along each vertical axis 399 (shown as dashed lines terminating in upward pointing arrows). Figure 3 , a relative phase shift Φ between control signals for switches such as primary switch 58 and secondary switch 60 is shown (e.g., a maximum phase shift of approximately 180 degrees, where the relative phase shift Φ can be adjusted to reduce switching losses). Additionally, the control signals (301, 302, 303, 304) are shown to have a duty cycle 389 (D) of approximately fifty (50) percent.

[0061] exist Figure 3 In the top graph 381, the first control signal 301 is applied to the high-side switch 64 (S1) of the first pair 50 of primary switches 58 and the low-side switch 62 (S4) of the second pair 52 of primary switches 58. For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0062] In the second topmost graph 382, ​​the second control signal 302 is applied to the low-side switch 62 (S2) of the first pair 50 of primary switches 58 and the high-side switch 64 (S3) of the second pair 52 of primary switches 58. For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0063] exist Figure 3 , in the third topmost graph 383, a third control signal 303 is applied to the high-side switch 64 (S5) of the third pair 54 of switches (e.g., secondary switch 60) and the low-side switch 62 (S8) of the fourth pair 56 of switches (e.g., secondary switch 60). For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (VGS).

[0064] In the fourth topmost graph 384, a fourth control signal 304 is applied to the low-side switch 62 (S6) of the third pair 54 of switches (e.g., secondary switch 60) and the high-side switch 64 (S7) of the second pair 52 of switches (e.g., secondary switch 60). For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (VGS).

[0065] In the penultimate graph 305 , a relative phase shift Φ between the primary voltage 307 of the transformer 14 and the secondary voltage 308 of the transformer 14 is shown (e.g., a maximum phase shift of approximately 180 degrees, where the relative phase shift Φ can be adjusted to reduce switching losses). Figure 3 In the penultimate graph 305 , the primary voltage 307 is indicated as a solid line, and the secondary voltage 308 is indicated as a dashed line.

[0066] exist Figure 3 In the last graph 306 or bottom graph of FIG, the signal output waveform is associated with the load 24 while the DC to DC converter 11 is operating in the first control mode 26. Figure 3 In the final graph of FIG. 1 , inductor voltage 309 (eg, across the inductor terminals of inductor 16 or associated with the model inductance) is indicated by a solid line, while inductor current 310 is indicated by a dashed line.

[0067] Figure 4A is an exemplary graph of possible primary voltage 402 and secondary voltage 403 associated with transformer 14 versus time in a first control mode 26 (e.g., phase-shift control mode) for a fixed duty cycle modulation at the transformer windings of transformer 14 (e.g., approximately 50% duty cycle modulation at the switches). Figure 4A , the vertical axis indicates signal magnitude 401, and the horizontal axis indicates time. The waveform of the primary voltage 402 is indicated by a solid line, and the waveform of the secondary voltage 403 is indicated by a dotted line.

[0068] For example, Figure 4ATransformer waveforms resulting across the primary winding 80 and the secondary winding 82 are shown based on: (a) a first phase of a control signal applied at the control terminal 70 of the high-side switch (S1) of the first pair 50 switches of the first phase and a second phase of a control signal applied at the control terminal 70 of the high-side switch (S5) of the third pair 54 switches of the third phase of the secondary full bridge 12; and (b) a third phase of a control signal applied at the control terminal 70 of the low-side switch (S2) of the pair of switches of the first phase and a fourth phase of a control signal applied at the control terminal 70 of the low-side switch (S6) of the third pair 54 switches of the third phase of the secondary full bridge 12. The above-described phase shifts 405 do not refer to complementary phase shifts (e.g., approximately 180 degrees) between the low-side switches and the high-side switches of either phase of the primary full bridge 10 or the secondary full bridge 12. Instead, as described in more detail above, the electronic controller 38 or electronic data processor 32 determines another phase shift (Φ) (e.g., the phase shift of switches S5 and S8 relative to switches S1 and S4, respectively, and the phase shift of switches S6 and S7 relative to switches S2 and S3, respectively, as follows: Figure 3 shown):

[0069] Figure 4B are exemplary graphs of possible primary and secondary voltages versus time for variable duty cycle modulation associated with or at the transformer windings to control the inductor current L (through the model inductor 16 associated with the transformer 14 or its primary winding 80) to increase soft switching events within the second control mode 28 (e.g., triangular waveform control mode) or the third control mode 30 (e.g., trapezoidal waveform control mode). Figure 4A and Figure 4B Like reference numbers in the drawings indicate like elements or features.

[0070] Figure 4B The waveforms resulting across the primary winding 80 and the secondary winding 82 for a variable duty cycle modulation determined by or aligned with the transmission power are shown. For example, based on the maximum power transfer for a given control mode (e.g., the second control mode 28 or the third control mode 30), the phase shift Φ TRM The output power of the output voltage corresponds to a substantially linear slope of the corresponding operating mode. In addition, based on the lower and upper limits of the output power of the corresponding control mode, the slope of the output power of the output voltage can be intercepted at the midpoint of the output power of each control mode (e.g., the triangular waveform control mode or the trapezoidal waveform control mode). Specifically, Figure 4B The waveforms resulting across the primary winding 80 and the secondary winding 82 are shown based on: (a) a variable or adjustable phase shift Φ between the first pair 50 of switches of the first phase and the second pair 52 of switches of the second phase of the primary full bridge 10; TRMand (b) a variable or adjustable phase shift Φ between the third pair 54 of switches of the third phase of the secondary full bridge 12 and the fourth pair 56 of switches of the fourth phase TRM .

[0071] For the second control mode 28, the phase shift Φ is determined according to the following equation TRM :

[0072] where Φ TRM is the phase shift (in radians) between the midpoint of the primary voltage of the primary winding 80 and the midpoint of the secondary voltage of the secondary winding 82. Furthermore, in the second control mode 28, the maximum power transfer is determined according to the following equation:

[0073] Where n is the transformation ratio between the primary winding 80 and the secondary winding 82; V1 is the DC voltage input to the primary full bridge 10 at the DC primary terminal 84 (e.g., the input voltage provided by the energy source 22); V2 is the output DC voltage of the secondary full bridge 12 associated with the DC secondary terminal 86; f s is the switching frequency of the switches; L is the inductance modeled as the model inductor 16 connected in series with the primary winding 80 of the transformer 14.

[0074] Figure 5 The operation of the DC to DC converter 11 is shown in the second control mode 28 (eg, triangular waveform control mode). Figure 5 , primary switches 58 include a first pair 50 of switches for the first phase and a second pair 52 of switches for the second phase. In the second control mode 28 and in the third control mode 30, the first pair 50 has a non-complementary phase offset (not 180 degrees offset) relative to the second pair 52. Secondary switches 60 include a third pair 54 of switches for the third phase and a fourth pair 56 of switches for the fourth phase. In the second control mode 28 and in the third control mode 30, the third pair 54 has a non-complementary phase offset (e.g., not 180 degrees offset) relative to the fourth pair 56. However, similar to the first control mode 26, operation in the second control mode 28 has complementary phase offsets within each pair of switches in any phase. In the second control mode 28, within each of the first pair 50 and the second pair 52 of primary switches, the high-side switch 64 has a complementary phase offset and approximately a 50% duty cycle relative to the low-side switch 62. A 50% duty cycle means that either the low-side switch 62 or the high-side switch 64 within a pair is active or conducting approximately half of the time, with a tolerance of ±10% of the 50% duty cycle being approximately defined. Similarly, the secondary switches 60 include a third pair 54 of switches for the third phase and a fourth pair 56 of switches for the fourth phase; in the second control mode 28, within each of the third and fourth pairs 54, 56 of primary switches 58, the high-side switch 64 has a complementary phase offset relative to the low-side switch 62 and approximately a 50% duty cycle.

[0075] Figure 5 The top four graphs (501, 502, 503, 504) show a plurality of control signals (501, 502, 503, 504) applied to the control terminals 70 of the switches (58, 60) in the DC-DC converter 11 for the second control mode 28. The second to last graph (505) shows the corresponding primary voltage 507 (V pri ) ) and the secondary voltage 508 (V sec The last or bottom graph (506) shows the inductor voltage 509 (V L ) and the inductor current 510 (I L ) or the model inductance associated with the primary winding 80 of the transformer 14. Figure 5 All of the graphs of have a common time scale along each horizontal axis 300 and individual signal magnitudes for each signal along each vertical axis 399 (shown as dashed lines terminating in upward pointing arrows). Figure 5 1 and 2 (e.g., represented in the time domain as T1 or T1+T2) are shown relative phase shifts between control signals for switches, such as: (a) between primary switch 58 and secondary switch 60, (b) between first pair 50 and second pair 52 within primary switch 58, and (c) between third pair 54 and fourth pair 56 within secondary switch 60. Additionally, control signals (501, 502, 503, 504) are shown.

[0076] In one example, for the second control mode 28 , the relative phase shift between the control signals applied to the switches of the converter 11 obeys the following equation:

[0077] T1+T2+T3=T s / 2, where T1 is a first time delay or a first relative phase shift (e.g., between respective leading edges of the control signals of switches S1 and S3), where T1+T2 is a second time delay or a second relative phase shift (e.g., between respective leading edges of the control signals of S1 and S7), T3 is a third time delay or a third relative phase shift, and where T s is the time period or full duty cycle of the control signal, such that T s / 2 means 50% duty cycle.

[0078] Figure 5In the top four graphs (581, 582, 583, 584) are shown a number of control signals to the DC to DC converter 11. The second to last graph 505 shows the respective primary and secondary voltages across the transformer 14 of the DC to DC converter 11. The last or bottom 506 graph shows the inductor voltage (V L ) and the inductor current (I L ).for Figure 5 All graphs of have a common time scale 300 along each horizontal axis and individual signal magnitudes 399 for each signal along each vertical axis.

[0079] exist Figure 5 In the uppermost graph 581, a first control signal 501 is applied to the high-side switch 64 (S1) of the first pair 50 of primary switches 58. For example, if each switch is a field effect transistor (FET), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0080] In the second topmost graph 582, the second control signal 502 is applied to the high side switch 64 (S3) of the second pair 52 of primary switches 58. For example, if each switch is a field effect transistor (FET), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0081] exist Figure 5 In the third topmost graph 583, the third control signal 503 is applied to the high-side switch 64 (S5) of the third pair 54 of switches (e.g., the secondary switch 60). For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0082] In the fourth topmost graph 584, the fourth control signal 504 is applied to the high-side switch 64 (S7) of the fourth pair 56 of switches (e.g., the secondary switch 60). For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0083] In the penultimate graph 505 , the relative phase shift Φ between the primary voltage of the transformer 14 and the secondary voltage of the transformer 14 is shown. TRM (e.g., fixed phase shift). Figure 5 In the penultimate graph 505 of FIG. 1 , the primary voltage 507 associated with the ends of the primary winding 80 is indicated as a solid line, while the secondary voltage in the secondary winding 82 associated with the ends of the secondary winding 82 is indicated as a dashed line.

[0084] exist Figure 5 In the last graph 506 or bottom graph of FIG, the signal output waveform is associated with the load 24 while the DC to DC converter 11 is operating in the second control mode 28 (eg, the triangle waveform control mode). Figure 5 In the last graph 506, the inductor voltage 509 (V L ) or model inductance is indicated by the solid line, and the inductor current 510 (I L ) is indicated by a dotted line.

[0085] Figure 6 The operation of the DC to DC converter 11 in the third control mode 30 (eg, trapezoidal waveform control mode) is shown. Figure 6 In FIG, primary switches 58 include a first pair 50 of switches for the first phase and a second pair 52 of switches for the second phase. In the second control mode 28 and in the third control mode 30, the first pair 50 has a non-complementary phase offset (not 180 degrees offset) relative to the second pair 52. Secondary switches 60 include a third pair 54 of switches for the third phase and a fourth pair 56 of switches for the fourth phase. In the second control mode 28 and in the third control mode 30, the third pair 54 has a non-complementary phase offset (e.g., not 180 degrees offset) relative to the fourth pair 56.

[0086] However, similar to the first control mode 26, the operation of the third control mode 30 has complementary phase offsets within each pair of switches in any phase. In the third control mode 30, in each of the first pair 50 and the second pair 52 of primary switches, the high-side switch 64 has a complementary phase offset and approximately a 50% duty cycle relative to the low-side switch 62. A 50% duty cycle means that the low-side switch 62 or the high-side switch 64 within a pair is active or conducting approximately half of the time, where approximately means a tolerance of ±10% of the 50% duty cycle. Similarly, the secondary switches 60 include a third pair 54 of switches for the third phase and a fourth pair 56 of switches for the fourth phase; in the third control mode 30, in each of the third pair 54 and the fourth pair 56 of primary switches 58, the high-side switch 64 has a complementary phase offset and approximately a 50% duty cycle relative to the low-side switch 62.

[0087] In the third control mode 30 (eg, trapezoidal waveform control mode), the phase shift (Φ or Φ) is determined according to the following equation: trap ):

[0088]

[0089]

[0090] However, in the third control mode 30, the maximum phase shift is limited to the maximum phase shift according to the following equation:

[0091]

[0092] Furthermore, the following conditions (eg, boundary conditions) are required to operate in the third mode 30 (eg, trapezoidal mode):

[0093]

[0094] T1+T2+T3=Ts / 2

[0095] T1+T2+T3≥0, where:

[0096]

[0097] and

[0098]

[0099] Where T1 is a first control variable, T2 is a second control variable, and T3 is a third control variable. In one configuration, T1, T2, and T3 represent equal times of phase shift between respective pairs of control signals applied to the control terminals 70 of the switches (58, 60).

[0100] In the third control mode 30, the maximum power transmitted is determined according to the following equation:

[0101]

[0102] Figure 6 The control signals (601, 602, 603, 604) of the DC to DC converter 11 are shown in the top four graphs (681, 682, 683, 684). The penultimate graph 605 shows the corresponding primary voltages 607 (V pri ) and secondary voltage 608(V sec The last or bottom graph 606 shows the inductor voltage 609 (V L ) and the inductor current 610 (I L ) or the model inductance associated with the primary winding 80 of the transformer 14. Figure 6 All graphs of have a common time scale 300 along each horizontal axis and individual signal magnitudes 399 for each signal along each vertical axis. Figure 6 The relative phase shift Φ between the control signals of the switches is shown in trap(e.g., expressed in the time domain as T1+T2 or T2+T3), for example: (a) between the primary switch 58 and the secondary switch 60, (b) between the first pair 50 and the second pair 52 within the primary switch 58, and (c) between the third pair 54 and the fourth pair 56 within the secondary switch 60.

[0103] exist Figure 6 In the top graph 681, the first control signal 601 is applied to the high-side switch 64 (S1) of the first pair 50 of primary switches 58. For example, if each switch is a field effect transistor (FET), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0104] In the second topmost graph 682, a second control signal 602 having a first phase offset (e.g., T1+T2) is applied to the high-side switch 64 (S3) of the second pair 52 of primary switches 58. For example, if each switch is a field effect transistor (FET), the control signal is applied as a control voltage or gate-source voltage (V GS ).

[0105] exist Figure 6 In the third topmost graph 683, the third control signal 603 is applied to the high side switch 64 (S5) of the third pair 54 of switches (eg, the secondary switch 60). Here, Figure 6 In FIG. 7 , switches S1 and S5 may be aligned with the phase of the respective control signals applied to their control inputs 70. For example, if the respective switches are field effect transistors (FETs), the control signals may be applied as a control voltage or gate-source voltage (V GS ).

[0106] In the fourth topmost graph, a fourth control signal 604 is applied to the high-side switch 64 (S7) of the fourth pair 56 of switches (e.g., secondary switch 60), wherein switch S7 has a second phase offset (e.g., -(T2+T3)) relative to switch S5. For example, if the respective switches are field effect transistors (FETs), the control signal is applied as a control voltage or gate-source voltage (VGS).

[0107] In one example, for the third control mode 30 , the relative phase shift between the control signals applied to the switches of the converter 11 obeys the following equation:

[0108] T1+T2+T3=T s / 2, where T1+T2 is a first time delay or a first relative phase shift (e.g., between respective leading edges of the control signals of switches S1 and S3), where -(T1+T2) is a second time delay or a second relative phase shift (e.g., between respective leading edges of the control signals of S1 and S7), T3 is a third time delay or a third relative phase shift associated with the control signals of the switches of converter 11, and where T s is the time period or full duty cycle of the control signal, such that T s / 2 means 50% duty cycle.

[0109] In the penultimate graph 605, the primary voltage 607 (V pri ) (eg, where in some embodiments the primary voltage 607 (V pri ) can be defined as including the inductor voltage of the inductor 16) and the secondary voltage 608 (V sec ) between the relative phase shift (Φ or Φ trap (e.g., variable phase shift or phase shift based on transmit power). Figure 6 In the penultimate graph 605 , the primary voltage 607 is indicated as a solid line, and the secondary voltage 608 is indicated as a dashed line.

[0110] exist Figure 6 In the last graph 606 or bottom graph of , the signal output waveform is associated with the load 24 while the DC-to-DC converter 11 operates in the first control mode 26 .

[0111] Figure 7 is an exemplary graph of operating modes associated with efficiency and power delivered to load 24.

[0112] During an initialization or startup time period of the converter 11, the electronic controller 38 or data processor 32 is configured to control the converter 11 to operate in the first control mode 26. After the initialization or startup time period of the converter 11, the electronic data processor 32 controls the converter 11 to operate efficiently in the first control mode 26, the second control mode 28, or the third control mode 30, wherein the first control mode 26 comprises a phase-shift mode, the second control mode 28 comprises a triangular waveform control mode, and wherein the third control mode 30 comprises a trapezoidal waveform control mode.

[0113] exist Figure 7, each control mode (26, 28, 30) is associated with a corresponding operating region (701, 702, 703) or a corresponding transmission power range. For example, the second control mode 28 (e.g., triangular waveform control mode) is associated with the second region 702 (e.g., rectangular operating region) associated with the lowest transmission power range of the DC-DC converter 11; the third control mode 30 (e.g., trapezoidal waveform control mode) is associated with the third region 703 (e.g., rectangular operating region) having an intermediate transmission power range that is greater than the lowest transmission power range of the DC-DC converter 11; and the first control mode 26 (e.g., phase shift control mode) is associated with the first region 701 (e.g., rectangular operating region) having the highest transmission power range of the DC-DC converter 11. The transition power threshold (36, 136) defines Figure 7 The boundary between two adjacent regions in (e.g., a vertical line segment).

[0114] exist Figure 7 In FIG. 8 , the vertical axis represents the efficiency 90 of the converter, which can be measured as a percentage efficiency. The horizontal axis represents the transmitted power 88, which can be measured, for example, in watts. Figure 7 As shown, the modulation line 705 of the proposed converter 11 is shown as a solid line and represents the data processor 32 or electronic controller 38, which selects the control mode within each corresponding region (701, 702, 703) based on the transmission power (88) of the DC-to-DC converter 11. The existing phase-shift-only modulation of the converter 11 is shown as a dashed line to compare the efficiency of the existing phase-shift mode with the improved efficiency of the three-mode system set forth in the present disclosure.

[0115] Advantageously, the electronic controller 38 or data processor 32 is well suited to select one or more control modes (26, 28, 30) among the available control modes to maximize efficiency. In one embodiment, based on a first voltage sensor 46 ( Figure 1A Middle) and the second voltage sensor 48 ( Figure 1AThe electronic controller 38 or data processor 32 is configured to select a preferred operating mode for a time interval based on whether the DC-to-DC converter is at a transition power level threshold based on the voltage sensor readings of the first voltage sensor (46 or 146) and the second voltage sensor (48 or 148) for the corresponding time interval to provide soft switching (ZVS, ZCS, or both) of the primary switch 58 and the secondary switch 60 to reduce or minimize switching losses. For one or more control modes for each interval, the data processor 32 or electronic controller 38 determines the transfer power based on the observed primary voltage (307, 507, 607) and the observed secondary voltage (308, 508, 608) for the interval and reference parameters of the DC-to-DC converter 11 (which can be stored or retrieved from the data storage device 40) according to the applicable transfer power equation.

[0116] For each time interval, the electronic controller 38 or the data processor 32 evaluates whether the determined transmission power is within an operating region (701, 702, 703), zone, range, or limit (e.g., lower limit, upper limit, or both) of the corresponding control mode (e.g., 26, 28, 30 within the corresponding operating region) or multiple control modes (e.g., at the boundary between operating regions). If the determined transmission power of the converter 11 is within the corresponding operating region (701, 702, 703), the electronic controller 38 or the data processor 32 selects the control mode (26, 28, 30) corresponding to the corresponding operating region as the priority control mode for the time interval.

[0117] In one embodiment, first control mode 26 is associated with a first power range of load 24 that is greater than a second power range of second control mode 28 and a third power range of third control mode 30. Second control mode 28 is associated with a second power range of load 24 that is lower than the first power range of first control mode 26 and lower than the third power range of third control mode 30. Third control mode 30 is associated with a third power range of load 24 that is lower than the first power range of first control mode 26 and greater than the second power range of second control mode 28.

[0118] For example, in the first power range, if the transmission power falls between the second boundary (e.g., approximately 6900 watts) and the third boundary (e.g., the maximum transmission energy under the first control mode 26), the corresponding first region 701 (e.g., the first operating zone) includes the first control mode 26 (e.g., the phase-shift control mode) as the priority control mode. Therefore, the electronic controller 38 or the data processor 32 controls the control signals to the primary switch 58 and the secondary switch 60 to be consistent with any phase offset required for operation under the second control mode 28 as the priority control mode. For example, the phase offsets of the intervals are determined based on a fixed phase offset or another phase offset determined by the data processor 32 based on a data structure (e.g., a lookup table) stored as reference data in the data storage device 40.

[0119] For example, in the second power range, if the transmission power falls between zero and the first boundary (e.g., approximately 3600 watts) or transition power threshold 36, the corresponding second region 702 (e.g., second operating zone) includes the second control mode 28 (e.g., triangle waveform control mode) as the priority control mode. Therefore, the electronic controller 38 or data processor 32 controls the control signals to the primary switch 58 and the secondary switch 60 to be consistent with any phase offset required for operation in the second control mode 28 as the priority control mode. For example, the phase offset is determined based on the phase offset of the second control mode 28 determined by the data processor 32 based on the application of an equation or based on a data structure (e.g., a lookup table) stored as reference data in the data storage device 40.

[0120] For example, in the third power range, if the transmission power falls between the first boundary (e.g., approximately 3600 watts) and the second boundary (e.g., approximately 6900 watts) or between the first transition power threshold 36 and the second transition power threshold 136, the corresponding third region 703 (e.g., third operating zone) includes the third control mode 30 (e.g., trapezoidal waveform control mode) as the priority control mode. Therefore, the electronic controller 38 or the data processor 32 controls the control signals to the primary switch 58 and the secondary switch 60 to be consistent with any phase offset required for operation in the third control mode 30 as the priority control mode. For example, the phase offset is determined based on the phase offset of the third control mode 30 determined by the data processor based on application of an equation or based on a data structure (e.g., a lookup table) stored as reference data in the data storage device 40.

[0121] First, among possible control modes, such as the second control mode 28 and the third control mode 30, the first control mode 26 is the least efficient. The first control mode 26 is the most versatile power transfer range and can replace the second control mode 28 or the third control mode 30, and the associated efficiency loss, even outside the first region 701 (e.g., the first operating region) associated with the first control mode 26 or the phase-shifted control mode. Therefore, assuming the transfer power is less than the maximum allowable transfer power of the DC-DC converter 11, the first control mode 26 can be used for initialization or startup of the DC-DC converter 11 before estimating the transfer power. The first control mode 26 is associated with the lowest ratio of possible soft switching states to all possible switching states, where the lowest ratio is less than the middle ratio (of the possible soft switching states to all possible switching states) and less than the highest ratio (of the possible soft switching states to all possible switching states). For example, in one embodiment, the first control mode 26 or the phase-shifted mode has the fewest soft switching events in the 8 / 16 switching state.

[0122] Secondly, the second control mode 28 or triangle waveform control mode offers the highest potential efficiency because the triangle mode has the most soft switching events or the highest ratio of possible soft switching states to all possible switching states. For example, in one embodiment, the highest ratio is approximately 14 / 16 (possible soft switching states / all possible switching states). However, of the three possible modes, the second control mode 28 or triangle mode is limited to Figure 7 The operating region associated with the lowest power transmission range.

[0123] Third, the third control mode 30 or trapezoidal wave mode is more efficient than the first control mode 26 or phase shift mode. The third control mode 30 is associated with an intermediate ratio of possible soft switching states to all possible switching states, where the corresponding soft switching state / event is less than the highest ratio and greater than the lowest ratio. The third control mode 30 has an intermediate soft switching of possible soft switching states to all possible switching states. For example, in one embodiment, the intermediate level has approximately 12 / 16 (possible soft switching states / all possible switching states). However, the third control mode 30 or trapezoidal mode is limited to Figure 7 An operating region associated with an intermediate power transfer range is between the power transfer ranges of the first mode (eg, phase-shift mode) and the second mode (eg, triangle mode).

[0124] The electronic controller 38 or data processor 32 dynamically determines the transition voltage level between modes based on the maximum achievable power transfer for any corresponding mode. For any mode, the maximum achievable power transfer depends on the DC primary voltage (V1) at the DC primary terminal 84 and the DC secondary voltage (V2) at the DC secondary terminal 86. The DC primary voltage (V1) can be referred to as the primary input voltage of the primary full bridge 10, while the DC secondary voltage (V2) can be referred to as the secondary output voltage of the secondary full bridge 12. In the DC to DC converter 11, the maximum achievable power transfer for the first control mode 26 is P PS，max and described in the previous equations set forth in this disclosure; the maximum achievable power of the second control mode 28 is P TRM，max , and described in the previous equations set forth in this disclosure, the maximum achievable power of the third control mode 30 is P TZM，max , as described in the previous equations set forth in this disclosure.

[0125] In certain applications, the transformer winding ratio and inductance of transformer 14 are constant; wherein the primary input voltage (V1) is varied; and wherein the secondary output voltage (V2) is regulated to a fixed value for a dynamic load.

[0126] In some applications or vehicle configurations, V1 is variable and V2 is fixed. V1 may vary based on the application or transient load 24 conditions on the DC bus shared with V1. Although in some applications or vehicle configurations, the primary voltage, secondary voltage and frequency f s , but n and the inductance L of the transformer 14 do not vary. In one embodiment, the electronic controller 38 or the data processor 32 dynamically determines, at individual time intervals or at continuous time intervals, a transition power level threshold value that is dependent on an observed primary voltage across the transformer primary winding terminal 80 (or the DC primary terminal 84 of the converter) or a fixed or observed secondary voltage across the transformer secondary terminal (or the DC secondary terminal 86 of the converter), wherein the primary voltage varies, wherein the load 24 on the secondary terminal is fixed, and wherein the transformer winding ratio (n) and the inductance of the transformer 14 are constant.

[0127] In one embodiment, the electronic controller 38 or the data processor 32 (e.g., during operation or converter initialization) determines a transition power level threshold for each control mode at a boundary between two adjacent control modes based on a power transfer required by the load 24, a primary transition power level threshold associated with a primary boundary between the second control mode 28 and the third control mode 30, and a secondary transition power level threshold associated with a secondary boundary between the third control mode 30 and the first control mode 26, wherein the primary power level threshold is associated with a power transfer at the secondary output of the secondary full bridge 12 associated with the load 24 that is lower than the secondary power level threshold. In one configuration, the transition power level threshold is associated with a corresponding hysteresis band to avoid subsequent repeated oscillatory switching between the two adjacent regions (701, 702, 703) (or associated corresponding control modes) within a time interval following an initial switch between the two adjacent regions (701, 702, 703) (or associated corresponding control modes). In another configuration, the transition power level threshold is associated with a corresponding hysteresis band to avoid subsequent repeated oscillatory switching between any two respective control modes (26, 28, 30) after an initial switching between the respective control modes (26, 28, 30) (e.g., within a time interval or user-definable time period).

[0128] In some configurations, conduction losses are associated with parameters of the switches (58, 60) in the primary full bridge 10 and the secondary full bridge 12, such as the conduction state, drain-source resistance of the field effect transistors of the respective switches, and wherein the conduction losses may depend on whether the duty cycle of the switches or the modulation duty cycle at the transformer windings or at the switches of the converter varies.

[0129] In any and all operating control modes, current flows in diodes 66 connected in parallel with the primary and secondary switches 60 to support zero voltage turn-on of the primary and secondary switches 60 in any of the three control modes (26, 28, 30). In the second control mode 28 or the third control mode 30, the electronic controller 38 or the data processor 32 is configured to control the high-side switches 64 (S1) of the first pair 50 of primary switches 58 to be in phase with the high-side switches 64 (S5) of the third pair 54 of secondary switches 60. In addition, in the second control mode 28 or in the third control mode 30, the electronic controller 38 or the data processor 32 is configured to control the high-side switches 64 (S3) of the second pair 52 of primary switches 58 to be phase offset with respect to the high-side switches 64 (S7) of the fourth pair 56 of secondary switches 60 to establish voltages in the transformer 14 that can support zero current turn-on and zero current turn-off events (states) of the primary and secondary switches 58, 60. At the control terminal 70 in the first control mode 26, the primary switch 58 has a fixed duty cycle and a variable or fixed phase offset relative to the secondary switch 60. For example, the electronic controller or data processor is configured to control the control terminal in a first control mode based on a target power output (e.g., available at the load 24) such that the primary switch has a fixed duty cycle and a varying phase offset relative to the secondary switch.

[0130] Although the present disclosure has been shown and described in detail in the drawings and the above description, such illustration and description are to be regarded as illustrative rather than restrictive, and it will be understood that exemplary embodiments are shown and described, and that protection is desired for all changes and modifications that fall within the spirit of the present disclosure. It will be noted that alternative embodiments of the present disclosure may not include all of the features described, but still benefit from at least some of the advantages of these features. Those skilled in the art can readily devise their own implementations that incorporate one or more features of the present disclosure and fall within the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A method for controlling a DC to DC converter, wherein: The primary full bridge is coupled to the secondary full bridge via a transformer, the method comprising: controlling the converter to effectively operate in a first control mode, a second control mode, or a third control mode after a startup time period, wherein the first control mode comprises a phase-shift mode, the second control mode comprises a triangular waveform control mode, and wherein the third control mode comprises a trapezoidal waveform control mode; determining a maximum target power range and a transition power level threshold for each control mode; estimating a transition power level threshold based on reference loss data stored in a data storage device, the reference loss data being based on predetermined or simulated converter switching losses and conduction losses associated with different control modes, or based on measurements of observed primary voltage and observed secondary voltage applied to corresponding equations for one or more respective control modes; and managing transitions between two or more control modes based on a maximum target power range and an estimated power level threshold, wherein the control modes apply time-synchronized control signals to respective control terminals of a primary switch in the primary full bridge and a secondary switch in the secondary full bridge, in: a first control mode and a possible switching state associated with a lowest ratio corresponding to a soft switching event, the lowest ratio being less than a middle ratio of the possible switching states and a highest ratio of the possible switching states; The second control mode and possible switching states are associated with the highest ratio of corresponding soft switching events; The third control mode and possible switching states are associated with an intermediate ratio corresponding to soft switching events, the intermediate ratio being smaller than the highest ratio and larger than the lowest ratio.

2. The method according to claim 1, wherein The converter includes a single-phase dual active bridge direct current (DC) to DC converter having a DC input at a primary full bridge and a DC output at a secondary full bridge.

3. The method according to claim 1, further comprising: During a startup time period, the converter is controlled to operate in a first control mode.

4. The method according to claim 1, wherein Estimating the transition power level threshold determined at runtime includes selecting an optimal control mode among the control modes to provide maximum soft switching of the primary switch and the secondary switch to reduce or minimize switching losses.

5. The method according to claim 1, wherein The primary switches include a first pair of switches for a first phase and a second pair of switches for a second phase, the first pair having a complementary phase offset (i.e., 180 degrees) relative to the second pair in a first control mode; within each of the first and second pairs of primary switches, the high-side switch has a complementary phase offset relative to the low-side switch and a 50% duty cycle; The secondary switches include a third pair of switches for the third phase and a fourth pair of switches for the fourth phase, wherein in the first control mode, the third pair has a complementary phase offset relative to the fourth pair, i.e., a 180-degree offset; within each of the third and fourth pairs of primary switches, the high-side switch has a complementary phase offset relative to the low-side switch and a 50% duty cycle.

6. The method according to claim 1, wherein The primary switches include a first pair of switches for a first phase and a second pair of switches for a second phase, the first pair having a non-complementary phase offset (non-180 degree offset) relative to the second pair in the second control mode and in the third control mode; and within each of the first and second pairs of primary switches, the high-side switches have a complementary phase offset relative to the low-side switches and a 50% duty cycle. The secondary switches include a third pair of switches for the third phase and a fourth pair of switches for the fourth phase, the third pair having a non-complementary phase offset, i.e., non-180 degree offset, relative to the fourth pair in the second control mode and the third control mode; Within each of the third and fourth pairs of primary switches, the high-side switch has a complementary phase offset relative to the low-side switch and a 50% duty cycle.

7. The method according to claim 1, wherein In the second control mode and the third control mode, the high-side switches of the first pair of primary switches are in phase with the high-side switches of the third pair of secondary switches, and wherein the high-side switches of the second pair of primary switches are phase-offset with the high-side switches of the fourth pair of secondary switches to establish a voltage in the transformer to support zero current turn-on and zero current turn-off events of the primary switches and the secondary switches.

8. The method according to claim 1, wherein Current flows in diodes in parallel with the primary and secondary switches to support zero voltage turn-on of the primary and secondary switches in any of the described control modes.

9. The method according to claim 1, wherein The transition power level threshold is dynamically determined and depends on a primary input voltage across the primary input terminal or a secondary output voltage across the secondary output terminal, wherein the transformer winding ratio and inductance of the transformer are constant; wherein the primary input voltage is variable, and wherein the secondary output voltage is regulated to a fixed value for a dynamic load.

10. The method according to claim 1, wherein At the control terminal in the first control mode, the primary switch has a fixed duty cycle and a variable phase offset relative to the secondary switch based on a target power output.

11. The method according to claim 1, wherein The first control mode is associated with a first power range of the load, the first power range being greater than a second power range of the second control mode and a third power range of the third control mode.

12. The method according to claim 1, wherein The second control mode is associated with a second power range of the load that is lower than the first power range of the first control mode and lower than a third power range of the third control mode.

13. The method according to claim 1, wherein The third control mode is associated with a third power range of the load, which is lower than the first power range of the first control mode and greater than the second power range of the second control mode.

14. The method according to claim 1, wherein When the converter is operating, a transition power level threshold is determined for each control mode as the boundary between two adjacent control modes, based on the power transfer required by the load, a primary transition power level threshold associated with the primary boundary between the second control mode and the third control mode, and a secondary transition power level threshold associated with the secondary boundary between the third control mode and the first control mode, wherein the primary power level threshold is associated with a power transfer associated with the load at the secondary output of the secondary full bridge that is lower than the secondary power level threshold.

15. The method according to claim 1, wherein The transition power level threshold is associated with a corresponding hysteresis band to avoid subsequent repetitive oscillatory switching between the two control modes after an initial switching between the two control modes.

16. The method according to claim 1, wherein The conduction loss is associated with parameters of the switches, including the conduction state and drain-source resistance of the field effect transistors of each switch in the primary full bridge and the secondary full bridge, and the conduction loss may depend on whether the duty cycle of the switch changes.

17. A system for controlling a DC-to-DC converter, the system comprising: a primary full bridge comprising a first pair of primary switches and a second pair of primary switches coupled between DC input terminals of the primary full bridge; a secondary full bridge comprising a third pair of secondary switches and a fourth pair of secondary switches coupled between DC output terminals of the secondary full bridge; a transformer connected between the primary full bridge and the secondary full bridge, the primary winding of the transformer connected to the output terminals of the first and second pairs of primary switches, and the secondary winding of the transformer connected to the output terminals of the secondary switches; a load for coupling to the DC output terminal; wherein the electronic controller is configured to provide time-synchronized control signals to control terminals of the primary switch and the secondary switch to control the converter to effectively operate in a first control mode, a second control mode, or a third control mode, wherein the first control mode includes a phase-shift mode, the second control mode includes a triangular waveform control mode, and wherein the third control mode includes a trapezoidal waveform control mode; an electronic controller configured to determine a maximum target power range and a transition power level threshold for each control mode; the electronic controller being configured to estimate the transition power level threshold based on reference loss data stored in the data storage device, the reference loss data being based on predetermined or simulated converter switching losses and conduction losses associated with different control modes, measurements of the observed primary voltage and the observed secondary voltage based on corresponding equations for one or more respective control modes; and The electronic controller manages transitions in and between the plurality of control modes based on the maximum target power range and the estimated power level thresholds.

18. The system according to claim 17, wherein: At the control terminal in the first control mode, the primary switch has a fixed duty cycle based on the target power output and a variable phase offset relative to the secondary switch.

19. The system of claim 17, wherein: a first control mode and a possible switching state associated with a lowest ratio corresponding to a soft switching event, the lowest ratio being less than a middle ratio of the possible switching states and a highest ratio of the possible switching states; The second control mode and possible switching states are associated with the highest ratio of corresponding soft switching events; The third control mode and possible switching states are associated with an intermediate ratio corresponding to soft switching events, the intermediate ratio being smaller than the highest ratio and larger than the lowest ratio.

20. The system of claim 17, wherein: The primary switches include a first pair of switches for a first phase and a second pair of switches for a second phase, the first pair having a complementary phase offset (180 degrees offset) relative to the second pair in a first control mode; within each of the first and second pairs of primary switches, a high-side switch has a complementary phase offset relative to a low-side switch and a 50% duty cycle; The secondary switches include a third pair of switches for the third phase and a fourth pair of switches for the fourth phase, wherein in the first control mode, the third pair has a complementary phase offset relative to the fourth pair, i.e., a 180-degree offset; within each of the third and fourth pairs of primary switches, the high-side switch has a complementary phase offset relative to the low-side switch and a 50% duty cycle.

21. The system of claim 17, wherein: The primary switches include a first pair of switches for a first phase and a second pair of switches for a second phase, the first pair having a non-complementary phase offset (non-180 degree offset) relative to the second pair in the second control mode and in the third control mode; and within each of the first and second pairs of primary switches, the high-side switches have a complementary phase offset relative to the low-side switches and a 50% duty cycle. The secondary switches include a third pair of switches for a third phase and a fourth pair of switches for a fourth phase, wherein in the second control mode and the third control mode, the third pair has a non-complementary phase offset relative to the fourth pair; within each of the third and fourth pairs of primary switches, the high-side switch has a complementary phase offset relative to the low-side switch and a 50% duty cycle.

22. The system of claim 17, wherein: For the second control mode and the third control mode, the high-side switches of the first pair of primary switches are in phase with the high-side switches of the third pair of secondary switches, and wherein the high-side switches of the second pair of primary switches are phase offset with the high-side switches of the fourth pair of secondary switches to establish a voltage in the transformer to support zero current turn-on and zero current turn-off events of the primary switches and the secondary switches.

23. The method according to claim 1, wherein Current flows in diodes in parallel with the primary and secondary switches to support zero voltage turn-on of the primary and secondary switches in any of the described control modes.

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