Power management circuit and method for an integrated circuit having multiple power domains

Abstract

The present application discloses a power management circuit and a method for managing an integrated circuit. The power management circuit includes an inverter circuit and a latch circuit. The inverter circuit receives a first control signal from an inverter input terminal and generates a second control signal at an inverter output terminal. The first control signal carries power status information of a first power supply voltage. The latch circuit has a latch power supply terminal, a first latch input terminal and a second latch input terminal. The latch power supply terminal is coupled to a second power supply voltage, and the second power supply voltage is ready earlier than the first power supply voltage. The first latch input terminal and the second latch input terminal are respectively coupled to the inverter output terminal and the inverter input terminal. The latch circuit generates a third control signal according to the respective signal levels of the first control signal and the second control signal, and performs power control of the integrated circuit accordingly. The power management circuit can reduce chip area and power consumption.

Description

Technical Field

[0001] The present application relates to power management, and more particularly to a power management circuit for an integrated circuit having multiple power domains, and a method for managing an integrated circuit having multiple power domains. Background Art

[0002] System-on-chip (SoC) design can realize multiple functions by integrating different circuit blocks (including analog and digital circuits) into a single chip. In order to reduce power consumption, the system-on-chip can be divided into different power domains, where different power domains can withstand different voltage levels. A power domain refers to a collection of hierarchical instances that share the same power supply. For example, each circuit block can operate at a suitable voltage level to reduce dynamic and static power consumption. In addition, unused power domains can be turned off so that the circuit blocks located therein can be disabled to reduce leakage power consumption. Summary of the invention

[0003] Embodiments of the present application disclose a power management circuit for an integrated circuit having multiple power domains, and a power management scheme including power-on control and power isolation in a circuit design having multiple power domains.

[0004] Certain embodiments of the present application disclose a power management circuit for an integrated circuit. The power management circuit includes an inverter circuit and a latch circuit. The inverter circuit has an inverter input terminal and an inverter output terminal. The inverter circuit is used to receive a first control signal from the inverter input terminal and generate a second control signal at the inverter output terminal, wherein the first control signal carries power state information of a first power supply voltage supplied to the integrated circuit. The latch circuit has a latch power supply terminal, a first latch input terminal and a second latch input terminal. The latch power supply terminal is coupled to a second power supply voltage supplied to the integrated circuit. The second power supply voltage is ready earlier than the first power supply voltage. The first latch input terminal is coupled to the inverter output terminal to receive the second control signal. The second latch input terminal is coupled to the inverter input terminal to receive the first control signal. The latch circuit is used to generate a third control signal according to the signal levels of the first control signal and the second control signal, and perform power control of the integrated circuit accordingly.

[0005] Certain embodiments of the present application disclose a power management circuit for an integrated circuit. The power management circuit includes a level converter and an output buffer. The level converter is powered by at least a first power supply voltage that can be used in a first power domain of the integrated circuit. The level converter is used to convert a first control signal into a second control signal that can be used in the first power domain. The first control signal indicates a power state of a second power supply voltage that can be used in a second power domain of the integrated circuit. The first power supply voltage is ready earlier than the second power supply voltage. The second power domain is different from the first power domain. The output buffer is coupled to the level converter to buffer the second control signal to generate a third control signal, and to perform power control of the integrated circuit accordingly.

[0006] Certain embodiments of the present application disclose a method for managing an integrated circuit. The method includes: operating a level converter at a first power supply voltage supplied to a first power domain of the integrated circuit, wherein the first power domain is used to receive an input signal from a second power domain of the integrated circuit, and the second power domain is powered by the second power supply voltage; when the first power supply voltage is ready and the second power supply voltage is not ready, using the level converter to convert a first control signal into a second control signal having a first logic level to isolate the second power domain from the first power domain, wherein the first control signal at least indicates the power state of the second power supply voltage; and when both the first power supply voltage and the second power supply voltage are ready, using the level converter to convert the first control signal into the second control signal having a second logic level to allow the first power domain to receive the input signal from the second power domain.

[0007] The power management scheme disclosed in the present application can perform power control operations on integrated circuits, such as power-on control operations or power isolation, while achieving zero quiescent current. In addition, the power management scheme disclosed in the present application can use a single control signal to isolate different power domains, thereby reducing circuit chip area and power consumption. The physical layer of the integrated circuit can allow different power-on / off sequences. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an integrated circuit including multiple power domains according to an embodiment of the present application. Figure 2 It is a functional block diagram of an embodiment of at least a part of the power management circuit of the present application.

[0009] Figure 3 yes Figure 2 A schematic diagram of a specific implementation of a power management circuit is shown.

[0010] Figure 4 yes Figure 3 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of a power management circuit.

[0011] Figure 5 yes Figure 2 A schematic diagram of another specific implementation of a power management circuit is shown.

[0012] Figure 6 yes Figure 5 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of a power management circuit.

[0013] Figure 7 yes Figure 2 A schematic diagram of another specific implementation of a power management circuit is shown.

[0014] Figure 8 yes Figure 7 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of a power management circuit.

[0015] Fig. 9 yes Figure 1 A schematic diagram of a specific embodiment of an integrated circuit is shown.

[0016] Fig.10 yes Figure 2 A schematic diagram of another specific implementation of a power management circuit is shown.

[0017] Fig.11 yes Fig.10 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of a power management circuit.

[0018] Fig.12 yes Fig.10 FIG. 1 is a schematic diagram of another embodiment of signal waveforms involved in the operation of a power management circuit.

[0019] Fig.13 yes Figure 2 A schematic diagram of another specific implementation of a power management circuit is shown.

[0020] Fig.14 yes Fig.13 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of a power management circuit.

[0021] Fig.15 yes Fig.13FIG. 1 is a schematic diagram of another embodiment of signal waveforms involved in the operation of a power management circuit.

[0022] Fig.16 yes Figure 2 A schematic diagram of another specific implementation of a power management circuit is shown.

[0023] Fig.17 It is a flow chart of an embodiment of a method for managing an integrated circuit of the present application. DETAILED DESCRIPTION

[0024] The following disclosure discloses a variety of implementations or illustrations that can be used to implement different features of the present application. The specific examples of parameter values, components and configurations described below are used to simplify the present application. As can be imagined, these descriptions are only examples and are not intended to limit the present application. For example, the present application may reuse component symbols and / or labels in multiple embodiments. This repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0025] In addition, it will be understood that if a component is described as being “connected to” or “coupled to” another component, the two components may be directly connected or coupled, or other intervening components may be present between the two components.

[0026] In a circuit system with multiple power domains, power-supply sequencing is used to reduce transient inrush current to a tolerable level. Incorrect power-supply sequencing can cause damage to the circuit system. For example, in the case of unwanted propagation of signals between the power-down domain and the power-on domain, the functioning block in the power-on domain will receive an input signal with an unknown state from the power-down domain, which will cause a large inrush current to be generated in the functioning block. In order to reduce leakage power consumption, power isolation is performed using a control signal dedicated to the power-on domain to disconnect the functioning blocks in the power-down domain and the power-on domain. However, since each power domain requires its own dedicated control signal, a circuit design with multiple different power domains requires a large number of control signals, thereby increasing chip area and power consumption.

[0027] Another issue of concern is the power consumption of power-on control (POC), which includes power-on reset (POR) and brownout detection (BOD). For example, after a circuit system powered by a supply voltage is started, the power-on control circuit (POC circuit) can put the circuit system in a reset state until the supply voltage is stable. When the supply voltage is stable, the power-on control circuit can release the circuit system from the reset state and initialize the circuit system. However, the power-on control circuit consumes non-zero quiescent current. In low-power applications, the power consumption caused by this non-zero quiescent current accounts for a large part of the overall power consumption.

[0028] The present application discloses a plurality of power management circuits for an integrated circuit, wherein the integrated circuit may have a plurality of power domains, including a first power domain powered by a first power voltage and a second power domain powered by a second power voltage. The plurality of power management circuits may perform power control of the integrated circuit according to the second power voltage and a control signal, wherein the control signal may carry power status information of the first power voltage. The second power voltage may be ready earlier than the first power voltage, or may become an available power voltage earlier than the first power voltage. In some embodiments, the power control includes (but is not limited to) power-on reset, power-off detection, and power isolation between different power domains. In some embodiments, the control signal may be a delayed version of the first power voltage, a power status signal indicating whether the first power voltage is ready, or other control signals capable of carrying power status information of the first power voltage.

[0029] In some embodiments, at least one power management circuit may include a latch circuit controlled by the control signal. In some embodiments, at least one power management circuit may include a level shifter controlled by the control signal. In some embodiments, the level shifter may be implemented using a latch-type level shifter, a single-ended level shifter, or other types of level shifters. In some embodiments, at least one power management circuit may use the same control signal to implement power isolation between any two of a plurality of power domains of the integrated circuit. Additionally, or alternatively, at least one power management circuit may consume zero transient current during a power control operation. Further description is as follows.

[0030] See also Figure 1, which shows an integrated circuit 10 including multiple power domains 11 and 12 of certain embodiments of the present application. The multiple power domains 11 and 12 are powered by different power supply voltages VCC1 and VCC2, respectively. When the power domain 11 is powered up, it will take some time for the power supply voltage VCC1 to become an available or ready power supply voltage. Similarly, when the power domain 12 is powered up, it will take some time for the power supply voltage VCC2 to become an available or ready power supply voltage. The multiple power supply voltages VCC1 and VCC2 can all be provided by a power control module (PCM) 16 located in the always-on power domain. The power control module 16 can be an on-chip PCM in the integrated circuit 10, or an off-chip PCM outside the integrated circuit 10. In some embodiments, one of the multiple power supply voltages VCC1 and VCC2 may be a core voltage at which a processor core operates, and another of the multiple power supply voltages VCC1 and VCC2 may be an input / output voltage (I / O voltage) at which an input / output circuit (I / O circuit) operates. The processor core may be used to control the input / output circuit.

[0031] The power management circuit 100 is coupled to a plurality of power domains 11 and 12, and can be used to perform power control of the integrated circuit 10 according to the power voltage VCC2 and a control signal CS, wherein the control signal CS carries power status information of the power voltage VCC1. The power control performed by the power management circuit 100 may include (but is not limited to) power-on reset, power-off detection, and power isolation between the plurality of power domains 11 and 12, wherein the power isolation may be referred to as power gating or power shut-off (PSO). For example, in certain embodiments where the power voltage VCC2 is ready earlier than the power voltage VCC1, the power management circuit 100 may detect whether the power voltage VCC1 is ready according to the power voltage VCC2 and the control signal CS, and perform power-on control operation on the integrated circuit 10 accordingly. In addition, alternatively, in certain embodiments where the power supply voltage VCC2 operative in the power domain 12 is ready earlier than the power supply voltage VCC1 operative in the power domain 11 , the power management circuit 100 can selectively isolate the power domain 11 from the power domain 12 based on the power supply voltage VCC2 and the control signal CS.

[0032] The control signal CS may be implemented using (but not limited to) a power supply voltage VCC1, a delayed version of the power supply voltage VCC1, or other power status signals that can indicate whether the power supply voltage VCC1 is ready. For example, the power status signal may indicate whether the power supply voltage VCC1 has reached a threshold level. When the voltage level of the power supply voltage VCC1 is lower than the threshold level, the power supply voltage VCC1 is not ready. When the voltage level of the power supply voltage VCC1 reaches or exceeds the threshold level, the power supply voltage VCC1 is ready. In some embodiments, the control signal CS may be implemented using a power status signal that can indicate whether both the power supply voltage VCC1 and the power supply voltage VCC2 are ready. For example, the control signal CS may be implemented using a power status signal provided by a normally-open power domain.

[0033] In this embodiment, the power management circuit 100 may be implemented as an on-chip circuit in the integrated circuit 10. However, this is not intended to limit the scope of protection of the present application. In some embodiments, the power management circuit 100 may be implemented as an off-chip circuit outside the integrated circuit 10. In some embodiments, the power management circuit 100 may be integrated into the power control module 16 without departing from the scope of protection of the present application.

[0034] Figure 2 FIG. 2 is a functional block diagram of an embodiment of a power management circuit of the present application. The power management circuit 200 can be used to implement Figure 1 The power management circuit 200 includes (but is not limited to) an inverter circuit 210 and a latch circuit 220. The inverter circuit 210 has an inverter input terminal T I and an inverter output terminal T O The inverter circuit 210 can be used to generate a voltage from the inverter input terminal T I The control signal CS is received and a control signal CSB is generated at the inverter output terminal TO.

[0035] The latch circuit 220 has a latch supply terminal T SL , a latch input terminal T I1 and a latch input terminal T I2 . Latch power supply terminal T SL Coupled to the power supply voltage VCC2. Latch input terminal T I1 and the latch input terminal T I2 are respectively coupled to the inverter output terminal TO and the inverter input terminal T I The latch circuit 220 can be used to generate a latch input terminal T I1 and the latch input terminal T I2 The respective signal levels generate a control signal S OUTB , and based on this Figure 1 The power supply control of the integrated circuit 10 shown in FIG. 1 is to say that the latch circuit 220 can be used to control the power supply of the integrated circuit 10 according to the input to the latch input terminal T I1 The control signal CSB is input to the latch input terminal T I2 The control signal CS generates the control signal S OUTB In some embodiments, the control signal S OUTB and the supply voltage VCC2 can be used in the same power domain.

[0036] Since the control signal CS carrying the power state information of the power supply voltage VCC1 is input to the latch circuit 220, the control signal S output from the latch circuit 220 OUTB The power state information may be presented. For example, the power state information may indicate the voltage level of the power voltage VCC1 or the power state of the power voltage VCC1, such as whether the power voltage VCC1 is ready. In addition, when the power voltage VCC2 reaches a threshold level and thus becomes a ready power voltage, the latch circuit 220 may start to operate properly. Therefore, the control signal S OUTB It can also indicate whether the power supply voltage VCC1 and the power supply voltage VCC2 are both ready.

[0037] In some embodiments, when the power status information indicates that the power supply voltage VCC1 is not ready, the latch input terminal T I1 and the latch input terminal T I2 The signal level of each signal will be higher than the latch input T I1 and the latch input terminal T I2 The respective signal levels are the other signal levels of the two control signals S OUTB The latch input terminal T may have a first level, such as one of a logic high level and a logic low level. When the power status information indicates that the power supply voltage VCC1 is ready, the latch input terminal T I1 and the latch input terminal T I2 One of the signal levels of the two respective signal levels will be lower than the latch input terminal T I1 and the latch input terminal T I2 The respective signal levels of both control signals S OUTBThe control signal S may have a second level different from the first level, such as the other of the logic high level and the logic low level. Therefore, when the power supply voltage VCC2 is ready earlier than the power supply voltage VCC1, the control signal S OUTB The power supply voltage VCC1 may have different levels before and after it becomes a ready power supply voltage.

[0038] For example, when the power status information indicates that the power supply voltage VCC1 is not yet ready, the signal level of the control signal CSB generated from the inverter circuit 210 may be higher than the signal level of the control signal CS. When the power status information indicates that the power supply voltage VCC1 is ready, the signal level of the control signal CSB may be lower than the signal level of the control signal CS. For another example, when the power status information indicates that the power supply voltage VCC1 is not yet ready, the signal level of the control signal CSB generated from the inverter circuit 210 may be lower than the signal level of the control signal CS. When the power status information indicates that the power supply voltage VCC1 is ready, the signal level of the control signal CSB may be higher than the signal level of the control signal CS.

[0039] In this embodiment, the power management circuit 200 may further include an output buffer 230, which may be used to buffer the control signal S OUTB To generate a control signal S OUT The power management circuit 200 can be configured to generate a power supply according to the control signal S OUT conduct Figure 1 In some embodiments, the output buffer 230 can be used to reduce the loading effect and / or change the control signal S OUTB The output buffer 230 may be implemented using (but not limited to) a buffer amplifier, a voltage follower, or an inverter circuit. In some embodiments, the output buffer 230 may be omitted. The power management circuit 200 may directly output the control signal S OUTB , thus Figure 1 In some embodiments, the control signal S output from the latch circuit 220 is a power control signal of the integrated circuit 10 shown in FIG. OUTB The operative power domain may be different from the operative power domain of the control signal CS input to the inverter circuit 210. For example (but the present application is not limited thereto), the control signal CS may be implemented using the power voltage VCC1 or a delayed version of the power voltage VCC1, wherein the power voltage VCC1 is applicable to the power domain 11 (i.e., the power voltage VCC1 can be used in the power domain 11), which is different from the control signal S OUTBThe applicable power domain 12 (ie, the control signal S OUTB For example, the control signal CS may be implemented using a power status signal provided by a normally-on power domain different from the power domain 12. Therefore, the inverter circuit 210 and the latch circuit 220 may be implemented as at least a portion of a level converter 202, wherein the level converter 202 may be used to convert the control signal CS into a control signal S that may be used in the power domain 12. OUTB The control signal CS may be used in a power domain different from the power domain 12. In this embodiment, the level converter 202 may be considered as a latching level converter. In some embodiments, the power management scheme disclosed in the present application may utilize a single-ended level converter or other types of level converters to generate the control signal S OUTB , without departing from the protection scope of this application. The relevant description will be given later.

[0040] Please also read Figure 1 and Figure 2 In some embodiments, the power management circuit 200 can be configured to generate a power supply according to the control signal S OUTB / S OUT , performs power-on control operation on the integrated circuit 10. The latch circuit 220 operates at the power supply voltage VCC2, which can be ready earlier than the power supply voltage VCC1. When the power status information carried by the control signal CS indicates that the power supply voltage VCC1 is not ready, the latch circuit 220 can be used to generate the control signal S OUTB , to keep the integrated circuit 10 in a reset state. For example, the latch circuit 220 may generate a control signal S having a first level. OUTB , so as to keep at least one circuit block operating in the power domain 12 in a reset state, and / or keep at least one circuit block operating in the power domain 11 in a reset state. When the power state information carried by the control signal CS indicates that the power voltage VCC1 is ready, the latch circuit 220 can be used to generate the control signal S OUTB , to release the integrated circuit 10 from the reset state. For example, the latch circuit 220 may generate a control signal S having a second level. OUTB , so as to release the at least one circuit block operating in the power domain 12 from the reset state, and / or release the at least one circuit block operating in the power domain 11 from the reset state.

[0041] In some embodiments, the power management circuit 200 can be configured to generate a power supply according to the control signal S OUTB / S OUT, providing power isolation between different power domains in the integrated circuit 10. For example, the latch circuit 220 can operate at the power voltage VCC2, which can be ready earlier than the power voltage VCC1. When the power status information carried by the control signal CS indicates that the power voltage VCC1 used by the power domain 11 is not ready, the latch circuit 220 can be used to generate the control signal S OUTB , to isolate the power domain 11 from a portion of the integrated circuit 10. The portion of the integrated circuit 10 operates in the power domain 12. When the power status information carried by the control signal CS indicates that the power voltage VCC1 used by the power domain 11 is ready, the latch circuit 220 can be used to generate the control signal S OUTB , to allow the power domain 11 to be coupled to the portion of the integrated circuit 10 .

[0042] It is worth noting that the power management scheme disclosed in the present application can perform power-on control operations or power isolation under the condition of achieving zero quiescent current. For example, when multiple power supply voltages VCC1 and power supply voltages VCC2 are ready or stable, the inverter circuit 210 and the latch circuit 220 can consume zero transient current.

[0043] To facilitate understanding of the content of this application, the power management solution disclosed in this application is further described below based on certain embodiments. First, the power management solution disclosed in this application is described by using the application of power-on control. Figure 3 Shows Figure 2 In this embodiment, the power management circuit 300 can be used to Figure 1 The integrated circuit 10 shown performs power-on control operations. The power-on control operations may include (but are not limited to) power-on reset and power-off detection. The power management circuit 300 may include an inverter circuit 310, a latch circuit 320, an output buffer 330, a resistive element 340, and a delay element 350. The inverter circuit 310, the latch circuit 320, and the output buffer 330 may be respectively used as Figure 2 An embodiment of an inverter circuit 210, a latch circuit 220, and an output buffer 230 is shown.

[0044] In this embodiment, the inverter circuit 310 may use a plurality of transistors M PI and M NI To implement. Multiple transistors M PI and M NI The gates of the inverter circuit 310 are connected to the inverter input terminal T I . Multiple transistors M PI and M NIThe respective drains are coupled to the inverter output terminal T O . Transistor M PI The source of the inverter circuit 310 is coupled to the inverter power supply terminal T SI . Transistor M NI The source of is coupled to a reference voltage, such as a ground voltage.

[0045] The latch circuit 320 can be used as a comparator having a non-inverting input terminal and an inverting input terminal. I1 and the latch input terminal T I2 can be used as the non-inverting input terminal and the inverting input terminal respectively. Therefore, when the latch input terminal T I1 The signal level is higher than the latch input T I2 The signal level from the latch output terminal T OL The output control signal S OUTB Can have a high level or a logic high level. When the latch input terminal T I1 The signal level is lower than the latch input T I2 The signal level from the latch output terminal T OL The output control signal S OUTB Can have a low level or logic low level.

[0046] The output buffer 330 is coupled to the latch circuit 320 to buffer the control signal S OUTB To generate a control signal S OUT In this embodiment, the output buffer 330 can be implemented by an inverter circuit operating at the power supply voltage VCC2. Therefore, the power management circuit 300 can use the control signal S OUTB The inverted signal, that is, the control signal S OUT , to perform power-on control operations.

[0047] The resistor unit 340 is coupled to the power supply voltage VCC2 and the inverter power supply terminal T SI between the resistor unit 340 according to a current signal I R Produces a voltage drop V D In some embodiments, the resistance unit 340 can be implemented using at least one resistor, at least one diode, at least one diode-connected transistor, at least one circuit unit capable of providing electrical resistance, and combinations thereof.

[0048] The delay unit 350 is coupled to the inverter input terminal T I, for receiving the power supply voltage VCC1 and outputting a delayed version of the power supply voltage VCC1 to the inverter input terminal T I The delayed version of the power supply voltage VCC1, hereinafter referred to as the power supply voltage VCCR1, may carry power supply status information indicating the voltage level of the power supply voltage VCC1. The power supply voltage VCCR1 may be used as Figure 2 The control signal CS is shown in the embodiment. From the inverter output terminal T O Output voltage signal V COM Available as Figure 2 An embodiment of the control signal CSB is shown.

[0049] Figure 4 Shows Figure 3 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of the power management circuit 300. Figure 1 , Figure 3 See also Figure 4 At time point t0, the power control module 16 may start (power up) the power domain 12, and the power voltage VCC2 begins to rise. Since the power voltage VCC2 is not ready (unready), the power management circuit 300 may keep the integrated circuit 10 in a reset state. For example, the output buffer 330 may control the signal S OUTB Inverting to generate a control signal S with a logic low level OUT , so that one or more circuit blocks operating in the power domain 12 are in a reset state.

[0050] Between time point t0 and time point t1, since the power supply voltage VCCR1 / VCC1 is at a low level, the transistor M PI can be turned on, and transistor M NI can be turned off. Applying a latch input T I1 The voltage signal V COM When the power supply voltage VCC2 reaches a threshold level, so that the latch circuit 320 can operate correctly, since the power supply voltage VCC1 and the power supply voltage VCC2 are not ready yet, the control signal S OUT Still at the logic low level.

[0051] At time point t1, the power supply voltage VCC2 reaches a nominal / rated level, such as 3.3V. COM may have a voltage equal to or approximately equal to the rated level minus the voltage drop V DIn addition, the power control module 16 can start the power domain 11, and the power supply voltage VCC1 / VCCR1 starts to rise. Between the time point t1 and the time point t2, due to the latch input terminal T I1 The signal level (voltage signal V COM The voltage level of the latch input terminal T I2 The signal level (the voltage level of the power supply voltage VCCR1) is high enough, so the control signal S OUTB It may have a logic high level, such as 3.3V. The control signal S OUT may be at the logic low level.

[0052] At time t2, the power supply voltage VCC1 reaches or exceeds a threshold level V CT1 , so that transistor M NI Can be turned on. Voltage signal V COM can be reduced to zero or substantially zero. For example (but the present application is not limited thereto), when the power supply voltage VCCR1 ramps up / gradually rises (ramp up) to the transistor M NI When the power supply voltage VCC1 reaches the threshold voltage V CT1 In addition, the latch input terminal T I1 and the latch input terminal T I2 The difference between the respective signal levels, such as |V COM -VCCR1|, will reach or exceed a transition threshold. OUTB The control signal S may be changed from the logic high level to the logic low level, thereby indicating that the power supply voltage VCC1 is ready. The power management circuit 300 may release the integrated circuit 10 from the reset state. For example, the output buffer 330 may control the signal S OUTB Inverting to generate a control signal S having the logic high level (such as 3.3V) OUT , thereby releasing the one or more circuit blocks integrated circuit 10 operating in the power domain 12 from the reset state. Between time point t2 and time point t3, the control signal S OUTB can be at the logic low level, the control signal S OUT The transistor M may be at the logic high level. PI During the period when both the power supply voltage VCC1 and the power supply voltage VCC2 are ready, the power management circuit 300 consumes zero transient current.

[0053] At time point t3, for example, due to a power failure, the power supply voltage VCC1 drops below or reaches a threshold level V CT2 . Transistor MNI can be turned off, and transistor M PI Can be turned on. Voltage signal V COM can be increased to be equal to or substantially equal to the nominal level of the power supply voltage VCC2 minus the voltage drop V D For example (but the present application is not limited thereto), when the power supply voltage VCCR1 ramps down / gradually decreases (ramp down) to the voltage level of transistor M NI When the power supply voltage VCC1 reaches the threshold voltage V CT2 . Control signal S OUTB The control signal S may be changed from the logic low level to the logic high level, thereby indicating that the power supply voltage VCC1 is not ready. The power management circuit 300 may put the integrated circuit 10 in a reset state. For example, the output buffer 330 may control the control signal S OUTB Inverting to generate a control signal S having the logic low level OUT , thereby keeping the one or more circuit block integrated circuits 10 operating in the power domain 12 in a reset state.

[0054] The above is based on Figure 3 and Figure 4 The circuit structure and operation described above are for the purpose of convenience of explanation and are not intended to limit the scope of protection of the present application. SI The latch input terminal T may be directly coupled to a power supply voltage, wherein the power supply voltage may be ready earlier than the power supply voltage VCC1 and have a nominal / rated voltage level lower than the nominal / rated voltage level of the power supply voltage VCC2. I1 and the latch input terminal T I2 The output buffer 330 may be implemented by other types of buffers (such as a voltage follower). In some embodiments, the output buffer 330 may be omitted. The power management circuit 300 may directly output the control signal S OUTB In some embodiments, the delay unit 350 may be omitted. The power supply voltage VCC1 may be directly input to the inverter input terminal T I and the latch input terminal T I2 These modifications and variations are all included in the protection scope of this application.

[0055] In some embodiments, the delay unit 350 can be used to ensure that the power supply voltage VCC1 is within the control signal S OUTWhen the control signal S is changed to the high logic level, it is already in a stable state. For example, when the power supply voltage VCCR1 ramps up to a voltage level, since the power supply voltage VCCR1 is a delayed version of the power supply voltage VCC1, the power supply voltage VCC1 may have risen to a voltage level higher than the voltage level. Therefore, when the control signal S OUT When the power supply voltage VCC1 is changed from the low logic level to the high logic level to indicate that the power supply voltage VCC1 is ready, the power supply voltage VCC1 is closer to the rated level of the power supply voltage VCC1, such as 1.2V, than the power supply voltage VCCR1.

[0056] See also Figure 5 , in certain embodiments, Figure 3 The delay unit 350 shown in the figure can be implemented using a delay unit 550, wherein the delay unit 550 includes a resistor R D1 and a transistor M D1 In this embodiment, the resistor R D1 is coupled to the power supply voltage VCC1 to provide the power supply voltage VCCR1. D1 The gate of transistor M is coupled to the power supply voltage VCCR1. D1 The drain and source of transistor M are short-circuited to each other. D1 The delay unit 550 can be used as a resistor-capacitor delay unit (RC delay element). In addition, the resistor unit 540 of the power management circuit 500 can be used as a resistor-capacitor delay unit (RC delay element). Figure 3 The resistor unit 540 includes a plurality of diode-connected transistors M connected in series. R1 -M R3 When multiple diodes are connected to form a transistor M R1 -M R3 When each diode-connected transistor is turned on, the voltage drop V D It can be approximately equal to a number of diode-connected transistors M R1 -M R3 The sum of their respective threshold voltages.

[0057] In this embodiment, the power management circuit 500 may further include a transistor M L , which can be used as a latch power supply terminal T coupled to the latch circuit 320 SL The latch output T OL During the ramp-up period of the power supply voltage VCC2, the latch output terminal T OL The signal level can be achieved by using transistor M LAnd is pulled up to the power supply voltage VCC2.

[0058] Figure 6 Shows Figure 5 FIG. 5 is a schematic diagram of an embodiment of signal waveforms involved in the operation of the power management circuit 500. Please also refer to FIG. Figure 5 and Figure 6 , at time point tA1, the power supply voltage VCC1 starts to rise. For example, Figure 1 The power domain 11 shown can be activated at time point tA1. In addition, since the power voltage VCC1 can be connected through the resistor R D1 is applied to transistor M D1 (as a capacitor), the power supply voltage VCCR1 can start to rise. After a period of time tP, the power supply voltage VCC1 can rise to the threshold level V CT1 The power supply voltage VCCR1 can rise to the transistor M NI Therefore, transistor M NI can be turned on at time tA2. In addition, the voltage signal V COM Can be reduced to zero or approximately zero

[0059] At time point tA3, the power supply voltage VCCR1 can be greater than the voltage signal V COM A higher transition threshold makes the latch input T I1 and the latch input terminal T I2 The difference between the respective signal levels, such as |VCCR1-V COM |, the transition threshold can be reached. Control signal S OUTB can be changed from the logic high level to the logic low level. In addition, the control signal S OUT It can be changed from the logic low level to the logic high level, thereby indicating that the power supply voltage VCC1 is ready. It is worth noting that when the control signal S OUT When changing from the logic low level to the logic high level, the voltage level of the power supply voltage VCC1 can be higher than the voltage level of the power supply voltage VCCR1 due to the delay unit 550. The power supply voltage VCC1 can become a sufficiently stable power supply voltage so that the device can operate correctly.

[0060] At time tA4, the power supply voltage VCC1 drops below or reaches the threshold level V CT2 (For example, a brownout occurs). The power supply voltage VCCR1 may drop to the transistor M NI The control signal S OUTB can be changed from the logic low level to the logic high level. In addition, the control signal S OUTThe threshold level V CT2 Can be equal to the threshold level V CT1 .

[0061] Since those skilled in the art read Figures 1 to 4 After reading the relevant paragraphs of the description, the operation details of the power management circuit 500 should be understood, so further description is not repeated here.

[0062] Please refer again Figure 3 and Figure 4 In some embodiments, the delay unit 350 can provide hysteresis to increase noise immunity and system stability. For example, the delay unit 350 can utilize a delay unit with hysteresis function, which can be used to generate a delayed version of the power supply voltage VCC1. During the ramp-up period of the power supply voltage VCC1, the delayed version of the power supply voltage VCC1 rises to a reference level when the VCC1 power supply voltage rises to a first threshold level. During the ramp-down period of the power supply voltage VCC1, the delayed version of the power supply voltage VCC1 drops to the reference level when the power supply voltage VCC1 drops to a second threshold level lower than the first threshold level. The reference level is the transistor M NI When the voltage level of the threshold voltage is the first threshold level and the second threshold level may be the threshold level V CT1 and threshold level V CT2 When the power supply voltage VCC1 slopes down to the threshold level V due to noise interference, CT1 With the threshold level V CT2 When the voltage level is between the two, the voltage level of the power supply voltage VCCR1 can still be higher than that of the transistor M NI The voltage level of the threshold voltage, therefore, the control signal S OUT The delay unit with hysteresis function can reduce the control signal S OUTB / S OUT The possibility of false transitions occurring in the signal level.

[0063] See also Figure 7 , in certain embodiments, Figure 3 The delay unit 350 shown in FIG. 1 can be implemented using a delay unit 750. The circuit structure of the power management circuit 700 is similar to that of FIG. Figure 5The circuit structure of the power management circuit 500 is similar / same. The main difference between the two is that the delay unit 750 further includes a resistor R D2 and a transistor M D2 In this embodiment, the resistor R D2 One end is coupled to the inverter input terminal T I1 and transistor M D2 . Transistor M D2 According to the voltage signal V COM Selectively place resistor R D2 The other end of is coupled to the reference voltage VSS.

[0064] Figure 8 Shows Figure 7 FIG. 7 is a schematic diagram of an embodiment of signal waveforms involved in the operation of the power management circuit 700 shown in FIG. Figure 7 and Figure 8 At time point tB1, the power supply voltage VCC1 starts to rise from a low voltage level. PI can be turned on, and transistor M NI Can be turned off. Voltage signal V COM can have a level high enough to turn on transistor M D2 Therefore, the resistor R D1 and resistor R D2 It can be used as a voltage divider to divide the power supply voltage VCC1. Since the power supply voltage VCC1 can be applied to the transistor M through the voltage divider, D1 (As a capacitor), the power supply voltage VCCR1 can start to rise. The power supply voltage VCCR1 can be regarded as a voltage division related to the power supply voltage VCC1.

[0065] After a period of time tQ, the power supply voltage VCC1 can rise to the threshold level V CT1 In addition, the power supply voltage VCCR1 can rise to the transistor M NI Therefore, transistor M NI can be turned on at time tB2. In some embodiments, due to Figure 8 The threshold level shown is V CT1 Can be higher than Figure 6 The threshold level shown is V CT1 Therefore, the length of the period tQ may be longer than Figure 6 The length of the time period tP shown. Between time point tB2 and time point tB3, transistor M PI Can be turned off. Voltage signal V COM can have a low level, making transistor M D2The voltage level of the power supply voltage VCCR1 may be substantially equal to the voltage level of the power supply voltage VCC1.

[0066] At time tB3, the latch input terminal T I1 and the latch input terminal T I2 The difference between the respective signal levels, such as |VCCR1-V COM |, a transition threshold can be reached. Control signal S OUTB can be changed from the logic high level to the logic low level. In addition, the control signal S OUT The logic level may be changed from the logic low level to the logic high level, thereby indicating that the power supply voltage VCC1 is ready.

[0067] At time tB4, the power supply voltage VCC1 drops below or reaches the threshold level V CT2 (For example, a brownout occurs). The power supply voltage VCCR1 may drop below or reach the transistor M. NI The threshold voltage of transistor M NI can be turned off, and transistor M PI Can be turned on. Voltage signal V COM can have a level high enough to turn on transistor M D2 The power supply voltage VCCR1 can again become a divided voltage related to the power supply voltage VCC1. OUTB can be changed from the logic low level to the logic high level. In addition, the control signal S OUT can be changed from the logic high level to the logic low level, thereby indicating that the power supply voltage VCC1 becomes a power supply voltage that is not yet ready. In this embodiment, Figure 8 The threshold level shown is V CT2 Can be equal to Figure 6 The threshold level shown is V CT1 .

[0068] Since those skilled in the art read Figures 1 to 6 After reading the relevant paragraphs of the description, the operation details of the power management circuit 700 should be understood, so further description is not repeated here.

[0069] In some embodiments, the power management scheme disclosed in this application can be applied to power isolation. Fig. 9 yes Figure 1 In this embodiment, the integrated circuit 90 has multiple power domains, including a power domain 13, a normally-on power domain 14, and Figure 1The power domains 11 and 12 are shown. The power domains 11-13 may be powered by the power voltages VCC1-VCC3 transmitted by the normally-on power domain 14. In some embodiments, the power voltages VCC1-VCC3 may be switchable power domains.

[0070] The integrated circuit 90 may utilize one or more power gating mechanisms to isolate power between different power domains. For example, the integrated circuit 90 may include a power management circuit 900 that can be used to isolate power between multiple power domains 11 and 12. The power management circuit 900 may be used as Figure 1 The embodiment of the power management circuit 100 shown in the figure. For another example, the integrated circuit 90 may include an isolation cell 901, which can be used for power isolation between multiple power domains 11 and 13. The isolation cell 901 can be implemented using (but not limited to) an OR gate. It is worth noting that in some embodiments, the power management circuit 900 can be used for power isolation between any two power domains in the multiple power domains 11-13 without departing from the scope of protection of the present application. In addition, the isolation cell 901 can be used for power isolation between any two power domains in the multiple power domains 11-13 without departing from the scope of protection of the present application. Furthermore, in some embodiments, the power management circuit 900 can be set in a physical medium attachment layer (PMA) 961, a physical coding sublayer (PCS) 962 or a power control module 16 without departing from the scope of protection of the present application.

[0071] For ease of description, the integrated circuit 90 is described below as at least a portion of an application processor (AP), which can support the specification of the Mobile Industry Processor Interface (MIPI). Those skilled in the art will appreciate that the integrated circuit 90 can be implemented as an integrated circuit that can support other types of communication interface specifications without departing from the scope of protection of the present application.

[0072] In this embodiment, the integrated circuit 90 may also include Figure 1The power control module 16, an image signal processor (ISP) 92, a graphic processing unit (GPU) 94 and a receiver 96 are shown. The power control module 16 operates in the normally-on power domain 14 and can be used to provide multiple power supply voltages VCC1-VCC3 to multiple power domains 11-13, and control the power startup / shutdown timing of the multiple power domains 11-13. In addition, the power control module 16 can be used to generate a power status signal, such as a power good signal PWR_OK, to indicate that the multiple power supply voltages VCC1-VCC3 are ready or available for use.

[0073] The image signal processor 92 operates in the power domain 11 and can be started by a start-up signal PWR_ON provided by the power control module 16. The graphics processing unit 94 operates in the power domain 13 and can be controlled by the isolation unit 901 to be selectively isolated from the image signal processor 92. For example (but the present application is not limited thereto), when the power domain 11 is not ready or unavailable, the power control module 16 can transmit a control signal ISO_EN1 with a predetermined level (such as a high logic level). The isolation unit 901 can isolate the signal from the power domain 11 from the graphics processing unit 94 in the power domain 13 according to the control signal ISO_EN1.

[0074] The receiver 96, such as a MIPI differential physical receiver (MIPI D-PHY receiver), may have a physical layer, which may include a physical medium connection layer (PMA) 961 and a physical coding sublayer (PCS) 962. By using a power management circuit 900 coupled between the physical medium connection layer 961 and the physical coding sublayer 962, the physical layer of the receiver 96 may allow different power startup / shutdown timings. For example (but the present application is not limited thereto), when the power domain 11 is not ready or unavailable, the power management circuit 900 may disconnect the physical medium connection layer 961 in the power domain 11 from the physical coding sublayer 962 in the power domain 12 according to a control signal ISO_EN2 provided by the power control module 16. In some embodiments, the control signal ISO_EN2 may carry power status information of the power voltage VCC1, thereby indicating whether the power voltage VCC1 is ready. In some embodiments, the control signal ISO_EN2 may carry power status information of each of the plurality of power supply voltages VCC1 and VCC2, thereby indicating whether the plurality of power supply voltages VCC1 and VCC2 are ready. In some embodiments, the control signal ISO_EN2 may be a power status signal, such as a power ready signal PWR_OK or an inverted signal of the power ready signal PWR_OK.

[0075] Fig.10 yes Figure 2 A specific implementation of the power management circuit 200 is shown. In this embodiment, Fig.10 The power management circuit 1000 shown can be used to Fig. 9 The power management circuit 1000 has a circuit structure similar to that of the integrated circuit 90 shown in FIG. Figure 3 The circuit structure of the power management circuit 300 is similar / same, and the main difference between the two is that the inverter power supply terminal T SI In this embodiment, the power management circuit 1000 may include an inverter circuit 1010, a latch circuit 1020, a switch circuit 1060, an output buffer 1070, and Figure 3 The output buffer 330 is shown. The inverter circuit 1010 and the latch circuit 1020 can be used as Figure 2 An embodiment of an inverter circuit 210 and a latch circuit 220 is shown.

[0076] The latch circuit 1020 may utilize (but is not limited to) a cross-coupled inverter pair, which may include a plurality of transistors M LU1 、M LD1 、M LU2 and M LD2 . Latch input terminal T I1 Coupled to transistor M LD1 The gate of the latch is used to receive a voltage signal PWRB generated by the inverter circuit 1010. I2 Coupled to transistor M LD2 The gate of the inverter circuit 1010 is used to receive the control signal ISO_EN2 input to the inverter circuit 1010. The control signal ISO_EN2 can be used as Figure 2 The voltage signal PWRB can be used as the control signal CS. Figure 2 The latch power supply terminal T SL Coupled to a plurality of transistors M LU1 and M LU2 The respective sources are used to receive the power supply voltage VCC2. The latch output terminal T OL Coupled to a plurality of transistors M LU2 and M LD2 Between their respective drains, used to output a control signal S OUTB The other latch output terminal T OLC Coupled to a plurality of transistors M LU1 and M LD1 Between their respective drains, used to output a control signal S OUTB The inverted or complementary signal.

[0077] The switching circuit 1060 may include a resistor unit 1062, a switch 1064, and a switch 1066. The resistor unit 1062 is coupled to a circuit node N C and the inverter power supply terminal T SI In this embodiment, the resistor unit 1062 can be composed of a resistor R G In some embodiments, the resistor unit 1062 may be implemented using at least one resistor, at least one diode, at least one diode-connected transistor, at least one circuit unit capable of providing a resistor, and combinations thereof, without departing from the scope of protection of the present application. The switch 1064 may be configured to switch the output terminal T of the latch 1064 according to a control signal PWRS (i.e., the latch output terminal T OLC The signal level) is selectively coupled to the power supply voltage VCC1 and the inverter power supply terminal T SI The switch 1066 can selectively couple the power supply voltage VCC2 and the circuit node N according to the control signal PWRS. CWhen one of the switch 1064 and the switch 1066 is turned on, the other of the switch 1064 and the switch 1066 can be turned off. In this embodiment, the switch 1064 and the switch 1066 can be respectively connected by the transistor M S1 and transistor M S2 In some embodiments, the switch 1064 and the switch 1066 may be implemented using other types of switch units without departing from the protection scope of the present application.

[0078] The output buffer 1070 is coupled to the latch output terminal T of the latch circuit 1020. OLC , and can be used to buffer the control signal S OUTB In this embodiment, the output buffer 1070 can be implemented by a voltage follower operating at the power supply voltage VCC2.

[0079] Fig.11 Shows Fig.10 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of the power management circuit 1000. Fig. 9 , Fig.10 See also Fig.11 , before the time point tC1, the control signal ISO_EN2 from the normally-on power domain 14 has a logic low level (such as 0V). In this embodiment, the control signal ISO_EN2 can be implemented using the power ready signal PWR_OK. The power ready signal PWR_OK with the logic low level can indicate that the multiple power supply voltages VCC1 and VCC2 are not ready. In addition, the voltage signal PWRB can rise in response to the power supply voltage VCC2 having a rated level V1 (such as 3.3V). For example, the inverter circuit 1010 can use Figure 3 The inverter circuit 310 shown in FIG. Figure 3 The transistor M shown PI ) has the logic low level, so the power supply voltage VCC2 can be applied to the inverter output terminal T through the resistor unit 1062 and the p-channel transistor. O .

[0080] At time point tC1, since the voltage signal PWRB reaches or exceeds a threshold level, the latch input terminal T I1 and the latch input terminal T I2The difference between the respective signal levels (such as |PWRB-VCCR1|) may reach or exceed a transition threshold (such as 0.9V). The control signal PWRS may have a logic low level, such as 0V, which is effective in the power domain 12. The control signal S OUTB The control signal S for the power domain 12 may have a logic high level, such as 3.3V, which is effective in the power domain 12. OUT The logic low level may be provided to indicate that the power supply voltages VCC1 and VCC2 are not ready. In addition, since the control signal PWRS may be at the logic low level in response to the power ready signal PWR_OK, the switch 1064 is turned off and the switch 1066 is turned on before the power supply voltage VCC1 is ready.

[0081] At time point tC2, the power supply voltage VCC1 reaches its rated level V2, such as 1.2 V. After a delay time, the power ready signal PWR_OK changes to a logic high level V3, such as 1.2 V, at time point tC3. At time point tC4, the voltage signal PWRB may drop to a voltage level V4, which may be equal to or substantially equal to the power supply voltage VCC2 minus the voltage drop V DG . Voltage drop V DG It is generated according to a current signal flowing through the resistor RG. For example (but the present application is not limited thereto), the voltage level V4 may be close to 0V, such as 0.2V.

[0082] At time tC5, due to the latch input T I1 and the latch input terminal T I2 The difference between the respective signal levels (such as |PWR_OK-PWRB|) reaches or exceeds a transition threshold (such as 0.9V), and thus, the control signal PWRS and the control signal S OUT can be converted to the logic high level (such as 3.3V) in the power domain 12. Since the control signal PWRS can be at the logic high level in response to the power ready signal PWR_OK, when the multiple power supply voltages VCC1 and VCC2 are ready, the switch 1064 is turned on and the switch 1066 is turned off. At the time point tC6, since the switch 1064 is turned on to couple the power supply voltage VCC1 to the inverter input terminal T I , therefore, the voltage signal PWRB may be reduced to the logic low level (such as 0V) in the power domain 11.

[0083] At time point tC7, the power control module 16 may deactivate the power ready signal PWR_OK (i.e., the control signal ISO_EN2) to turn off the power domain 11. The power ready signal PWR_OK may change from the logic high level in the normally-on power domain 14 to the logic low level. At time point tC8, due to the latch input terminal T I1 and the latch input terminal T I2 The difference between the respective signal levels (such as |PWRB-PWR_OK|) reaches or exceeds a transition threshold (such as 0.9V), and thus, the control signal PWRS and the control signal S OUT The voltage signal PWRB can rise to a rated level (such as 1.2V) substantially equal to the power supply voltage VCC1. At time point tC9, since the switch 1066 is turned on according to the control signal PWRS, the power supply voltage VCC2 is coupled to the inverter power supply terminal T through the resistor unit 1062. I The voltage signal PWRB may rise to a rated level V1 of the power supply voltage VCC2.

[0084] By using the power ready signal PWR_OK that can indicate the power state of the power supply voltage VCC1, when the power supply voltage VCC1 is not ready or cannot be used, the power management circuit 1000 can isolate one or more circuit blocks (such as the physical medium connection layer 961) in the power domain 11 and the power domain 12. In addition, when the power supply voltage VCC1 and the power supply voltage VCC2 are both ready, the power management circuit 1000 can generate a control signal S OUTB / S OUT , to allow the power domain 11 to be coupled to the one or more circuit blocks in the power domain 12.

[0085] In some embodiments, the control signal ISO_EN2 may also carry power state information of the power supply voltage VCC2. When one of the multiple power supply voltages VCC1 and VCC2 is ready and the other is not ready (for example, during a power startup sequence), the control signal ISO_EN2 may be at a first level (such as one of a logic high level and a logic low level). When both of the multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 may be at a second level different from the first level. Fig.12 Shows Fig.10 FIG. 1 is a schematic diagram of another embodiment of signal waveforms involved in the operation of the power management circuit 1000 . Fig.12 The signal waveform shown is similar to Fig.11The signal waveforms shown are similar / same, and the difference between the two is that before the power supply voltage VCC2 is ready, the control signal ISO_EN2 can be at a logic high level. In addition, when the power supply voltage VCC2 is ready and the power supply voltage VCC1 is not ready, the control signal ISO_EN2 can be at a logic low level. When the multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 can return to a logic high level. As those skilled in the art can understand by reading Figures 1 to 11 After reading the relevant paragraphs, you should be able to understand Fig.10 The power management circuit 1000 shown uses Fig.12 The operation details of the signal waveform shown are omitted here for further explanation.

[0086] In some embodiments, the power management scheme disclosed in the present application can utilize the inverted signal of the power ready signal (provided by the normally-on power domain) to perform power isolation. Fig.13 yes Figure 2 Another specific implementation of the power management circuit 200 is shown. In this embodiment, Fig.13 The power management circuit 1300 shown can be used to Fig. 9 The power management circuit 1300 has a circuit structure similar to that of the integrated circuit 90. Fig.10 The circuit structure of the power management circuit 1000 is similar / same. The main difference between the two is that the power supply voltage VCC1 can be coupled to the inverter power supply terminal T before it is ready. SI In addition, the output buffer 1330 can be implemented using a voltage follower. In this embodiment, the power management circuit 1300 can use a power status signal PWR_OKN (which is Fig. 9 The power status signal PWR_OKN can be used as the inverted signal of the power ready signal PWR_OK shown in the figure to isolate the power supply. Fig. 9 An embodiment of the control signal ISO_EN2 is shown.

[0087] Fig.14 Shows Fig.13 FIG. 1 is a schematic diagram of an embodiment of signal waveforms involved in the operation of the power management circuit 1300. Fig. 9 , Fig.13 See also Fig.14 Before the time point tD1, the power state signal PWR_OKN may be at a logic high level to indicate that the multiple power supply voltages VCC1 and VCC2 are not all ready. I1 The voltage signal PWRB may have a logic low level. Therefore, the latch input terminal T I1 The signal level will be lower than the latch input T I2The signal level of the control signal S OUTB The power management circuit 1300 may generate a control signal S having a logic low level to indicate that the power voltage VCC1 is not ready. OUT , thereby isolating the power domain 11 and the physical medium connection layer 961 operating in the power domain 12.

[0088] At time point tD1, the power status signal PWR_OKN may be converted to a logic low level to indicate that the power supply voltages VCC1 and VCC2 are ready. I1 The signal level will be higher than the latch input T I2 The signal level of the control signal S OUTB The power management circuit 1300 can generate a control signal S having a logic high level accordingly. OUT , thereby allowing the signal to be transmitted from the power domain 11 to the physical medium connection layer 961 operating in the power domain 12. At time point tD2, the power control module 16 can deactivate the power ready signal PWR_OK to turn off the power domain 11. The power state signal PWR_OKN can be converted to the logic high level. The power domain 11 can be isolated from the physical medium connection layer 961 operating in the power domain 12 again.

[0089] In some embodiments, the control signal ISO_EN2 may also carry power state information of the power supply voltage VCC2. When one of the multiple power supply voltages VCC1 and VCC2 is ready and the other is not ready (for example, during a power startup sequence), the control signal ISO_EN2 may be at a first level (such as one of a logic high level and a logic low level). When both of the multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 may be at a second level different from the first level. Fig.15 Shows Fig.13 FIG. 1 is a schematic diagram of another embodiment of signal waveforms involved in the operation of the power management circuit 1300 . Fig.15 The signal waveform shown is similar to Fig.14 The signal waveforms shown are similar / same, and the difference between the two is that before the power supply voltage VCC2 is ready, the control signal ISO_EN2 can be at a logic low level. In addition, when the power supply voltage VCC2 is ready and the power supply voltage VCC1 is not ready, the control signal ISO_EN2 can be changed to a logic high level. When the multiple power supply voltages VCC1 and VCC2 are ready, the control signal ISO_EN2 can return to a logic low level. As those skilled in the art can understand by reading Figures 1 to 14 After reading the relevant paragraphs, you should be able to understand Fig.13 The power management circuit 1300 shown uses Fig.15 The operation details of the signal waveform shown are omitted here for further explanation.

[0090] As described above, the power management scheme disclosed in the present application can convert a control signal applicable to one power domain into a control signal applicable to another power domain, thereby performing a power control operation. For example (but the present application is not limited thereto), the aforementioned power management circuit 200 / 300 / 1000 / 1300 can be implemented to include a level converter and an output buffer. Figure 2 In the illustrated embodiment, the inverter circuit 210 and the latch circuit 220 may be used to implement at least a portion of the level shifter 202. Figure 3 In the illustrated embodiment, the inverter circuit 310, the latch circuit 320, and the resistor unit 340 may be used to implement at least a portion of the level converter 302. Fig.10 In the illustrated embodiment, the inverter circuit 1010, the latch circuit 1020, and the switching circuit 1060 may be used to implement at least a portion of the level shifter 1002. Fig.13 In the illustrated embodiment, the inverter circuit 1010 and the latch circuit 1020 may be used to implement at least a portion of the level shifter 1302 .

[0091] In some embodiments, the power management scheme disclosed in this application can utilize a single-ended level shifter and an output buffer for power isolation. Fig.16 yes Figure 2 Another specific implementation of the power management circuit 200 is shown in FIG. In this embodiment, the power management circuit 1600 can be used to Fig. 9 The different power domains of the integrated circuit 90 are shown to be power isolated. In addition, the power management circuit 1600 can be implemented to include a single-ended level shifter.

[0092] Please also read Fig. 9 and Fig.16 , the power management circuit 1600 may include a level converter 1602 and Figure 3 The output buffer 330 is shown. The level converter 1602 is powered by the power supply voltage VCC2 used in the power domain 12. The level converter 1602 can be used to convert the control signal ISO_EN2 into a control signal S suitable for the power domain 12. OUTB In this embodiment, the level converter 1602 includes a transistor M LS and a resistor unit R S (such as a resistor). In addition, it is used to control the transistor M LS The switch state control signal ISO_EN2 may be implemented using a power state signal (such as a power ready signal PWR_OK).

[0093] In operation, before the power voltage VCC1 is ready, the power ready signal PWR_OK is at a logic low level. LS The control signal S OUTB The control signal S may have a logic high level, such as the nominal level of the power supply voltage VCC2. OUT The power management circuit 1600 may have a logic low level to indicate that the power supply voltage VCC1 is not ready. OUT The physical medium connection layer 961 in the power domain 11 and the power domain 12 is isolated. When the multiple power supply voltages VCC1 and VCC2 are ready, the power ready signal PWR_OK changes from the logic low level to a logic high level to turn on the transistor M LS . Control signal S OUTB The control signal S OUT The power management circuit 1600 can be changed to the logic high level, which can indicate that the multiple power supply voltages VCC1 and VCC2 are ready. OUT A physical medium connection layer 961 that allows power domain 11 to be coupled to power domain 12 .

[0094] It is worth noting that the power management scheme disclosed in this application can use a single control signal (such as a power status signal provided directly from a normally-on power domain) to perform power isolation between different power domains. Fig. 9 and Fig.13 In some embodiments, since the control signal ISO_EN2 can be level-converted to a control signal suitable for the power domain 13, the power management circuit 900 can isolate one or more circuit blocks in the power domain 11 and the power domain 13 according to the control signal ISO_EN2. For example, when the power management circuit 900 is used to isolate the graphics processing unit 94 in the power domain 11 and the power domain 13, the inverter circuit 110 and the latch circuit 1020 can be powered by the power voltages VCC1 and VCC3, respectively. The level converter 1302 can still receive the power state signal PWR_OKN to convert the power state signal PWR_OKN into the control signal S OUTB , which can be used in the power domain VCC3. Using the power management solution disclosed in this application, a single control signal can be used to isolate power between multiple power domains, thereby reducing circuit chip area and power consumption.

[0095] Fig.17 is a flow chart of an embodiment of the method for managing an integrated circuit of the present application. Fig. 9 The integrated circuit shown and Figure 2The level converter shown is used to illustrate the method 1700. Those skilled in the art will appreciate that the method 1700 can be applied to Figure 1 The integrated circuit 10 shown or other integrated circuits having multiple power domains may be used without departing from the scope of protection of the present application. In addition, those skilled in the art will appreciate that the method 1700 may utilize other level converters, such as Figure 3 The level converter 302 shown, Fig.10 The level converter 1002 shown, Fig.13 The level converter 1302 shown, Fig.16 The level converter 1602 shown, or other types of level converters, may be used without departing from the scope of protection of the present application. In addition, in some embodiments, other operations may be performed in method 1700. In some embodiments, the operations in method 1700 may be performed in a different order or implemented by other operations. In some embodiments, one or more operations in method 1700 may be omitted.

[0096] In operation 1702, a level converter is used and operated at a first power supply voltage of a first power domain of the integrated circuit. The first power domain is used to receive an input signal from a second power domain of the integrated circuit, and the second power domain is powered by a second power supply voltage. For example, the level converter 202 can be powered by the power supply voltage VCC2 in the power domain 12. The physical medium connection layer 961 in the power domain 12 can receive an input signal, such as a data input or a control input, from the physical coding sublayer 962 in the power domain 11 powered by the power supply voltage VCC1.

[0097] In operation 1704, when the first power supply voltage is ready and the second power supply voltage is not ready, the level converter is used to convert a first control signal into a second control signal having a first logic level to isolate the second power domain from the first power domain, wherein the first control signal at least indicates the power state of the second power supply voltage. For example, the level converter 202 can be implemented in the power management circuit 900. When the power supply voltage VCC2 is ready and the power supply voltage VCC1 is not ready, the level converter 202 can be used to convert the control signal CS into a control signal S having a first logic level (such as one of a logic high level and a logic low level). OUTB , to isolate the power domain 11 from the power domain 12. Therefore, the input signal (which may have an unknown state transmitted from the power domain 11) can be isolated from the power domain 12. The physical coding sublayer 962 in the power domain 11 may not be coupled to the physical medium connection layer 961 in the power domain 12.

[0098] In certain embodiments, Figure 2The control signal CS shown can be implemented using a power state signal provided by the normally-on power domain 14. In some embodiments, Figure 2 The control signal CS shown can be implemented using a power status signal that can indicate whether the power supply voltage VCC1 is ready. Figure 2 The control signal CS shown can be implemented by a power status signal that can indicate whether the power voltage VCC1 and the power voltage VCC2 are both ready. For example, the control signal CS can be implemented by a power ready signal PWR_OK transmitted by the power control module 16. For another example, the control signal CS can be implemented by a power state signal having the same Fig.11 , Fig.12 , Fig.14 or Fig.15 A similar / identical signal waveform is implemented by the control signal ISO_EN2.

[0099] In operation 1706, when both the first power supply voltage and the second power supply voltage are ready, the first control signal is converted into the second control signal having a second logic level by using the level converter to allow the first power domain to receive the input signal from the second power domain. For example, when both the power supply voltage VCC1 and the power supply voltage VCC2 are ready, the level converter 202 may be used to convert the control signal CS into a control signal S having a second logic level (such as the other of the logic high level and the logic low level). OUTB , to allow the power domain 12 to receive the input signal from the power domain 11. Therefore, the input signal provided by the power domain 11 can be transmitted to the power domain 12. The physical coding sublayer 962 in the power domain 11 can be allowed to be coupled with the physical medium connection layer 961 in the power domain 12.

[0100] Since those skilled in the art read Figures 1 to 16 After reading the relevant paragraphs of the description, the operation details of the power management circuit 1700 should be understood, so further description is not repeated here.

[0101] The above description briefly presents the features of certain embodiments of the present application, so that those skilled in the art can more fully understand the various aspects of the present application. Those skilled in the art of the present application should understand that they can easily use the content of the present application as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art of the present application should understand that these equivalent embodiments still belong to the spirit and scope of the content of the present application, and they can be variously changed, replaced and modified without departing from the spirit and scope of the content of the present application.

Claims

1. A power management circuit for an integrated circuit, characterized in that: include: an inverter circuit having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive a first control signal from the inverter input terminal and generate a second control signal at the inverter output terminal, wherein the first control signal carries power state information of a first power supply voltage supplied to the integrated circuit; as well as A latch circuit, comprising a latch power supply terminal, a first latch input terminal and a second latch input terminal, wherein the latch power supply terminal is coupled to a second power supply voltage supplied to the integrated circuit, the second power supply voltage is ready in advance of the first power supply voltage, the first latch input terminal is coupled to the inverter output terminal to receive the second control signal, the second latch input terminal is coupled to the inverter input terminal to receive the first control signal, the latch circuit is used to generate a third control signal according to the signal levels of the first control signal and the second control signal, and perform power control of the integrated circuit accordingly; wherein when the power status information indicates that the first power supply voltage is not ready, one of the signal levels of the first control signal and the second control signal is higher than the other of the signal levels of the first control signal and the second control signal; When the power status information indicates that the first power voltage is ready, the one of the first control signal and the second control signal is lower than the other of the first control signal and the second control signal.

2. The power management circuit according to claim 1, characterized in that: When the power status information indicates that the first power voltage is not yet ready, the latch circuit is used to generate the third control signal to keep the integrated circuit in a reset state; when the power status information indicates that the first power voltage is ready, the latch circuit is used to generate the third control signal to release the integrated circuit from the reset state.

3. The power management circuit according to claim 1, wherein: The integrated circuit includes a first power domain powered by the first power voltage and a second power domain powered by the second power voltage; when the power status information indicates that the first power voltage is not ready, the latch circuit is used to generate the third control signal to isolate the first power domain from a portion of the integrated circuit operating in the second power domain; When the power status information indicates that the first power voltage is ready, the latch circuit is configured to generate the third control signal to allow the first power domain to be coupled to the portion of the integrated circuit.

4. The power management circuit according to claim 1, characterized in that: Also includes: The resistor unit includes a resistor supply terminal of the inverter circuit configured to be coupled to the second power supply voltage through the resistor unit.

5. The power management circuit according to claim 4, characterized in that: Also includes: A delay unit is coupled to the inverter input terminal, the delay unit is used to receive the first power supply voltage and output a delayed version of the first power supply voltage to the inverter input terminal, the delayed version of the first power supply voltage serves as the first control signal.

6. The power management circuit according to claim 5, characterized in that: During the ramp-up of the first power supply voltage, the delayed version of the first power supply voltage rises to a reference level when the first power supply voltage rises to a first threshold level; During the ramp-down of the first supply voltage, the delayed version of the first supply voltage drops to the reference level when the first supply voltage drops to a second threshold level below the first threshold level.

7. The power management circuit according to claim 4, characterized in that: The latch circuit further comprises a first latch output terminal and a second latch output terminal, wherein the first latch output terminal is used to output the third control signal; The power management circuit further includes: a first switch selectively coupled between the first power supply voltage and the inverter power supply terminal according to a signal level of the second latch output terminal; and a second switch selectively coupled between the second power supply voltage and the resistance unit according to a signal level of the output terminal of the second latch; When the first power supply voltage is not ready, the first control signal has a logic low level, the first switch is turned off, and the second switch is turned on; when the first power supply voltage and the second power supply voltage are both ready, the first control signal has a logic high level, the first switch is turned on, and the second switch is turned off.

8. The power management circuit according to claim 1, wherein: The inverter power supply terminal of the inverter circuit is used to receive the first power supply voltage; when the first power supply voltage is not ready, the first control signal has a logic high level; when the first power supply voltage and the second power supply voltage are both ready, the first control signal has a logic low level.

9. The power management circuit according to claim 1, characterized in that: The first control signal is provided by a normally-on power domain.

10. The power management circuit according to claim 1, wherein: The first control signal also carries power state information of the second power supply voltage; when the second power supply voltage is not ready, the first control signal has a first logic level; when the second power supply voltage is ready but the first power supply voltage is not ready, the first control signal has a second logic level different from the first logic level; When the first power supply voltage and the second power supply voltage are both ready, the first control signal has the first logic level.

11. A power management circuit for an integrated circuit, characterized in that: include: a level converter, powered by at least a first power supply voltage that can be used in a first power supply domain of the integrated circuit, the level converter is used to convert a first control signal into a second control signal that can be used in the first power supply domain, the first control signal indicates a power state of a second power supply voltage that can be used in a second power supply domain of the integrated circuit, the first power supply voltage is ready earlier than the second power supply voltage, the second power supply domain is different from the first power supply domain, wherein before the second power supply voltage is ready, the first control signal is at a first logic level during a level transition of the second power supply voltage; when the second power supply voltage is ready after transitioning to a predetermined voltage level, the first control signal is at a second logic level different from the first logic level; as well as The output buffer is coupled to the level converter and is used for buffering the second control signal to generate a third control signal, and the third control signal is used to perform power control of the integrated circuit.

12. The power management circuit according to claim 11, characterized in that: When the first control signal indicates that the second power supply voltage is not ready, the output buffer is used to generate the third control signal to isolate the second power domain from a portion of the integrated circuit operating in the first power domain; When the first control signal indicates that the second power supply voltage is ready, the output buffer is configured to generate the third control signal to allow the second power domain to be coupled to the portion of the integrated circuit.

13. The power management circuit according to claim 11, characterized in that: The level converter comprises: an inverter circuit having an inverter input terminal and an inverter output terminal, the inverter circuit being configured to receive the first control signal from the inverter input terminal and generate a fourth control signal at the inverter output terminal; and A latch circuit having a latch power supply terminal, a first latch input terminal and a second latch input terminal, wherein the latch power supply terminal is coupled to supply power to the first power supply voltage, the first latch input terminal is coupled to the inverter output terminal to receive the fourth control signal, the second latch input terminal is coupled to the inverter input terminal to receive the first control signal, and the latch circuit is used to generate the second control signal according to the respective signal levels of the first control signal and the fourth control signal.

14. The power management circuit according to claim 13, characterized in that: The inverter power supply terminal of the inverter circuit is used to receive the second power supply voltage; the first logic level is a logic high level, and the second logic level is a logic low level.

15. The power management circuit according to claim 13, characterized in that: The latch circuit further comprises a first latch output terminal and a second latch output terminal, wherein the first latch output terminal is used to output the second control signal; The level converter further comprises: A resistor unit coupled between a circuit node and an inverter power supply terminal of the inverter circuit; a first switch selectively coupled between the first power supply voltage and the circuit node according to a signal level of the second latch output terminal; and a second switch selectively coupled between the second power supply voltage and the inverter power supply terminal according to a signal level of the second latch output terminal; The first logic level is a logic low level, and the second logic level is a logic high level; when the second power supply voltage is not ready, the first switch is turned on and the second switch is turned off; when both the first power supply voltage and the second power supply voltage are ready, the first switch is turned off and the second switch is turned on.

16. The power management circuit according to claim 11, characterized in that: The first control signal also indicates the power state of the first power supply voltage; when both the first power supply voltage and the second power supply voltage are not ready, the first control signal has the second logic level; When the first power supply voltage is ready and the second power supply voltage is not ready, the first control signal has the first logic level; When both the first power supply voltage and the second power supply voltage are ready, the first control signal has the second logic level.

17. The power management circuit according to claim 11, characterized in that: The first control signal is provided by a normally-on power domain.

18. A method for managing an integrated circuit, characterized in that: include: operating the level converter at a first power supply voltage supplied to a first power supply domain of the integrated circuit, wherein the first power supply domain is configured to receive an input signal from a second power supply domain of the integrated circuit, the second power supply domain being supplied by a second power supply voltage; When the first power supply voltage is ready but the second power supply voltage is not ready, using the level converter to receive a first control signal at a first logic level during a level transition of the second power supply voltage, and converting the first control signal into a second control signal to isolate the second power domain from the first power domain, wherein the first control signal at least indicates a power state of the second power supply voltage; as well as When the first power supply voltage and the second power supply voltage are both ready, the first control signal is switched from the first logic level to a second logic level different from the first logic level, and the first control signal at the second logic level is converted into the second control signal using the level converter to allow the first power domain to receive the input signal from the second power domain.

19. The method according to claim 18, characterized in that The first control signal is a power status signal provided by a normally-on power domain, and the power status signal indicates whether the first power voltage and the second power voltage are both ready.

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