Comparator Architecture and Related Methods

Abstract

A system is disclosed. The system includes a first stage (M12, M14) configured to receive an input voltage (VIN) and a reference voltage (VREF), the first stage including an input transistor pair (M12, M14), wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes a high gain node (VHGN) having a voltage at a common drain. The system further includes a second stage (130), the second stage is coupled to the high gain node and is configured to generate an output voltage (VOUT) based on a difference between the input voltage and the reference voltage, the second stage includes a resistor (R11) and an inverter transistor pair (M15, M16), wherein the gate of the inverter transistor pair is coupled to the high gain node of the first stage, and the resistor couples the high gain node of the first stage to the common drain of the inverter transistor pair, and is configured to provide and / or sink current to and / or from the high gain node of the first stage.

Description

Technical Field

[0001] This patent application claims priority to application number 15 / 995,069, entitled “COMPARATOR ARCHITECTURES AND ASSOCIATED METHODS,” filed on May 31, 2018, and assigned to the present assignee and expressly incorporated herein by reference. Background Art

[0002] Aspects of the present disclosure relate generally to comparator architectures, and more particularly to maximizing the speed of comparators.

[0003] Comparators can be used to monitor voltages. In particular, the comparator determines the input voltage V IN Is it greater than or less than the reference voltage V REF The comparator can generate an indication V IN Is it greater than or less than V REF The output voltage V OUT For example, if V IN Greater than V REF , then V OUT can be high (logic 1), and if V IN Less than V REF , then V OUT Can be low (logic 0).

[0004] V REF The selection may be arbitrary depending on the application. For example, a device may include a power management system configured to maintain a power supply voltage of the device within an optimal range. If the power supply voltage is outside the optimal range, the processor speed and / or performance may be negatively affected. For example, if the power supply voltage is below the optimal value, the processing speed may be reduced; and if the power supply voltage is above the optimal value, the device may consume too much power unnecessarily. To monitor the power supply voltage, the power management system may use a voltage threshold monitor (VTM) including one or more comparators. The power supply voltage of the device may be provided as an input voltage V IN and can provide the optimum supply voltage limit as the reference voltage V REF .

[0005] For example, suppose the optimal range for the supply voltage of a particular device is one volt, plus or minus fifty millivolts. Therefore, the VTM can provide a 1.05V reference voltage V to the comparator. REF . Use V REF , the comparator can determine whether the device's supply voltage has exceeded the 1.05V reference threshold and is therefore outside the optimal range. In this example, if the device's supply voltage is below the threshold, then V OUT can provide a logic 0 output, and if the 1.05V threshold is exceeded, V OUTA logic 1 output may be provided. Thus, a logic 1 output may indicate that the supply voltage of the device has exceeded the upper limit of its optimal range.

[0006] When the VTM indicates that the power supply voltage of the device is too high, for example, the power management system can make adjustments to reduce the power supply voltage of the device to an optimal range. It should be understood that the faster the adjustment can be made, the greater the improvement in speed and / or performance. In conventional architectures, one or more comparators that make up the VTM may not be able to switch quickly. The speed of the comparator can be considered as V OUT In response to V IN Move to V REF The above is the amount of time it takes to flip from a logic 0 to a logic 1.

[0007] To return to the earlier example, assume that the supply voltage of the device is initially within the optimal range. As a result, the output voltage of the comparator, V OUT Can be a logic 0, indicating that the device’s supply voltage is not excessive. If the device’s supply voltage later rises to V REF Above, then V OUT It may take about four hundred picoseconds to flip from a logic 0 output to a logic 1 output. At this point, the power management system will sense that the supply voltage is too high and can take action to adjust the supply voltage. However, the four hundred picosecond delay prevents the power management system from effectively correcting the supply voltage (as it would if there were less delay). Therefore, new techniques are needed to increase the speed of one or more comparators. Summary of the invention

[0008] The following summary is an overview provided only to aid in describing various aspects of the disclosure and is provided for purposes of illustration of these aspects only and not limitation of the disclosure.

[0009] According to various aspects of the present disclosure, a system is disclosed. The system includes a first stage, the first stage is configured to receive an input voltage and a reference voltage, the first stage includes an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes a high gain node with a high gain node voltage at a common drain. The system further includes a second stage, the second stage is coupled to the high gain node and is configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage includes a resistor and an inverter transistor pair, wherein the gate of the inverter transistor pair is coupled to the high gain node of the first stage, and the resistor couples the high gain node of the first stage to the common drain of the inverter transistor pair, and is configured to provide and / or draw current to and / or from the high gain node of the first stage.

[0010] According to other aspects of the present disclosure, a method is disclosed. The method includes receiving an input voltage and a reference voltage at a first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes a high gain node having a high gain node voltage at a common drain. The method further includes receiving the high gain node voltage at a second stage including a resistor and an inverter transistor pair, wherein the gate of the inverter transistor pair is coupled to the high gain node of the first stage, and the resistor couples the high gain node of the first stage to the common drain of the inverter transistor pair. The method further includes providing current to the high gain node of the first stage or drawing current from the high gain node of the first stage, and generating an output voltage based on the difference between the input voltage and the reference voltage.

[0011] According to other aspects of the present disclosure, another system is disclosed. The system includes means for receiving an input voltage and a reference voltage, wherein the means for receiving includes means for providing a high gain node having a high gain node voltage, means for receiving the high gain node voltage, means for providing current to the high gain node of the first stage or drawing current from the high gain node of the first stage, and means for generating an output voltage based on a difference between the input voltage and the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are presented to aid in describing various aspects of the present disclosure and are provided solely for illustration of the aspects and not limitation of the aspects.

[0013] Figure 1 A comparator architecture according to aspects of the present disclosure is generally shown when an input voltage rises above a reference voltage.

[0014] Figure 2 The overall figure shows that when the input voltage drops below the reference voltage Figure 1 Comparator architecture.

[0015] Figure 3 A comparator architecture with increased impedance seen by a reference voltage is generally shown in accordance with aspects of the present disclosure.

[0016] Figure 4 A comparator architecture is generally shown with increased impedance seen by the reference voltage and the input voltage.

[0017] Figure 5 A method for comparing an input voltage to a reference voltage according to aspects of the present disclosure is generally shown.

[0018] Figure 6 An exemplary electronic device is generally shown in which aspects of the present disclosure may be advantageously employed. DETAILED DESCRIPTION

[0019] As mentioned above, a comparator fabricated using conventional architecture may not be able to switch quickly. For example, in response to an input voltage V IN Moves outside the optimal range, V OUT Flipping from logic 0 to logic 1 (or in response to V IN Move to the optimal range, V OUT A transition from a logic 1 to a logic 0) may take four hundred picoseconds. A four hundred picosecond delay may delay the power management system and reduce the speed and / or performance gains associated with the power management algorithm.

[0020] As will be discussed in more detail below, the comparator architecture of the present disclosure can reduce the delay to less than one hundred picoseconds. In one embodiment, the comparator can include a high gain stage and an inverter stage, wherein the inverter stage assists the high gain stage by providing current to the high gain stage or draining current from the high gain stage. In another embodiment, the comparator can further include a high impedance stage to prevent the comparator from being induced by the input voltage V IN and / or reference voltage V REF In yet another embodiment, the comparator may include a cascode differential to single-ended converter and / or a protection voltage clamp.

[0021] Figure 1 A comparator architecture 100 according to aspects of the present disclosure is generally shown when an input voltage rises above a reference voltage.

[0022] The comparator architecture 100 may include a high gain stage 120 and an inverter stage 130. As will be discussed in more detail below, the rising input voltage V IN Current may be caused to flow out of the high gain stage 120 and into the inverter stage 130 .

[0023] High gain stage 120 may include two transistor pairs, each transistor pair including a p-type transistor and an n-type transistor. The reference pair may include transistor M11 as a p-type transistor and transistor M13 as an n-type transistor. The input pair may include transistor M12 as a p-type transistor and transistor M14 as an n-type transistor. The n-type transistors (transistor M13 and transistor M14) may each include a source coupled to ground and a source coupled to a bias voltage V N-BIAS The gate of V N-BIAS can be selected so that the n-type transistor is biased to an on position. Transistor M11 may include a transistor coupled to a reference voltage V REF The transistor M12 may include a source coupled to the input voltage V IN The source.

[0024] The drains of the transistors in the reference pair (transistor M11 and transistor M13) can be coupled to a transistor having a drain-gate voltage V DG The drain-gate node can be coupled to the gates of the p-type transistors (transistor M11 and transistor M12). The drains of the transistors in the input pair (transistor M12 and transistor M14) can be coupled to a high gain node voltage V HGN The high gain node may be coupled to an inverter stage 130, as will be discussed in more detail below. The high gain stage 120 may include a ΔVgs circuit.

[0025] The inverter stage 130 may include a first inverter including a transistor M15, a transistor M16, and a resistor R11. The inverter stage 130 may further include a second inverter 132. The transistor M15 may be a p-type transistor having a source coupled to a power supply voltage V DD and the drain is coupled to a first inverter node voltage V INV1 The transistor M16 may be an n-type transistor having a source coupled to ground and a drain coupled to the first inverter node. The inverter stage 130 may include a class A biased inverter.

[0026] The high gain node of the high gain stage 120 can be coupled to the gates of transistors M15 and M16. In addition, resistor R11 can couple the high gain node to a first inverter node. The first inverter node can be coupled to a second inverter 132, which generates an output voltage V of the comparator architecture 100. OUT .

[0027] In the following paragraphs, we will use V IN Initially less than V REF (Make V HGN is a low voltage) but later becomes greater than V REF (Make V HGN The behavior of various components is described by the case of rising from low voltage to high voltage.

[0028] When V IN Increase to V REF When V HGN In order to make V HGN rises, transistor M12 turns on, causing M12 current 112 through transistor M12 to increase. As M12 current 112 increases, V HGN Rising accordingly (towards V IN ). It can be understood that the faster the M12 current 112 increases, the faster V HGN reaches its final value faster. As V HGNAs the voltage rises, the gate voltages of the transistors M15 and M16 also rise, which turns on the transistor M16 and turns off the transistor M15.

[0029] From the high gain node, the M12 current 112 can be divided into the M14 current 114 (flowing to ground through the transistor M14) and the M16 current 116 (flowing to ground through the resistor R11 and the transistor M16). It should be understood that if the resistor R11 does not exist, the M12 current 112 will be equal to the M14 current 114. Therefore, the speed at which the M12 current 112 increases will be limited by the speed at which the M14 current 114 increases. However, if Figure 1 As shown in , resistor R11 ensures an additional path to ground via resistor R11 and transistor M16. Because resistor R11 absorbs a portion of M12 current 112 flowing into the high gain node, M12 current 112 is no longer strictly limited to be equal to the amount of M14 current 114. As a result, M12 current 112 can increase faster, and V HGN can rise faster. Because V HGN The stronger the response, the faster the comparator is advantageously increased.

[0030] Figure 2 The overall figure shows that when the input voltage drops below the reference voltage Figure 1 The comparator architecture 100 has been Figure 1 The structure of the comparator architecture 100 is described. For the sake of brevity, further discussion of the comparator architecture 100 will be omitted. In the following paragraphs, the comparator architecture 100 will be described according to V IN Initially greater than V REF (make V HGN is a high voltage) but later becomes less than V REF (make V HGN Describe the behavior of various components from a high voltage drop to a low voltage.

[0031] When V IN Down to V REF When V HGN To make V HGN drops, transistor M12 is turned off, so that no current passes through transistor M12. N-BIAS is a high voltage, then transistor M14 is turned on, so that the charge at the high gain node can pass through transistor M14 to ground (M14 current 114). As M14 current 114 increases, V HGN It can be understood that the faster the M14 current 114 increases, the faster V HGN reaches its final value faster. As V HGN As the voltage drops, the gate voltages of the transistors M15 and M16 also drop.

[0032] like Figure 2 As shown in HGN When the voltage drops, transistor M15 turns on and transistor M16 turns off. Resistor R11 ensures that the M15 current 115 is diverted from the power supply voltage V DD is drawn through transistor M15 and into the high gain node through resistor R11. Because M15 current 115 is provided from inverter stage 130 to high gain stage 120, M14 current 114 can increase faster and V HGN can drop faster. Because V HGN The stronger the response, the faster the comparator is advantageously increased.

[0033] Figure 3 A comparator architecture 300 with increased impedance seen by a reference voltage is generally shown in accordance with aspects of the present disclosure.

[0034] The comparator architecture 300 may include a high impedance stage 310 , a high gain stage 320 , and an inverter stage 330 .

[0035] The high gain stage 320 may be similar in some respects to Figure 1-2 1. For example, transistor M31 may be similar to transistor M11, transistor M32 may be similar to transistor M12, transistor M33 may be similar to transistor M13, and transistor M34 may be similar to transistor M14. High gain stage 320 may include transistors having V HGN The high gain node, V HGN is provided to the inverter stage 330 .

[0036] Inverter stage 330 may be similar in some respects to Figure 1-2 For example, transistor M35 may be similar to transistor M15, transistor M36 may be similar to transistor M16, resistor R31 may be similar to resistor R11, and second inverter 332 may be similar to second inverter 132.

[0037] The high impedance stage 310 can be used to increase the impedance seen by the provider of the reference voltage. Figure 3 It can be seen that providing V REF to transistor M31, like Figure 1-2 Provide V REF to transistor M11. However, with Figure 1-2 Unlike the situation depicted in FIG. 1 , the reference voltage provider may not be directly exposed to transistor M31 or high gain stage 320. Alternatively, the reference voltage provider may provide a reference voltage V REF*, which is coupled to the positive terminal of operational amplifier 312. Because operational amplifier 312 has a high input impedance, less current will be drawn from the provider of the reference voltage, thereby improving the efficiency of the comparator.

[0038] The output of the operational amplifier 312 may be coupled to the gate of the transistor M37. The transistor M37 may be a transistor coupled to a power supply V DD-PX The drain of an n-type transistor. The power supply V DD-PX Can be similar to V DD , or in some embodiments may have a ratio of V DD The source of transistor M37 can be coupled to a Figure 1-2 V depicted in REF The voltage V REF The reference node may be coupled to the negative terminal of the operational amplifier 312 and to the high gain stage 320, in particular the source of the transistor M31.

[0039] It should also be understood that a high impedance stage (not shown) similar to high impedance stage 310 may be provided to isolate the input voltage V IN For example, a high impedance stage may have a high impedance input voltage V IN* , and can provide an input voltage V to the high gain stage 320 IN .

[0040] Figure 4 A comparator architecture 400 with increased impedance seen by a reference voltage and an input voltage is generally shown in accordance with aspects of the present disclosure.

[0041] The comparator architecture 400 may include a high impedance stage 410 , a high gain stage 420 , and an inverter stage 430 .

[0042] Inverter stage 430 may be similar in some respects to Figure 1-2 For example, transistor M45 may be similar to transistor M15, transistor M46 may be similar to transistor M16, resistor R41 may be similar to resistor R11, and second inverter 432 may be similar to second inverter 132.

[0043] The high gain stage 420 may be similar in some respects to Figure 1-2 The high gain stage 120 depicted in FIG. Figure 3 For example, the high gain stage 420 may be provided with an input voltage V IN and reference voltage V REF The high gain stage 420 can also provide a high gain node voltage V to the inverter stage 430. HGN .

[0044] However, high gain stage 420 may differ in important respects from Figure 1 to Figure 2 The high gain stage 120 depicted in FIG. Figure 3 In particular, the low impedance voltage V LOW-Z The low impedance transistor pair may include transistor M41 and transistor M43. The source of transistor M41 may be coupled to V LOW-Z , and the source of transistor M43 may be coupled to ground. Transistor M41 may be a p-type transistor. The drain of transistor M41 may be coupled to the gate of transistor M41 and the drain of transistor M43. Transistor M43 may be an n-type transistor. The gate of transistor M43 may be coupled to an n-type bias voltage V N-BIAS .

[0045] The drain of transistor M41 may also be coupled to the gate of transistor M42 and the gate of transistor M47. Transistor M42 and transistor M47 may be p-type transistors. The source of transistor M42 may be coupled to the input voltage V IN , and the source of transistor M47 can be coupled to the reference voltage V REF The drain of transistor M42 may be coupled to a transistor similar in some respects to Figure 1-3 In particular, similar to Figure 1 The high gain node may be coupled to inverter stage 430 in the manner depicted in FIG. 1 and 2 . In addition, the high gain node may be coupled to the drain of transistor M44. Transistor M44 may be an n-type transistor having a source coupled to ground. The gate of transistor M44 may be coupled to the gate of transistor M48. Transistor M48 may also be an n-type transistor having a source coupled to ground. The drain of transistor M48 may be coupled to the drain of transistor M47. High gain stage 420 may include a folded cascode differential to single-ended converter.

[0046] Alternatively, if Figure 4 As shown in , an active clamp including a clamp transistor M55 may be provided. In particular, the source of the clamp transistor M55 may be coupled to the high gain node, the drain of the clamp transistor M55 may be coupled to the gate and drain of transistor M48 and the gate of transistor M44, and the gate of the clamp transistor M55 may be coupled to a clamp voltage V CLM In some embodiments, the n-type transistor (transistor M44) coupled to the high gain node can have a higher speed than the p-type transistor, but has a lower voltage rating. To protect transistor M44 from high voltages (e.g., power supply voltage V DD-PX ) can provide active clamping. In particular, when V HGNWhen becomes too high, clamp transistor M55 turns on, allowing current to flow from the high gain node through transistor M48 to ground.

[0047] High impedance stage 410 may be similar in some respects to Figure 3 For example, the high impedance stage 410 may be provided with a high impedance input voltage V IN* and a high impedance reference voltage V REF* The high impedance stage 410 can also provide an input voltage V which is provided to the high gain stage 420. IN and the reference voltage V provided to the high gain stage 420 REF .

[0048] However, high impedance stage 410 may differ from Figure 3 The high impedance stage 310 is depicted in FIG. In particular, V IN* and V REF* Can be coupled to the gates of different transistor pairs. V IN* It can be coupled to a high impedance input transistor pair including transistor M49 (which can be an n-type transistor) and transistor M51 (which can be a p-type transistor). REF* A high impedance reference transistor pair including transistor M50 (which may be an n-type transistor) and transistor M52 (which may be a p-type transistor) may be coupled.

[0049] The sources of the p-type transistors (transistor M51 and transistor M52) can be coupled to the drain of transistor M54 (which can be a p-type transistor). The source of transistor M54 can be coupled to a power supply voltage V DD-PX , and the gate of transistor M54 can be coupled to the p-type bias voltage V P-BIAS-PX .

[0050] The sources of the n-type transistors (transistor M49 and transistor M50) can be coupled to the drain of transistor M53 (which can be an n-type transistor). The source of transistor M53 can be coupled to ground, and the gate of transistor M54 can be coupled to an n-type bias voltage V N-BIAS .

[0051] The drains of transistors M49 and M51 may be coupled to a voltage V supplied to high gain stage 420. IN The drains of transistors M50 and M52 may be coupled to a transistor having a voltage V REF The voltage is also provided to the high gain stage 420. The high impedance stage 410 may include a complementary symmetrical differential pair.

[0052] Figure 5A method 500 for comparing an input voltage to a reference voltage according to aspects of the present disclosure is generally shown. It will be understood that the method 500 or certain aspects thereof may be performed in whole or in part by any suitable system according to aspects of the present disclosure, for example, Figure 1-2 The comparator architecture 100 depicted in Figure 3 The comparator architecture 300 depicted in Figure 4 The comparator architecture 400 depicted in FIG.

[0053] At 505, the comparator architecture 400 optionally provides an input voltage based on the high impedance input voltage and the high voltage power supply, and / or provides a reference voltage based on the high impedance reference voltage and the high voltage power supply. The providing at 505 can be performed by, for example, the high impedance stage 310 and / or the high impedance stage 410. Therefore, the high impedance stage 310 and / or the high impedance stage 410 can constitute a device for increasing impedance.

[0054] At 510, the comparator architecture 400 receives an input voltage and a reference voltage at a first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes a high gain node having a high gain node voltage at a common drain. The receiving at 510 may be performed by, for example, Figure 1-2 The high gain stage 120 depicted in FIG. Figure 3 The high gain stage 320 depicted in FIG. Figure 4 Thus, high gain stage 120, high gain stage 320 and / or high gain stage 420 may constitute means for receiving an input voltage and a reference voltage and / or means for providing a high gain node having a high gain node voltage.

[0055] At 520, the comparator architecture 400 receives a high gain node voltage at a second stage including a resistor and an inverter transistor pair, wherein the gate of the inverter transistor pair is coupled to the high gain node of the first stage, and the resistor couples the high gain node of the first stage to the common drain of the inverter transistor pair. The receiving at 520 may be performed by, for example, Figure 1-2 The inverter stage 130 depicted in Figure 3 The inverter stage 330 and / or Figure 4 Thus, inverter stage 130, inverter stage 330, and / or inverter stage 430 may constitute a device for receiving a high gain node voltage.

[0056] At 530, the comparator architecture 400 provides current to the high gain node of the first stage, or draws current from the high gain node of the first stage. The providing or drawing at 530 may be performed by, for example Figure 1-2 The inverter stage 130 depicted in Figure 3 The inverter stage 330 and / or Figure 4 Thus, inverter stage 130, inverter stage 330, and / or inverter stage 430 may constitute means for sourcing current to or sinking current from a high gain node of a first stage.

[0057] At 540, the comparator architecture 400 generates an output voltage based on the difference between the input voltage and the reference voltage. The generation at 540 may be performed by, for example Figure 1-2 The inverter stage 130 depicted in Figure 3 The inverter stage 330 and / or Figure 4 Thus, inverter stage 130, inverter stage 330, and / or inverter stage 430 may constitute a device for generating an output voltage based on a difference between an input voltage and a reference voltage.

[0058] Figure 5 The functions depicted in the can be implemented in various ways consistent with the teachings of this article. In some designs, the functions can be implemented as one or more electrical components. In some designs, the functions can be implemented as a processing system including one or more processor components. In some designs, the functions can be implemented using, for example, at least a portion of one or more integrated circuits (e.g., ASICs). As discussed herein, an integrated circuit can include a processor, software, other related components, or any combination thereof. Therefore, the functions of different modules can be implemented, for example, as different subsets of integrated circuits, different subsets of software module sets, or combinations thereof. Moreover, it will be understood that a given subset (e.g., of an integrated circuit and / or software module set) can provide at least a portion of the functions for more than one module.

[0059] in addition, Figure 5 The functions depicted in and other components and functions described herein may be implemented using any suitable means. Such means may also be implemented, at least in part, using corresponding structures as taught herein. The above components may also correspond to similarly specified "codes" for functions. Therefore, in some aspects, one or more of such means may be implemented using one or more of processor components, integrated circuits, or other suitable structures as taught herein.

[0060] Figure 6 An exemplary electronic device 600 is generally shown in which aspects of the present disclosure may be advantageously employed.

[0061] The electronic device 600 may include Figure 1-2 The comparator architecture 100 described in Figure 3The comparator architecture 300 described in Figure 4 The comparator architecture 400 described in and / or any combination thereof. Figure 6 In the depiction of FIG. 6 , the electronic device 600 is shown as including a processor 610. The electronic device 600 may further include a cache 620. Figure 6 6 , the processor 610 is illustratively shown as being coupled to the memory 630 via a cache 620 between the processor 610 and the memory 630, but it will be understood that the electronic device 600 may also support other memory configurations known in the art.

[0062] Figure 6 Also depicted is a display controller 640 coupled to the processor 610 and a display 642.

[0066] In some cases, the electronic device 600 may be configured for wireless communications. Figure 6 Optional blocks are depicted in dashed lines, such as a coder / decoder (CODEC) 660 (e.g., an audio and / or voice CODEC) coupled to the processor 610. A speaker 662 and a microphone 664 may also be coupled to the CODEC 660. Additionally, a wireless antenna 652 may be coupled to a wireless controller 650, which is coupled to the processor 610. In the presence of one or more of these optional blocks, in certain aspects, the processor 610, display controller 640, memory 630, and wireless controller 650 are included in a system-in-package or system-on-chip device 670.

[0063] Thus, in certain aspects, the input device 612 and the power supply 672 are coupled to the system-on-chip device 670. Additionally, in certain aspects, as Figure 6 , where one or more optional blocks are present, the display 642, input device 612, speaker 662, microphone 664, wireless antenna 652, and power supply 672 are external to the system-on-chip device 670. However, each of the display 642, input device 612, speaker 662, microphone 664, wireless antenna 652, and power supply 672 can be coupled to a component, such as an interface or controller, of the system-on-chip device 670. In some embodiments, one or more of the components of the electronic device 600 can communicate with each other via a system bus.

[0064] It should be noted that although Figure 6 A generic electronic device 600 is generally depicted, but one or more of the components of the electronic device 600 may additionally or alternatively be integrated into a set-top box, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop computer, tablet computer, communication device, mobile phone, or other similar device.

[0065] Those skilled in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. In addition, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether this function is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art may implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0066] The methods, sequences and / or algorithms described in conjunction with the various aspects disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral with the processor.

[0067] Therefore, one aspect of the present invention may include a computer readable medium embodying a method for bus control. Therefore, the present invention is not limited to the illustrated examples, and any means for performing the functions described herein are included in aspects of the present invention.

[0068] In view of the above description and explanation, it will be appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithm steps described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits and steps have been generally described above in terms of their functionality. Whether this function is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0069] Thus, it will be understood that, for example, a device or any component of a device may be configured (or made operable or adapted) to provide functionality as taught herein. This may be achieved, for example, by manufacturing (e.g., preparing) the device or component so that it provides the functionality; by programming the device or component so that it provides the functionality; or by using some other appropriate implementation technique. As an example, an integrated circuit may be prepared to provide the necessary functionality. As another example, an integrated circuit may be prepared to support the necessary functionality and then configured (e.g., via programming) to provide the necessary functionality. As yet another example, a processor circuit may execute code to provide the necessary functionality.

[0070] In addition, the methods, sequences and / or algorithms described in conjunction with the various aspects disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of non-transitory storage medium known in the art. As used herein, the term "non-transitory" does not exclude any physical storage medium or memory, and in particular does not exclude dynamic memory (e.g., RAM), but only excludes interpretations that the medium can be interpreted as a signal that is temporarily propagated. An example storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral to the processor (e.g., cache memory).

[0071] Although the foregoing disclosure shows various illustrative aspects, it should be noted that various changes and modifications may be made to the illustrated examples without departing from the scope defined by the appended claims. The present disclosure is not intended to be limited to the specifically illustrated examples. For example, unless otherwise indicated, the functions, steps, and / or actions of the device claims according to the various aspects of the present disclosure described herein do not need to be performed in any particular order. In addition, although certain aspects may be described or claimed in singular form, plural forms may be contemplated unless expressly stated to be limited to the singular form.

[0072] It should be understood that any reference to the elements of this article using designations such as "first", "second", etc. generally does not limit the number or order of those elements. On the contrary, these designations can be used as a convenient method to distinguish two or more elements or element instances here. Therefore, the reference to the first and second elements does not mean that there are only two elements, and further does not mean that the first element must be before the second element in some way. In addition, unless otherwise specified, a group of elements may include one or more elements. In addition, the term "at least one of A, B or C" or "one or more of A, B or C" or "at least one of the group consisting of A, B and C" used in the specification or claims means "A or B or C or any combination of these elements".

[0073] The terms used herein are only used for the purpose of describing specific embodiments, rather than limiting any embodiments disclosed herein. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "include", "comprise", "contain", and / or "include" when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. Similarly, the phrase "based on" as used herein does not necessarily exclude the influence of other factors, and should be interpreted as "based at least in part on" rather than, for example, "based only on" in all cases.

[0074] It should be understood that terms such as "top" and "bottom", "left" and "right", "vertical" and "horizontal", etc. are strictly relative terms used relative to each other and do not indicate or imply any relationship with gravity, manufacturing equipment used to manufacture the components described herein, or some other device to which the components described herein are coupled, mounted, etc. The term "exchange" can refer to one or more data transmissions from one component to another component. For example, with respect to a particular component, the exchange function can be composed of a send function, a receive function, or any combination thereof.

Claims

1. A system comprising: a first stage configured to receive an input voltage and a reference voltage, the first stage comprising an input transistor pair, wherein: The input voltage is coupled to the input transistor pair; The input transistor pair is coupled to ground; and The input transistor pair includes a high gain node having a high gain node voltage at a common drain; and a second stage coupled to the high gain node and configured to generate an output voltage based on a difference between the input voltage and the reference voltage, the second stage comprising a resistor and an inverter transistor pair, wherein: The gates of the inverter transistor pair are coupled to the high gain node of the first stage; and The resistor couples the high gain node of the first stage to a common drain of the inverter transistor pair, and the resistor is configured to source current to and / or sink current from the high gain node of the first stage.

2. The system of claim 1 , wherein the first stage further comprises a reference transistor pair, wherein: The reference voltage is coupled to the reference transistor pair; The reference transistor pair is coupled to ground; The reference transistor pair includes a drain-gate node having a drain-gate voltage at a common drain; as well as The drain-gate node is coupled to corresponding gates of p-type transistors respectively included in the input transistor pair and the reference transistor pair. 3 . The system of claim 1 , wherein the second stage is configured to draw current from the high gain node when the high gain node voltage increases. 4 . The system of claim 1 , wherein the second stage is configured to provide current to the high gain node when the high gain node voltage decreases.

5. The system of claim 1 , further comprising a third stage comprising an operational amplifier and a transistor and configured to: providing the input voltage, wherein the input voltage is provided based on a high impedance input voltage and a high voltage power supply; or The reference voltage is provided, wherein the reference voltage is provided based on a high impedance reference voltage and a high voltage power supply.

6. The system of claim 1 , further comprising a third stage comprising a high impedance input transistor pair and a high impedance reference transistor pair, wherein: the high impedance input transistor pair being configured to receive a high impedance input voltage at gates of the high impedance input transistor pair and to provide the input voltage to the first stage from a common drain of the high impedance input transistor pair; as well as The high impedance reference transistor pair is configured to receive a high impedance reference voltage at gates of the high impedance reference transistor pair and to provide the reference voltage to the first stage from a common drain of the high impedance reference transistor pair.

7. The system of claim 6, wherein the third stage further comprises: a p-type transistor having a gate coupled to a p-type bias voltage, a source coupled to a power supply, and a drain coupled to sources of the p-type transistor in the high impedance input transistor pair and the p-type transistor in the high impedance reference transistor pair; as well as an n-type transistor having a gate coupled to an n-type bias voltage, a source coupled to ground, and a drain coupled to sources of the n-type transistor in the high impedance input transistor pair and the n-type transistor in the high impedance reference transistor pair.

8. The system of claim 1 , wherein the first stage comprises a folded cascode, the folded cascode comprising: the input transistor pair; a reference transistor pair coupled to the reference voltage, to ground, and including a reference transistor pair node coupled to a drain of the reference transistor pair; as well as a low impedance transistor pair coupled to a low impedance voltage, to ground, and including a low impedance transistor pair node coupled to the drains of the low impedance transistor pair, wherein: The low impedance transistor pair node is coupled to gates of p-type transistors included in the low impedance transistor pair, the input transistor pair, and the reference transistor pair.

9. The system of claim 8, wherein the first stage further comprises a clamp transistor, wherein a source of the clamp transistor is coupled to the high gain node, a gate of the clamp transistor is coupled to a clamp voltage, and a drain of the clamp transistor is coupled to gates of p-type transistors included in the input transistor pair and the reference transistor pair, respectively.

10. The system of claim 1, wherein the system is provided in a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a desktop computer, a laptop computer, a tablet computer, a communication device, and a mobile phone.

11. A method comprising: An input voltage and a reference voltage are received at a first stage including an input transistor pair, wherein: The input voltage is coupled to the input transistor pair; The input transistor pair is coupled to ground; and The input transistor pair includes a high gain node having a high gain node voltage at a common drain; and A high gain node voltage is received at a second stage including a resistor and an inverter transistor pair, wherein: The gates of the inverter transistor pair are coupled to the high gain node of the first stage; and the resistor coupling the high gain node of the first stage to a common drain of the inverter transistor pair; sourcing current to or sinking current from the high gain node of the first stage; and An output voltage is generated based on a difference between the input voltage and the reference voltage.

12. The method of claim 11, wherein the first stage further comprises a reference transistor pair, wherein: The reference voltage is coupled to the reference transistor pair; The reference transistor pair is coupled to ground; The reference transistor pair includes a drain-gate node having a drain-gate voltage at a common drain; as well as The drain-gate node is coupled to corresponding gates of p-type transistors respectively included in the input transistor pair and the reference transistor pair.

13. The method of claim 11, further comprising drawing current from the high gain node when the high gain node voltage increases. 14 . The method of claim 11 , further comprising providing a current to the high gain node when the high gain node voltage decreases.

15. The method according to claim 11, further comprising: providing the input voltage from a third stage including an operational amplifier and a transistor, wherein the input voltage is provided based on a high impedance input voltage and a high voltage power supply; and / or The reference voltage is provided from the third stage, wherein the reference voltage is provided based on a high impedance reference voltage and a high voltage power supply.

16. The method according to claim 11, further comprising: receiving, at a third stage including a high impedance input transistor pair, a high impedance input voltage at gates of the high impedance input transistor pair; providing the input voltage to the first stage from a common drain of the high impedance input transistor pair; receiving, at a high impedance reference transistor pair included in the third stage, a high impedance reference voltage at gates of the high impedance reference transistor pair; as well as The reference voltage is provided to the first stage from a common drain of the pair of high impedance reference transistors.

17. The method of claim 16, wherein the third stage further comprises: a p-type transistor having a gate coupled to a p-type bias voltage, a source coupled to a power supply, and a drain coupled to a source of the p-type transistor in the high impedance input transistor pair and a source of the p-type transistor in the high impedance reference transistor pair; as well as an n-type transistor having a gate coupled to an n-type bias voltage, a source coupled to ground, and a drain coupled to a source of the n-type transistor in the high impedance input transistor pair and a source of the n-type transistor in the high impedance reference transistor pair.

18. The method of claim 11, wherein the first stage comprises a folded cascode, the folded cascode comprising: the input transistor pair; a reference transistor pair coupled to the reference voltage, to ground, and including a reference transistor pair node coupled to a drain of the reference transistor pair; as well as a low impedance transistor pair coupled to a low impedance voltage, to ground, and including a low impedance transistor pair node coupled to the drains of the low impedance transistor pair, wherein: The low impedance transistor pair node is coupled to gates of p-type transistors included in the low impedance transistor pair, the input transistor pair, and the reference transistor pair.

19. The method of claim 18, wherein the first stage further comprises a clamp transistor, wherein a source of the clamp transistor is coupled to the high gain node, a gate of the clamp transistor is coupled to a clamp voltage, and a drain of the clamp transistor is coupled to gates of p-type transistors included in the input transistor pair and the reference transistor pair, respectively.

20. The method of claim 11, wherein the method is implemented in a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a desktop computer, a laptop computer, a tablet computer, a communication device, and a mobile phone.

21. A system comprising: means for receiving an input voltage and a reference voltage, wherein the means for receiving comprises an input transistor pair coupled to the input voltage, wherein the input transistor pair comprises a high gain node having a high gain node voltage at a common drain; means for receiving said high gain node voltage; means for sourcing current to or sinking current from the high gain node of the means for receiving an input voltage and a reference voltage; as well as Means for generating an output voltage based on a difference between the input voltage and the reference voltage.

22. The system of claim 21, wherein the means for receiving further comprises means for providing a drain-gate voltage.

23. The system of claim 21, wherein the means for sourcing or sinking current comprises means for sinking current from the high gain node when the high gain node voltage is increased.

24. The system of claim 21, wherein the means for sourcing or sinking current comprises means for providing current to the high gain node when the high gain node voltage decreases.

25. The system of claim 21, further comprising means for increasing impedance, the means for increasing impedance further comprising: means for providing the input voltage, wherein the input voltage is provided based on a high impedance input voltage and a high voltage power supply; or means for providing the reference voltage, wherein the reference voltage is provided based on a high impedance reference voltage and a high voltage power supply.

26. The system of claim 21, further comprising means for increasing impedance, the means for increasing impedance further comprising: means for receiving a high impedance input voltage and a high impedance reference voltage; as well as means for providing the input voltage and the reference voltage to the means for receiving.

27. The system of claim 26, wherein the means for increasing impedance further comprises: means for providing current to said means for increasing impedance, wherein said means for providing current is coupled to a power source; as well as means for sinking current from the means for increasing impedance, wherein the means for sinking current is coupled to ground.

28. The system of claim 21, wherein the means for receiving comprises a folded cascode, the folded cascode comprising: the input transistor pair; a reference transistor pair coupled to the reference voltage, to ground, and including a reference transistor pair node coupled to a drain of the reference transistor pair; as well as a low impedance transistor pair coupled to a low impedance voltage, to ground, and including a low impedance transistor pair node coupled to the drains of the low impedance transistor pair, wherein: The low impedance transistor pair node is coupled to gates of p-type transistors included in the low impedance transistor pair, the input transistor pair, and the reference transistor pair.

29. The system of claim 21, further comprising means for clamping the high gain node.

30. The system of claim 21, wherein the system is provided in a device selected from the group consisting of: a set-top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a desktop computer, a laptop computer, a tablet computer, a communication device, and a mobile phone.

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