Semiconductor devices including dummy patterns

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region, a peripheral region, and a boundary region; a stacked structure located on the cell region and including alternately stacked insulating layers and interconnect layers; a molding layer located on the peripheral region and the boundary region; a selected line isolation pattern extending into the stacked structure; a cell channel structure passing through the stacked structure; and a first dummy pattern extending into the molding layer on the peripheral region, wherein the upper surface of the first dummy pattern, the upper surface of the selected line isolation pattern, and the upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends from the upper surface of the first dummy pattern, the upper surface of the selected line isolation pattern, and the upper surface of the cell channel structure toward the substrate parallel to the selected line isolation pattern or the cell channel structure.

Description

[0001] Korean Patent Application No. 10-2019-0083230, entitled "Semiconductor Device Including Dummy Patterns," filed on July 10, 2019, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a semiconductor device including a dummy pattern. Background Technology

[0003] Methods for forming semiconductor devices may include multiple thin film formation processes, multiple patterning processes, and multiple annealing processes. Summary of the Invention

[0004] An embodiment can be implemented by providing a semiconductor device comprising: a substrate having a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a stacked structure on the cell region of the substrate, the stacked structure including a plurality of insulating layers and a plurality of interconnect layers alternately stacked; a molding layer on the peripheral region and the boundary region of the substrate; a selected line isolation pattern extending into the stacked structure; a cell channel structure passing through the stacked structure; and a plurality of first dummy patterns extending into the molding layer on the peripheral region, wherein the upper surfaces of the plurality of first dummy patterns, the upper surface of the selected line isolation pattern, and the upper surface of the cell channel structure are substantially coplanar, and at least one of the plurality of first dummy patterns extends substantially parallel to the selected line isolation pattern or the cell channel structure toward the substrate from the upper surfaces of the plurality of first dummy patterns, the upper surface of the selected line isolation pattern, and the upper surface of the cell channel structure.

[0005] An embodiment can be implemented by providing a semiconductor device comprising: a substrate having a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a stacked structure located on the cell region of the substrate and including a plurality of insulating layers and a plurality of interconnect layers alternately stacked; a molding layer on the peripheral region and the boundary region of the substrate; a cell channel structure passing through the stacked structure; and a first dummy channel structure extending into the molding layer on the peripheral region, wherein the upper surface of the first dummy channel structure and the upper surface of the cell channel structure are substantially coplanar, and the first dummy channel structure extends substantially parallel to the cell channel structure from the upper surface of the first dummy channel structure and the upper surface of the cell channel structure toward the substrate.

[0006] The embodiment can be implemented by providing a semiconductor device comprising: a substrate having cell regions and peripheral regions; a stacked structure located on the cell regions of the substrate and including a plurality of insulating layers and a plurality of interconnect layers alternately stacked; a molding layer on the peripheral regions of the substrate; a selected line isolation pattern extending into the stacked structure; a cell channel structure passing through the stacked structure; and a dummy isolation pattern extending into the molding layer, wherein the upper surface of the dummy isolation pattern and the upper surface of the selected line isolation pattern are substantially coplanar, and the dummy isolation pattern extends from the upper surface of the dummy isolation pattern and the upper surface of the selected line isolation pattern toward the substrate substantially parallel to the selected line isolation pattern. Attached Figure Description

[0007] The features will be clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0008] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment is shown;

[0009] Figure 2 A layout diagram of a semiconductor device according to an embodiment is shown;

[0010] Figures 3 to 5 It shows Figure 1 A magnified view of a portion;

[0011] Figure 6 A layout diagram of a semiconductor device according to an embodiment is shown;

[0012] Figures 7 to 9 A cross-sectional view of a semiconductor device according to an embodiment is shown;

[0013] Figure 10 A layout diagram of a semiconductor device according to an embodiment is shown;

[0014] Figure 11 A cross-sectional view of a semiconductor device according to an embodiment is shown;

[0015] Figure 12 A layout diagram of a semiconductor device according to an embodiment is shown;

[0016] Figure 13 and Figure 14 A cross-sectional view of a semiconductor device according to an embodiment is shown;

[0017] Figure 15 and Figure 16 A layout diagram of a semiconductor device according to an embodiment is shown; and

[0018] Figures 17 to 24 A cross-sectional view is shown of a stage in a method for forming a semiconductor device according to an embodiment. Detailed Implementation

[0019] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment is shown. Figure 2 A layout diagram of a semiconductor device is shown. Figure 1 It is along Figure 2 The sectional view taken by lines 1-1′ and 2-2′. Figures 3 to 5 It shows Figure 1 A magnified view of a portion thereof. The semiconductor device according to embodiments may include non-volatile memory such as V-NAND memory or three-dimensional (3D) flash memory. The semiconductor device according to embodiments can be interpreted as including a cell-on-periphery (COP) structure.

[0020] Reference Figure 1 The semiconductor device according to the embodiment may include, for example, a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support 38, a lower molding layer 39, a stacked structure 40, a molding layer 49, a select line isolation pattern 55, a plurality of first dummy isolation patterns 55D1, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a second dummy channel structure 59D2, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89. The substrate 21 may include a cell region CA, a connection region EX, a boundary region BR, and a peripheral region PR. The stacked structure 40 may include a plurality of insulating layers 41 and a plurality of interconnecting layers 45 stacked alternately and repeatedly.

[0021] Reference Figure 2 The semiconductor device according to the embodiment may include a plurality of select line isolation patterns 55, a plurality of first dummy isolation patterns 55D1, a plurality of second dummy isolation patterns 55D2, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a plurality of second dummy channel structures 59D2, a plurality of third dummy channel structures 59D3, a plurality of word line isolation patterns 75, through electrodes 87, and a plurality of word line plugs 97.

[0022] Reference Figure 3In one embodiment, each of the plurality of unit channel structures 59 may include a core pattern 61, a channel layer 62 surrounding the outer side of the core pattern 61, a data storage pattern 66 surrounding the outer side of the channel layer 62, and a pad 67. The data storage pattern 66 may include a tunnel insulation layer 63 surrounding the outer side of the channel layer 62, a charge storage layer 64 surrounding the outer side of the tunnel insulation layer 63, and a barrier layer 65 surrounding the outer side of the charge storage layer 64.

[0023] The core pattern 61 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, polycrystalline silicon, or combinations thereof. The channel layer 62 may include a semiconductor layer such as polycrystalline silicon, amorphous silicon, monocrystalline silicon, or combinations thereof. The tunnel insulating layer 63 may include an insulating layer such as silicon oxide. The charge storage layer 64 may include an insulating layer such as silicon nitride. The barrier layer 65 may include an insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof. The pad 67 may include a conductive layer such as metal, metal nitride, metal oxide, metal silicide, conductive carbon, polycrystalline silicon, or combinations thereof.

[0024] Reference Figure 4 In the implementation scheme, each of the plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, and the plurality of third dummy channel structures 59D3 may include the same material as the plurality of unit channel structures 59. For example, each of the plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, and the plurality of third dummy channel structures 59D3 may include a core pattern 61, a channel layer 62, a data storage pattern 66, and a pad 67. The data storage pattern 66 may include a tunnel insulation layer 63, a charge storage layer 64, and a barrier layer 65.

[0025] Reference Figure 5 In the implementation scheme, the second embedded conductive pattern 37 can pass through the data storage pattern 66 and directly contact the side surface of the channel layer 62.

[0026] Refer again Figures 1 to 5 The connecting region EX can be continuous with the cell region CA (e.g., it can be directly adjacent to and continuously extend from the cell region CA). The boundary region BR can be between the cell region CA and the peripheral region PR. In this embodiment, the boundary region BR can be between the connecting region EX and the peripheral region PR.

[0027] The stacked structure 40 can be on the cell region CA of the substrate 21. The stacked structure 40 can extend to the connection region EX. The molded layer 49 can be on the peripheral region PR and the boundary region BR of the substrate 21. The molded layer 49 can extend on the stacked structure 40 on the connection region EX.

[0028] Multiple word line isolation patterns 75 may be parallel to each other. Each of the multiple word line isolation patterns 75 may intersect the stack structure 40 (e.g., may extend in a first direction). Each of the multiple word line isolation patterns 75 may extend into the stack structure 40 in a second direction intersecting the first direction. In an embodiment, each of the multiple word line isolation patterns 75 may pass through the stack structure 40, the support 38, and the second embedded conductive pattern 37, and extend into the first embedded conductive pattern 34. The second direction may intersect the upper surface of the substrate 21 (e.g., the second direction may be...). Figure 1 The vertical direction in the diagram). In an embodiment, the second direction may be perpendicular to the upper surface of the substrate 21. The first direction may be perpendicular to the second direction. The first direction may be parallel to the upper surface of the substrate 21 (e.g., the first direction may be the vertical direction in the diagram). Figure 2 (Horizontal direction in the middle).

[0029] Multiple word line isolation patterns 75 may correspond to word line cutouts. Some of the multiple interconnect layers 45 may correspond to word lines. At least one of the multiple interconnect layers 45 adjacent to the lower surface of the stack structure 40 (e.g., the surface close to the substrate 21 in the second direction) may correspond to a ground select line (GSL). A second buried conductive pattern 37 may correspond to a source line or a common source line (CSL).

[0030] Each of the plurality of select line isolation patterns 55 may exist between a plurality of word line isolation patterns 75. Each of the plurality of select line isolation patterns 55 may intersect with the stack structure 40 on the cell region CA (e.g., may extend in a first direction). Each of the plurality of select line isolation patterns 55 may extend in the first direction into the connection region EX. Each of the plurality of select line isolation patterns 55 may extend in a second direction into the stack structure 40. In an embodiment, at least one of the plurality of interconnect layers 45 adjacent to the upper surface of the stack structure 40 (e.g., the surface away from the substrate 21 in the second direction) may correspond to a string select line (SSL). Each of the plurality of select line isolation patterns 55 may pass through some of the plurality of interconnect layers 45 adjacent to the upper surface of the stack structure 40.

[0031] Each of the plurality of first dummy isolation patterns 55D1 may extend in a second direction into the molding layer 49 on the peripheral region PR. Each of the plurality of first dummy isolation patterns 55D1 may partially penetrate the molding layer 49. The plurality of first dummy isolation patterns 55D1 may comprise the same material as the plurality of select line isolation patterns 55. The plurality of select line isolation patterns 55 and the plurality of first dummy isolation patterns 55D1 may comprise silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. The upper surfaces of the plurality of select line isolation patterns 55 and the plurality of first dummy isolation patterns 55D1 may be substantially coplanar.

[0032] As described above, the second direction can correspond to the direction from the upper surface of the plurality of selected line isolation patterns 55 and the plurality of first dummy isolation patterns 55D1 toward the substrate 21, for example, Figure 1 The vertical direction in the middle. Each of the plurality of first dummy isolation patterns 55D1 may be substantially parallel to each of the plurality of selection line isolation patterns 55, for example, each of the plurality of first dummy isolation patterns 55D1 may extend in the second direction. The lower ends of the plurality of first dummy isolation patterns 55D1 (e.g., the ends facing or near the substrate 21) may be at a similar level relative to the lower ends of the plurality of selection line isolation patterns 55 (e.g., at a similar distance from the substrate 21 in the second direction).

[0033] Each of the plurality of second dummy isolation patterns 55D2 can be on the boundary region BR. The plurality of second dummy isolation patterns 55D2 can have a similar construction to that of the plurality of first dummy isolation patterns 55D1 and the plurality of selected line isolation patterns 55.

[0034] Each of the plurality of cell channel structures 59 may extend in a second direction into the stacked structure 40 on the cell region CA. Each of the plurality of cell channel structures 59 may pass through the stacked structure 40, the support 38, and the second embedded conductive pattern 37, and extend into the first embedded conductive pattern 34. Bit line plugs 77 may be on the plurality of cell channel structures 59. Multiple bit lines 79 may be on the plurality of bit line plugs 77.

[0035] Each of the plurality of first dummy channel structures 59D1 can extend in the second direction into the molding layer 49 on the peripheral region PR. Some of the plurality of first dummy channel structures 59D1 can pass through the molding layer 49, the support 38, and the source molding layer 35, and extend into the plurality of dummy conductive patterns 34D. Each of the plurality of second dummy channel structures 59D2 can extend in the second direction into the molding layer 49 on the boundary region BR. Each of the plurality of second dummy channel structures 59D2 can pass through the molding layer 49 and extend into the lower molding layer 39. Each of the plurality of third dummy channel structures 59D3 can extend in the second direction into the molding layer 49 on the connection region EX and into the stack structure 40. Some of the plurality of third dummy channel structures 59D3 can pass through the molding layer 49, the stack structure 40, the support 38, and the second embedded conductive pattern 37, and extend into the first embedded conductive pattern 34.

[0036] The plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, and the plurality of third dummy channel structures 59D3 may comprise the same material as the plurality of unit channel structures 59. The upper surfaces (e.g., surfaces facing away from or away from the substrate 21) of the plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, the plurality of third dummy channel structures 59D3, and the plurality of unit channel structures 59 may be substantially coplanar. Each of the plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, and the plurality of third dummy channel structures 59D3 may extend in a second direction and may be substantially parallel to each of the plurality of unit channel structures 59. The lower ends of the plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, and the plurality of third dummy channel structures 59D3 may be at a similar level to the lower ends of the plurality of unit channel structures 59.

[0037] In the implementation scheme, the upper surfaces of the plurality of select line isolation patterns 55, the plurality of first dummy isolation patterns 55D1, the plurality of second dummy isolation patterns 55D2, the plurality of first dummy channel structures 59D1, the plurality of second dummy channel structures 59D2, the plurality of third dummy channel structures 59D3, and the plurality of unit channel structures 59 may be substantially coplanar. The plurality of first dummy isolation patterns 55D1 and / or the plurality of first dummy channel structures 59D1 may be referred to as a plurality of first dummy patterns. The plurality of second dummy isolation patterns 55D2 and / or the plurality of second dummy channel structures 59D2 may be referred to as a plurality of second dummy patterns.

[0038] Each of the plurality of through electrodes 87 may extend in the second direction into the molding layer 49 on the peripheral region PR. Each of the plurality of through electrodes 87 may pass through the third upper insulating layer 85, the second upper insulating layer 83, the first upper insulating layer 73, the molding layer 49, the lower molding layer 39, the fourth lower insulating layer 33, and the third lower insulating layer 31, and contact a selected one of the plurality of peripheral circuit interconnects 29. Each of the plurality of through electrodes 87 may be between a selected one of the plurality of first dummy channel structures 59D1 and the cell region CA. In an embodiment, each of the plurality of through electrodes 87 may be between a selected one of the plurality of first dummy channel structures 59D1 and the boundary region BR.

[0039] Figure 6 A layout diagram of a semiconductor device according to an embodiment is shown. Figures 7 to 9 It shows along Figure 6 The lines 3-3′ and 4-4′ are used to describe Figure 6 A cross-sectional view of a semiconductor device.

[0040] Reference Figure 6The semiconductor device according to the embodiment may include a plurality of select line isolation patterns 55, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a plurality of second dummy channel structures 59D2, a plurality of third dummy channel structures 59D3, a plurality of word line isolation patterns 75, a plurality of through electrodes 87, and a plurality of word line plugs 97. The plurality of cell channel structures 59 may be on a cell region CA. The plurality of first dummy channel structures 59D1 and the plurality of through electrodes 87 may be on a peripheral region PR. The plurality of second dummy channel structures 59D2 may be on a boundary region BR. The plurality of third dummy channel structures 59D3 may be on a connection region EX.

[0041] Reference Figure 7 The semiconductor device according to the embodiment may include a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support member 38, a lower molding layer 39, a stacked structure 40, a molding layer 49, a select line isolation pattern 55, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a second dummy channel structure 59D2, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89.

[0042] Each of the plurality of first dummy channel structures 59D1 can extend in the second direction into the molding layer 49 on the peripheral region PR. Some of the plurality of first dummy channel structures 59D1 can pass through the molding layer 49, the support 38, and the source molding layer 35, and extend into the plurality of dummy conductive patterns 34D. Others of the plurality of first dummy channel structures 59D1 can pass through the molding layer 49 and extend into the lower molding layer 39. A second dummy channel structure 59D2 can extend in the second direction into the molding layer 49 on the boundary region BR. The second dummy channel structure 59D2 can pass through the molding layer 49 and extend into the lower molding layer 39. Each of the plurality of third dummy channel structures 59D3 can extend in the second direction into the molding layer 49 on the connection region EX and into the stack structure 40. Some of the plurality of third dummy channel structures 59D3 can pass through the molding layer 49, the stack structure 40, the support 38, and the second embedded conductive pattern 37, and extend into the first embedded conductive pattern 34.

[0043] The upper surfaces of the plurality of first dummy channel structures 59D1, second dummy channel structures 59D2, plurality of third dummy channel structures 59D3, and plurality of unit channel structures 59 can be substantially coplanar. The lower ends of the plurality of first dummy channel structures 59D1, second dummy channel structures 59D2, and third dummy channel structures 59D3 can be at similar levels to the lower ends of the plurality of unit channel structures 59. The lateral width of each of the plurality of first dummy channel structures 59D1, second dummy channel structures 59D2, and third dummy channel structures 59D3 can be substantially equal to the lateral width of each of the plurality of unit channel structures 59.

[0044] Reference Figure 8 The semiconductor device according to the embodiment may include a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support member 38, a lower molding layer 39, a lower stack structure 140, an upper stack structure 240, a first molding layer 149, a second molding layer 249, a select line isolation pattern 55, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a second dummy channel structure 59D2, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89.

[0045] The lower stack structure 140 may include a plurality of first insulating layers 141 and a plurality of first interconnect layers 145 stacked alternately and repeatedly. The upper stack structure 240 may include a plurality of second insulating layers 241 and a plurality of second interconnect layers 245 stacked alternately and repeatedly. The upper stack structure 240 may be on the lower stack structure 140. The lower stack structure 140 and the upper stack structure 240 may constitute a stack structure. A second molding layer 249 may be on the first molding layer 149. The first molding layer 149 and the second molding layer 249 may constitute a molding layer. The interface between the lower stack structure 140 and the upper stack structure 240, and the interface between the first molding layer 149 and the second molding layer 249, may be substantially coplanar.

[0046] Each of the plurality of unit channel structures 59 can pass through the upper stack structure 240, the lower stack structure 140, the support member 38, and the second embedded conductive pattern 37, and can extend into the first embedded conductive pattern 34. Some of the plurality of first dummy channel structures 59D1 can pass through the second molding layer 249, the first molding layer 149, the support member 38, and the source molding layer 35, and can extend into the plurality of dummy conductive patterns 34D. Some of the other plurality of first dummy channel structures 59D1 can pass through the second molding layer 249 and the first molding layer 149, and can extend into the lower molding layer 39. The second dummy channel structure 59D2 can pass through the second molding layer 249 and the first molding layer 149, and extends into the lower molding layer 39.

[0047] Some of the plurality of third dummy channel structures 59D3 may pass through the second molding layer 249, the upper stack structure 240, the lower stack structure 140, the support member 38, and the second embedded conductive pattern 37, and may extend into the first embedded conductive pattern 34. Others of the plurality of third dummy channel structures 59D3 may pass through the second molding layer 249, the first molding layer 149, the lower stack structure 140, the support member 38, and the second embedded conductive pattern 37, and may extend into the first embedded conductive pattern 34.

[0048] The lower ends of the plurality of first dummy channel structures 59D1, the lower ends of the second dummy channel structure 59D2, and the lower ends of the plurality of third dummy channel structures 59D3 can be at a similar level to the lower ends of the plurality of unit channel structures 59. Compared to the interface between the lower stack structure 140 and the upper stack structure 240, the lower ends of the plurality of first dummy channel structures 59D1, the lower ends of the second dummy channel structure 59D2, and the lower ends of the plurality of third dummy channel structures 59D3 can be relatively closer to the upper surface of the substrate 21. The lateral width of each of the plurality of first dummy channel structures 59D1, second dummy channel structures 59D2, and third dummy channel structures 59D3 can be substantially equal to the lateral width of each of the plurality of unit channel structures 59.

[0049] Reference Figure 9The semiconductor device according to the embodiment may include a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support member 38, a lower molding layer 39, a lower stack structure 140, an upper stack structure 240, a first molding layer 149, a second molding layer 249, a select line isolation pattern 55, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a second dummy channel structure 59D2, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89.

[0050] The lower ends of the plurality of first dummy channel structures 59D1 and the lower ends of the second dummy channel structure 59D2 may be at a higher level than the lower ends of the plurality of third dummy channel structures 59D3 and the lower ends of the plurality of unit channel structures 59 (e.g., further away from the substrate 21 in the second direction). For example, the lower ends of the plurality of first dummy channel structures 59D1 and the lower ends of the second dummy channel structure 59D2 may be further away from the upper surface of the substrate 21 than the distances from the lower ends of the plurality of third dummy channel structures 59D3 and the lower ends of the plurality of unit channel structures 59 to the upper surface of the substrate 21.

[0051] The lower ends of the plurality of first dummy channel structures 59D1 and the lower ends of the second dummy channel structure 59D2 may be located at the level of the interface between the lower stack structure 140 and the upper stack structure 240, adjacent to or close to it. In an embodiment, the lower ends of the plurality of first dummy channel structures 59D1 and the lower ends of the second dummy channel structure 59D2 may be relatively closer to the upper surface of the substrate 21 than the interface between the lower stack structure 140 and the upper stack structure 240 to the upper surface of the substrate. Each of the second dummy channel structure 59D2 and the plurality of first dummy channel structures 59D1 may pass through the second molding layer 249 and extend into the first molding layer 149.

[0052] Figure 10 A layout diagram of a semiconductor device according to an embodiment is shown. Figure 11 It shows along Figure 10 The lines 5-5′ and 6-6′ are used to describe Figure 10 A cross-sectional view of a semiconductor device.

[0053] Reference Figure 10The semiconductor device according to the embodiment may include a plurality of select line isolation patterns 55, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a plurality of second dummy channel structures 59D2, a plurality of third dummy channel structures 59D3, a plurality of word line isolation patterns 75, through electrodes 87 and a plurality of word line plugs 97.

[0054] Reference Figure 11 The semiconductor device according to the embodiment may include a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support member 38, a lower molding layer 39, a stacked structure 40, a molding layer 49, a select line isolation pattern 55, a plurality of cell channel structures 59, a plurality of first dummy channel structures 59D1, a second dummy channel structure 59D2, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89.

[0055] Each of the second dummy channel structure 59D2 and the plurality of first dummy channel structures 59D1 may have a width relatively smaller than each of the plurality of third dummy channel structures 59D3 and / or each of the plurality of unit channel structures 59. For example, each of the plurality of first dummy channel structures 59D1 (e.g., in a first direction or horizontal direction) may have a first width W1. The second dummy channel structure 59D2 may have a second width W2. Each of the plurality of third dummy channel structures 59D3 may have a third width W3. Each of the plurality of unit channel structures 59 may have a fourth width W4. Each of the first width W1 and the second width W2 may be smaller than the third width W3 or the fourth width W4. The second width W2 may be substantially equal to the first width W1. The third width W3 may be substantially equal to the fourth width W4.

[0056] Figure 12 A layout diagram of a semiconductor device according to an embodiment is shown. Figure 13 and Figure 14 It shows along Figure 12 The lines 7-7′ and 8-8′ are used to describe Figure 12 A cross-sectional view of a semiconductor device.

[0057] Reference Figure 12The semiconductor device according to the embodiment may include a plurality of select line isolation patterns 55, a plurality of first dummy isolation patterns 55D1, a plurality of second dummy isolation patterns 55D2, a plurality of cell channel structures 59, a plurality of third dummy channel structures 59D3, a plurality of word line isolation patterns 75, through electrodes 87, and a plurality of word line plugs 97. The plurality of select line isolation patterns 55 may be on cell regions CA. The plurality of first dummy isolation patterns 55D1 may be on peripheral regions PR. The plurality of second dummy isolation patterns 55D2 may be on boundary regions BR.

[0058] Reference Figure 13 The semiconductor device according to the embodiment may include a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support member 38, a lower molding layer 39, a stacked structure 40, a molding layer 49, a select line isolation pattern 55, a plurality of first dummy isolation patterns 55D1, a second dummy isolation pattern 55D2, a plurality of cell channel structures 59, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89.

[0059] Each of the second dummy isolation pattern 55D2 and the plurality of first dummy isolation patterns 55D1 may extend into the molding layer 49 in a second direction. Each of the second dummy isolation pattern 55D2 and the plurality of first dummy isolation patterns 55D1 may include the same material as the selection line isolation pattern 55. The upper surfaces of the selection line isolation pattern 55, the plurality of unit channel structures 59, the plurality of third dummy channel structures 59D3, the plurality of first dummy isolation patterns 55D1, and the second dummy isolation pattern 55D2 may be substantially coplanar.

[0060] As described above, the second direction can correspond to the direction from the upper surface of the selection line isolation pattern 55, the plurality of unit channel structures 59, the plurality of third dummy channel structures 59D3, the plurality of first dummy isolation patterns 55D1 and the second dummy isolation pattern 55D2 toward the substrate 21 (e.g., Figure 13(Vertical direction in the middle). Each of the second dummy isolation pattern 55D2 and the plurality of first dummy isolation patterns 55D1 can extend in the second direction and can be substantially parallel to each of the plurality of selection line isolation patterns 55. The lower ends of the plurality of first dummy isolation patterns 55D1 and the lower ends of the second dummy isolation pattern 55D2 can be substantially at the same level as the lower ends of the selection line isolation patterns 55. Compared with the lower ends of the plurality of unit channel structures 59 and the plurality of third dummy channel structures 59D3, the lower ends of the plurality of first dummy isolation patterns 55D1 and the lower ends of the second dummy isolation pattern 55D2 can be further away from the upper surface of the substrate 21.

[0061] Reference Figure 14 The semiconductor device according to the embodiment may include a substrate 21, a first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, a fourth lower insulating layer 33, a first buried conductive pattern 34, a plurality of dummy conductive patterns 34D, a source molding layer 35, a second buried conductive pattern 37, a support member 38, a lower molding layer 39, a stacked structure 40, a molding layer 49, a select line isolation pattern 55, a plurality of first dummy isolation patterns 55D1, a second dummy isolation pattern 55D2, a plurality of cell channel structures 59, a plurality of third dummy channel structures 59D3, a first upper insulating layer 73, a plurality of word line isolation patterns 75, a plurality of bit line plugs 77, a plurality of bit lines 79, a second upper insulating layer 83, a third upper insulating layer 85, a through electrode 87, and an upper interconnect 89.

[0062] Each of the second dummy isolation pattern 55D2 and the plurality of first dummy isolation patterns 55D1 may have a width greater than the width of the selection line isolation pattern 55. Each of the plurality of first dummy isolation patterns 55D1 may have a fifth width W11. The second dummy isolation pattern 55D2 may have a sixth width W12. The selection line isolation pattern 55 may have a seventh width W13. The sixth width W12 may be substantially equal to the fifth width W11. Each of the fifth width W11 and the sixth width W12 may be larger than the seventh width W13. The lower ends of the plurality of first dummy isolation patterns 55D1 and the lower ends of the second dummy isolation pattern 55D2 may be at a lower level than the lower end of the selection line isolation pattern 55. The lower ends of the plurality of first dummy isolation patterns 55D1 and the lower ends of the second dummy isolation pattern 55D2 may be relatively closer to the upper surface of the substrate 21 than the lower end of the selection line isolation pattern 55.

[0063] Figure 15 and Figure 16 A layout diagram of a semiconductor device according to an embodiment is shown.

[0064] Reference Figure 15 and Figure 16The plurality of first dummy isolation patterns 55D1 and the plurality of second dummy isolation patterns 55D2 can have various sizes and shapes, and can be arranged at various intervals. For example, each of the plurality of first dummy isolation patterns 55D1 and the plurality of second dummy isolation patterns 55D2 can have a strip shape.

[0065] Figures 17 to 24 The following is illustrated along the stages in the method of forming a semiconductor device according to an embodiment. Figure 2 The sectional view taken by lines 1-1′ and 2-2′.

[0066] Reference Figure 17 A substrate 21 can be provided, which has a cell region CA, a connection region EX, a boundary region BR, and a peripheral region PR. A first lower insulating layer 23, a plurality of transistors 25, a second lower insulating layer 27, a plurality of peripheral circuit interconnects 29, a third lower insulating layer 31, and a fourth lower insulating layer 33 can be formed on the substrate 21.

[0067] Substrate 21 may include a semiconductor substrate such as a silicon wafer. Each of the first lower insulating layer 23, the second lower insulating layer 27, the third lower insulating layer 31, and the fourth lower insulating layer 33 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The first lower insulating layer 23 may correspond to a device isolation layer. The first lower insulating layer 23 may include an insulating layer formed using a shallow trench isolation (STI) method. The third lower insulating layer 31 may correspond to an etch stop layer. The third lower insulating layer 31 may include a material that has etch selectivity relative to the fourth lower insulating layer 33.

[0068] Multiple transistors 25 can be formed inside and / or on the substrate 21 using suitable methods. The multiple transistors 25 may include fin field-effect transistors (finFETs), multi-bridge channel (MBC) transistors, nanowire transistors, vertical transistors, recessed channel transistors, three-dimensional (3D) transistors, planar transistors, or combinations thereof.

[0069] The second lower insulating layer 27 can cover the first lower insulating layer 23 and the plurality of transistors 25. A third lower insulating layer 31 and a fourth lower insulating layer 33 can be sequentially formed on the second lower insulating layer 27. A plurality of peripheral circuit interconnects 29 can be formed in the second lower insulating layer 27, the third lower insulating layer 31, and the fourth lower insulating layer 33. The plurality of peripheral circuit interconnects 29 can be connected to the plurality of transistors 25. The plurality of peripheral circuit interconnects 29 can include horizontal interconnects and vertical interconnects of various shapes. The plurality of transistors 25 and the plurality of peripheral circuit interconnects 29 can constitute a peripheral circuit.

[0070] Reference Figure 18A first embedded conductive pattern 34, multiple dummy conductive patterns 34D, a source molding layer 35, a support member 38, and a lower molding layer 39 can be formed on the fourth lower insulating layer 33.

[0071] A first embedded conductive pattern 34 may be formed on the cell region CA. The first embedded conductive pattern 34 may extend on the connection region EX. The first embedded conductive pattern 34 may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. In an embodiment, the first embedded conductive pattern 34 may include polysilicon. A plurality of dummy conductive patterns 34D may be formed on the peripheral region PR. The plurality of dummy conductive patterns 34D may include the same material as the first embedded conductive pattern 34.

[0072] A source molding layer 35 can be formed on the first embedded conductive pattern 34 and a plurality of dummy conductive patterns 34D. In an embodiment, the source molding layer 35 may include a silicon nitride layer between a pair of silicon oxide layers. A support 38 may cover the source molding layer 35. A portion of the support 38 may extend through the source molding layer 35 and may contact the first embedded conductive pattern 34. The support 38 may include polysilicon.

[0073] A lower molding layer 39 can be formed between the first embedded conductive pattern 34 and a plurality of dummy conductive patterns 34D. The formation of the first embedded conductive pattern 34, the plurality of dummy conductive patterns 34D, the source molding layer 35, the support member 38, and the lower molding layer 39 may include multiple thin film formation processes, multiple patterning processes, and planarization processes. Planarization processes may include chemical mechanical polishing (CMP), etching back processes, or combinations thereof. The upper surface of the support member 38 and the upper surface of the lower molding layer 39 may be substantially coplanar and may be exposed.

[0074] Reference Figure 19 An initial stack structure 40T and a molding layer 49 can be formed on the support member 38 and the lower molding layer 39. The initial stack structure 40T may include a plurality of insulating layers 41 and a plurality of sacrificial layers 43 stacked alternately and repeatedly.

[0075] An initial stacked structure 40T can be formed on the cell region CA. The initial stacked structure 40T can extend onto the connection region EX. A molding layer 49 can be formed on the boundary region BR and the peripheral region PR. The molding layer 49 can extend onto the initial stacked structure 40T on the connection region EX. The plurality of sacrificial layers 43 can include materials that are etch-selective relative to the plurality of insulating layers 41. For example, the plurality of insulating layers 41 can include silicon oxide, and the plurality of sacrificial layers 43 can include silicon nitride. The molding layer 49 can include an insulating layer such as silicon oxide. For example, the molding layer 49 can include a silicon oxide layer formed using tetraethyl orthosilicate (TEOS).

[0076] Reference Figure 20 A mask pattern 52 can be formed on the initial stack structure 40T and the molding layer 49. The mask pattern 52 can be used as an etching mask to form select line isolation trenches 54 and multiple dummy select line isolation trenches 54D. The select line isolation trenches 54 can partially penetrate the initial stack structure 40T. The multiple dummy select line isolation trenches 54D can partially penetrate the molding layer 49.

[0077] Reference Figure 21 A selective line isolation pattern 55 can be formed within a selective line isolation trench 54, and a plurality of first dummy isolation patterns 55D1 can be formed within a plurality of dummy selective line isolation trenches 54D. The selective line isolation pattern 55 and the plurality of first dummy isolation patterns 55D1 may comprise the same material and may be formed simultaneously. For example, the selective line isolation pattern 55 and the plurality of first dummy isolation patterns 55D1 may comprise an insulating layer comprising silicon oxide. The selective line isolation pattern 55 may penetrate at least one of the plurality of sacrificial layers 43 adjacent to the upper surface of the initial stacked structure 40T.

[0078] Reference Figure 22 A patterning process can be used to form multiple unit channel holes 57 and multiple dummy channel holes 57D1, 57D2, and 57D3. The multiple dummy channel holes 57D1, 57D2, and 57D3 may include multiple first dummy channel holes 57D1, second dummy channel holes 57D2, and multiple third dummy channel holes 57D3. In an embodiment, before forming the multiple unit channel holes 57 and the multiple dummy channel holes 57D1, 57D2, and 57D3, another mask pattern may be formed on the mask pattern 52, the selection line isolation pattern 55, and the multiple first dummy isolation patterns 55D1; for the sake of brevity, its repeated description can be omitted.

[0079] Each of the plurality of cell vias 57 can pass through the initial stack structure 40T, support 38, and source molding layer 35 in cell region CA, and extend into the first embedded conductive pattern 34. Each of the plurality of first dummy vias 57D1 can pass through the molding layer 49, support 38, and source molding layer 35 on peripheral region PR, and extend into the plurality of dummy conductive patterns 34D. The second dummy via 57D2 can pass through the molding layer 49 on boundary region BR, and extend into the lower molding layer 39. Some of the plurality of third dummy vias 57D3 can pass through the molding layer 49, initial stack structure 40T, support 38, and source molding layer 35 on connection region EX, and extend into the first embedded conductive pattern 34.

[0080] Reference Figure 23Multiple unit channel structures 59 can be formed inside multiple unit channel holes 57, multiple first dummy channel structures 59D1 can be formed inside multiple first dummy channel holes 57D1, multiple second dummy channel structures 59D2 can be formed inside multiple second dummy channel holes 57D2, and multiple third dummy channel structures 59D3 can be formed inside multiple third dummy channel holes 57D3. The multiple unit channel structures 59, multiple first dummy channel structures 59D1, multiple second dummy channel structures 59D2, and multiple third dummy channel structures 59D3 can all be made of the same material and can be formed simultaneously.

[0081] The mask pattern 52 can be removed to expose the upper surfaces of the initial stacked structure 40T, the molding layer 49, the selected line isolation pattern 55, multiple first dummy isolation patterns 55D1, multiple unit channel structures 59, multiple first dummy channel structures 59D1, second dummy channel structures 59D2, and multiple third dummy channel structures 59D3. The upper surfaces of the initial stacked structure 40T, the molding layer 49, the selected line isolation pattern 55, the multiple first dummy isolation patterns 55D1, the multiple unit channel structures 59, the multiple first dummy channel structures 59D1, second dummy channel structures 59D2, and multiple third dummy channel structures 59D3 can be substantially coplanar.

[0082] The process of forming the molding layer 49, the selective line isolation pattern 55, and the multiple unit channel structures 59 may include multiple annealing processes. Multiple first dummy isolation patterns 55D1, multiple first dummy channel structures 59D1, second dummy channel structures 59D2, and multiple third dummy channel structures 59D3 can serve as pathways for discharging gases generated around and within the molding layer 49.

[0083] Reference Figure 24 The source molding layer 35 can be partially removed, and a second embedded conductive pattern 37 can be formed. The second embedded conductive pattern 37 can be referred to as a replacement conductor. The second embedded conductive pattern 37 can be formed on the cell region CA. The second embedded conductive pattern 37 can extend onto the connection region EX. The source molding layer 35 can remain between multiple dummy conductive patterns 34D on the peripheral region PR and the support member 38. The second embedded conductive pattern 37 can include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or combinations thereof.

[0084] Multiple sacrificial layers 43 can be removed, and multiple interconnect layers 45 can be formed. The multiple interconnect layers 45 may include metals, metal nitrides, metal oxides, metal silicides, polysilicon, conductive carbon, or combinations thereof. In embodiments, the multiple interconnect layers 45 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or combinations thereof. Multiple insulating layers 41 and multiple interconnect layers 45 stacked alternately and repeatedly can constitute a stacked structure 40.

[0085] Multiple word line isolation patterns 75 can be formed, which can pass through the stacked structure 40, the support member 38, and the second embedded conductive pattern 37 and extend into the first embedded conductive pattern 34. A first upper insulating layer 73 can be formed on the multiple word line isolation patterns 75, the stacked structure 40, the select line isolation pattern 55, the multiple unit channel structures 59, the molding layer 49, the multiple first dummy isolation patterns 55D1, the multiple first dummy channel structures 59D1, the second dummy channel structures 59D2, and the multiple third dummy channel structures 59D3. Each of the multiple word line isolation patterns 75 and the first upper insulating layer 73 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0086] Refer again Figure 1 Multiple bit line plugs 77 can be formed, which can pass through the first upper insulating layer 73 and contact multiple unit channel structures 59. A second upper insulating layer 83 and multiple bit lines 79 can be formed on the first upper insulating layer 73. The multiple bit lines 79 can contact the multiple bit line plugs 77. A third upper insulating layer 85 can be formed on the second upper insulating layer 83. A through electrode 87 can be formed, which passes through the third upper insulating layer 85, the second upper insulating layer 83, the first upper insulating layer 73, the molding layer 49, the lower molding layer 39, the fourth lower insulating layer 33, and the third lower insulating layer 31, and contacts a selected one of multiple peripheral circuit interconnects 29. An upper interconnect 89 can be formed on the third upper insulating layer 85. The upper interconnect 89 can contact the through electrode 87.

[0087] Each of the plurality of bit plugs 77, the plurality of bit lines 79, the through electrode 87, and the upper interconnect 89 may include a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the second upper insulating layer 83 and the third upper insulating layer 85 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0088] Through summarization and review, it was found that film formation and annealing processes can cause various types of venting. These venting issues can lead to product defects such as bursting defects.

[0089] According to embodiments, multiple dummy isolation patterns and / or multiple dummy channel structures can be provided extending into the molding layer. The multiple dummy isolation patterns or multiple dummy channel structures can serve as pathways for discharging gases generated inside and around the molding layer. This allows for the realization of semiconductor devices that improve mass production efficiency and possess excellent electrical performance.

[0090] One or more embodiments may provide a semiconductor device that is advantageous for improving mass production efficiency and has excellent electrical performance, and a method for forming the semiconductor device.

[0091] One or more embodiments may provide a semiconductor device having a structure that helps control venting during its manufacture, thereby reducing the likelihood of defects that might otherwise occur due to uncontrolled venting.

[0092] Example embodiments have been disclosed herein. Although specific terminology has been used, it is used and will be interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art from the date of filing of this application that, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The base has a unit region, a peripheral region, and a boundary region between the unit region and the peripheral region; A stacked structure, located on a cell region of a substrate, comprises multiple insulating layers and multiple interconnect layers stacked alternately; The molding layer is located on the outer and boundary areas of the substrate; Select a line isolation pattern and extend it into the stacked structure; Unit channel structure, passing through stacked structure; as well as Multiple first dummy patterns extend into the molding layer on the outer area. The plurality of first dummy patterns includes: a first dummy channel structure, which extends substantially parallel to the unit channel structure towards the substrate from the upper surface of the plurality of first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the unit channel structure. Wherein: the upper surfaces of the plurality of first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the unit channel structure are substantially coplanar. The stacked structure includes: a lower stacked structure comprising a plurality of alternately stacked lower insulating layers and a plurality of lower interconnect layers; and an upper stacked structure located on the lower stacked structure and comprising a plurality of alternately stacked upper insulating layers and a plurality of upper interconnect layers. The lower end of the first dummy channel structure is located at a horizontal position adjacent to the interface between the lower stacked structure and the upper stacked structure.

2. The semiconductor device according to claim 1, wherein: Each of the unit trench structure and the first dummy trench structure includes: a trench layer; a tunnel insulation layer located outside the trench layer; a charge storage layer located outside the tunnel insulation layer; and a barrier layer located outside the charge storage layer.

3. The semiconductor device according to claim 2, the semiconductor device further comprising a through electrode that passes through a molding layer on the peripheral region and is located between the first dummy channel structure and the cell region.

4. The semiconductor device according to claim 1, wherein: The plurality of first dummy patterns also include a first dummy isolation pattern, and The first dummy isolation pattern extends substantially parallel to the selection line isolation pattern toward the substrate from the upper surface of the plurality of first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the unit channel structure.

5. The semiconductor device of claim 1, further comprising a plurality of second dummy patterns in a molding layer extending onto the boundary region. in: The upper surfaces of the plurality of first dummy patterns, the plurality of second dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the unit channel structure are substantially coplanar with the upper surface of the molding layer. At least one of the plurality of second dummy patterns includes a second dummy isolation pattern or a second dummy channel structure. The second dummy isolation pattern extends from the upper surface of the molding layer toward the substrate, substantially parallel to the selection line isolation pattern, and The second dummy channel structure extends from the upper surface of the molding layer toward the substrate, essentially parallel to the unit channel structure.

6. A semiconductor device, the semiconductor device comprising: The base has a unit region, a peripheral region, and a boundary region between the unit region and the peripheral region; A stacked structure, located on a cell region of a substrate, comprising multiple insulating layers and multiple interconnect layers stacked alternately; The molding layer is located on the outer and boundary areas of the substrate; Unit channel structure, passing through stacked structure; as well as The first dummy channel structure extends into the molded layer on the outer perimeter. Wherein: the upper surface of the first dummy channel structure and the upper surface of the unit channel structure are substantially coplanar, and the first dummy channel structure extends from the upper surface of the first dummy channel structure and the upper surface of the unit channel structure toward the substrate substantially parallel to the unit channel structure. The stacked structure includes: a lower stacked structure comprising a plurality of alternately stacked lower insulating layers and a plurality of lower interconnect layers; and an upper stacked structure located on the lower stacked structure and comprising a plurality of alternately stacked upper insulating layers and a plurality of upper interconnect layers. The lower end of the first dummy channel structure is located at a horizontal position adjacent to the interface between the lower stacked structure and the upper stacked structure.

7. The semiconductor device according to claim 6, wherein, Compared to the lower end of the unit channel structure being further from the upper surface of the substrate, the lower end of the first dummy channel structure is further away from the upper surface of the substrate.

8. The semiconductor device according to claim 6, wherein, The first dummy channel structure has a width smaller than that of the unit channel structure.

9. The semiconductor device according to claim 6, wherein, Compared to the interface between the lower and upper stacked structures being further from the upper surface of the substrate, the lower end of the first dummy channel structure is closer to the upper surface of the substrate.

10. The semiconductor device according to claim 6, wherein, Each of the first dummy channel structure and the unit channel structure includes: Channel layer; The tunnel insulation layer is located on the outside of the trench layer; The charge storage layer is located outside the tunnel insulation layer; and The barrier layer is located outside the charge storage layer.

11. The semiconductor device of claim 6, further comprising a second dummy channel structure in a molding layer extending over a boundary region.

12. The semiconductor device according to claim 11, wherein, The upper surfaces of the second dummy channel structure, the first dummy channel structure, and the unit channel structure are essentially coplanar.

13. The semiconductor device according to claim 11, wherein, The second dummy channel structure extends substantially parallel to the unit channel structure toward the substrate from the upper surface of the first dummy channel structure and the upper surface of the unit channel structure.

14. The semiconductor device of claim 6, further comprising a through electrode that passes through a molding layer on a peripheral region and is located between the first dummy channel structure and the cell region.

15. The semiconductor device according to claim 6, wherein: The substrate also includes a connection region between the unit region and the boundary region, and the connection region and the unit region are continuous. The stacked structure extends to the connection area. The molded layer extends over the stacked structure in the connection area, and The semiconductor device also includes a third dummy channel structure that passes through the molding layer and stacked structure on the interconnect region.

16. A semiconductor device, the semiconductor device comprising: The base has a unit region and a peripheral region; A stacked structure, located on a cell region of a substrate, comprising multiple insulating layers and multiple interconnect layers stacked alternately; The molding layer is located on the outer perimeter of the substrate; Select a line isolation pattern and extend it into the stacked structure; Unit channel structure, passing through stacked structure; as well as A virtual isolation pattern extends into the molding layer. Wherein: the upper surface of the dummy isolation pattern and the upper surface of the selection line isolation pattern are substantially coplanar, and the dummy isolation pattern extends from the upper surface of both the dummy isolation pattern and the upper surface of the selection line isolation pattern toward the substrate substantially parallel to the selection line isolation pattern. The semiconductor device further includes: a first dummy channel structure extending into a molding layer on the peripheral region. Wherein: the upper surface of the first dummy channel structure and the upper surface of the unit channel structure are substantially coplanar, and the first dummy channel structure extends from the upper surface of the first dummy channel structure and the upper surface of the unit channel structure toward the substrate substantially parallel to the unit channel structure. The stacked structure includes: a lower stacked structure comprising a plurality of alternately stacked lower insulating layers and a plurality of lower interconnect layers; and an upper stacked structure located on the lower stacked structure and comprising a plurality of alternately stacked upper insulating layers and a plurality of upper interconnect layers. The lower end of the first dummy channel structure is located at a horizontal position adjacent to the interface between the lower stacked structure and the upper stacked structure.

17. The semiconductor device according to claim 16, wherein, Compared to the selected line isolation pattern which is located away from the upper surface of the substrate, the lower end of the dummy isolation pattern is closer to the upper surface of the substrate.

18. The semiconductor device according to claim 16, wherein, The dummy isolation pattern has a width greater than that of the selected line isolation pattern.

19. The semiconductor device according to claim 16, wherein, Compared to the lower end of the unit channel structure being further from the upper surface of the substrate, the lower end of the dummy isolation pattern is further away from the upper surface of the substrate.

20. The semiconductor device of claim 16, wherein, The dummy isolation pattern includes the same material as the selected line isolation pattern.

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