Electrode formation

Abstract

The present invention describes apparatus, methods and systems related to electrode formation. A first portion of a top electrode is formed above a dielectric material of a storage node. A metal oxide is formed above the first portion of the electrode. A second portion of the electrode is formed above the metal oxide.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and methods, and more particularly focuses on enhancing the electrical barrier capabilities of existing electrode materials and the electrical barriers they form. Background Art

[0002] For computing, artificial intelligence or other electronic device applications, memory devices are generally provided as one of the main internal parts of advanced integrated semiconductor logic circuits. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM) and flash memory, etc. Some types of memory devices may be non-volatile memory (e.g., ReRAM) and can be used for a wide range of electronic applications requiring high memory density, high reliability and low power consumption. Volatile memory cells (e.g., DRAM cells) require power to maintain their stored data state (e.g., through a refresh process), which is different from non-volatile memory cells (e.g., flash memory cells) that maintain their storage state without power. However, various volatile memory cells (e.g., DRAM cells) can operate (e.g., program, read, erase, etc.) faster than various non-volatile memory cells (e.g., flash memory cells). Summary of the invention

[0003] In one aspect, the present application provides an apparatus comprising: a first portion of an electrode formed over a dielectric material of a storage node; a metal oxide formed over the first portion of the electrode; and a second portion of the electrode formed over the metal oxide.

[0004] In another aspect, the present application further provides a method comprising: depositing a first portion of an electrode over a dielectric material to a storage node of a memory cell; depositing a metal oxide over the first portion of the electrode; and depositing a second portion of the electrode over the metal oxide.

[0005] In yet another aspect, the present application further provides a system comprising: a storage node of a memory cell, the storage node comprising: a dielectric material; a first portion of an electrode formed on the dielectric material; a metal oxide formed on the first portion of the electrode; and a second portion of the electrode formed on the metal oxide. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 3Example cross-sectional views illustrating electrodes formed on a dielectric material according to several embodiments of the present invention.

[0007] Figures 4A to 4B Example top view illustrating a storage node according to several embodiments of the invention.

[0008] Figure 5 Example cross-sectional side views illustrating storage nodes according to several embodiments of the invention.

[0009] Figure 6 Cross-sectional views illustrating access devices that may be coupled to storage nodes having electrodes according to several embodiments of the present invention.

[0010] Figure 7 A flow chart illustrating an example method for forming electrodes in a capacitor cell according to several embodiments of the invention.

[0011] Figure 8 is a functional block diagram of a system for implementing an example semiconductor manufacturing process according to several embodiments of the present invention.

[0012] Fig. 9 is a functional block diagram of a computing system including at least one memory array having electrodes formed according to several embodiments of the present invention. DETAILED DESCRIPTION

[0013] Various types of memory devices, including arrays of volatile and / or nonvolatile memory cells (e.g., memory arrays), may include thin conductive electrodes, such as top electrodes to capacitor structures. The dimensions of memory cells continue to shrink in order to provide higher memory density per die area; thus, for example, top electrode thickness is typically about twenty angstroms. As high density devices shrink design rules, it becomes increasingly relevant to protect underlying materials during subsequent semiconductor processing steps. For example, protecting high-k dielectric materials beneath or adjacent to a top conductive electrode from damage during subsequent processing steps is relevant to overall prevention of dielectric damage that ultimately becomes cell leakage control and protecting cell capacitance. That is, as the physical size of memory devices decreases, dielectric leakage control becomes increasingly difficult. To reduce dielectric leakage, some embodiments of the present invention include depositing a metal oxide material within an electrode.

[0014] In some embodiments, the metal oxide material may be aluminum oxide (AlOx). Although examples in the present disclosure discuss depositing AlOx as a metal oxide barrier in the formation of an electrode on a dielectric material, embodiments are not so limited and may include silicon oxide (SiOx), yttrium oxide (YOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), germanium oxide (GaOx), strontium oxide (SrO), magnesium oxide (MgOx), etc. In the example of AlOx, AlOx may be deposited in different locations within the top electrode. In the example of AlOx, the deposition of AlOx may protect the underlying dielectric and, in some instances, may increase the conduction band offset (CBO) between the dielectric material and the top electrode.

[0015] The manufacture of semiconductor structures (e.g., storage nodes of memory devices) may involve processing semiconductor wafers, after which specific semiconductor structures are formed in a vacuum environment (i.e., "in situ") and outside of a vacuum environment ("ex situ"), depending on the capabilities of a particular semiconductor manufacturing sequence and the availability of current process equipment capabilities. This may include using multiple semiconductor chambers to perform various semiconductor manufacturing sequences. Semiconductor wafers and semiconductor structures formed thereon may be transported between different semiconductor manufacturing equipment during a semiconductor manufacturing sequence.

[0016] A memory device may include a thin layer of metallic material that serves as a component of a storage node (e.g., an electrode to a capacitor structure). For example, in a particular architecture, a capacitor cell of a DRAM device may include a 20 angstrom thick layer of metallic material. The electrode (e.g., top or bottom electrode) may be a thicker or smaller conductive material. The electrode may include a metallic material or a metal-containing compound (e.g., titanium nitride (TiN)) and may be deposited onto a dielectric material to form one of two electrodes separated by a dielectric material to form a capacitor cell. Damage to the underlying dielectric may occur in subsequent processing steps in the semiconductor manufacturing process as design rules shrink, thus resulting in a higher probability of charge leaking out of the capacitor cell. Cell current leakage may result in erroneous reading of a signal (e.g., charge) stored to a storage node (e.g., a capacitor cell) and / or cause a short circuit.

[0017] Various embodiments of the present invention include forming an electrode of a storage node on a dielectric material in a semiconductor manufacturing sequence. The electrode is formed to include a metal oxide material that is claimed to protect the dielectric material when the electrode is formed in a subsequent semiconductor manufacturing step and is primarily designed to prevent the cell storage charge from leaking from the storage node in use. In one example embodiment, a first portion of an electrode (e.g., a top electrode) is deposited on the dielectric material. The metal oxide material is then deposited on the first portion of the electrode. A second portion of the conductive electrode is deposited on the metal oxide material. In one example, by way of illustration only and not by way of limitation, a first portion of titanium nitride (TiN) may be deposited on the dielectric material as an electrode material. An aluminum oxide (AlOx) material may be deposited on the first portion of the TiN electrode material and a second portion of the TiN may be deposited on the AlOx material to complete the entire electrode composition (e.g., a top electrode) on the dielectric material.

[0018] It should be noted that although the present discussion (e.g., illustration) relates to forming an electrode of a storage node of a capacitor cell as a process of a storage node of a dynamic random access memory (DRAM) cell, the embodiments are not limited to this example structure, circuit, or device formation in a semiconductor manufacturing sequence. The embodiments may include forming electrodes on other semiconductor components that benefit from increased leakage control and high work function, such as access lines (e.g., word lines), sense lines (e.g., digit lines, bit lines, etc.) formed according to the techniques described herein, or other conductive surfaces and devices resulting therefrom.

[0019] Additionally or alternatively, shrinking design rules may result in semiconductor components being formed closer together. And as design rules shrink, damage to previously formed structures and materials in subsequent processing steps may become more likely. For example, adjacent dielectric materials damaged in subsequent processing steps may lead to signal (e.g., charge) leakage issues. The integrity of protective materials and components, along with the proximity of semiconductor components, and the reduction in the size of the dielectric to comply with shrinking design rules may increase instances of charge leakage through dielectric materials. This leakage may cause a weaker signal (e.g., charge) to be maintained or detectable on a storage node and may result in negative effects, such as inaccurate readings, short circuits, etc. Depositing a metal oxide material into an electrode as described herein may reduce this damage and may reduce or even eliminate some of the leakage caused by shrinking design rules. In some embodiments, the metal oxide material may increase the CBO between the dielectric material and the first portion of the electrode. Thus, more energy may be required to transport charge from the electrode to the dielectric, thereby increasing the energy barrier resulting in an increase in the amount of energy required to cause the charge to travel through the dielectric. This may reduce the amount of leakage through the dielectric material without significantly affecting the conductivity of the electrode.

[0020] The present invention includes methods, apparatus, and systems related to forming a top electrode to reduce damage and / or leakage through an underlying dielectric material. Examples of methods described herein include forming a first portion of a top electrode of a storage node on a dielectric material, forming a metal oxide material on the first portion of the top electrode, and forming a second portion of the top electrode on the metal oxide material. Apparatus embodiments may include a first portion of an electrode deposited above the dielectric material. The metal oxide material may be deposited above the first portion of the electrode and the second portion of the electrode may be deposited above the metal oxide material.

[0021] In the following detailed description of the present invention, reference is made to the accompanying drawings forming a part thereof, and one or more embodiments of the present invention are shown by way of illustration. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present invention, and it is understood that other embodiments may be utilized and process, electronic and / or structural changes may be made without departing from the scope of the present invention. As used herein, "several" something may refer to one or more such things. For example, several capacitors may refer to at least one capacitor.

[0022] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the figure and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, element number 104 may refer to Figure 1 Component "04" in, and similar components can be found in Figure 2 204. Multiple similar components within a figure may be referenced by a reference symbol followed by a hyphen and another number or letter. For example, 102-1 may be referenced by Figure 1 102-2 may refer to element 02-2, which may be similar to element 102-1. Such similar elements may be generally referred to without hyphens and additional numbers or letters. For example, elements 102-1 and 102-2 or other similar elements may be generally referred to as 102.

[0023] Figures 1 to 3 Example cross-sectional views illustrating an electrode of a storage node formed on a dielectric material according to several embodiments of the present invention. In an example, the electrode can be a top electrode of a capacitor cell formed on a dielectric material. Figure 1 An apparatus 100 is illustrated that includes a first portion 102 - 1 of a top electrode and a second portion 102 - 2 of a top electrode (individually or collectively referred to as top electrode 102 ), a metal oxide material 104 , and a dielectric material 106 .

[0024] The top electrode 102 may be formed of various materials. The electrode may be an electrical conductor. The top electrode may be used to conduct electricity to the semiconductor device. In one embodiment, the top electrode may be formed of titanium nitride (TiN). In other embodiments, the top electrode may be aluminum nitride (AlN), tungsten nitride (WN), molybdenum nitride (MN), ruthenium nitride (RuN), etc. and / or combinations or compounds thereof. Therefore, non-limiting examples of the top electrode 102 may include platinum (Pt), ruthenium (Ru), titanium nitride (TiN), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), aluminum (Al), rhodium (Rh), tungsten nitride (WN) and ruthenium oxide (RuO).

[0025] The electrode 102 may be formed in contact with the dielectric material 106. Non-limiting examples of dielectric materials may include nitrides, oxides, and / or combinations or compounds thereof.

[0026] According to some embodiments, the metal oxide material 104 may be deposited on a portion of the electrode 102. Metal oxides are chemical compounds formed by a combination of metals and oxygen. Non-limiting examples of metal oxides may include yttrium oxide (YOx), silicon oxide (SiOx), germanium oxide (GeOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), strontium oxide (SrOx), magnesium oxide (MgOx), and calcium oxide (CaO). In some embodiments, the metal oxide 104 may be formed of AlOx. AlOx may be deposited ex situ. According to some embodiments, the metal oxide 104 may be deposited on a first portion of the electrode 102.

[0027] In some embodiments, the electrode 102, dielectric 106, and metal oxide 104 may be deposited using chemical vapor deposition (CVD). CVD is a vacuum deposition method in which a wafer is exposed to one or more volatile precursors that react and / or decompose on the wafer surface to produce the desired deposition. In some embodiments, the electrode 102, dielectric 106, and metal oxide 104 may be deposited using atomic layer deposition (ALD). ALD is a subclass of CVD. During ALD, a material is repeatedly exposed to separate precursors that react with the material surface one at a time in sequence. Through these exposures, a thin film is slowly deposited.

[0028] In some embodiments, the first portion 102-1 of the electrode can be deposited in situ. The first portion 102-1 of the electrode can be removed from the vacuum chamber, and the metal oxide 104 can be deposited on the first portion 102-1 of the electrode ex situ. Once the metal oxide 104 has been deposited, the first portion 102-1 of the electrode and the metal oxide 104 can be placed in a vacuum chamber to deposit the second portion 102-2 of the electrode in situ. In some embodiments, the electrode 102 can be deposited ex situ. In some embodiments, the metal oxide 104 can be deposited in situ.

[0029] Depositing metal oxide 104 with electrode 102 can protect dielectric material 106 from damage during subsequent processing steps and can reduce voltage leakage of storage nodes. In some embodiments, voltage leakage can be reduced for various reasons, including increasing work function, increasing electron barrier and increasing band gap at the interface of electrode 102.

[0030] For example, charge leakage can be reduced by increasing the work function of the electrode 102. The work function of a material is the minimum amount of energy required to eject an electron from the surface of the material. Increasing the work function can alleviate leakage problems because increasing the work function reduces the probability of charge moving through the dielectric 106.

[0031] Charge leakage can be reduced by increasing the bandgap offset of different materials. The bandgap offset is the difference between the energy bands of different semiconductor materials at a semiconductor heterojunction (e.g., an interface). The bandgap is the energy range in which electronic states may not exist. Increasing the bandgap can increase the amount of energy required for electrons to move to different energy bands. Therefore, increasing the bandgap offset can increase the amount of energy required to make electrons flow through the material. This can increase the amount of energy required to make charge flow through the material. Increasing the amount of energy required to make electricity flow through the material can reduce leakage because it may cost a higher level of energy to make the charge leak through the material.

[0032] Depositing the metal oxide 104 into the electrode 102 can increase the conduction band offset between the first portion 102-1 of the electrode and the dielectric 106. The metal oxide 104 can reduce the electron density in the region of the electrode 102 surrounding the metal oxide 104. Depositing the metal oxide 104 into the electrode 102 can form a positively charged region between the electrode 102 and the dielectric 106. Electrons can move away from this region, leaving a trap between the metal oxide 104 and the dielectric 106. This can result in an increased band gap offset between the first portion 102-1 of the electrode and the dielectric 106.

[0033] The metal oxide 104 may be deposited into different regions of the electrode 102. The metal oxide 104 may be deposited as a layer. In some embodiments, the metal oxide may be deposited as a discontinuous layer. As used herein, a discontinuous layer may be a layer of the metal oxide 104 that may have a gap therein. The gap may allow the first and second portions of the electrode 102 to contact each other. In some embodiments, the metal oxide 104 may be deposited into regions of the electrode 102 such that the second portion 102-2 of the electrode is thicker than the first portion 102-1 of the electrode. In some embodiments, leakage protection may increase when the distance between the metal oxide 104 and the dielectric 106 decreases.

[0034] The dielectric 106 may be deposited before the electrode 102. The dielectric 106 may act as an insulator that hinders accidental conduction between elements of the storage node. In some embodiments, the dielectric 106 may have a high dielectric constant (k). Forming the dielectric 106 with a high k may increase the capacitance of the capacitor in the storage node. As stated above, depositing the metal oxide 104 into the electrode 102 may increase the bandgap offset between the electrode 102 and the dielectric 106. Increasing the bandgap offset may increase the amount of energy used to transport electrons across an electrical boundary (e.g., to move electrons across a material interface). Therefore, increasing the bandgap offset between the electrode 102 and the dielectric 106 may reduce the amount of leakage in the storage node.

[0035] exist Figure 1 In the example of FIG. 1 , the thickness (t1) of the first portion 102-1 of the electrode between the metal oxide material 104 and the dielectric 106 is less than the thickness (t2) of the second portion 102-2 of the electrode. Thus, the metal oxide material 104 is formed in the lower portion of the electrode 102, closer to the interface with the dielectric 106 than the upper surface of the electrode 102.

[0036] Figure 2 2 illustrates an example cross-sectional view of a top electrode of a capacitor cell formed on a dielectric material according to several embodiments of the present invention. Apparatus 200 and its components may be similar to Figure 1 The device 100 and its components are described in FIG. Figure 2 A first portion 202 - 1 of an electrode and a second portion 202 - 2 of an electrode (individually or collectively referred to as electrodes 202 ), a metal oxide 204 , and a dielectric material 206 are illustrated.

[0037] As in Figure 2 As shown in FIG. 1 , electrode 202 may be deposited over dielectric 206. Dielectric 206 may be a high-k dielectric. Metal oxide 204 may be deposited into electrode 202. Figure 2 In the example of , the first portion 202-1 of the electrode is deposited over the dielectric 206. The metal oxide 204 is deposited over the first portion 202-1 of the electrode and the second portion 202-2 of the electrode is deposited over the metal oxide 204. Figure 2 2, the metal oxide 204 may be deposited such that the first portion 202-1 of the electrode has a greater thickness than the second portion 202-2 of the electrode. Thus, the metal oxide material 204 is formed in the upper portion of the electrode 202, closer to the upper surface of the electrode than the interface to the dielectric 206. In some embodiments, the metal oxide 204 may also be deposited such that the thickness of the metal oxide 204 may be ten percent (10%) to fifteen percent (15%) of the thickness of the electrode 202.

[0038] Figure 31 illustrates an example cross-sectional view of a top electrode of a capacitor cell formed on a dielectric material according to several embodiments of the present invention. Apparatus 300 and its components may be similar to Figure 1 The device 100 and its components are described in FIG. Figure 3 Portions of electrodes 302 - 1 , 302 - 2 , . . . , 302 -N (individually or collectively referred to as electrodes 302 ), metal oxides 304 - 1 , . . . , 304 -N (individually or collectively referred to as metal oxides 304 ), and dielectric material 306 are illustrated.

[0039] As in Figure 3 , the metal oxide 304 can be deposited in a plurality of different locations on the electrode 302. In some embodiments, the metal oxide 304-1 can be deposited over a first portion 302-1 of the electrode. The metal oxide 304-1 can be deposited as a material layer. In some embodiments, the metal oxide 304-1 can be deposited as a discontinuous material layer. A second portion 302-2 of the electrode can be deposited over the metal oxide 304-1. The metal oxide 304-N can be deposited over the second portion 302-2 of the electrode. In some embodiments, the metal oxide 304-N can be deposited as a discontinuous layer. A third portion 302-N of the electrode can be deposited over the metal oxide 304-N. The metal oxide 304 can be deposited over a plurality of different locations on the electrode 302. In some embodiments, the metal oxide 304-1 can be deposited over a first portion 302-1 of the electrode. The metal oxide 304-1 can be deposited as a discontinuous material layer. Figure 3 More different locations of deposition into electrode 302 are shown in FIG.

[0040] Figures 4A to 4B Example top view illustrating a storage node according to several embodiments of the invention. Figures 4A to 4B The storage nodes 408, 409 are illustrated as capacitors 408, 409. However, the embodiments of the present invention are not limited to capacitors as storage nodes.

[0041] Figure 4A A single-sided capacitor 408 is illustrated in which a bottom electrode 418 may be formed in contact with a fill material 419. Non-limiting examples of fill material 419 include polysilicon nitride, titanium nitride, tungsten, and doped versions thereof. A dielectric material 406 may be formed in contact with the bottom electrode 418. The dielectric material 406 may be a high-k dielectric material. A first portion 402-1 of a top electrode may be formed in contact with the dielectric material 406. A metal oxide material 404 may be formed on the first portion 402-1 of the top electrode. A second portion 402-2 of the top electrode may be formed on the metal oxide material 404.

[0042] Figure 4BA single-sided capacitor 409 is illustrated in which a first portion 418-1 of a bottom electrode may be formed in contact with a fill material 419. A metal oxide material 404 may be formed on top of the first portion 418-1 of the bottom electrode. A second portion 418-2 of the bottom electrode may be formed on the metal oxide material 404. A dielectric material 406 may be formed on the second portion 418-2 of the bottom electrode. A top electrode 402 may be formed on the dielectric material 406.

[0043] Figure 5 Example cross-sectional side views illustrating storage nodes according to several embodiments of the invention. Figure 5 Storage node 508, first portion 502-1 of the top electrode, second portion 502-2 of the top electrode (individually or collectively referred to as top electrode 502), dielectric material 506, bottom electrode 518, fill material 519, and substrate material 501 are illustrated as capacitor 508. However, embodiments of the present invention are not limited to capacitors as storage nodes.

[0044] Figure 5 A single-sided capacitor 508 is illustrated in which a bottom electrode 518 may be formed in contact with a fill material 519. A dielectric material 506 may be formed in contact with the bottom electrode 518. In some embodiments, the dielectric material 506 may be a ZrOx material. A first portion 502-1 of the top electrode may be formed in contact with the dielectric material 506. A metal oxide 504 may be formed over the first portion 502-1 of the electrode. A second portion 502-2 of the electrode may be formed over the metal oxide 504. Non-limiting examples of the top electrode 502 may include platinum (Pt), ruthenium (Ru), titanium nitride (TiN), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), aluminum (Al), rhodium (Rh), tungsten nitride (WN), molybdenum nitride (MoN), and ruthenium oxide (RuO).

[0045] Bottom electrode 518 may be formed in contact with substrate material 510. Fill material 519 may be formed within the cavity formed by bottom electrode 518. Dielectric material 506 may be formed in contact with bottom electrode 518 and fill material 519. Top electrode 502 may be formed in contact with dielectric material 506.

[0046] Figure 6 A cross-sectional view of a memory cell including an access device coupled to a storage node according to several embodiments of the present invention is illustrated. According to some embodiments, the memory cell structure includes an electrode formed according to the techniques described herein. For example, the storage node may include a capacitor having an electrode formed according to the techniques described herein.

[0047] Figure 6An apparatus 620 is illustrated having gates 621-1, ..., 621-N (individually or collectively referred to as gate 621). Gate 621 may also be referred to as a gate electrode. Gate 621 may be a gate to a recessed access device, such as a buried recessed access device (BRAD). In the example shown, gate 621 may include: a first portion 626 including a metal, such as titanium nitride (TiN); and a second portion 636 including doped polysilicon to form a hybrid metal gate (HMG) 621. Gate 621 may be separated from channel 635, thereby separating first source / drain regions 616-1 and 616-2 (collectively referred to as first source / drain regions 616) from second source / drain regions 612-1 and 612-2 (collectively referred to as second source / drain regions 612) by a gate dielectric 637. In the example shown, gate 621 may include: a first portion 626 including a metal, such as titanium nitride (TiN); and a second portion 636 including doped polysilicon to form a hybrid metal gate (HMG) 621. Gate 621 may be separated from channel 635, thereby separating first source / drain regions 616-1 and 616-2 (collectively referred to as first source / drain regions 616) from second source / drain regions 612-1 and 612-2 (collectively referred to as second source / drain regions 612). Figure 6 In the example of FIG. 6 , two adjacent access devices 621 and 623 are shown sharing a second source / drain region 612 at the junction. The adjacent access devices 621 and 623 are built into a substrate material 624 .

[0048] exist Figure 6 In an example of , a storage node 631 having an electrode formed according to the techniques described herein can be coupled to the second source / drain region 612. An insulating material 640 (e.g., a dielectric material) can be formed on the spacer material 626 and the gate mask material 638, and contact the metal material 630. In at least one embodiment, the metal material 630 can be formed in contact with the spacer material 626, the source / drain regions 612 and 616, and the junction. The insulating material 640 can be formed on the spacer material 626 and the gate mask material 638, and contact the metal material 630.

[0049] Figure 7 Flowchart illustrating an example method 750 for forming an electrode in a capacitor cell according to several embodiments of the present invention. Unless explicitly stated, the elements of the methods described herein are not limited to a specific order or sequence. In addition, several method embodiments or elements thereof described herein may be performed at the same or substantially the same time point.

[0050] At block 752, method 750 may include depositing a first portion of a top electrode over a dielectric material of a storage node of a capacitor cell. The dielectric material may be a high-k dielectric material. The dielectric material may be formed of a zirconium-based material.

[0051] At block 754, method 750 may include depositing a metal oxide over the first portion of the top electrode. The metal oxide may be deposited to a depth of 0 to The metal oxide may have a thickness in the range of . The metal oxide may be deposited using chemical vapor deposition (CVD). In some embodiments, the metal oxide may be deposited using atomic layer deposition (ALD). In some embodiments, the metal oxide may be deposited using multiple ALD cycles. In some embodiments, the metal oxide may be deposited using conformal deposition. The metal oxide may be deposited to reduce charge leakage in the capacitor cell.

[0052] At block 756, method 750 may include depositing a second portion of the top electrode over the metal oxide. The top electrode may be deposited to a depth of 0 to In some embodiments, the first portion of the top electrode may be deposited to a thickness that is less than the thickness of the second portion of the top electrode. In some embodiments, the first portion of the top electrode may be deposited to a thickness that is greater than the thickness of the second portion of the top electrode.

[0053] Figure 8 An example processing device 851 that can be used in a semiconductor manufacturing process is described. Figure 8 The numbering convention used does not follow the one applicable to Figures 1 to 7 851 may include a chamber 852 that surrounds components configured to perform deposition and / or etching operations on a number of semiconductor devices. The chamber 852 may further surround a carrier 853 to accommodate a batch of semiconductor wafers 854. The processing equipment 851 may include and / or be associated with tools that include, for example, a pump 855 unit and a purge 856 unit that are configured to introduce and remove appropriate etching chemicals at each point in the semiconductor manufacturing sequence, as described herein. The processing equipment 851 may further include a temperature control 857 unit that is configured to maintain the chamber 852 at an appropriate temperature at each point in the manufacturing sequence. The system 850 may include a number of chambers 852, each of which is configured to perform a specific process (e.g., a wet etching process, a dry etching process, and / or a deposition process, etc.) during the manufacturing sequence.

[0054] The system 850 may further include a controller 858. The controller 858 may include or be associated with circuitry and / or programming for implementing, for example, depositing portions of a top electrode. In some embodiments, the top electrode may be deposited over a high-k dielectric material. Adjusting such deposition, removal, and etching operations by the controller 858 may control the critical dimension (CD) of the semiconductor device produced in the processing apparatus 851.

[0055] A host computer may be configured to generate instructions related to protecting a top region of a pillar and adjacent trenches during removal of substrate material at a bottom region of a trench of a semiconductor device. An example of a host computer is shown in FIG. Fig. 9 958, but the embodiment is not limited to coupling to Fig. 9 851. Instructions may be sent to a controller 858 of the processing device 851 via the host interface 960. The instructions may be based at least in part on scaling preferences (e.g., gradients defined in numerical values ​​and / or structures) stored by the host 958, provided via input from another storage system (not shown), and / or provided via input from a user (e.g., a human operator), among other possibilities. The controller 858 may be configured to enable input of instructions and scaling preferences to define a CD for fabrication of a semiconductor device to be implemented by the processing device 851.

[0056] The scaling preferences may determine the final structure (e.g., CD) of the top region of the pillars, the sidewalls of the pillars, the width of the pillars, the width of the trenches, and / or the depth of the trenches. A particular CD may be achieved by a particular scaling preference input via the instructions. Receiving and implementing the scaling preferences by the controller 858 may result in corresponding adjustments to the deposition time of the electrodes of the processing device 851, adjustments to the coverage area, height, and / or volume of the electrodes, adjustments to the trimming direction and / or trimming time performed on the electrodes, and / or adjustments to the punch etching direction and / or punch etching time performed on the substrate material, as well as other possible implementations of the scaling preferences.

[0057] The controller 858 may be configured in several embodiments to use hardware as a control circuit. This control circuit may be, for example, an application specific integrated circuit (ASIC) having logic to control the manufacturing steps of pillar formation adjacent to the trenches, as well as the formation of electrodes on the pillars and trenches and the removal of electrodes from the pillars and trenches through associated deposition and etching processes.

[0058] The controller 858 may be configured to receive instructions and direct the execution of operations to perform the deposition of metal oxide into the top electrode, such as in conjunction with Figure 7 describe.

[0059] Fig. 9 is a functional block diagram of a computing system 956 including at least one memory system 962 according to one or more embodiments of the present invention. Fig. 9 The numbering convention used does not follow the one applicable to Figures 1 to 7 The memory system 962 may be, for example, a solid state drive (SSD).

[0060] exist Fig. 9In the embodiment illustrated in , the memory system 962 includes a memory interface 964, a number of memory devices 968-1, ..., 968-N, and a controller 966 that is selectively coupled to the memory interface 964 and the memory devices 968-1, ..., 968-N. The memory interface 964 can be used to transfer information between the memory system 962 and another device (e.g., a host 958). The host 958 may include a processor (not shown). As used herein, a "processor" may be a number of processors, such as a parallel processing system, a number of coprocessors, and the like. An example host may include or be implemented by a laptop computer, a personal computer, a digital camera, a digital recording device and playback device, a mobile phone, a PDA, a memory card reader, an interface bus, and the like. This host 958 may be used with, for example, a computer shown as 851 and in combination with Figure 8 The processing equipment described herein is associated with manufacturing operations performed on semiconductor devices and / or SSDs.

[0061] In several embodiments, the host 958 may be associated with (e.g., include or be coupled to) a host interface 960. The host interface 960 may enable input of scaling preferences (e.g., gradients defined in numerical values ​​and / or structures) to define, for example, a final structure or intermediate structure of a memory device (e.g., as shown at 968) and / or a critical dimension (CD) of a memory cell array formed thereon (e.g., as shown at 970) for implementation by the processing device 851. The array includes storage nodes having top electrodes formed according to embodiments described herein. The scaling preferences may be provided to the host interface 960 via input of a number of preferences stored by the host 958, input of preferences from another storage system (not shown), and / or input of preferences by a user (e.g., a human operator).

[0062] The memory interface 964 may be in the form of a standardized physical interface. For example, when the memory system 962 is used for information (e.g., data) storage in the computing system 956, the memory interface 964 may be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, or a universal serial bus (USB) interface, as well as other physical connectors and / or interfaces. However, in general, the memory interface 964 may provide an interface for passing control, addresses, information, scaling preferences, and / or other signals between the controller 966 of the memory system 962 and the host 958 (e.g., via the host interface 960).

[0063] Controller 966 may include, for example, firmware and / or control circuitry (e.g., hardware). Controller 966 may be operably coupled to and / or included on the same physical device (e.g., die) as one or more of memory devices 968-1, ..., 968-N. For example, controller 966 may be or may include an ASIC that is hardware operably coupled to a circuit (e.g., printed circuit board) that includes memory interface 964 and memory devices 968-1, ..., 968-N. Alternatively, controller 966 may be included on a separate physical device that is communicatively coupled to a physical device (e.g., die) that includes one or more of memory devices 968-1, ..., 968-N.

[0064] Controller 966 may communicate with memory devices 968-1, ..., 968-N to direct operations of sensing (e.g., reading), programming (e.g., writing), and / or erasing information, as well as other functions and / or operations for managing memory cells. Controller 966 may have circuitry that may include a number of integrated circuits and / or discrete components. In several embodiments, the circuitry in controller 966 may include control circuitry for controlling access across memory devices 968-1, ..., 968-N and / or circuitry for providing a translation layer between host 958 and memory system 962.

[0065] The memory devices 968-1, ..., 968-N may include, for example, a number of memory arrays 970 (e.g., arrays of volatile and / or non-volatile memory cells). For example, the memory devices 968-1, ..., 968-N may include arrays of memory cells, such as portions of an example memory device structured to include sense line contacts. At least one array includes an access device having a gate structure formed according to embodiments disclosed herein. As will be appreciated, the memory cells in the memory arrays 970 of the memory devices 968-1, ..., 968-N may be in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM, etc.), a flash architecture (e.g., NAND, NOR, etc.), a three-dimensional (3D) RAM, and / or a flash cell architecture, or some other memory array architecture including pillars and adjacent trenches.

[0066] The memory devices 968 may be formed on the same die. A memory device (e.g., memory device 968-1) may include one or more memory cell arrays 970 formed on a die. The memory device may include sensing circuits 972 and control circuits 974, or portions thereof, associated with one or more arrays 970 formed on a die. The sensing circuits 972 may be used to determine (sense) a specific data value (e.g., 0 or 1) stored at a specific memory cell in a row of the array 970. In addition to directing the storage, erasure, etc. of data values ​​in response to commands from the host 958 and / or the host interface 960, the control circuits 974 may be used to direct the sensing circuits 972 to sense specific data values. Commands may be sent directly to the control circuits 974 via the memory interface 964 or sent to the control circuits 974 via the controller 966.

[0067] Fig. 9 960. The embodiments illustrated in the drawings may include additional circuits that are not illustrated so as not to obscure the embodiments of the invention. For example, the memory device 968 may include address circuits that latch address signals provided on the I / O connectors by the I / O circuits. The address signals may be received and decoded by the row decoder and the column decoder to access the memory array 970. It will be appreciated that the number of address input connectors may depend on the density and / or architecture of the memory device 968 and / or the memory array 970.

[0068] In the above detailed description of the invention, reference is made to the accompanying drawings which form a part thereof and in which one or more embodiments of the invention are shown by way of illustration how they may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the invention, and it is to be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the invention.

[0069] It will be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" include singular and plural references, unless the context clearly indicates otherwise, as do "several," "at least one," and "one or more" (e.g., several memory arrays may refer to one or more memory arrays), while "multiple" is intended to refer to more than one such thing. In addition, the words "can and may" are used throughout this application in a permissive sense (i.e., it is possible, able to), rather than in a mandatory sense (i.e., must). The term "including" and its derivatives mean "including, but not limited to." The term "coupled" and "coupling" means a direct or indirect physical connection, and unless otherwise stated, may include wireless connections for access to instructions (e.g., control signals, address signals, etc.) and data and / or for moving (transmitting) the instructions and data, depending on the context.

[0070] Although example embodiments including various combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemistries, etching processes, solvents, memory devices, memory cells, openings, and other materials and / or components related to patterning materials on active areas for sense line contacts have been illustrated and described herein, embodiments of the invention are not limited to the combinations explicitly set forth herein. Other combinations and configurations of semiconductor materials, underlying materials, structural materials, dielectric materials, capacitor materials, substrate materials, silicate materials, nitride materials, buffer materials, etching chemistries, etching processes, solvents, memory devices, memory cells, openings, and / or sidewalls of trenches related to patterning materials on active areas for sense line contacts are expressly included within the scope of the invention except as disclosed herein.

[0071] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present invention is intended to cover adaptations or variations of one or more embodiments of the present invention. It should be understood that the above description has been made in an illustrative and non-restrictive manner. Those skilled in the art will understand the combination of the above embodiments and other embodiments not specifically described herein after reading the above description. The scope of one or more embodiments of the present invention includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present invention should be determined with reference to the attached claims together with the full scope of equivalents to which such claims are granted.

[0072] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the invention. This approach of the invention should not be interpreted as reflecting an intention that the disclosed embodiments of the invention must use more features than those explicitly stated in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in fewer features than all of the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim acting independently as a separate embodiment.

Claims

1. A memory device, comprising: a bottom electrode of a storage node; a dielectric material of the storage node formed above the bottom electrode; a first portion of a top electrode of the storage node formed above the dielectric material; a first metal oxide formed over the first portion of the top electrode, wherein the first metal oxide is a discontinuous layer separating the first portion of the top electrode from a second portion of the top electrode such that the first portion of the top electrode contacts the second portion of the top electrode through a gap in the first metal oxide; the second portion of the top electrode formed above the first metal oxide; a second metal oxide formed over the second portion of the top electrode, wherein the second metal oxide is a discontinuous layer separating the second portion of the top electrode from a third portion of the top electrode such that the second portion of the top electrode contacts the third portion of the top electrode through gaps in the second metal oxide; and The third portion of the top electrode is formed above the second metal oxide.

2. The memory device of claim 1, wherein the top electrode (102, 202, 302, 402, 502) is a titanium nitride (TiN) electrode to the storage node as a capacitor cell. 3 . The memory device of claim 1 , wherein the first metal oxide is aluminum oxide (AlOx). 4 . The memory device of claim 1 , wherein the first metal oxide is silicon oxide (SiOx).

5. The memory device of claim 1, wherein the first metal oxide is formed to a thickness in a range of ten percent (10%) to fifteen percent (15%) of a thickness of the top electrode.

6. The memory device of claim 1, wherein the first metal oxide is positioned in a first different region of the top electrode and the second metal oxide is positioned in a second different region of the top electrode.

7. The memory device of claim 1, wherein the dielectric material is a high dielectric constant (k) material.

8. A method for forming an electrode, comprising: depositing a bottom electrode of a storage node to the memory cell; depositing a dielectric material of the storage node to the memory cell over the bottom electrode; depositing a first portion of a top electrode of the storage node to the memory cell over the dielectric material; depositing a first metal oxide over the first portion of the top electrode, wherein the first metal oxide is a discontinuous layer that separates the first portion of the top electrode from a second portion of the top electrode such that the first portion of the top electrode contacts the second portion of the top electrode through gaps in the first metal oxide; depositing the second portion of the top electrode over the first metal oxide; depositing a second metal oxide over the second portion of the top electrode, wherein the second metal oxide is a discontinuous layer that separates the second portion of the top electrode from a third portion of the top electrode such that the second portion of the top electrode contacts the third portion of the top electrode through gaps in the second metal oxide; and The third portion of the top electrode is deposited over the second metal oxide.

9. The method of claim 8, further comprising depositing the top electrode to a depth of 0 to 40 angstroms. The thickness is in the range of 10. The method of claim 8, further comprising depositing the first metal oxide to a temperature between 0 and The thickness is in the range of 11 . The method of claim 8 , further comprising depositing the first metal oxide and the second metal oxide using atomic layer deposition (ALD). 12 . The method of claim 8 , further comprising depositing the first metal oxide and the second metal oxide using multiple cycles of atomic layer deposition (ALD).

13. The method of claim 8, further comprising depositing the first metal oxide and the second metal oxide using conformal deposition.

14. The method of claim 8, further comprising depositing the first metal oxide and the second metal oxide using chemical vapor deposition (CVD).

15. The method of claim 8, further comprising forming the dielectric material from a zirconium-based material.

16. The method of claim 8, further comprising in-situ depositing the first metal oxide and depositing the first and second portions of the top electrode.

17. The method of claim 8, wherein: the first portion of the top electrode being deposited in situ; The first metal oxide is deposited ex situ; and The second portion of the top electrode is deposited in-situ.

18. A system for forming an electrode, comprising: A storage node of a memory unit, the storage node comprising: bottom electrode; a first dielectric material formed on the bottom electrode; a first portion of a top electrode formed on the first dielectric material; a first metal oxide formed on the first portion of the top electrode, wherein the first metal oxide is a discontinuous layer separating the first portion of the top electrode from a second portion of the top electrode such that the first portion of the top electrode contacts the second portion of the top electrode through a gap in the first metal oxide; the second portion of the top electrode formed on the first metal oxide; a second metal oxide formed on the second portion of the top electrode, wherein the second metal oxide is a discontinuous layer that separates the second portion of the top electrode from a third portion of the top electrode such that the second portion of the top electrode contacts the third portion of the top electrode through gaps in the second metal oxide; The third portion of the top electrode is formed on the second metal oxide, wherein the third portion of the top electrode has a third thickness.

19. The system of claim 18, wherein a thickness of the first portion of the top electrode is less than a thickness of the second portion of the top electrode.

20. The system of claim 18, wherein the storage node is coupled to a buried recessed access device (BRAD).

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