Thin Film Transistor Substrate

Abstract

A thin film transistor substrate includes an insulating substrate, a first insulating layer, a first thin film transistor including a first oxide semiconductor film, a second insulating layer located above the first insulating layer, and a second thin film transistor including a second oxide semiconductor film having a different composition from the first oxide semiconductor film. At least a portion of the first oxide semiconductor film is disposed above and in contact with the first insulating layer. The first insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the first oxide semiconductor film. At least a portion of the second oxide semiconductor film is disposed above and in contact with the second insulating layer. The second insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the second oxide semiconductor film.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor substrate. Background Art

[0002] Thin film transistors (TFTs) including oxide semiconductor materials such as indium gallium zinc oxide (IGZO) are used in display devices, including liquid crystal display panels and organic light emitting diode (OLED) display devices, as well as other types of devices. Oxide semiconductor TFTs generate small leakage currents, and thus result in low power consumption of the device. However, oxide semiconductor TFTs have low mobility compared to low-temperature polysilicon TFTs. To solve this problem, US 2017 / 0184893 A discloses a display device that achieves both low power consumption and narrow bezels by including oxide semiconductor TFTs with different mobilities. Summary of the invention

[0003] There are various requirements for display devices or other types of devices. For example, a device requires lower power consumption, smaller circuit size, and higher reliability. In order to meet such different requirements of oxide semiconductor TFTs, oxide semiconductor TFTs including oxide semiconductor films (made of different materials) with different characteristics must be manufactured on the same substrate. In order to appropriately meet various requirements, it is important that the material of each oxide semiconductor TFT can be selected from various oxide semiconductor materials.

[0004] One aspect of the present disclosure is a thin film transistor substrate, which includes: an insulating substrate; a first insulating layer disposed on the insulating substrate; a first thin film transistor disposed on the insulating substrate and including a first oxide semiconductor film; a second insulating layer disposed on the insulating substrate and located above the first insulating layer; and a second thin film transistor disposed on the insulating substrate and including a second oxide semiconductor film having a different composition from the first oxide semiconductor film. At least a portion of the first oxide semiconductor film is disposed above and in contact with the first insulating layer. The first insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the first oxide semiconductor film. At least a portion of the second oxide semiconductor film is disposed above and in contact with the second insulating layer. The second insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the second oxide semiconductor film.

[0005] Another aspect of the present disclosure is a method for manufacturing a thin film transistor substrate, the method comprising: forming a first insulating layer on an insulating substrate; forming a first oxide semiconductor layer including a channel region of a first thin film transistor after forming the first insulating layer; forming a second insulating layer to cover the first oxide semiconductor layer; and forming a second oxide semiconductor film including a channel region of a second thin film transistor in a state where the first oxide semiconductor layer is covered by the second insulating layer.

[0006] One aspect of the present disclosure provides a technology for correctly manufacturing oxide semiconductor TFTs on the same substrate, the oxide semiconductor TFTs being made of oxide semiconductor materials with different characteristics, the oxide semiconductor materials being selected from a group of oxide semiconductor materials.

[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A configuration example of a liquid crystal display panel is schematically shown;

[0009] Figure 2 A cross section schematically shows a configuration example of a TFT substrate used for a liquid crystal display panel;

[0010] Figure 3A Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0011] Figure 3B Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0012] Figure 3C Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0013] Figure 3D Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0014] Figure 3E Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0015] Figure 3F Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0016] Figure 3G Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0017] Figure 3H Shows Figure 2 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0018] Figure 4 A cross section schematically shows another configuration example of a TFT substrate for a liquid crystal display panel;

[0019] Figure 5A Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0020] Figure 5B Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0021] Figure 5C Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0022] Figure 5D Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0023] Figure 5E Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0024] Fig. 5F Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0025] Figure 5G Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0026] Figure 5H Shows Figure 4 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0027] Figure 6 A cross section schematically shows still another configuration example of a TFT substrate for a liquid crystal display panel;

[0028] Fig. 7A Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0029] Figure 7B Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0030] Figure 7C Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0031] Fig.7D Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0032] Fig. 7E Shows Figure 6The steps of the method for manufacturing a TFT substrate shown in FIG.

[0033] Figure 7F Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0034] Figure 7G Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0035] Figure 7H Shows Figure 6 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0036] Figure 8 A cross section schematically shows still another configuration example of a TFT substrate for a liquid crystal display panel;

[0037] Fig. 9A Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0038] Fig. 9B Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0039] Fig. 9C Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0040] Fig.9D Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0041] Fig.9E Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0042] Fig.9F Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0043] Figure 9G Shows Figure 8 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0044] Fig.10 A cross section schematically shows still another configuration example of a TFT substrate for a liquid crystal display panel;

[0045] Fig.11A Shows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0046] Fig. 11BShows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0047] Fig. 11C Shows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0048] Fig.11D Shows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0049] Fig.11E Shows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0050] Fig.11F Shows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0051] Fig.11G Shows Fig.10 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0052] Fig.12 An example of a first-stage circuit of a shift register is shown;

[0053] Fig.13 An example of a pixel circuit for an OLED display device is shown;

[0054] Fig.14 A cross section schematically shows still another configuration example of a TFT substrate for a liquid crystal display panel;

[0055] Fig.15 A cross section schematically shows still another configuration example of a TFT substrate for a liquid crystal display panel;

[0056] Fig.16A Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0057] Fig. 16B Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0058] Fig. 16C Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0059] Fig.16D Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0060] Fig.16E Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0061] Fig.16F Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0062] Figure 16G Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0063] Fig.16H Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in FIG.

[0064] Fig.16I Shows Fig.15 The steps of the method for manufacturing a TFT substrate shown in

[0065] Fig.17 A cross section schematically shows a configuration example of a pixel region of a TFT substrate used for a top emission type OLED display device. DETAILED DESCRIPTION

[0066] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that these embodiments are merely examples for implementing the present disclosure and do not limit the technical scope of the present disclosure. Commonly used elements in the figures are represented by the same reference symbols, and some elements in the figures are exaggerated in size or shape to facilitate a clear understanding of the description.

[0067] Overview

[0068] Hereinafter, the structure and manufacturing method of the TFT substrate including the oxide semiconductor TFT of the present disclosure are described. The TFT substrate of the present disclosure can be used in various devices such as a sensor device and a display device.

[0069] The requirements for devices are various, such as the requirement for low power consumption, the requirement for smaller circuit size, and the requirement for higher reliability. In order to meet such different requirements for oxide semiconductor TFTs, it is necessary to manufacture oxide semiconductor TFTs including oxide semiconductor films having different characteristics (made of different materials) on the same substrate. In order to appropriately meet various requirements, it is important that the oxide semiconductor material of each oxide semiconductor TFT can be selected from various oxide semiconductor materials.

[0070] The TFT substrate of the present disclosure includes an oxide semiconductor TFT, including an oxide semiconductor film made of different materials (having different elemental compositions). Different materials meet different requirements for the TFT substrate. At least a portion of the oxide semiconductor film of the first oxide semiconductor TFT is disposed above the first insulating layer and in contact with the first insulating layer, while at least a portion of the oxide semiconductor film of the second oxide semiconductor TFT is disposed above and in contact with a second insulating layer different from the first insulating layer. This configuration allows different oxide semiconductor materials for TFT to be selected from a variety of oxide semiconductor materials.

[0071] Compared with low-temperature polysilicon TFTs, oxide semiconductor TFTs exhibit low leakage current and low temperature dependence, but have low mobility and low reliability. In particular, oxide semiconductor TFTs have low negative bias illumination temperature stress (NBITS) reliability. NBITS reliability refers to the reliability of a TFT under stress conditions of negative gate bias, illumination, and high temperature. The gate threshold voltage of an oxide semiconductor TFT varies significantly with NBITS.

[0072] It is believed that the photogenerated carriers cause a change in the gate threshold voltage. Therefore, in order to improve the reliability of the oxide semiconductor TFT, it is important to use an oxide semiconductor material with a wide bandgap. On the other hand, in order to achieve a smaller circuit size, the mobility of the oxide semiconductor TFT therein should be high, that is, it is important to use an oxide semiconductor material with high mobility.

[0073] For example, in order to make the display device have a thin frame and high reliability, the TFT substrate may include an oxide semiconductor TFT using an oxide semiconductor material having high mobility in a peripheral circuit and an oxide semiconductor TFT using an oxide semiconductor material having a wide bandgap in a display area (pixel circuit). Hereinafter, as an application example of the TFT substrate of the present disclosure, a TFT substrate for a display device is described.

[0074] Example 1

[0075] Display device configuration

[0076] Figure 1 1 shows a configuration example of a liquid crystal display panel 1. The liquid crystal display panel 1 includes a thin film transistor (TFT) substrate 10 on which TFTs and pixel electrodes for applying an electric field to liquid crystals are provided, an opposing substrate 20, and a sealant 30 for bonding the TFT substrate 10 to the opposing substrate 20. Liquid crystal material is enclosed between the TFT substrate 10 and the opposing substrate 20. A common electrode is provided on the TFT substrate 10 or the opposing substrate 20, which is used to generate an electric field applied to the liquid crystal together with the pixel electrode.

[0077] On the surfaces of the TFT substrate 10 and the opposite substrate 20 facing each other, an alignment film (not shown) for initial alignment of liquid crystal is provided. On the other outer surfaces of the TFT substrate 10 and the opposite substrate 20, a polarizing plate (not shown) is provided. The liquid crystal display panel also includes a backlight unit (not shown).

[0078] In the outer periphery of the display area 25 of the TFT substrate 10, a peripheral circuit is provided. The area outside the display area 25 where the peripheral circuit is provided is referred to as a peripheral circuit area. Examples of the peripheral circuit include a first scan driver 31, a second scan driver 32, a protection circuit 33, and a multiplexer 36. In addition, a driver IC 34 is provided outside the display area 25.

[0079] The protection circuit 33 includes an electrostatic discharge (ESD) protection element and protects elements in the pixel circuit from ESD. The driver IC 34 is connected to an external device via a flexible printed circuit (FPC) 35. The driver IC 34 is mounted with, for example, an anisotropic conductive film (ACF).

[0080] The scan drivers 31 and 32 drive the scan lines on the TFT substrate 10. The driver IC 34 supplies power and timing signals (control signals) to the scan drivers 31 and 32, and further supplies signals corresponding to video data to the data lines through the multiplexer 36. The multiplexer 36 outputs the output of one pin of the driver IC 34 in series to d data lines (d is an integer greater than 1). The multiplexer 36 changes the output data line of the data signal from the driver IC 34 d times per scan cycle to a data line that drives d times the output pin of the driver IC 34.

[0081] Organic light emitting diode (OLED) display devices have similar Figure 1 The structure shown in the figure is a structure of a structure. The OLED display device includes an organic light emitting element (OLED element) and a TFT substrate on which a TFT is arranged, a packaging substrate for packaging the OLED element, and a bonding member (glass frit sealant) for bonding the TFT substrate to the packaging substrate. The space between the TFT substrate and the packaging substrate is filled with, for example, dry nitrogen and sealed with a bonding member 30. The packaging substrate and the bonding member constitute a structural packaging unit. The structural packaging unit may have a thin film encapsulation (TFE) structure.

[0082] One or more scan drivers, protection circuits, driver ICs, and multiplexers are arranged at the periphery of the display area of ​​the TFT substrate. The scan driver and the protection circuit are peripheral circuits arranged on the TFT substrate. For example, the first scan driver drives the scan line on the TFT substrate; the second scan driver drives the control line to control the light emission period of the pixel and supplies a reference potential to the pixel. The driver IC provides power and timing signals (control signals) to the scan driver, and further provides power and data signals to the multiplexer. The multiplexer has the same function as the multiplexer 36 in the liquid crystal display panel 1.

[0083] TFT substrate structure

[0084] Figure 2 A cross section of a configuration example of a TFT substrate 100 used for a liquid crystal display panel is schematically shown. Figure 2 By way of example, one first oxide semiconductor TFT 130 in the peripheral circuit region 110 of the TFT substrate 100 and one second oxide semiconductor TFT 170 in the display region 150 of the TFT substrate 100 are shown. The peripheral circuit region 110 is located outside the display region 150 and is a region where a peripheral circuit is mounted. The display region 150 is a region including pixels. For example, the first oxide semiconductor TFT 130 is an oxide semiconductor TFT in a scan driver, and the second oxide semiconductor TFT 170 is a switching TFT for selecting a pixel to provide a data signal.

[0085] The first oxide semiconductor TFT 130 and the second oxide semiconductor TFT 170 are constructed on a flexible or non-flexible insulating substrate 113 made of resin or glass. In the following description, between two stacked layers (two layers having an interface) in contact with each other, a layer closer to the insulating substrate 113 is a lower layer, and a layer farther from the insulating substrate 113 is an upper layer.

[0086] The oxide semiconductor film (first oxide semiconductor film) 133 of the first oxide semiconductor TFT 130 and the oxide semiconductor film (second oxide semiconductor film) 173 of the second oxide semiconductor TFT 170 are made of different oxide semiconductor materials and have different characteristics. In this example, the mobility of the first oxide semiconductor film 133 is higher than that of the second oxide semiconductor film 173, and the band gap of the second oxide semiconductor film 173 is wider than that of the first oxide semiconductor film 133. Due to the difference in characteristics of the two oxide semiconductor films, both films achieve narrow frames and high reliability.

[0087] Examples of an oxide semiconductor material that can be used for the first oxide semiconductor film 133 include ITZO, IGZTO, In-Zn-Ti-O, and In-WZO. Examples of an oxide semiconductor material that can be used for the second oxide semiconductor film 173 include IGZO, GaZnO, and IGO.

[0088] The oxide semiconductor film (first oxide semiconductor film) 133 of the first oxide semiconductor TFT 130 is provided above and in contact with the first insulating layer 117. The oxide semiconductor film (second oxide semiconductor film) 173 of the first oxide semiconductor TFT 170 is provided above and in contact with the second insulating layer 119. The second insulating layer 119 is located above the first insulating layer 117. The first oxide semiconductor film 133 is located below the second oxide semiconductor film 173. The first insulating layer 117 and the second insulating layer 119 may be made of silicon nitride or silicon oxide.

[0089] exist Figure 2 In the configuration example in , the entire first oxide semiconductor film 133 is provided over and in contact with the first insulating layer 117, and the entire second oxide semiconductor film 173 is provided over and in contact with the second insulating layer 119. The second insulating layer 119 is provided over and in contact with the first insulating layer 117. Both the first oxide semiconductor film 133 and the second insulating layer 119 are provided over and in contact with the first insulating layer 117.

[0090] The first oxide semiconductor TFT 130 includes a first oxide semiconductor film 133, a gate electrode 131 located below the first oxide semiconductor film 133, and a gate insulating film 132 (in the layer structure direction) located between the gate electrode 131 and the first oxide semiconductor film 133. The gate electrode 131 is disposed above and in contact with the insulating base layer 115. The gate insulating film 132 is a part of the first insulating layer 117. The base layer 115 may be made of silicon nitride or silicon oxide.

[0091] The first oxide semiconductor film 133 includes two source / drain regions (not shown) and a channel region (not shown) between the source / drain regions. The source / drain region is a low resistance region, while the channel region is a high resistance region. The source / drain region is a portion in contact with the source / drain electrodes 135 and 137. The source / drain electrodes 135 and 137 are disposed above and in contact with the second insulating layer 119, and they are in contact with the top surface of the first oxide semiconductor film 133 within the opening formed in the second insulating layer 119. Although Figure 2 The source / drain electrodes 135 and 137 in the example are in contact with only the top surface of the first oxide semiconductor film 133 , but the source / drain electrodes 135 and 137 may be in contact with both the end surface and the top surface of the first oxide semiconductor film 133 .

[0092] The second oxide semiconductor TFT 170 includes a second oxide semiconductor film 173, a gate electrode 171 located at a lower portion than the first oxide semiconductor film 173, and a gate insulating film 172 located between the gate electrode 171 and the second oxide semiconductor film 173 (in the layer structure direction). The gate electrode 171 is provided above and in contact with the insulating base layer 115. The gate insulating film 172 has a stacked structure consisting of a portion of the first insulating layer 117 and a portion of the second insulating layer 119. The gate insulating film 172 of the second oxide semiconductor TFT 170 is thicker than the gate insulating film 132 of the first oxide semiconductor TFT 130 to increase the reliability of the gate insulating film 172 of the second oxide semiconductor TFT 170.

[0093] The second oxide semiconductor TFT 173 includes two source / drain regions (not shown) and a channel region (not shown) between the source / drain regions. The source / drain regions are portions in contact with source / drain electrodes 175 and 177. The source / drain electrodes 175 and 177 are disposed above and in contact with the second insulating layer 119. The source / drain electrodes 175 and 177 are in contact with portions of the second oxide semiconductor film 173 including either end thereof.

[0094] The first oxide semiconductor film 133 and the second oxide semiconductor film 173 are covered by an interlayer dielectric (ILD) layer or an interlayer insulating layer 121. The interlayer insulating layer 121 may be made of an inorganic or organic material. The pixel electrode 181 is disposed above and in contact with the interlayer insulating layer 121, and is connected to the source / drain 177 of the second oxide semiconductor TFT 170 through a through hole provided in a via hole in the interlayer insulating layer 121. The pixel electrode 181 may be made of indium tin oxide (ITO).

[0095] The insulating base layer 115 is disposed above and in contact with the insulating substrate 113; two gate electrodes 131, 171 and a first insulating layer 117 are disposed above and in contact with the base layer 115. The gate electrodes 131 and 171 are portions included in the same metal layer. The material for the gate electrodes 131 and 171 can be ideally selected; the gate electrodes 131 and 171 can be a single layer of Mo, W, Nb, Al, Ta, Cr, Ti, a metal stack selected from these materials, or a metal alloy selected from these materials. The gate electrodes 131 and 171 are completely covered with the first insulating layer 117.

[0096] The source / drain electrodes 135, 137, 175, and 177 of the first oxide semiconductor TFT 130 and the second oxide semiconductor TFT 170 are portions included in the same metal layer. The source / drain electrodes 135, 137, 175, and 177 may be prepared by depositing and patterning a conductive film of Ti / Al / Ti or Mo / Al / Mo. The source / drain electrodes 135, 137, 175, and 177 may have a single-layer structure or be made of a metal other than these metals.

[0097] Method for manufacturing TFT substrate

[0098] Describes Figure 2 An example of a method for manufacturing a TFT substrate 100 is shown in FIG. Figure 3A As shown in, the method for manufacturing the TFT substrate 100 forms a base layer 115 having a thickness of about 100 nm on an insulating substrate 113 by CVD. Next, the method forms a metal layer (gate layer) including gate electrodes 131 and 171 on the base layer 115. Specifically, the method forms a metal film having a thickness of about 300 nm by sputtering, and patterns the metal film by photolithography and etching. In addition, the method forms a first insulating layer 117 having a thickness of about 300 nm by CVD to cover the gate layer.

[0099] Next, if Figure 3B As shown in , the method forms an oxide semiconductor layer (first oxide semiconductor layer) including a first oxide semiconductor film 133 on the first insulating layer 117. Specifically, the method forms an oxide semiconductor layer having a thickness of about 50 nm by sputtering, and patterns the oxide semiconductor layer by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0100] Next, if Figure 3C As shown in , the method forms a second insulating layer 119 with a thickness of about 100 nm by CVD to cover the first oxide semiconductor film 133. Next, as Figure 3D As shown in , the method forms an oxide semiconductor layer (second oxide semiconductor layer) including a second oxide semiconductor film 173 on the second insulating layer 119. Specifically, the method forms an oxide semiconductor layer having a thickness of about 50 nm by sputtering, and patterns the oxide semiconductor layer by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0101] Next, if Figure 3E As shown in , the method opens an opening 120 in the second insulating layer 119 by photolithography and etching. The opening 120 is formed to expose the top surface of the first oxide semiconductor film 133 in the opening. Although the end surfaces of the first oxide semiconductor film 133 are not exposed in the opening 120 in this example, they may be exposed.

[0102] Next, if Figure 3F As shown in , the method forms a metal layer (source / drain layer) 140 with a thickness of about 300 nm by sputtering. The metal layer 140 includes source / drain electrodes 135, 137, 175, and 177, and covers the second insulating layer 119, the first oxide semiconductor film 133, and the second oxide semiconductor film 173. The metal layer 140 fills the opening 120 provided in the second insulating layer 119 and contacts the top surface of the first oxide semiconductor film 133. Next, as Figure 3G As shown in FIG. 1 , the method patterns the metal layer 140 by photolithography and etching to form source / drain electrodes 135 , 137 , 175 , and 177 .

[0103] Next, if Figure 3H As shown in , the method forms an interlayer insulating layer 121 with a thickness of about 400 nm by CVD to cover the source / drain electrodes 135, 137, 175, 177, the first oxide semiconductor film 133 and the second oxide semiconductor film 173, and opens a via hole in the interlayer insulating layer 121 by photolithography and etching to expose a portion of the top surface of the source / drain electrode 177. In addition, the method forms a pixel electrode 181 on the interlayer insulating layer 121, and a through hole for connecting the pixel electrode 181 and the source / drain electrode 177 in the interlayer insulating layer 121. Specifically, the method forms an ITO film with a thickness of about 50 nm by sputtering, and patterns the ITO film by photolithography and etching.

[0104] like Figure 3D As shown in , when the second oxide semiconductor film 173 is formed, the first oxide semiconductor film 133 is covered with the second insulating layer 119. Therefore, the first oxide semiconductor film 133 is not affected by the formation and patterning of the second oxide semiconductor film 173. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 133 and the second oxide semiconductor film 173.

[0105] Example 2

[0106] TFT substrate structure

[0107] Hereinafter, another configuration example of a TFT substrate and a method of manufacturing the TFT substrate are described. Figure 4 Schematically shows a cross section of another configuration example of a TFT substrate 200 for a liquid crystal display panel. Figure 2 The difference between the construction examples shown in .

[0108] The TFT substrate 200 includes a first oxide semiconductor TFT 230 in the peripheral circuit region 210 and a second oxide semiconductor TFT 170 in the display region 150. The second oxide semiconductor TFT 170 is configured similarly to the first oxide semiconductor TFT 230 in the peripheral circuit region 210. Figure 2 The same construction as in . Figure 2 In addition to the configuration of the first oxide semiconductor TFT 130 in FIG. 2 , the first oxide semiconductor TFT 230 further includes an etch stop film 233. The etch stop film 233 is disposed in contact with the first oxide semiconductor film 133. The etch stop film 233 is located between the source / drain electrodes 135 and 137 and above the channel region of the first oxide semiconductor film 133.

[0109] The etch stopper film 233 is a part of the second insulating layer 219. The etch stopper film 233 prevents the channel region of the oxide semiconductor film 133 from being exposed to an etchant during etching of the second insulating layer 219 for contact between the oxide semiconductor film 133 and the source / drain electrodes 135 and 137.

[0110] Method for manufacturing TFT substrate

[0111] Describes Figure 4 An example of a method for manufacturing a TFT substrate 200 is shown in FIG. Figure 5A As shown in , the method for manufacturing the TFT substrate 200 forms a base layer 115 on an insulating substrate 113 by CVD. Next, the method forms a metal layer (gate layer) including gate electrodes 131 and 171 on the base layer 115. Specifically, the method forms a metal film by sputtering, and patterns the metal film by photolithography and etching. In addition, the method forms a first insulating layer 117 by CVD to cover the gate layer.

[0112] Next, if Figure 5B As shown in , the method forms an oxide semiconductor layer (first oxide semiconductor layer) including a first oxide semiconductor film 133 on the first insulating layer 117. Specifically, the method forms the oxide semiconductor layer by sputtering, and patterns the oxide semiconductor layer by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0113] Next, if Figure 5C As shown in , the method forms the second insulating layer 219 by CVD to cover the first oxide semiconductor film 133. Next, as Figure 5D As shown in , the method forms an oxide semiconductor layer (second oxide semiconductor layer) including a second oxide semiconductor film 173 on the second insulating layer 219. Specifically, the method forms the oxide semiconductor layer by sputtering, and patterns the oxide semiconductor layer by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0114] Next, if Figure 5EAs shown in , the method opens openings 235 and 236 in the second insulating layer 219 by photolithography and etching. The opening 235 is used for contact between the source / drain 135 and the first oxide semiconductor film 133, and the opening 236 is used for contact between the source / drain 137 and the first oxide semiconductor film 133. The openings 235 and 236 are formed to expose the top surface of the first oxide semiconductor film 133 in the openings. As a result of forming the openings 235 and 236, an etching stopper film 233 is prepared. Although the end surfaces of the first oxide semiconductor film 133 are not exposed in the openings 235 and 236, they can be exposed.

[0115] Next, if Fig. 5F As shown in , the method forms a metal layer (source / drain layer) 140 including source / drain electrodes 135, 137, 175, and 177 by sputtering. The metal layer 140 covers the second insulating layer 219 and the second oxide semiconductor film 173. The metal layer 140 fills the openings 235 and 236 in the second insulating layer 219 and contacts the top surface of the first oxide semiconductor film 133. Next, as Figure 5G As shown in FIG. 1 , the method patterns the metal layer 140 by photolithography and etching to form source / drain electrodes 135 , 137 , 175 , and 177 .

[0116] Next, if Figure 5H As shown in , the method forms the interlayer insulating layer 121 by CVD to cover the source / drain electrodes 135, 137, 175, 177, etches the stop film 233 and the second insulating layer 219, and opens a via hole in the interlayer insulating layer 121 by photolithography and etching to expose a portion of the top surface of the source / drain electrode 177. In addition, the method forms a pixel electrode 181 on the interlayer insulating layer 121, and a through hole for connecting the pixel electrode 181 and the source / drain electrode 177 in the interlayer insulating layer 121. Specifically, the method forms an ITO film by sputtering, and patterns the ITO film by photolithography and etching.

[0117] like Figure 5D As shown in , when the second oxide semiconductor film 173 is formed, the first oxide semiconductor film 133 is covered with the second insulating layer 219. Therefore, the first oxide semiconductor film 133 is not affected by the formation and patterning of the second oxide semiconductor film 173. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 133 and the second oxide semiconductor film 173.

[0118] Example 3

[0119] TFT substrate structure

[0120] Hereinafter, still another configuration example of a TFT substrate and a method of manufacturing the TFT substrate are described. Figure 6A cross section of a configuration example of another TFT substrate 300 used for a liquid crystal display panel is schematically shown. Figure 6 One first oxide semiconductor TFT 370 in the display region 350 of the TFT substrate 300 and one second oxide semiconductor TFT 330 in the peripheral circuit region 310 of the TFT substrate 300 are shown. The peripheral circuit region 310 is located outside the display region 350 and is a region where a peripheral circuit is mounted. The display region 350 is a region including pixels. Figure 6 The pixel electrode and the interlayer insulating layer covering the first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 are omitted.

[0121] The first oxide semiconductor TFT 370 is a switching TFT for selecting a pixel to supply a data signal. The second oxide semiconductor TFT 330 may be an oxide semiconductor TFT in a scan driver. The first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 have a top gate structure.

[0122] The first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 are manufactured on a flexible or non-flexible insulating substrate 313 made of resin or glass. The oxide semiconductor film (first oxide semiconductor film) 373 of the first oxide semiconductor TFT 370 and the oxide semiconductor film (second oxide semiconductor film) 333 of the second oxide semiconductor TFT 330 are made of different oxide semiconductor materials and have different characteristics. In this example, the mobility of the second oxide semiconductor film 333 is higher than the mobility of the first oxide semiconductor film 173, and the band gap of the first oxide semiconductor film 373 is wider than the band gap of the second oxide semiconductor film 333. Due to the difference in characteristics of the two oxide semiconductor films, both films achieve narrow frame and high reliability.

[0123] Examples of an oxide semiconductor material that can be used for the second oxide semiconductor film 333 include ITZO, IGZTO, In-Zn-Ti-O, and In-WZO. Examples of an oxide semiconductor material that can be used for the first oxide semiconductor film 373 include IGZO, GaZnO, and IGO.

[0124] The oxide semiconductor film (second oxide semiconductor film) 333 of the second oxide semiconductor TFT 330 is disposed above and in contact with the insulating film 317 included in the second insulating layer. The second insulating layer including the insulating film 317 is located above the first insulating layer 315. The oxide semiconductor film (first oxide semiconductor film) 373 of the first oxide semiconductor TFT 370 is disposed above and in contact with the first insulating layer 315. The first insulating layer 315 is a base layer. The second oxide semiconductor film 333 is located above the first oxide semiconductor film 373. The first insulating layer 315 and the second insulating layer including the second insulating film 317 may be made of silicon nitride or silicon oxide.

[0125] exist Figure 6 In the configuration example in , the entire second oxide semiconductor film 333 is provided over and in contact with the insulating film 317, and the entire first oxide semiconductor film 373 is provided over and in contact with the first insulating layer 315. The second insulating layer including the insulating film 317 is provided over and in contact with the first insulating layer 315. Both the second oxide semiconductor film 333 and the second insulating layer including the insulating film 317 are provided over and in contact with the first insulating layer 315.

[0126] The second oxide semiconductor TFT 330 includes a second oxide semiconductor film 333 , a gate electrode 331 located above the second oxide semiconductor film 333 , and a gate insulating film 339 located between the gate electrode 331 and the second oxide semiconductor film 333 (in the layer structure direction).

[0127] The second oxide semiconductor film 333 includes source / drain regions 334 and 336 and a channel region 332 between the source / drain regions 334 and 336. The source / drain regions 334 and 336 are low resistance regions, while the channel region 332 is a region where resistance is not reduced, i.e., a high resistance region. A gate insulating film 339 is disposed above and in contact with the channel region 332. A gate 331 is disposed above and in contact with the gate insulating film 339.

[0128] The source / drain electrodes 335 and 337 are disposed over and in contact with the interlayer insulating layer 321. The source / drain electrodes 335 and 337 are connected to the source / drain regions 334 and 336 through via holes 340 and 341 disposed in the interlayer insulating layer 321. The via holes 340 and 341 continue from the source / drain electrodes 335 and 337 and are disposed over and in contact with the source / drain regions 334 and 336.

[0129] The first oxide semiconductor TFT 370 includes a first oxide semiconductor film 373 , a gate electrode 371 located above the first oxide semiconductor film 373 , and a gate insulating film having a stacked structure including insulating films 378 and 379 (in the layer structure direction) disposed between the gate electrode 371 and the first oxide semiconductor film 373 .

[0130] The first oxide semiconductor film 373 includes source / drain regions 374 and 376 and a channel region 372 between the source / drain regions 374 and 376. The source / drain regions 374 and 376 are low resistance regions, while the channel region 372 is a region where the resistance is not reduced, i.e., a high resistance region. A lower gate insulating film 378 is disposed above and in contact with the channel region 372. The lower gate insulating film 378 is a portion of a second insulating layer (e.g., an insulating film 317). The upper gate insulating film 379 is a portion of the same insulating layer as the insulating film 339. The gate 371 is disposed above and in contact with the gate insulating film 379.

[0131] The source / drain electrodes 375 and 377 are disposed over and in contact with the interlayer insulating layer 321. The source / drain electrodes 375 and 377 are connected to the source / drain regions 374 and 376 through via holes 380 and 381 disposed in the interlayer insulating layer 321. The via holes 380 and 381 continue from the source / drain electrodes 375 and 377 and are disposed over and in contact with the source / drain regions 374 and 376.

[0132] The interlayer insulating layer 321 covers the constituent elements except the source / drain electrodes 335, 337, 375, and 377 of the second oxide semiconductor TFT 330 and the first oxide semiconductor TFT 370. The interlayer insulating layer 321 may be made of silicon oxide or silicon nitride. The insulating layer (third insulating layer) including the insulating films 339 and 379 may be made of silicon oxide or silicon nitride.

[0133] The gate electrodes 331 and 371 are portions included in the same metal layer. For example, the materials of the gate electrodes 331 and 371 may be ideally selected from Mo, W, Nb, and Al. The source / drain electrodes 335, 337, 375, and 377 of the second oxide semiconductor TFT 330 and the first oxide semiconductor TFT 370 are portions included in the same metal layer. The source / drain electrodes 335, 337, 375, and 377 may be prepared by depositing and patterning a conductive film of, for example, Ti / Al / Ti. The source / drain electrodes 335, 337, 375, and 377 may have a single-layer structure or may be made of a metal other than these metals.

[0134] Method for manufacturing TFT substrate

[0135] Describes Figure 6 An example of a method for manufacturing a TFT substrate 300 is shown in FIG. Fig. 7A As shown in the figure, the method of manufacturing the TFT substrate 300 forms a first insulating layer 315 of a base layer on an insulating substrate 313 by CVD. Next, the method forms an oxide semiconductor layer (first oxide semiconductor layer) including a first oxide semiconductor film 373 on the first insulating layer 315. Specifically, the method forms an oxide semiconductor film by sputtering, and patterns the oxide semiconductor film by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0136] Next, if Figure 7B As shown in FIG. 1 , the method forms the second insulating layer 318 by CVD to cover the first oxide semiconductor film 373. The second insulating layer 318 includes Figure 6 The insulating films 317 and 378 in FIG.

[0137] Next, if Figure 7C As shown in , the method forms an oxide semiconductor layer (second oxide semiconductor layer) including a second oxide semiconductor film 333 on the second insulating layer 318. Specifically, the method forms an oxide semiconductor film by sputtering, and patterns the oxide semiconductor film by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0138] Next, if Fig.7D As shown in FIG. 1 , the method forms a third insulating layer 319 by CVD to cover the second oxide semiconductor film 333 and the second insulating layer 318. The third insulating layer 319 includes Figure 6 Insulating films 339 and 379 are formed in the third insulating layer 319. In addition, the method forms a metal layer (gate layer) 320 including gate electrodes 331 and 371 on the third insulating layer 319 by sputtering.

[0139] Next, if Fig. 7E As shown, the method etches the second insulating layer 318, the third insulating layer 319 and the gate layer 320 together to prepare insulating films 339, 317, insulating films 379, 378 and gates 331, 371. Next, as Figure 7F As shown, by exposing these portions to He plasma, the method reduces the resistance of the portion not covered by the gate insulating film 339 in the second oxide semiconductor film 333 and the portion not covered by the gate insulating film 378 in the second oxide semiconductor film 373. As a result, the source / drain regions 334, 336, 374, and 376 are prepared.

[0140] Next, if Figure 7G As shown, the method forms an interlayer insulating layer 321 by CVD to cover the components of the prepared first oxide semiconductor TFT 370, the components of the prepared second oxide semiconductor TFT 330, and the first insulating layer 315. Next, as Figure 7H As shown, the method opens a via hole in the interlayer insulating layer 321 by photolithography and etching, and further prepares source / drain electrodes 335, 337, 375, 377 and through holes 340, 341, 380, 381. Specifically, the method forms a metal layer on the interlayer insulating layer 321 (including in the via hole) by sputtering and forms the source / drain electrodes 335, 337, 375, 377 and through holes 340, 341, 380, 381 by photolithography and etching. The following description of the formation of the interlayer insulating layer for covering the first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 and the pixel electrode is omitted here.

[0141] like Figure 7C As shown in , when the second oxide semiconductor film 333 is formed, the first oxide semiconductor film 373 is covered by the second insulating layer 318. Therefore, the first oxide semiconductor film 373 is not affected by the formation and patterning of the second oxide semiconductor film 333. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 373 and the second oxide semiconductor film 333.

[0142] Example 4

[0143] TFT substrate structure

[0144] Hereinafter, still another configuration example of a TFT substrate and a method of manufacturing the TFT substrate are described. Figure 8 Schematically shows a cross section of another configuration example of a TFT substrate 400 for a liquid crystal display panel. Figure 2 The difference between the construction examples shown in .

[0145] The TFT substrate 400 includes a first oxide semiconductor TFT 130 in the peripheral circuit region 110 and a second oxide semiconductor TFT 470 in the display region 450. The first oxide semiconductor TFT 130 is configured similarly to the first oxide semiconductor TFT 130. Figure 2 The same construction as in . Figure 2 In the illustrated configuration example, the second oxide semiconductor TFT 470 is different from the second oxide semiconductor TFT 170 in the shapes of a second oxide semiconductor film 473 , a gate insulating film 472 , and source / drain electrodes 475 , 477 .

[0146] The second insulating layer 419 disposed over and in contact with the first insulating layer 117 has an opening; a portion of the second oxide semiconductor film 473 is disposed in the opening. The second oxide semiconductor film 473 is in contact with the first insulating layer 117 within the opening of the second insulating layer 419. A portion of the second oxide semiconductor film 473 including an end portion thereof is located over the second insulating layer 419. As can be seen from this description, the second oxide semiconductor film 473 is partially located over and in contact with the second insulating layer 419, and is partially located over and in contact with the first insulating layer 117.

[0147] The first insulating layer 117 is the lowermost insulating layer among the insulating layers located below and in contact with the second oxide semiconductor film 473. The second insulating layer 419 is the uppermost insulating layer among the insulating layers located below and in contact with the second oxide semiconductor film 473.

[0148] The gate insulating film 472 has a single-layer structure and is a part of the first insulating layer 117. Thinning the gate insulating film 472 enhances the driving capability of the second oxide semiconductor TFT 470. Each source / drain 475 and 477 is in contact with a portion of the second oxide semiconductor film 473 on the second insulating layer 419 and a portion of the second oxide semiconductor film 473 in the opening. This contact structure realizes low contact resistance between the second oxide semiconductor film 473 and the source / drain 475, 477.

[0149] Method for manufacturing TFT substrate

[0150] Describes Figure 8 An example of a method for manufacturing a TFT substrate 400 is shown in FIG. Figure 3A and 3B After the steps described above, Fig. 9A As shown, the method forms the second insulating layer 419 by CVD to cover the first oxide semiconductor film 133 .

[0151] Next, if Fig. 9B As shown in FIG. 1 , the method opens an opening 420 in the second insulating layer 419 by photolithography and etching. The top surface of the first insulating layer 117 is exposed in the opening 420. Next, as shown in FIG. Fig. 9C As shown in , the method forms an oxide semiconductor layer (second oxide semiconductor layer) including a second oxide semiconductor film 473 on the second insulating layer 419. Specifically, the method forms the oxide semiconductor layer by sputtering, and patterns the oxide semiconductor layer by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed. A portion of the second oxide semiconductor film 473 is located in the opening 420 of the second insulating layer 419, and another portion including its end portion is located above and in contact with the second insulating layer 419.

[0152] Next, if Fig.9D As shown in , the method opens an opening 421 in the second insulating layer 419 by photolithography and etching. The opening 421 is formed to expose the top surface of the first oxide semiconductor film 133 in the opening. In this example, the end surface of the first oxide semiconductor film 133 is not exposed in the opening 421, but can be exposed.

[0153] Next, if Fig.9E As shown in , the method forms a metal layer (source / drain layer) 440 including source / drain electrodes 135, 137, 475, and 477 by sputtering. The metal layer 440 covers the second insulating layer 419, the first oxide semiconductor film 133, and the second oxide semiconductor film 473. The metal layer 440 fills the opening 421 in the second insulating layer 419 and contacts the top surface of the first oxide semiconductor film 133. Next, as Fig.9F As shown in FIG. 4 , the method patterns the metal layer 440 by photolithography and etching to form source / drain electrodes 135 , 137 , 475 , and 477 .

[0154] Next, if Figure 9G As shown, the method forms an interlayer insulating layer 121 by CVD to cover the source / drain electrodes 135, 137, 475, 477, the first oxide semiconductor film 133, the second oxide semiconductor film 473 and the second insulating layer 419, and further opens a via hole in the interlayer insulating layer 121 by photolithography and etching to expose a portion of the top surface of the source / drain electrode 477. In addition, the method forms a pixel electrode 181 on the interlayer insulating layer 121, and a through hole for connecting the pixel electrode 181 and the source / drain electrode 477 in the interlayer insulating layer 121. Specifically, the method forms an ITO film by sputtering, and patterns the ITO film by photolithography and etching.

[0155] like Fig. 9C As shown in FIG. 4 , when the second oxide semiconductor film 473 is formed, the first oxide semiconductor film 133 is covered by the second insulating layer 419. Therefore, the first oxide semiconductor film 133 is not affected by the formation and patterning of the second oxide semiconductor film 473. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 133 and the second oxide semiconductor film 473.

[0156] The first oxide semiconductor TFT may have a structure similar to the second oxide semiconductor TFT 470 together with or instead of the second oxide semiconductor TFT. For example, a third insulating layer having an opening may be provided between the first insulating layer and the second insulating layer. The first oxide semiconductor film of the first oxide semiconductor TFT is formed in such a manner that a portion is located above and in contact with the first insulating layer within the opening in the third insulating layer and another portion is located above and in contact with the third insulating layer outside the opening. The third insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the first oxide semiconductor film.

[0157] Example 5

[0158] TFT substrate structure

[0159] Hereinafter, still another configuration example of a TFT substrate and a method of manufacturing the TFT substrate are described. Fig.10 Schematically shows a cross section of another configuration example of a TFT substrate 500 for a liquid crystal display panel. Figure 2 The difference between the construction examples shown in .

[0160] The TFT substrate 500 includes a first oxide semiconductor TFT 130 in the peripheral circuit region 110 and a second oxide semiconductor TFT 570 in the display region 550. The first oxide semiconductor TFT 130 is configured similarly to the first oxide semiconductor TFT 130. Figure 2 The same construction as in . Figure 2 In the illustrated configuration example, the second oxide semiconductor TFT 570 is different from the second oxide semiconductor TFT 170 in the shapes of a second oxide semiconductor film 573 , a gate insulating film 572 , and source / drain electrodes 575 , 577 .

[0161] The second insulating layer 519 provided over and in contact with the first insulating layer 117 has an opening. The second oxide semiconductor film 573 is provided in the opening. The second oxide semiconductor film 573 is in contact with the first insulating layer 117 in the opening in the second insulating layer 519. An end of the second oxide semiconductor film 573 is away from an inner wall of the opening.

[0162] The gate insulating film 572 has a single-layer structure and is a part of the first insulating layer 117. Thinning the gate insulating film 572 enhances the driving capability of the second oxide semiconductor TFT 570. The source / drain electrodes 575 and 577 are in contact with a portion of the second oxide semiconductor film 573 including the end thereof. The source / drain electrodes 575 and 577 are in contact with the end surface and the top surface of the second oxide semiconductor film 573. This contact structure realizes low contact resistance between the second oxide semiconductor film 573 and the source / drain electrodes 575, 577.

[0163] Method for manufacturing TFT substrate

[0164] Describes Fig.10 An example of a method for manufacturing a TFT substrate 500 is shown in FIG. Figure 3A and 3B After the steps described above, Fig.11A As shown, the method forms the second insulating layer 519 by CVD to cover the first oxide semiconductor film 133 .

[0165] Next, if Fig. 11B As shown in FIG. 1 , the method opens an opening 520 in the second insulating layer 519 by photolithography and etching. The top surface of the first insulating layer 117 is exposed in the opening 520. Next, as shown in FIG. Fig. 11C As shown in , the method forms an oxide semiconductor layer (second oxide semiconductor layer) including a second oxide semiconductor film 573 on the second insulating layer 519. Specifically, the method forms the oxide semiconductor layer by sputtering, and patterns the oxide semiconductor layer by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed. The second oxide semiconductor film 573 is disposed above the first insulating layer 117 in the opening 520 of the second insulating layer 519 and in contact with it.

[0166] Next, if Fig.11D As shown in , the method opens an opening 521 in the second insulating layer 519 by photolithography and etching. The opening 521 is formed to expose the top surface of the first oxide semiconductor film 133 in the opening. In this example, the end surface of the first oxide semiconductor film 133 is not exposed in the opening 521, but can be exposed.

[0167] Next, if Fig.11E As shown in , the method forms a metal layer (source / drain layer) 540 including source / drain electrodes 135, 137, 575, and 577 by sputtering. The metal layer 540 covers the second insulating layer 519, the first oxide semiconductor film 133, and the second oxide semiconductor film 573. The metal layer 540 fills the opening 521 in the second insulating layer 519 and contacts the top surface of the first oxide semiconductor film 133. Next, as Fig.11F As shown in FIG. , the method patterns the metal layer 540 by photolithography and etching to form source / drain electrodes 135 , 137 , 575 , and 577 .

[0168] Next, if Fig.11GAs shown, the method forms an interlayer insulating layer 121 by CVD to cover the source / drain electrodes 135, 137, 575, 577, the first oxide semiconductor film 133, the second oxide semiconductor film 573 and the second insulating layer 519, and further opens a via hole in the interlayer insulating layer 121 by photolithography and etching to expose a portion of the top surface of the source / drain electrode 577. In addition, the method forms a pixel electrode 181 on the interlayer insulating layer 121, and a through hole for connecting the pixel electrode 181 and the source / drain electrode 577 in the interlayer insulating layer 121. Specifically, the method forms an ITO film by sputtering, and patterns the ITO film by photolithography and etching.

[0169] like Fig. 11C As shown in FIG. 5 , when the second oxide semiconductor film 573 is formed, the first oxide semiconductor film 133 is covered by the second insulating layer 519. Therefore, the first oxide semiconductor film 133 is not affected by the formation and patterning of the second oxide semiconductor film 573. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 133 and the second oxide semiconductor film 573.

[0170] Example 6

[0171] In the display area (pixel circuit), oxide semiconductor TFTs with wide band gap account for the majority (more than half) of TFTs to obtain high reliability. In the peripheral circuit, oxide semiconductor TFTs with high mobility account for the majority (more than half) of small circuit sizes. However, some oxide semiconductor TFTs in the display area may be oxide semiconductor TFTs with high mobility, and some oxide semiconductor TFTs in the peripheral circuit may be oxide semiconductor TFTs with wide band gap, depending on the characteristics required for a single oxide semiconductor TFT.

[0172] An oxide semiconductor TFT that is expected to mainly receive a negative gate bias (gate voltage) can achieve high reliability by adopting an oxide semiconductor TFT with a wide bandgap. In contrast, an oxide semiconductor TFT that is expected to mainly receive a positive gate bias can contribute to a small circuit size by adopting an oxide semiconductor TFT with high mobility.

[0173] The negative gate bias is supplied to the oxide semiconductor TFT that mainly receives the negative gate bias for a longer time than the positive gate bias is supplied during the operating time of the device. The negative gate bias turns off the oxide semiconductor TFT, while the positive gate bias turns on the oxide semiconductor TFT. Zero gate bias is neither a negative gate bias nor a positive gate bias.

[0174] If the TFT requires high driving capability, the TFT in the peripheral circuit achieves a small circuit size by adopting an oxide semiconductor TFT with high mobility; if such high driving capability is not required, the TFT in the peripheral circuit achieves high reliability by adopting an oxide semiconductor TFT with a wide bandgap.

[0175] In the peripheral circuit, the TFT or test TFT used for the electrostatic discharge protection element is a diode-connected TFT or a TFT with a floating gate used as a high resistance element. Such a TFT does not require a very high driving capability, and if the driving capability is too high, the TFT will interfere with the overall operation of the peripheral circuit. Therefore, an oxide semiconductor TFT with a wide bandgap can be used as an electrostatic discharge protection element or a test TFT.

[0176] Fig.12 An example of a first-stage circuit of a shift register is shown. The shift register includes transistors TR1 to TR9 and capacitors CA1 and CA2. Potential VGH is a high power supply potential, and potential VGL is a low power supply potential. Signal ST is a start pulse or an output of a previous stage. Signal OUT1 is an output. Signal OUT2 is a feedback signal from a next stage. Signal RST is a reset signal. Signal CK is a clock signal and signal XCK is an inverted clock signal.

[0177] exist Fig.12 In the circuit shown, transistor TR1 is a transistor that mainly receives a negative gate bias. Therefore, transistor TR1 can have high reliability by adopting an oxide semiconductor TFT with a wide band gap. On the other hand, transistors TR2 to TR9 are transistors that mainly receive a negative gate bias. Therefore, by using an oxide semiconductor TFT with high mobility for these transistors TR2 to TR9, a smaller circuit size can be achieved. In particular, transistor TR6 is a drive transistor and a data line for output to the next stage; using an oxide semiconductor TFT with high mobility for transistor TR6 effectively contributes to reducing the size of the circuit.

[0178] Fig.13 An example of a pixel circuit for an OLED display device is shown. The pixel circuit controls the current supplied to the anode of the OLED element E1. The pixel circuit includes a drive transistor T1, a select transistor T2, a control transistor T3 and a storage capacitor C1. The pixel circuit controls the light emission of the OLED element E1. Fig.13 The transistors T1 to T3 in the example are n-channel oxide semiconductor TFTs.

[0179] The selection transistor T2 is a switch for selecting a pixel. The gate terminal of the selection transistor T2 receives the scanning signal S1. One of its source / drain terminals is connected to the data line 15. The other source / drain terminal is connected to the gate terminal of the driving transistor T1.

[0180] The driving transistor T1 is a transistor for driving the OLED element E1. The gate terminal of the driving transistor T1 is connected to the source / drain terminal of the selection transistor T2. One of the source / drain terminals of the driving transistor T1 is connected to the power line (Vdd) 18. The other source / drain terminal is connected to the source terminal of the control transistor T3. The storage capacitor C1 is provided between the gate terminal and the source / drain terminal of the driving transistor T1.

[0181] When the selection transistor T2 is turned on, the data voltage supplied through the data line 15 is stored in the storage capacitor C1. During the period of one frame, the storage capacitor C1 holds the stored voltage. The conductivity of the driving transistor T1 changes in an analog manner according to the stored voltage, so that the driving transistor T1 supplies a forward bias current corresponding to the light emission level to the OLED element E1.

[0182] The control transistor T3 controls the electrical connection between the reference voltage supply line 11 for supplying the reference voltage Vref and the anode of the OLED element E1. The control signal S2 is supplied to the gate terminal of the control transistor T3 for this control. The control transistor T3 can be used for various purposes. The control transistor T3 can be used to reset the anode of the OLED element E1 once so that it has a sufficiently low voltage below the black signal level to prevent leakage current from causing crosstalk between the OLED elements E1.

[0183] The control transistor T3 can also be used to measure the characteristics of the drive transistor T1. For example, under selected bias conditions, by measuring the current flowing from the power supply line 18 to the reference voltage supply line 11, the voltage-current characteristics of the drive transistor T1 can be accurately measured so that the drive transistor T1 operates in the saturation region and the control transistor T3 operates in the linear region. If the difference in the voltage-current characteristics between the drive transistors T1 for a single pixel is compensated by generating a data signal at an external circuit, a highly uniform display image can be obtained.

[0184] Meanwhile, when the driving transistor T1 is turned off and the control transistor T3 operates in the linear region, the voltage-current characteristic of the OLED element E1 can be accurately measured by applying a voltage to light up the OLED element E1 from the reference voltage supply line 11. In the case where the OLED element E1 is degraded due to long-term use, for example, if the degradation is compensated by generating a data signal at an external circuit, the display device can have a long life.

[0185] exist Fig.13In the pixel circuit of , transistors T2 and T3 use oxide semiconductor TFTs with wide band gap. These transistors are mainly supplied by negative gate bias and show high reliability. On the other hand, the driving transistor T1 uses an oxide semiconductor TFT with high mobility. The driving transistor T1 is mainly supplied by positive gate bias and helps to reduce the transistor size. In the liquid crystal display panel, the switching TFT for controlling the signal input to the pixel electrode uses an oxide semiconductor TFT with a wide band gap. The switching TFT is mainly supplied by negative gate bias and shows high reliability.

[0186] As described above, the display device achieves high reliability and a narrow frame by appropriately selecting between an oxide semiconductor TFT having a wide bandgap and an oxide semiconductor TFT having high mobility.

[0187] Example 7

[0188] TFT substrate structure

[0189] Hereinafter, still another configuration example of the TFT substrate is described. Fig.14 Schematically shows a cross section of another configuration example of a TFT substrate 600 for a liquid crystal display panel. Figure 2 The difference between the construction examples shown in .

[0190] The TFT substrate 600 includes a first oxide semiconductor TFT 130 and a capacitor CA10 in the peripheral circuit region 110 and a second oxide semiconductor TFT 170 in the display region 150. The first oxide semiconductor TFT 130 and the second oxide semiconductor TFT 170 have the same Figure 2 The same construction as the corresponding construction shown in Figure 2 The difference is the addition of capacitor CA 10.

[0191] The capacitor CA10 is constituted by a gate electrode 131, a first insulating layer 117 provided over the gate electrode 131, and a first oxide semiconductor film 133 provided over the first insulating layer 117. The first oxide semiconductor film 133 is in contact with a source / drain electrode 137 in an opening provided in the second insulating layer 119.

[0192] The first insulating layer 117 is a gate insulating film of the first oxide semiconductor TFT 130. The gate insulating film is thinner than the gate insulating film of the second oxide semiconductor TFT 170 stacked by the first insulating layer 117 and the second insulating layer 119, and therefore, it can have a larger capacitance. Therefore, the area of ​​the capacitor CA 10 can be made smaller.

[0193] Fig.14 The TFT substrate 600 shown can be connected with Figures 3A to 3H The same steps as shown in the figure are used for manufacturing, and therefore, the description of the manufacturing method is omitted here.

[0194] Example 8

[0195] TFT substrate structure

[0196] Hereinafter, still another configuration example of the TFT substrate is described. Fig.15 Schematically shows a cross section of another configuration example of a TFT substrate 700 for a liquid crystal display panel. Figure 6 The difference between the construction examples shown in .

[0197] The TFT substrate 700 includes the second oxide semiconductor TFT 330 and the capacitor CA20 in the peripheral circuit region 310 and the first oxide semiconductor TFT 370 in the display region 350. The first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 have the same Figure 6 The same construction as the corresponding construction shown in Figure 6 The difference is the addition of capacitor CA 20.

[0198] The capacitor CA 20 is composed of a first oxide semiconductor film 342 provided over the first insulating layer 315, an insulating film 317 which is a part of the second insulating layer, and a second oxide semiconductor film 343 provided over the insulating film 317. The first oxide semiconductor film 342 is made of the same material as the first oxide semiconductor film 373, and reduces resistance like the source / drain regions 374 and 376 to become one electrode of the capacitor CA 20. The second oxide semiconductor film 343 is made of the same material as the second oxide semiconductor film 333, and reduces resistance like the source / drain regions 334 and 336 to become the other electrode of the capacitor CA 20. In addition, the first oxide semiconductor film 342 is connected to the capacitor line 345 via the through hole 344, and the second oxide semiconductor film 343 is connected to the capacitor line 347 via the through hole 346.

[0199] The insulating film 317 is thinner than the gate insulating film 339 of the second oxide semiconductor TFT 330. As a result, the capacitor CA 20 can have a thin insulating film, and thus, the capacitor CA 20 can store more charge, compared with the case where a stack of the lower gate insulating film 378 and the upper gate insulating film 379 is used as the gate insulating film of the first oxide semiconductor TFT 370 or the case where the gate insulating film 339 of the second oxide semiconductor TFT 330 is used. Therefore, the area of ​​the capacitor CA 20 can be made smaller.

[0200] Method for manufacturing TFT substrate

[0201] Describes Fig.15 An example of a method for manufacturing a TFT substrate 700 is shown in FIG. Fig.16A As shown in the method of manufacturing the TFT substrate 700, a first insulating layer 315 of a base layer is formed on an insulating substrate 313 by CVD. Next, the method forms an oxide semiconductor layer (first oxide semiconductor layer) including a first oxide semiconductor film 373 on the first insulating layer 315. Specifically, the method forms an oxide semiconductor film by sputtering, and patterns the oxide semiconductor film by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0202] Next, the method forms a resist pattern 799 by photolithography to cover a region other than the first oxide semiconductor film 373, wherein a resist pattern 799 is provided as shown in FIG. Fig. 16B The capacitor shown is formed, and the substrate is further exposed to He plasma to reduce the resistance of the first oxide semiconductor film 373. As a result, the first oxide semiconductor film 342 is prepared as an electrode of the capacitor CA20.

[0203] After removing the resist pattern 799, as Fig. 16C As shown, the method forms the second insulating layer 318 by CVD to cover the layer including the first oxide semiconductor films 373 and 342. The second insulating layer 318 includes Fig.15 The insulating films 317 and 378 in FIG.

[0204] Next, if Fig.16D As shown in , the method forms an oxide semiconductor layer (second oxide semiconductor layer) including a second oxide semiconductor film 333 on the second insulating layer 318. Specifically, the method forms an oxide semiconductor film by sputtering, and patterns the oxide semiconductor film by photolithography and etching. As a result, a pattern of the oxide semiconductor film is formed.

[0205] Next, if Fig.16E As shown in FIG. 1 , the method forms a third insulating layer 319 by CVD to cover the second oxide semiconductor film 333 and the second insulating layer 318. The third insulating layer 319 includes Fig.15 Insulating films 339 and 379 are formed in the third insulating layer 319. In addition, the method forms a metal layer (gate layer) 320 including gate electrodes 331 and 371 on the third insulating layer 319 by sputtering.

[0206] Next, if Fig.16F As shown, the method etches the second insulating layer 318, the third insulating layer 319 and the gate layer 320 together to prepare insulating films 339, 317, insulating films 379, 378 and gates 331, 371. Next, as Figure 16GAs shown, by exposing these portions to He plasma, the method reduces the resistance of the portion not covered by the gate insulating film 339 in the second oxide semiconductor film 333 and the portion not covered by the gate insulating film 378 in the first oxide semiconductor film 373. As a result, the source / drain regions 334, 336, 374, 376 and the second oxide semiconductor film 343 serving as the other electrode of the capacitor CA20 are prepared.

[0207] Next, if Fig.16H As shown, the method forms an interlayer insulating layer 321 by CVD to cover the constituent elements of the prepared first oxide semiconductor TFT 370 , the constituent elements of the prepared second oxide semiconductor TFT 330 , the constituent elements of the prepared capacitor CA20 , and the first insulating layer 315 .

[0208] Next, if Fig.16I As shown, the method opens a through hole in the interlayer insulating layer 321 by photolithography and etching, and further prepares source / drain electrodes 335, 337, 375, 377, capacitor lines 345, 347 and vias 340, 341, 380, 381, 344, 346. Specifically, the method forms a metal layer on the interlayer insulating layer 321 (including the through hole) by sputtering, and forms source / drain electrodes 335, 337, 375, 377, capacitor lines 345, 347 and vias 340, 341, 380, 381, 344, 345 by photolithography and etching. The following description of the formation of the interlayer insulating layer for covering the first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 and the pixel electrode is omitted here.

[0209] like Fig.16D As shown in , when the second oxide semiconductor film 333 is formed, the first oxide semiconductor film 373 is covered by the second insulating layer 318. Therefore, the first oxide semiconductor film 373 is not affected by the formation and patterning of the second oxide semiconductor film 333. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 373 and the second oxide semiconductor film 333.

[0210] Example 9

[0211] TFT substrate structure

[0212] Hereinafter, still another configuration example of the TFT substrate is described. Fig.17 A cross section schematically shows a configuration example of a pixel region of a TFT substrate 800 used for a top emission type OLED display device.

[0213] The TFT substrate 800 includes a driving TFT for supplying current to the OLED, a storage capacitor CA 30, and a switching TFT for sending a signal to the driving TFT. The switching TFT corresponds to Fig.17 The first oxide semiconductor TFT 370 is a first oxide semiconductor TFT 370 in the embodiment, and the driving TFT corresponds to the second oxide semiconductor TFT 330. The first oxide semiconductor TFT 370 and the second oxide semiconductor TFT 330 have Figure 6 The same construction as the corresponding construction shown in .

[0214] The capacitor CA 30 is composed of a portion of a first oxide semiconductor film 373 formed over the first insulating layer 315, an insulating film 317 which is a portion of a second insulating layer formed over the first oxide semiconductor film 373, and a portion of a second oxide semiconductor film 333 formed over the insulating film 317. The portion of the first oxide semiconductor film 373 included in the capacitor CA 30 is an extension of the source / drain region 374 of the first oxide semiconductor TFT 370. The portion of the second oxide semiconductor film 333 included in the capacitor CA 30 is an extension of the source / drain region 336 of the second oxide semiconductor TFT 330.

[0215] The insulating film 317 is thinner than the gate insulating film 339 of the second oxide semiconductor TFT 330. As a result, the capacitor CA 30 can have a thin insulating film, and thus, the capacitor CA 30 can store more charge, compared with the case where a stack of the lower gate insulating film 378 and the upper gate insulating film 379 is used as the gate insulating film of the first oxide semiconductor TFT 370 or the case where the gate insulating film 339 of the second oxide semiconductor TFT 330 is used. Therefore, the area of ​​the capacitor CA 30 can be made smaller.

[0216] The gate electrode 331 of the second oxide semiconductor TFT 330 is connected to the gate line 391 via the through hole 390. Fig.17 Although not shown in the figure, the gate line 391 is connected to the source / drain electrodes 375 of the first oxide semiconductor TFT 370.

[0217] A planarization film 392 is provided above the source / drain 335, 337, 375, 377, the gate 391 and the interlayer insulating film 321. The planarization film 392 can be formed by applying an organic material having good smoothing properties (e.g., acrylic or polyimide). An anode 394 is provided above the planarization film 392. The anode 394 is connected to the source / drain 337 of the second oxide semiconductor TFT 330 through a through hole 393 provided in the planarization film 392. The anode 394 can be a stack of an ITO film and a metal film having high reflectivity (e.g., aluminum or silver). A pixel definition layer 395 is provided above the anode 394. The pixel definition layer 395 can be made of an organic material such as acrylic or polyimide.

[0218] Fig.17 The method of manufacturing the TFT substrate 800 shown may be Figures 16A to 16I The constituent elements of the first oxide semiconductor TFT 370, the constituent elements of the second oxide semiconductor TFT 330, the constituent elements of the capacitor CA 30, and the interlayer insulating film 321 are prepared by the following same steps as shown in FIG. The following formation of the planarizing film 392 and subsequent processing can be performed by known film forming technology, photolithography technology, and etching technology, and therefore, a detailed description is omitted here.

[0219] like Fig.16D As shown in , when the second oxide semiconductor film 333 is formed, the first oxide semiconductor film 373 is covered by the second insulating layer 318. Therefore, the first oxide semiconductor film 373 is not affected by the formation and patterning of the second oxide semiconductor film 333. Therefore, an ideal oxide semiconductor material can be used for the first oxide semiconductor film 373 and the second oxide semiconductor film 333.

[0220] As explained above, the embodiments of the present disclosure are described; however, the present disclosure is not limited to the aforementioned embodiments. Those skilled in the art can easily modify, add or change each element in the aforementioned embodiments within the scope of the present disclosure. A part of the construction of one embodiment can be replaced with the construction of another embodiment, or the construction of one embodiment can be incorporated into the construction of another embodiment.

Claims

1. A thin film transistor substrate, comprising: Insulating substrate; A first insulating layer, disposed on the insulating substrate; a first thin film transistor provided on the insulating substrate and including a first oxide semiconductor film and included in a peripheral circuit region; a second insulating layer, disposed on the insulating substrate and located above the first insulating layer; as well as a second thin film transistor, which is disposed on the insulating substrate and includes a second oxide semiconductor film having a different composition from that of the first oxide semiconductor film and is included in a pixel circuit in a display region; wherein at least a portion of the first oxide semiconductor film is disposed above and in contact with the first insulating layer, The first insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the first oxide semiconductor film, wherein at least a portion of the second oxide semiconductor film is disposed above and in contact with the second insulating layer, and The second insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the second oxide semiconductor film, The first oxide semiconductor film has higher mobility than the second oxide semiconductor film, and the second oxide semiconductor film has a wider band gap than the first oxide semiconductor film.

2. The thin film transistor substrate according to claim 1, in, Either one of the first thin film transistor and the second thin film transistor is provided with a negative gate bias, and The other of the first thin film transistor and the second thin film transistor is provided with a positive gate bias.

3. The thin film transistor substrate according to claim 1, in, The entirety of the first oxide semiconductor film is provided above and in contact with the first insulating layer, and The entire second oxide semiconductor film is disposed above and in contact with the second insulating layer.

4. The thin film transistor substrate according to claim 1, in, A portion of the first insulating layer is included in a gate insulating film of the first thin film transistor, and Part of the first insulating layer and part of the second insulating layer are included in a gate insulating film of the second thin film transistor.

5. The thin film transistor substrate according to claim 1, in, One of the thin film transistors is a switching thin film transistor, and Another one of the thin film transistors is an output drive transistor in the shift register.

6. The thin film transistor substrate according to claim 1, in, One of the thin film transistors is a driving thin film transistor configured to control a current to a light emitting element in the pixel circuit, and Among them, another one of the thin film transistors is an electrostatic discharge protection element.

7. The thin film transistor substrate according to claim 1, in, One of the thin film transistors is a driving thin film transistor configured to control a current to a light emitting element in the pixel circuit, wherein another of the thin film transistors is included in a shift register, wherein a power supply potential is applied to a source / drain of another one of the thin film transistors, and Among them, the output of the previous stage is input to the gate of another one of the thin film transistors. 8 . The thin film transistor substrate according to claim 1 , wherein at least one of the first oxide semiconductor film and the second oxide semiconductor film includes a portion of an electrode of a capacitor. 9 . The thin film transistor substrate according to claim 8 , wherein a portion of the electrode of the capacitor is an extension portion from a first oxide semiconductor film of the first thin film transistor. 10 . The thin film transistor substrate according to claim 8 , wherein a portion of an electrode of the capacitor is an extension portion from a second oxide semiconductor film of the second thin film transistor. 11 . The thin film transistor substrate according to claim 1 , wherein a portion of the first oxide semiconductor film, a portion of the second oxide semiconductor film, and a portion of the second insulating layer constitute a capacitor.

12. A thin film transistor substrate, comprising: Insulating substrate; A first insulating layer, disposed on the insulating substrate; a first thin film transistor provided on the insulating substrate and including a first oxide semiconductor film; a second insulating layer, disposed on the insulating substrate and located above the first insulating layer; as well as a second thin film transistor provided on the insulating substrate and including a second oxide semiconductor film having a composition different from that of the first oxide semiconductor film, wherein at least a portion of the first oxide semiconductor film is disposed above and in contact with the first insulating layer, The first insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the first oxide semiconductor film, wherein at least a portion of the second oxide semiconductor film is disposed above and in contact with the second insulating layer, and wherein the second insulating layer is the uppermost insulating layer among the insulating layers located below and in contact with the second oxide semiconductor film, wherein the thin film transistor substrate is a component of a display device, The first thin film transistor and the second thin film transistor are included in a peripheral circuit outside a display area, wherein a channel region of the oxide semiconductor film of the first thin film transistor has a wider band gap than a channel region of the oxide semiconductor film of the second thin film transistor, and The channel region of the oxide semiconductor film of the first thin film transistor has lower mobility than the channel region of the oxide semiconductor film of the second thin film transistor.

13. The thin film transistor substrate according to claim 12, in, The first thin film transistor is an electrostatic discharge protection element, and The second thin film transistor is an output drive transistor in a shift register.

14. A method for manufacturing a thin film transistor substrate according to claim 1 or 12, the method comprising: forming a first insulating layer on an insulating substrate; forming a first oxide semiconductor layer including a channel region of a first thin film transistor after forming the first insulating layer; forming a second insulating layer to cover the first oxide semiconductor layer; and A second oxide semiconductor film including a channel region of a second thin film transistor is formed in a state where the first oxide semiconductor layer is covered with the second insulating layer.

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