Integrated chip and method for forming the same

Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a gate structure disposed above a substrate and between a source region and a drain region. A first interlayer dielectric (ILD) layer is disposed above the substrate and the gate structure, and a second interlayer dielectric layer is disposed above the first interlayer dielectric layer. A field plate etch stop structure is between the first interlayer dielectric layer and the second interlayer dielectric layer. A field plate extends from an uppermost surface of the second interlayer dielectric layer to the field plate etch stop structure. A plurality of conductive contacts extend from an uppermost surface of the second interlayer dielectric layer to the source region and the drain region.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated chip and a method for forming the same. Background Art

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Integrated chips (ICs) may use many different types of transistor devices depending on the application of the IC. In recent years, the increase in the market for mobile and RF (radio frequency) devices has caused a significant increase in the use of high voltage transistor devices. For example, power amplifiers in RF transmission / reception chains often use high voltage transistor devices because they can handle high breakdown voltages (e.g., breakdown voltages greater than about 50 volts) and high frequencies. Summary of the invention

[0003] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: a gate structure disposed above a substrate and between a source region and a drain region; a first interlayer dielectric (ILD) layer disposed above the substrate and the gate structure; a second ILD layer disposed above the first ILD layer; a field plate etch stop structure between the first ILD layer and the second ILD layer; a field plate extending from the uppermost surface of the second ILD layer to the field plate etch stop structure; and a plurality of conductive contacts extending from the uppermost surface of the second ILD layer to the source region and the drain region.

[0004] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: a gate structure disposed above a substrate between a source region and a drain region; a dielectric structure disposed above the substrate and the gate structure; a field plate etch stop structure disposed within the dielectric structure; a plurality of conductive contacts disposed within the dielectric structure; and a field plate disposed on the field plate etch stop structure, the field plate having a bottommost surface arranged along a first horizontal plane parallel to an upper surface of the substrate and intersecting sidewalls of the plurality of conductive contacts between top and bottom surfaces of the plurality of conductive contacts.

[0005] In yet other embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes: forming a gate structure between a source region and a drain region over a substrate; forming a contact etch stop layer over the substrate; forming a first ILD layer over the contact etch stop layer; forming a field plate etch stop structure between the gate structure and the drain region after forming the first ILD layer; forming a second ILD layer over the field plate etch stop structure; and simultaneously forming a plurality of contacts extending through the first ILD layer and the second ILD layer and a field plate extending through the second ILD layer to the field plate etch stop structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of the disclosed high voltage transistor devices having field plates are shown.

[0008] Figures 2 to 4 Cross-sectional views of some additional embodiments of the disclosed high voltage laterally diffused MOSFET (LDMOS) device with a field plate are shown.

[0009] Figure 5 to Figure 6 Cross-sectional views of some embodiments of field plate biasing configurations for high voltage LDMOS devices implemented by metal interconnect routing are shown.

[0010] FIG. 7A to FIG. 7C Cross-sectional views of some embodiments of high voltage LDMOS devices in different switched isolation configurations are shown.

[0011] Figure 8 A cross-sectional view of a source downward high voltage transistor device with a field plate is shown.

[0012] FIG. 9A to FIG. 9B Some embodiments of the disclosed high voltage LDMOS with a field plate on the metal line layer are shown.

[0013] Fig.10 Some embodiments of high voltage LDMOS devices with self-aligned drift regions are shown.

[0014] Fig.11 A flow chart illustrating some embodiments of a method of forming a high voltage transistor device having a field plate.

[0015] Figures 12 to 19 Cross-sectional views illustrating some embodiments of a method of forming a high voltage transistor device having a field plate are shown.

[0016] Figure 20 to Figure 24 Some embodiments of the disclosed high voltage transistor device having a composite etch stop layer defining a field plate are shown.

[0017] Figure 25 to Figure 32 Cross-sectional views illustrating some embodiments of a method of forming a high voltage transistor device having a composite etch stop layer defining a field plate are shown.

[0018] Fig.33 A flow chart illustrating some embodiments of a method of forming a high voltage transistor device having a composite etch stop layer defining a field plate.

[0019] Figure 34 to Figure 39 Cross-sectional views of some embodiments of the disclosed high voltage transistor device having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact are shown.

[0020] Figures 40 to 50 Cross-sectional views are shown depicting some embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact.

[0021] Figure 51 to Figure 65 Cross-sectional views are shown depicting some additional embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact.

[0022] Figure 66 to Figure 76 Cross-sectional views are shown depicting some additional embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact.

[0023] Fig.77 A flow chart illustrating some embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these components and arrangements are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted to form or be arranged, and may also include an embodiment in which an additional feature may be formed or arranged between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] High voltage transistor devices are typically configured with a field plate. A field plate is a conductive element placed above a channel region to improve the performance of a high voltage transistor device by manipulating the electric field generated by a gate electrode (e.g., reducing the peak electric field). By manipulating the electric field generated by the gate electrode, a high voltage transistor device can achieve a higher breakdown voltage. For example, a laterally diffused metal oxide semiconductor (LDMOS) transistor device typically includes a field plate extending from a channel region to an adjacent drift region disposed between the channel region and a drain region.

[0027] The field plate can be formed in a number of different ways. For example, it can be formed by extending from the gate electrode toward the drift region through a conductive gate material (e.g., polysilicon). However, in this type of configuration, the field plate is synchronized with the gate bias, which gives the gate-drain capacitance (C gd ) burden and deteriorate device switching losses. Alternatively, the conductive gate material can be patterned to form separate field plates. This type of configuration reduces the gate-drain capacitance (C gd ), but the placement of the field plate is often limited by design rules. In yet another alternative, non-gate materials can be used for field plate formation. However, such solutions use additional processing steps, increasing the manufacturing cost of the resulting integrated chip.

[0028] Thus, the present disclosure relates to a high voltage transistor device having a field plate made of a non-gate material, the high voltage transistor device being formed simultaneously with the formation of a back-end-of-the-line (BEOL) metal layer to achieve a low-cost manufacturing method. In some embodiments, the high voltage transistor device has a gate electrode disposed above a substrate, between a source region and a drain region positioned within the substrate. A dielectric layer extends laterally from above the gate electrode to a drift region disposed between the gate electrode and the drain region. The field plate is located within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends laterally from above the gate electrode to above the drift region and vertically from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts having the same material as the field plate extend vertically from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

[0029] Figure 1 A cross-sectional view of some embodiments of a high voltage transistor device 100 having a field plate 122 is shown.

[0030] The high voltage transistor device 100 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 have a second doping type with a higher doping concentration than the semiconductor substrate 102. In some embodiments, the first doping type may be p-type doping and the second doping type may be n-type doping.

[0031] The gate structure 116 is disposed above the semiconductor substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. When receiving a bias voltage, the gate electrode 108 is configured to generate an electric field that controls the movement of charge carriers within a channel region 112 that is laterally disposed between the source region 104 and the drain region 106. For example, during operation, a gate-source voltage (V GS ) can be selectively applied to the gate electrode 108 associated with the source region 104 to form a conductive channel in the channel region 112. GS To form a conductive channel, but the drain-source voltage (drain to source voltage; V DS ) is applied to move charge carriers between the source region 104 and the drain region 106 (eg, as indicated by arrows 105 ).

[0032] The channel region 112 extends laterally from the source region 104 to an adjacent drift region 114 (i.e., a drain extension region). The drift region 114 includes a second doping type having a relatively low doping concentration, which provides a higher resistance at high operating voltages. A gate structure 116 is disposed above the channel region 112. In some embodiments, the gate structure 116 may extend from above the channel region 112 to a position overlying a portion of the drift region 114.

[0033] A first interlayer dielectric (ILD) layer 118 is disposed over the semiconductor substrate 102. One or more conductive metal structures are disposed within the first ILD layer 118. In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 configured to provide vertical connections between the source region 104, the drain region 106, or the gate electrode 108 and a first back-end of line (BEOL) metal line layer 128 disposed within a second ILD layer 126 overlying the first ILD layer 118.

[0034] The one or more conductive metal structures may also include a field plate 122 disposed within the first ILD layer 118 at a position overlying portions of the gate electrode 108 and the drift region 114. The field plate 122 includes the same conductive material as the plurality of contacts 120. The field plate 122 may be disposed over a dielectric layer 124 configured to separate the field plate 122, the drift region 114, and the gate electrode 108. In some embodiments, the dielectric layer 124 extends laterally beyond the field plate 122 in one or more directions.

[0035] During operation, the field plate 122 is configured to act on the electric field generated by the gate electrode 108. The field plate 122 may be configured to change the distribution of the electric field generated by the gate electrode 108 in the drift region 114, which enhances the internal electric field of the drift region 114 and increases the offset doping concentration of the drift region 114, thereby enhancing the breakdown voltage capability of the high voltage transistor device 100.

[0036] Figure 2 Cross-sectional views of some additional embodiments of the disclosed high voltage transistor devices including a high voltage laterally diffused MOSFET (LDMOS) device 200 having a field plate 214 are shown.

[0037] LDMOS device 200 includes a source region 104 and a drain region 106 disposed within a semiconductor substrate 102. Semiconductor substrate 102 has a first doping, and source region 104 and drain region 106 include highly doped regions having a second doping type different from the first doping type. In some embodiments, the first doping type may be an n-type doping and the second doping type may be a p-type doping. In some embodiments, source region 104 and drain region 106 may have a doping range between about 10 19 cm -3 With about 1020 cm -3 The doping concentration is within the range of .

[0038] A contact region 208 (e.g., a "p-type contact" (p-tap) or an "n-type contact" (n-tap)) having a first doping type (e.g., p+ doping) laterally adjoins the source region 104. The contact region 208 provides an ohmic connection to the semiconductor substrate 102. In some embodiments, the contact region 208 may have a thickness between about 10 18 cm -3 With about 10 20 cm -3 The contact region 208 and the source region 104 are disposed in the body region 202. The body region 202 has a first doping type with a doping concentration higher than that of the semiconductor substrate 102. For example, the semiconductor substrate 102 may have a doping concentration between about 10 14 cm -3 With about 10 16 cm -3 The doping concentration of the main region 202 may be between about 10 16 cm -3 With about 10 18 cm -3 The doping concentration is within the range of .

[0039] The drain region 106 is disposed in a drift region 204 disposed in the semiconductor substrate 102 at a position laterally adjacent to the body region 202. The drift region 204 includes a second doping type having a relatively low doping concentration, which provides a higher resistance when the LDMOS device 200 operates at a high operating voltage. In some embodiments, the drift region 204 may have a voltage between about 10 V and about 20 V. 15 cm -3 With about 10 17 cm -3 The doping concentration is within the range of .

[0040] The gate structure 210 is disposed above the semiconductor substrate 102 at a position laterally arranged between the source region 104 and the drain region 106. In some embodiments, the gate structure 210 may extend from above the body region 202 to a position overlying a portion of the drift region 204. The gate structure 210 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may include silicon dioxide (SiO2) or a high-k gate dielectric material, and the gate electrode 108 may include polysilicon or a metal gate material (e.g., aluminum). In some embodiments, the gate structure 210 may also include sidewall spacers 212 disposed on opposite sides of the gate electrode 108. In various embodiments, the sidewall spacers 212 may include nitride-based sidewall spacers (e.g., including SiN) or oxide-based sidewall spacers (e.g., SiO2, SiOC, etc.).

[0041] One or more dielectric layers 124 are disposed over the gate electrode 108 and the drift region 204. In some embodiments, the one or more dielectric layers 124 extend continuously from over a portion of the gate electrode 108 to over a portion of the drift region 204. In some embodiments, the one or more dielectric layers 124 may be conformally disposed over the drift region 204, the gate electrode 108, and the sidewall spacers 212.

[0042] The field plate 214 is disposed above the one or more dielectric layers 124 and is laterally surrounded by the first ILD layer 118. The field plate 214 extends from above the gate electrode 108 to above the drift region 204. The size of the field plate 214 may vary depending on the size and characteristics of the LDMOS device 200. In some embodiments, the field plate 214 may have a size between about 50 nanometers and about 1 micron. In other embodiments, the field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may include a dielectric material having a relatively low dielectric constant (e.g., less than or equal to about 3.9), which provides electrical isolation between the plurality of contacts 120 and / or the field plates 122. In some embodiments, the first ILD layer 118 may include an ultra-low-k dielectric material or a low-k dielectric material (e.g., SiCO).

[0043] The field plate 214 extends vertically from the dielectric layer 124 to the top surface of the first ILD layer 118. In some embodiments, the field plate 214 may extend vertically to a height greater than or equal to the height of the top surface of the contact 120 and the first ILD layer 118. The field plate 122 has a non-flat surface adjacent to one or more dielectric layers 124. The non-flat surface causes the field plate 122 to have a first thickness t1 in a region above the gate electrode 108 and a second thickness t2 greater than the first thickness t1 in a region overlying the drift region 204.

[0044] The plurality of contacts 120 are also surrounded by the first ILD layer 118. The plurality of contacts 120 may include a first contact 120a coupled to the contact region 208, a second contact 120b coupled to the drain region 106, and a third contact 120c coupled to the gate electrode 108. In some embodiments, the first contact 120a may include an adjacent contact (not shown) that contacts both the contact region 208 and the source region 104. In some embodiments, the plurality of contacts 120 and the field plate 122 may include the same metal material. For example, the plurality of contacts 120 and the field plate 122 may include one or more of tungsten (W), tantalum-nitride (TaN), titanium (Ti), titanium-nitride (TiN), aluminum copper (AlCu), copper (Cu), and / or other similar conductive materials.

[0045] Figure 3 Cross-sectional views of some additional embodiments of the disclosed high voltage LDMOS device 300 having a field plate 214 are shown.

[0046] The LDMOS device 300 includes an isolation region 302 disposed in the drift region 204 at a position laterally arranged between the gate structure 210 and the drain region 106. The isolation region 302 improves the isolation between the gate structure 210 and the drain region 106 so as to prevent dielectric breakdown between the gate structure 210 and the drift region 204 when the LDMOS device 300 is operated at a large operating voltage. For example, the isolation region 302 may be introduced into the drift region 204 of the LDMOS device to increase the breakdown voltage of the LDMOS device 300 without significantly changing the manufacturing process of the LDMOS device, which is designed to operate at the breakdown voltage. In some embodiments, the isolation region 302 may include shallow trench isolation (STI). In other embodiments, the isolation region 302 may include a field oxide.

[0047] Figure 4 Cross-sectional views of some additional embodiments of the disclosed high voltage LDMOS device 400 with a field plate 408 are shown.

[0048] The LDMOS device 400 includes a plurality of dielectric layers (402-404) arranged between the field plate 122 and the gate structure 210 and / or the drift region 204. The plurality of dielectric layers (402-404) are configured to electrically isolate the field plate 408 from the gate structure 210 and / or the drift region 204. In an embodiment, the plurality of dielectric layers (402-404) may include two or more different dielectric materials. In some embodiments, the plurality of dielectric layers (402-404) may include one or more dielectric layers used during a typical CMOS manufacturing process. In order to limit additional manufacturing steps for electrically isolating the field plate 408 from the gate structure 210 and / or the drift region 204.

[0049] For example, the plurality of dielectric layers (402-404) may include a silicide blocking layer 402. In some embodiments, the silicide blocking layer 402 may include a resist-protection oxide (RPO) layer configured to prevent silicide formation. The silicide blocking layer 402 may be disposed over portions of the gate electrode 108 and the drift region 204. In some embodiments, the silicide blocking layer 402 may extend continuously from over the gate electrode 108 to over the drift region 204.

[0050] In some embodiments, the plurality of dielectric layers (402-404) may further include a field plate etch stop layer (ESL) 404. The field plate ESL 404 may be disposed over the silicide barrier layer 402 and configured to control etching of an opening of the field plate 408. The field plate ESL 404 may account for a difference in etch depth between the contact 120 and the field plate 408, and / or account for a difference in etch rate (e.g., due to an etch loading effect). In some embodiments, for example, the field plate ESL 404 may include a silicon nitride (SiN) layer.

[0051] In some alternative embodiments (not shown), the plurality of dielectric layers (402-404) may additionally or alternatively include a gate dielectric layer. In such embodiments, the gate dielectric layer may be disposed laterally adjacent to the gate structure 210, in a position overlying the drift region 204. In some embodiments, the dielectric layer oxide may include silicon dioxide (e.g., SiO2) or a high-k gate dielectric material. In yet other embodiments, the plurality of dielectric layers (402-404) may additionally or alternatively include an ILD layer (e.g., the first ILD layer 118).

[0052] A contact etch stop layer (CESL) 406 is disposed over the semiconductor substrate 102 and the field plate ESL 404. In some embodiments, the CESL 406 extends over the semiconductor substrate 102 at a location between the plurality of contacts 120 and the field plate 408 such that the CESL 406 abuts the sidewalls of the plurality of contacts 120 and the field plate 408. The CESL 406 overlies the gate structure 210. In some embodiments, the CESL 406 may also overlie the plurality of dielectric layers (402-404). In other embodiments, one or more of the plurality of dielectric layers (402-404) (e.g., the field plate ESL 404) may overlie the CESL 406. In some embodiments, the CESL 406 may include a nitride layer. For example, the CESL 406 may include silicon nitride (SiN).

[0053] The field plate 408 is disposed within the first ILD layer 118 and abuts the CESL 406 and one or more of the plurality of dielectric layers (402-404). In some embodiments, the field plate 408 extends through the CESL 406 to abut one or more of the plurality of dielectric layers (402-404). In such embodiments, one or more of the plurality of dielectric layers (402-404) separates the field plate 408 from the gate structure 210 and the drift region 204.

[0054] In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The first metal material 410 may include a colloid layer disposed along an outer edge of the field plate 408, while the second metal material 412 is embedded within the first metal material 410 in an inner region of the field plate 408 (i.e., the second metal material 412 is separated from the CESL 406 by the first metal material 410). In some embodiments, a liner 414 may be disposed between the first ILD layer 118 and the first metal material 410.

[0055] In some embodiments, the first metal material 410 disposed along the outer edge of the field plate 408 has a top surface arranged along a substantially planar surface 420 (i.e., a planar surface formed by a planarization process). The planar surface 420 may be aligned with the top surface of the plurality of contacts 120. In some embodiments, the first metal material 410 includes the same material as the plurality of contacts 120, and the second metal material 412 includes the same material as the first metal wire layer 418 overlying the plurality of contacts 120. For example, in some embodiments, the first metal material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).

[0056] It will be appreciated that the disclosed field plate allows for various field plate bias configurations to be readily available for different design considerations due to its integration with the back end of line (BEOL) metallization layers. For example, the field plate bias can be changed by changing the metal wiring layers rather than by changing the design of the disclosed high voltage device. Furthermore, it will be appreciated that biasing the high voltage transistor device through the BEOL metal interconnect wiring allows for various field plate bias configurations to be integrated on the same chip using a single manufacturing process flow.

[0057] Figure 5 to Figure 6 A cross-sectional view showing some embodiments of field plate biasing configurations for high voltage transistor devices implemented with BEOL metal interconnect wiring. Figure 5 to Figure 6 The connection between the field plate 214 and the contact region 208 or the gate electrode 108 is shown by means of a first metal line layer (e.g., 504 or 604), but the BEOL metal interconnect wiring is not limited thereto. In fact, it should be understood that the field plate 214 can be connected to the source region, the gate electrode, the drain region, or the bulk contact through any combination of BEOL metal interconnect layers (e.g., a first metal line layer, a first metal via layer, a second metal wire layer, etc.).

[0058] Figure 5 A cross-sectional view of a high voltage LDMOS device 500 is shown, wherein a field plate 214 is electrically coupled to a contact region 208 along a conductive path 506. The field plate 214 is connected to a first metal line layer 504, disposed within a second ILD layer 502. The first metal line layer 504 is coupled to a first contact 120a adjacent to the contact region 208. By electrically coupling the field plate 214 to the contact region 208, the field plate 214 is biased by a source voltage. Biasing the field plate 214 by the source voltage provides the high voltage LDMOS device 500 with a low on-state resistance Rds(on) and low dynamic power dissipation (e.g., low Rds(on)*Qgd vs. BV). The low dynamic power dissipation provides good performance during high frequency switching applications.

[0059] Figure 6 A cross-sectional view of a high voltage LDMOS device 600 is shown, wherein a field plate 214 is electrically coupled to a gate electrode 108 along a conductive path 606. The field plate 214 is connected to a first metal line layer 604, disposed within a second ILD layer 602. The first metal line layer 604 is connected to a second contact 120b adjacent to the gate electrode 108. By electrically coupling the field plate 214 to the gate electrode 108, the field plate 214 is biased by a gate voltage. Biasing the field plate 214 by the gate voltage provides a low Rds(on) vs. breakdown voltage to the high voltage LDMOS device 600.

[0060] A variety of field plate bias configurations allow the disclosed field plates to form a universal high voltage transistor device that can be used for different applications. For example, the on-state resistance Rds(on) of a high voltage transistor device with a gate biased field plate is lower than the Rds(on) of a high voltage transistor device with a source biased field plate. However, the Rds(on))*Qgd of a high voltage transistor device with a source biased field plate is lower than the Rds(on))*Qgd of a high voltage transistor device with a gate node biased field plate. Therefore, a high voltage transistor device with a gate biased field plate (e.g., high voltage LDMOS device 500) can be used in low frequency switching applications (e.g., below 10 megahertz), while a high voltage transistor device with a source biased field plate (e.g., high voltage LDMOS device 600) can be used in high frequency switching applications (e.g., above 10 megahertz).

[0061] FIG. 7A to FIG. 7C Cross-sectional views of some embodiments of high voltage LDMOS devices 700a-700c in different switched isolation configurations are shown.

[0062] like Fig. 7A As shown in FIG. 1 , the high voltage LDMOS device 700 a is configured as a low-side switch (eg, a switch connected to ground in an inverter). In such a configuration, the high voltage LDMOS device 700 a has a source region 104 that is floated during a switching cycle so that the voltage on the source region 104 can change.

[0063] like Figure 7B As shown in FIG. 1 , the high voltage LDMOS device 700 b is configured as a high-side switch (eg, connected to V in an inverter). DD In such a configuration, the high voltage LDMOS device 700b has a source region 104 connected to a source voltage. The high voltage LDMOS device 700b has a drift region 702 extending below the body region 202 to prevent the source voltage from rising above the substrate voltage by preventing charge carriers from traveling from the contact region 208 to the semiconductor substrate 102 (e.g., by punching through).

[0064] like Figure 7C As shown in , the high voltage LDMOS device 700c is completely isolated from the substrate to allow independent biasing. The high voltage transistor device 700c includes a deep well 704 and a reverse doped underlying buried layer 706 configured to provide vertical isolation. In some embodiments, the deep well 704 may have a first doping type (e.g., the same doping type as the body region 202), and the buried layer 706 may have a second doping type.

[0065] The high voltage LDMOS device 700c also includes one or more additional STI regions 206 that laterally separate the drain region from the bulk region 708 and a buried layer 710 having a second doping type. The bulk region 708 overlies the deep well 704, and the buried layer 710 overlies a well region 712 having a second first doping type and adjacent to the buried layer 706. The contact 120 is configured to provide a bias voltage to the bulk region 708 and the buried layer 710 so as to form a junction isolation between the deep well 704 and the buried layer 706 and the well region 712. The junction isolation allows the fully isolated high voltage LDMOS device 700c to operate within a range of bias voltages.

[0066] Figure 8 A cross-sectional view of a source-down high voltage transistor device 800 with a field plate 214 is shown.

[0067] The high voltage transistor device 800 includes a substrate 802 of a first doping type (e.g., p+ doping type) having a high doping concentration. A source region 804 is disposed along a back side 802b of the substrate 802. In various embodiments, the source region 804 may include a highly doped region or a metal layer. An epitaxial layer 806 having a first conductivity type is disposed above a front side surface 802f of the substrate 802. The dopant concentration of the epitaxial layer 806 is less than the dopant concentration of the substrate 802. A source contact region 810, a drain region 106, a body region 808, and a drift region 204 are disposed within a top surface of the epitaxial layer 806.

[0068] Conductive material 812 extends from the top surface of epitaxial layer 806 to substrate 802. Conductive material 812 may include a highly doped deep well region. Conductive material 812 allows source connection to be made from the back side of substrate 802, thereby reducing metal wiring complexity and enabling various packaging compatibilities. In some embodiments, field plate 214 may be biased by a source voltage by means of an electrical path 818 extending through a contact 814 adjacent to conductive material 812 and an overlying metal line layer 816 coupled to field plate 214.

[0069] FIG. 9A to FIG. 9B Some embodiments of the disclosed high voltage LDMOS device are shown with a field plate 902 in the metal line layer. FIG. 9A to FIG. 9B The field plate is shown as being on the first metal line layer, but it should be understood that the disclosed field plate is not limited to the first metal line layer, but may in fact be implemented on alternative layers of the BEOL metallization stack.

[0070] like Fig. 9AAs shown in the cross-sectional view 900 of , a field plate 902 is disposed in the first metal line layer, within a second ILD layer 904 overlying the first ILD layer 118. In some embodiments, the field plate 902 has substantially flat top and bottom surfaces to provide a flat profile for the field plate 902. The field plate 902 is vertically separated from the gate structure 210 and the drift region 204 by the first ILD layer 118. The field plate 902 overlies portions of the gate electrode 108 and the drift region 204 and is laterally separated from the source region 104 and the drain region 106. For example, the field plate 902 may be laterally separated from the drain region 106 by a distance d. In some embodiments, the field plate 902 may extend laterally from above the gate electrode 108 to above the drift region 204.

[0071] like Fig. 9B As shown in the top view 906 of FIG. 1 , the field plate 902 includes a metal structure overlying the gate electrode 108 and a portion of the drift region 204. The metal structure is not connected to an underlying component or to another metal structure on the first metal line layer by means of a contact 120. In practice, the metal structure will be connected to an overlying via (not shown) configured to connect the field plate to an overlying metal line layer that biases the field plate 902.

[0072] Fig.10 Some embodiments of the disclosed high voltage LDMOS device 1000 having a self-aligned drift region 1002 are shown.

[0073] The self-aligned drift region 1002 has a sidewall 1002s substantially aligned with the sidewall of the gate electrode 108 and the gate dielectric layer 110. In some alternative embodiments, the self-aligned drift region 1002 may be formed to have a sidewall 1002s substantially aligned with the edge of the sidewall spacer 212. By aligning the self-aligned drift region 1002 with the sidewall of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 is laterally separated from the body region 202 by a spacing s, thereby minimizing gate-drain overlap and achieving low gate-drain charge (Qgd) and good high frequency performance. The field plate 214 overlying the self-aligned drift region 1002 can further reduce the gate-drain charge (Qgd).

[0074] Fig.11 A flow chart of some embodiments of a method 1100 of forming a high voltage transistor device having a field plate is shown. The method can form the field plate using process steps already used during standard CMOS manufacturing processes, and thus can provide a low cost, general purpose field plate.

[0075] Although the disclosed methods (e.g., method 1100, method 3300, and method 7700) are illustrated and described herein as a series of actions or events, it should be understood that the illustrated ordering of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events illustrated and / or described herein, some actions may occur in a different order and / or simultaneously with other actions or events. In addition, not all of the illustrated actions may be required to implement one or more aspects or embodiments described herein. In addition, one or more of the actions depicted herein may be implemented in one or more separate actions and / or stages.

[0076] At act 1102, a substrate is provided, the substrate having a source region and a drain region separated by a channel region. In some embodiments, the substrate may further include a drift region located between the source region and the drain region, adjacent to the channel region.

[0077] At act 1104, a gate structure is formed over the substrate at a location disposed between the source region and the drain region. The gate structure may include a gate dielectric layer and an overlying gate electrode.

[0078] At act 1106 , a drift region may be formed using a self-aligned process, which in some embodiments selectively implants the semiconductor substrate according to the gate structure to form the drift region.

[0079] At act 1108 , one or more dielectric layers are selectively formed over the gate electrode and a portion of the drift region.

[0080] At act 1110 , a contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer are formed over a substrate.

[0081] At act 1112 , the first ILD layer is selectively etched to define contact openings and field plate openings.

[0082] At act 1114 , the contact openings and the field plate openings are filled with a first metal material.

[0083] At act 1116 , a planarization process may be performed to remove excess first metal material overlying the first ILD layer.

[0084] At act 1118, a second metal material corresponding to the first metal line layer is deposited. In some embodiments, the second metal material may further fill the field plate opening. In such embodiments, the second metal material is embedded within the first metal material within the field plate opening.

[0085] At act 1120 , a second inter-layer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line layer structure.

[0086] Figures 12 to 19 A cross-sectional view illustrating some embodiments of a method of forming a MOSFET device having a field plate is shown. Figures 12 to 19 , but it should be understood that Figures 12 to 19 The structures disclosed in the invention are not limited to the method, but can in fact stand alone as structures independent of the method.

[0087] Fig.12 Some embodiments of a cross-sectional view 1200 corresponding to act 1102 are shown.

[0088] As depicted in cross-sectional view 1200, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be substantially doped with a first doping type. In various embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., silicon, SOI) including but not limited to a semiconductor die or wafer or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated therewith.

[0089] The semiconductor substrate 102 may be selectively implanted using various implantation steps to form a plurality of implant regions (e.g., well regions, contact regions, etc.). For example, the semiconductor substrate 102 may be selectively implanted to form a body region 202, a drift region 204, a source region 104, a drain region 106, and a contact region 208. The plurality of implant regions may be formed by selectively masking the semiconductor substrate 102 (e.g., using a photoresist mask), and then introducing a high energy dopant 1204 (e.g., a p-type dopant species such as boron or an n-type dopant such as phosphorus) into exposed regions of the semiconductor substrate 102. For example, as depicted in the cross-sectional view 1200, the masking layer 1202 is selectively patterned to expose portions of the semiconductor substrate 102, and then the high energy dopant 1204 is implanted into the exposed portions to form the source region 104 and the drain region 106.

[0090] It should be understood that the implant region shown in cross-sectional view 1200 is one example of a possible implant region and that semiconductor substrate 102 may include other configurations of implant regions, such as, for example. Figures 1 to 10 Any of the configurations shown in .

[0091] Fig.13 Some embodiments of cross-sectional view 1300 corresponding to act 1104 are shown.

[0092] As shown in the cross-sectional view 1300, the gate structure 210 is formed over the semiconductor substrate 102 at a position disposed between the source region 104 and the drain region 106. The gate structure 210 may be formed by forming a gate dielectric layer 110 over the semiconductor substrate 102, and by forming a gate electrode material 108 over the gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 and the gate electrode material 108 may be deposited by a vapor deposition technique. The gate dielectric layer 110 and the gate electrode material 108 may then be patterned and etched (e.g., according to a photoresist mask) to define the gate structure 210. In some embodiments, the sidewall spacers 212 may be formed on opposite sides of the gate electrode 108 by depositing a nitride-based material or an oxide-based material onto the semiconductor substrate 102, and selectively etching the nitride-based material or the oxide-based material to form the sidewall spacers 212.

[0093] Fig.14 Some embodiments of cross-sectional view 1400 corresponding to act 1108 are shown.

[0094] As shown in cross-sectional view 1400, one or more dielectric layers 124 are selectively formed over gate electrode 108 and drift region 204. In some embodiments, one or more dielectric layers 124 may be deposited by vapor deposition techniques and subsequently patterned and etched (e.g., according to a photoresist mask). In some embodiments, one or more dielectric layers 124 may be etched to expose a portion of gate electrode 108 and to be laterally spaced apart from drain region 106.

[0095] In some embodiments, one or more dielectric layers 124 may include a silicide barrier layer, such as a photoresist protective oxide (RPO) layer. In other embodiments, one or more dielectric layers 124 may additionally and / or alternatively include a field plate etch stop layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by a vapor deposition technique. In yet other embodiments, one or more dielectric layers 124 may additionally and / or alternatively include a gate dielectric layer or an interlayer dielectric (ILD) layer.

[0096] Fig.15 Some embodiments of cross-sectional view 1500 corresponding to act 1110 are shown.

[0097] As shown in the cross-sectional view 1500, a contact etch stop layer (CESL) 1502 is formed over the semiconductor substrate 102. In some embodiments, the CESL 1502 may be formed by a vapor deposition process. A first interlayer dielectric (ILD) layer 1504 is then formed over the CESL 1502. In some embodiments, the first ILD layer 1504 may include an ultra-low-k dielectric material or a low-k dielectric material (e.g., SiCO). In some embodiments, the first ILD layer 1504 may also be formed by a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin coating process. It should be understood that the term interlayer dielectric (ILD) layer as used herein may also refer to an inter-metal dielectric (IMD) layer.

[0098] Fig.16 Some embodiments of cross-sectional view 1600 corresponding to act 1112 are shown.

[0099] As shown in the cross-sectional view 1600, the first ILD layer 1504 is selectively exposed to a first etchant 1602, which is configured to form a contact opening 1606 and a field plate opening 1608. In some embodiments, the contact opening 1606 may be smaller than the field plate opening 1608. In some embodiments, the first ILD layer 1504 is selectively exposed to the first etchant 1602 according to the masking layer 1604 (e.g., a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have a greater etching selectivity between the first ILD layer 1504 and the field plate ESL within one or more dielectric layers 124. In some embodiments, the first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may have an etching chemistry that includes one or more of oxygen (oxygen; O2), nitrogen (nitrogen; N2), hydrogen (hydrogen; H2), argon (argon; Ar), and / or fluorine species (e.g., CF4, CHF3, C4F8, etc.). In other embodiments, the first etchant 1602 may include a wet etchant including buffered hydrofluoric acid (BHF).

[0100] Fig.17 Some embodiments of cross-sectional view 1700 corresponding to acts 1114 through 1116 are shown.

[0101] As shown in cross-sectional view 1700, contact opening 1606 and field plate opening 1608 are filled with first metal material 1702. In some embodiments, first metal material 1702 may be deposited by means of a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, first metal material 1702 may be formed by depositing a seed layer by means of physical vapor deposition followed by a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess first metal material 1702 and form a planar surface along line 1704.

[0102] In some embodiments, the first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, a diffusion barrier layer and / or a liner layer may be deposited into the contact opening 1606 and the field plate opening 1608 before depositing the first metal material 1702.

[0103] Fig.18 Some embodiments of a cross-sectional view 1800 corresponding to act 1118 are shown.

[0104] As shown in cross-sectional view 1800, a second metallic material 1802 is deposited. The second metallic material 1802 is formed within the remaining opening in the field plate opening and over the first ILD layer 118. In some embodiments, the second metallic material 1802 may be deposited by means of a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.). In some embodiments, the second metallic material 1802 may be formed by depositing a seed layer by means of physical vapor deposition followed by a plating process. In some embodiments, the second metallic material 1802 may include copper (Cu) or an aluminum-copper (AlCu) alloy.

[0105] After formation, the second metallic material 1802 may be selectively patterned to define one or more metallic structures of the first metal line layer 418 overlying the first ILD layer 118. In some embodiments, the second metallic material 1802 may be selectively patterned by forming a patterned masking layer (e.g., a photoresist layer or a hard mask layer) (not shown) over the second metallic material 1802 and by subsequently etching the second metallic material 1802 in areas exposed by the patterned masking layer.

[0106] Fig.19 Some embodiments of cross-sectional view 1900 corresponding to act 1120 are shown.

[0107] As shown in the cross-sectional view 1900, the second ILD layer 416 is formed over the first ILD layer 118 and the one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may be formed by depositing a second ILD material over the first ILD layer 118 and the one or more metal structures of the first metal line layer 418. After the second ILD layer 416 is formed, a planarization process (e.g., CMP) is performed to remove excess second ILD layer 416 and expose the top surface of the one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may include an ultra-low-k dielectric material or a low-k dielectric material (e.g., SiCO) formed by a vapor deposition processor, a spin coating process.

[0108] It is understood that the height difference between the plurality of contacts (e.g., contact 120) and the field plate (e.g., field plate 122) can cause difficulties during the fabrication of the disclosed transistor device. For example, because the field plate (e.g., field plate 122) is formed above the dielectric layer 124 (e.g., photoresist protective oxide), the field plate (e.g., field plate 122) has a smaller height than the plurality of contacts (e.g., contact 120). However, the field plate (e.g., field plate 122) and the plurality of contacts (e.g., contact 120) are formed using the same etching process. The height difference can cause the field plate opening (e.g., Fig.16 Over-etching of the field plate opening 1608 of the transistor device may cause a short circuit between the field plate (eg, the field plate opening 122) and the conductive channel of the transistor device; or may cause a contact opening (eg, Fig.16 The contact opening 1606 is under-etched, which causes poor connections between multiple contacts (e.g., contact 120) and source regions (e.g., source region 104), drain regions (e.g., drain region 106) and / or gate regions (e.g., gate region 116).

[0109] To prevent over-etching of the field plate openings or under-etching of the contact openings, in some embodiments, a composite etch stop layer may be used to control the etch depth of the field plate openings. By controlling the etch depth of the field plate openings, the composite etch stop layer allows both the plurality of contacts (e.g., contacts 120) and the field plates (e.g., field plates 122) to be precisely formed to different heights.

[0110] Fig. 20 A cross-sectional view of some embodiments of a high voltage transistor device 2000 having a composite etch stop layer defining a field plate is shown.

[0111] The high voltage transistor device 2000 includes a gate structure 116 disposed above a semiconductor substrate 102. The gate structure 116 includes a gate dielectric layer 110 and an overlying gate electrode 108. In some embodiments, the gate structure 116 may have a first thickness th1 in a range between about 1000 angstroms and about 2000 angstroms. The source region 104 and the drain region 106 are disposed within the semiconductor substrate 102 on opposite sides of the gate structure 116.

[0112] A photoresist protective oxide (RPO) 2002 is disposed over the gate structure 116. The RPO 2002 extends from directly over the gate structure 116 to laterally exceed the outermost sidewalls of the gate structure 116. In some embodiments, the RPO 2002 may extend vertically from the upper surface of the gate structure 116 to the upper surface of the semiconductor substrate 102, and laterally extend from directly over the gate structure 116 to between the gate structure 116 and the drain region 106. In some embodiments, the RPO 2002 may include silicon dioxide, silicon nitride, etc. In some embodiments, the RPO 2002 may have a second thickness th2 in the range of about 100 angstroms to about 1000 angstroms.

[0113] A composite etch stop layer 2004 is disposed over the RPO 2002. In some embodiments, the composite etch stop layer 2004 directly contacts one or more upper surfaces of the RPO 2002. A first interlayer dielectric (ILD) layer 118 and a field plate 122 are disposed over the composite etch stop layer 2004. The first ILD layer 118 surrounds the field plate 122 and a plurality of contacts 120 coupled to the source region 104, the drain region 106, and the gate structure 116. In some embodiments, the field plate 122 and the plurality of contacts 120 may include a diffusion barrier (not shown) surrounding a conductive core including one or more metals.

[0114] The composite etch stop layer 2004 includes a plurality of different dielectric materials 2006 to 2008 stacked above the RPO 2002. In some embodiments, the plurality of different dielectric materials 2006 to 2008 may have outermost sidewalls substantially aligned along a line perpendicular to the upper surface of the semiconductor substrate 102. In some embodiments, the plurality of different dielectric materials 2006 to 2008 may have outermost sidewalls substantially aligned with the outermost sidewalls of the RPO 2002. In such embodiments, the RPO 2002 has a first width substantially equal to a second width of the composite etch stop layer 2004. The plurality of different dielectric materials 2006 to 2008 have different etching properties, and the different etching properties provide respective dielectric materials in the plurality of different dielectric materials 2006 to 2008 with different etching selectivities to the etchant. The different etch selectivities allow the composite etch stop layer 2004 to slowly etch the field plate opening (i.e., the opening defining the field plate 122), and thereby simultaneously tightly control the height of the field plate and achieve a height difference between the plurality of contacts 120 and the field plate 122 (e.g., enabling the plurality of contacts 120 to have a greater height than the field plate 122).

[0115] For example, in some embodiments, the bottom of the field plate 122 contacts the composite etch stop layer 2004 along an interface that is vertically higher than the bottom surface of one or more of the plurality of contacts 120 (e.g., contacts coupled to the source region 104 and the drain region 106). In such embodiments, the composite etch stop layer 2004 reduces the etch rate of an etchant used to form the field plate opening (i.e., the opening defining the field plate 122) during fabrication of the high voltage transistor device 2000. The reduction in the etch rate causes the field plate 122 to have a bottom surface that is higher than the bottom surface of one or more of the plurality of contacts 120.

[0116] In some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 directly contacting the upper surface of the RPO 2002 and a second dielectric material 2008 directly contacting the upper surface of the first dielectric material 2006. In some embodiments, the first dielectric material 2006 may have a third thickness th3, and the second dielectric material 2008 may have a fourth thickness th4. In some embodiments, the RPO 2002 and the composite etch stop layer 2004 may have a substantially constant thickness between the outermost sidewalls, respectively. If the third thickness th3 and the fourth thickness th4 are too small (e.g., less than the minimum value described below), the composite etch stop layer 2004 is not able to effectively terminate the etching that forms the field plate opening. If the third thickness th3 and the fourth thickness th4 are too large (e.g., greater than the maximum value described below), the effect of the field plate 122 on the high voltage transistor device 2000 is reduced, thereby negatively affecting the device performance.

[0117] In some embodiments, the first dielectric material 2006 may include or may be silicon nitride (Si x N y ), and the second dielectric material 2008 may include or may be silicon dioxide (SiO2). In such embodiments, the first thickness th1 may be in a first range of about 50 angstroms to about 400 angstroms, and the second thickness th2 may be in a second range of about 150 angstroms to about 700 angstroms. In other embodiments, the first dielectric material 2006 may include or may be silicon dioxide (SiO2), and the second dielectric material 2008 may include or may be silicon nitride (SiN x ) or silicon oxynitride (SiO x N y In such embodiments, the first thickness th1 may be within a first range of about 600 angstroms to about 900 angstroms. In some embodiments, the second thickness th2 may be within a second range of about 100 angstroms to about 500 angstroms.

[0118] FIG. 21A to FIG. 21B Some additional embodiments of the disclosed high voltage transistor device having a composite etch stop layer defining a field plate are shown.

[0119] like Fig.21A As shown in the cross-sectional view 2100 of , the high voltage transistor device includes a semiconductor substrate 102 having a body region 2106 disposed in a drift region 2104 above the substrate 2102. The source region 104 is disposed in the body region 2106, and the drain region 106 is disposed in the drift region 2104. In some embodiments, the source region 104, the drain region 106, and the drift region 2104 may have a first doping type (e.g., n-type), while the body region 2106 and the substrate 2102 have a second doping type (e.g., p-type) opposite to the first doping type. In some embodiments, the source region 104 and the drain region 106 may include a highly doped region (i.e., an n+ region) having a higher doping concentration than the drift region 2104.

[0120] The gate structure 116 is disposed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The RPO 2002 is disposed over the gate structure 116 and extends laterally beyond the outermost sidewalls of the gate structure 116. The composite etch stop layer 2004 is disposed between the RPO 2002 and the field plate 122. In some embodiments, the RPO 2002 may enclose the field plate 122 (i.e., extend beyond the outermost sidewalls of the field plate 122) by one or more lateral distances 2108 in the range of about 0 microns and about 2 microns.

[0121] In some embodiments, the field plate 122 may extend to a non-zero depth 2110 in the composite etch stop layer 2004. In such embodiments, the field plate 122 contacts the sidewalls of the composite etch stop layer 2004. In various embodiments, the field plate 122 may also contact the horizontally extending surface of the composite etch stop layer 2004 or the horizontally extending surface of the RPO 2002. In some embodiments, the non-zero depth 2110 may be in a range of about 400 angstroms to about 700 angstroms. Since the field plate 122 extends into the composite etch stop layer 2004, the composite etch stop layer 2004 has a first thickness 2112 directly below the field plate 122 and a second thickness outside the field plate 122 that is greater than the first thickness 2112. In some embodiments, the first thickness 2112 is in a range of about 0 angstroms to about 10,000 angstroms. In some additional embodiments, the first thickness 2112 is in a range of about 600 angstroms to about 300 angstroms.

[0122] like Fig.21B A top view 2120 (along Fig.21A As shown in the cross-sectional line AA′ of FIG. 1 , the field plate 122 has a width 2114 extending in the first direction for a distance in the range of about 150 nanometers to about 2000 nanometers. The field plate 122 also has a length 2122 extending in the second direction (perpendicular to the first direction) for a distance less than about 1000 micrometers.

[0123] Reference again Fig.21A 2100, in some embodiments, the field plate 122 can be laterally separated from the gate structure 116 by a distance 2116. For example, the field plate 122 can be laterally separated from the gate structure 116 by a distance 2116 in a range between about 0 nanometers and about 500 nanometers. In other embodiments (not shown), the field plate 122 can laterally overlap (i.e., extend directly above) the gate structure 116. For example, the field plate 122 can laterally overlap the gate structure 116 by a distance in a range between about 0 nanometers and about 200 nanometers.

[0124] In some embodiments, the silicide layer 2118 is disposed over the source region 104, the drain region 106, and the portion of the gate structure 116 not covered by the RPO 2002. In various embodiments, the silicide layer 2118 may include a compound having silicon and a metal such as nickel, platinum, titanium, tungsten, magnesium, etc. In some embodiments, the silicide layer 2118 has a thickness in a range between about 150 angstroms and about 400 angstroms.

[0125] Fig. 22 Cross-sectional views of some additional embodiments of a high voltage transistor device 2200 having a composite etch stop layer defining a field plate are shown.

[0126] The high voltage transistor device 2200 includes a gate electrode 108 disposed over a semiconductor substrate 102. An RPO 2002 and a composite etch stop layer 2004 are over the gate electrode 108 and the semiconductor substrate 102. A contact etch stop layer (CESL) 406 is disposed over the composite etch stop layer 2004. In some embodiments, a bottom surface of the composite etch stop layer 2004 may directly contact the RPO 2002, and a top surface of the composite etch stop layer 2004 may directly contact the CESL 406. The CESL 406 laterally extends beyond the outermost sidewalls of the composite etch stop layer 2004 and contacts the semiconductor substrate 102. In some embodiments, the CESL 406 may have a thickness th5 in a range between about 100 angstroms and about 1000 angstroms. In some embodiments, the CESL 406 may include silicon nitride, silicon carbide, and the like.

[0127] The field plate 408 is disposed within the first ILD layer 118 above the CESL 406. In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The composite etch stop layer 2004 is laterally disposed between the field plate 408 and the gate structure 116 and vertically disposed between the field plate 122 and the semiconductor substrate 102. The RPO 2002 and the composite etch stop layer 2004 have sidewalls that contact 406. The composite etch stop layer 2004 further has a horizontally extending surface (e.g., an upper surface) that contacts the CESL 406.

[0128] In some embodiments, the field plate 122 may extend into one or more of the plurality of different dielectric materials 2006 within the composite etch stop layer 2004. For example, in some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2008 that contacts an upper surface of the first dielectric material 2006. The field plate 122 may extend through the second dielectric material 2008 (e.g., silicon oxide) and have a bottom surface that contacts the first dielectric material 2006 (e.g., silicon nitride). In such embodiments, the second dielectric material 2008 may vertically separate the bottom-most point of the field plate 122 from the RPO 2002. In other embodiments, the field plate 122 may additionally extend through the first dielectric material 2006 and have a bottom surface and / or sidewalls that contact the RPO 2002. In some embodiments, the field plate 122 can extend vertically through the second dielectric material 2008 and also be laterally separated from the gate structure 116 by the second dielectric material 2008 .

[0129] Although the disclosed composite etch stop layer 2004 is Figure 20 to Figure 222002, but it should be understood that the disclosed composite etch stop layer 2004 is not limited to such a configuration. In fact, in various embodiments, the composite etch stop layer 2004 may include additional layers of dielectric materials. Figure 23 to Figure 24 Some non-limiting examples of alternative embodiments of the disclosed composite etch stop layer 2004 are shown.

[0130] Fig.23 Cross-sectional views of some additional embodiments of a high voltage transistor device 2300 having a composite etch stop layer defining a field plate are shown.

[0131] The high voltage transistor device 2300 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2302, a second dielectric material 2304 contacting an upper surface of the first dielectric material 2302, and a third dielectric material 2306 contacting an upper surface of the second dielectric material 2304. In some embodiments, the first dielectric material 2302 may include or may be silicon dioxide (SiO2), and the second dielectric material 2304 may include or may be silicon nitride (Si x N y ) or silicon oxynitride (SiO x N y ), and the third dielectric material 2306 may include or may be silicon dioxide (SiO2).

[0132] In some embodiments, the first dielectric material 2302 may have a first thickness, the second dielectric material 2304 may have a second thickness, and the third dielectric material 2306 may have a third thickness. In some embodiments, the first thickness may be in a first range of about 300 angstroms to about 900 angstroms, the second thickness may be in a second range of about 50 angstroms to about 200 angstroms, and the third thickness may be in a third range of about 200 angstroms to about 600 angstroms.

[0133] Fig.24 Cross-sectional views of some additional embodiments of a high voltage transistor device 2400 having a composite etch stop layer defining a field plate are shown.

[0134] The high voltage transistor device 2400 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2402, a second dielectric material 2404 contacting an upper surface of the first dielectric material 2402, a third dielectric material 2406 contacting an upper surface of the second dielectric material 2404, and a fourth dielectric material 2408 contacting an upper surface of the third dielectric material 2406. In some embodiments, the first dielectric material 2402 may include or may be silicon dioxide (SiO2), and the second dielectric material 2404 may be or may include silicon nitride (Si x N y ) or silicon oxynitride (SiO x N y ), the third dielectric material 2406 may include or may be silicon dioxide (SiO2), and the fourth dielectric material 2408 may include or may be silicon nitride (Si x N y ) or silicon oxynitride (SiO x N y ).

[0135] In some embodiments, the first dielectric material 2402 may have a first thickness, the second dielectric material 2404 may have a second thickness, the third dielectric material 2406 may have a third thickness, and the fourth dielectric material 2408 may have a fourth thickness. In some embodiments, the first thickness may be in a first range of about 300 angstroms and about 900 angstroms, the second thickness may be in a second range of about 50 angstroms and about 200 angstroms, the third thickness may be in a third range of about 200 angstroms and about 600 angstroms, and the fourth thickness may be in a fourth range of about 50 angstroms and about 200 angstroms.

[0136] Figure 25 to Figure 32 A cross-sectional view of some embodiments of a method of forming a high voltage transistor device having a composite etch stop layer defining a field plate is shown. Figure 25 to Figure 32 2500 to 3200, but it should be understood that Figure 25 to Figure 32 The structures depicted in the drawings are not limited to the methods and can in fact stand alone independently of the methods.

[0137] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 25, the semiconductor substrate 102 is selectively implanted to form a plurality of implant regions (e.g., well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 can be selectively implanted to form a body region 2106, a drift region 2104, a source region 104, and a drain region 106. In other embodiments, the semiconductor substrate 102 can be selectively implanted to form different implant regions (e.g., Figures 1 to 10). In some embodiments, multiple implant regions may be formed by selectively masking semiconductor substrate 102 (e.g., using a photoresist mask) and then introducing a high energy dopant (e.g., a p-type dopant species such as boron or an n-type dopant such as phosphorus) into exposed areas of semiconductor substrate 102.

[0138] A gate structure 116 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by depositing a gate dielectric layer 110 over the semiconductor substrate 102 and by depositing a gate electrode material 108 over the gate dielectric layer 110. The gate dielectric layer 110 and the gate electrode material 108 may then be patterned (e.g., etched according to a photoresist mask and / or a hard mask) to define the gate structure 116.

[0139] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 1 , a photoresist protective oxide (RPO) 2002 is formed above the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 beyond the outermost sidewalls of the gate structure 116. The RPO 2002 is configured to block the formation of silicide on the bottom layer. In some embodiments, the RPO 2002 can be deposited by a vapor deposition technique (e.g., CVD). In some embodiments, the RPO 2002 can include silicon dioxide (SiO2), silicon nitride, and the like.

[0140] like Fig. 27 As shown in the cross-sectional view 2700 of FIG. 27 , a composite etch stop layer 2004 including a plurality of different dielectric materials 2006 to a dielectric material 2008 is selectively formed on the RPO 2002. In some embodiments, the plurality of different dielectric materials 2006 to a dielectric material 2008 may be sequentially deposited by a vapor deposition technique. In some embodiments, the composite etch stop layer 2004 may include a dielectric material including silicon nitride (Si x N y ) layer, silicon oxynitride (SiO x N y ) layer and / or a stacked layer of two or more silicon dioxide (SiO2) layers.

[0141] In some embodiments, the plurality of different dielectric materials 2006 to 2008 and RPO 2002 may be patterned using the same masking layer 2702 (e.g., a photoresist layer) and etching process. Using the same masking layer 2702 to pattern the plurality of different dielectric materials 2006 to 2008 and RPO 2002 reduces the cost of forming the composite etch stop layer 2004. In such embodiments, the plurality of different dielectric materials 2006 to 2008 and RPO 2002 may have substantially aligned sidewalls.

[0142] like Fig.28 As shown in the cross-sectional view 2800 of FIG. 28 , a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the composite etch stop layer 2004. In some embodiments, the CESL 406 may be formed by a vapor deposition process. The CESL may include a nitride layer (e.g., Si3N4), a carbide layer (SiC), and the like.

[0143] like Fig.29 As shown in the cross-sectional view 2900 of FIG. 4 , a first interlayer dielectric (ILD) layer 118 is formed over the CESL 406. In some embodiments, the first ILD layer 118 may include an oxide (e.g., SiO2), an ultra-low-k dielectric material, a low-k dielectric material (e.g., SiCO), etc. In some embodiments, the first ILD layer 118 may be formed by a vapor deposition process.

[0144] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 1 , the first ILD layer 118 is selectively exposed to an etchant 3002 (e.g., based on a masking layer 3003) to form a contact opening 1606 and a field plate opening 1608 in the first ILD layer 118. The contact opening 1606 and the field plate opening 1608 have an etch depth offset of a non-zero distance 3004. In some embodiments, the non-zero depth 3004 may be in a range of about 400 angstroms to about 2000 angstroms. In some embodiments, the field plate opening 1608 extends into the composite etch stop layer 2004 such that a sidewall of the composite etch stop layer 2004 defines the field plate opening 1608. In various embodiments, the composite etch stop layer 2004 or the RPO 2002 may define a bottom of the field plate opening 1608.

[0145] In some embodiments, the etchant 3002 can reduce the thickness of the composite etch stop layer 2004 by an amount in a range between about 400 angstroms and about 700 angstroms. In some embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 0 angstroms and about 1,000 angstroms. In some additional embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 300 angstroms and about 900 angstroms.

[0146] The etchant 3002 used to form the contact openings 1606 and the field plate openings 1608 is selected to etch through the material of the CESL 406. However, because the composite etch stop layer 2004 is formed of a plurality of different materials, the composite etch stop layer 2004 is able to resist etching by the etchant 3002 to a high degree. The composite etch stop layer 2004 thereby allows the contact openings 1606 to extend to the semiconductor substrate 102 while preventing the field plate openings 1608 from extending to the semiconductor substrate 102. The composite etch stop layer 2004 also allows for a high degree of uniformity in etch depth at different locations on the substrate, between substrates of the same batch, and / or over different batches of substrates. For example, the composite etch stop layer 2004 allows the etch depth of the field plate openings 1608 on different substrates to be within a deviation of approximately 2% or less. This etch depth uniformity allows for improved device uniformity and performance compared to devices without the composite etch stop layer 2004.

[0147] like Fig.31 As shown in the cross-sectional view 3100 of , the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials. In some embodiments, the one or more conductive materials may be deposited by means of a vapor deposition technique (e.g., CVD, PVD, PE-CVD, etc.) and / or a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess one or more conductive materials and form a planar surface along line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, before depositing the one or more conductive materials, a diffusion barrier layer and / or a liner layer may be deposited into the contact opening 1606 and the field plate opening 1608.

[0148] like Fig.32 As shown in the cross-sectional view 3200 of , the second ILD layer 126 is formed over the first ILD layer 118, and the first back-end of line (BEOL) metal line layer 128 is formed in the second ILD layer 126. In various embodiments, the second ILD layer 126 may be formed by depositing a second ILD material over the first ILD layer 118. The second ILD layer 126 is then etched to form trenches extending in the second ILD layer 126. The trenches are filled with a conductive material, and a planarization process (e.g., CMP) is performed to remove excess conductive material from over the second ILD layer 126.

[0149] Fig.33 A flow chart illustrating some embodiments of a method 3300 of forming a high voltage transistor device having a composite etch stop layer defining a field plate.

[0150] At act 3302, a gate structure is formed over a substrate. Fig.25 Cross-sectional view 2500 corresponding to some embodiments of act 3302 is shown.

[0151] At act 3304, source and drain regions are formed within the substrate, on opposite sides of the gate structure. In some additional embodiments, one or more additional doped regions (eg, body regions, drift regions, etc.) may also be formed within the substrate. Fig.25 A cross-sectional view 2500 corresponding to some embodiments of act 3304 is shown.

[0152] At act 3306, a photoresist protective oxide (RPO) is formed over the gate structure and laterally between the gate structure and the drain region. Fig.26 Cross-sectional view 2600 is shown corresponding to some embodiments of act 3306 .

[0153] At act 3308, a composite etch stop layer is formed over the RPO. Fig. 27 A cross-sectional view 2700 corresponding to some embodiments of act 3308 is shown.

[0154] At act 3310, a contact etch stop layer (CESL) is formed on the composite etch stop layer. Fig.28 Cross-sectional view 2800 corresponding to some embodiments of act 3310 is shown.

[0155] At act 3312, a first inter-layer dielectric (ILD) layer is formed over the CESL. Fig.29 Cross-sectional view 2900 is shown corresponding to some embodiments of act 3312 .

[0156] At act 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The plurality of contact openings and field plate openings have different depths. Fig.30 Cross-sectional view 3000 is shown corresponding to some embodiments of act 3314 .

[0157] At act 3316 , the plurality of contact openings and the field plate openings are filled with one or more conductive materials. Fig.31 A cross-sectional view 3100 is shown corresponding to some embodiments of act 3316 .

[0158] At act 3318, a conductive interconnect is formed in a second ILD layer over the first ILD layer. Fig.32 A cross-sectional view 3200 is shown corresponding to some embodiments of act 3318 .

[0159] Fig.34A cross-sectional view of some embodiments of a high voltage transistor device 3400 having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact is shown.

[0160] The high voltage transistor device 3400 includes a gate structure 116 vertically arranged above the semiconductor substrate 102 at a position laterally between the source region 104 and the drain region 106. In some embodiments, the semiconductor substrate 102 may also include a body region 2106 surrounding the source region 104 and / or a drift region 2104 between the body region 2106 and the drain region 106. A photoresist protective oxide (RPO) 2002 is above the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 to laterally between the gate structure 116 and the drain region 106. A contact etch stop layer (CESL) 406 is disposed above the RPO 2002, the gate structure 116, and the semiconductor substrate 102.

[0161] The dielectric structure 3401 is disposed over the CESL 406. The dielectric structure 3401 includes a first ILD layer 3402 disposed over the CESL 406, a second ILD layer 3406 over the first ILD layer 3402, and a third ILD layer 3408 over the second ILD layer 3406. In some embodiments, the first ILD layer 3402 has an uppermost surface overlying a top of the gate structure 116 by a non-zero distance d1. In some embodiments, the second ILD layer 3406 is separated from the third ILD layer 3408 by an etch stop layer 3410. In such embodiments, the second ILD layer 3406 has a bottom surface directly contacting a top surface of the first ILD layer 3402 and a top surface directly contacting a bottom surface of the etch stop layer 3410. The plurality of contacts 120 vertically extend from the top surface of the second ILD layer 3406 to the bottom surface of the first ILD layer 3402 (through the interface 3403 of the first ILD layer 3402 and the second ILD layer 3406 ). The plurality of contacts 120 are configured to contact the source region 104 , the drain region 106 , and the gate structure 116 .

[0162] The field plate etch stop structure 3404 is disposed between the first ILD layer 3402 and the second ILD layer 3406. The bottommost surface and the topmost surface of the field plate etch stop structure 3404 are vertically between the bottom surface and the top surface of the plurality of contacts 120. In some embodiments, the field plate etch stop structure 3404 is disposed directly above the RPO 2002. In some such embodiments, the field plate etch stop structure 3404 is completely confined above the RPO 2002, while in other embodiments, the field plate etch stop structure 3404 may extend from directly above the RPO 2002 to laterally between the RPO 2002 and the drain region 106. In some embodiments, the field plate etch stop structure 3404 may have opposing outermost sidewalls laterally between the gate structure 116 and the drain region 106. For example, the field plate etch stop structure 3404 may have a first lateral distance d L1 The first outermost sidewall separated from the gate structure 116 and the second lateral distance d L2 An opposite second outermost sidewall is separated from the drain region 106. In other embodiments, the field plate etch stop structure 3404 may extend to directly above the gate structure 116 and / or the drain region 106.

[0163] The field plate 122 is disposed on the field plate etch stop structure 3404. The field plate 122 includes the same material as the plurality of contacts 120 (e.g., tungsten, cobalt, etc.). The bottommost surface of the field plate 122 is vertically between the bottom surface and the top surface of the plurality of contacts 120. For example, the bottommost surface of the field plate 122 can be arranged along a horizontal plane 3405 that is parallel to the upper surface of the substrate 102 and extends through the sidewalls of the plurality of contacts 120. The bottommost surface of the field plate 122 is at a distance d V Separated from the semiconductor substrate 102. In some embodiments, the distance d V has a value between about 400 angstroms and about 700 angstroms. The breakdown voltage of the high voltage transistor device 3400 and the distance d V For example, as the distance d V decreases, the breakdown voltage of the high voltage transistor device 3400 also decreases.

[0164] The field plate etch stop structure 3404 includes a material having a high etch selectivity relative to the first ILD layer 3402 and the second ILD layer 3406. For example, in various embodiments, the field plate etch stop structure 3404 may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y )、amorphous silicon (a-Si), hafnium oxide (HfO x )、ZrO x), metal oxide, etc. In various embodiments, the field plate etch stop structure 3404 may have a thickness t in a range between about 1 nanometer and about 100 nanometers. In various embodiments, the field plate etch stop structure 3404 may have a width w in a range between about 10 nanometers and about 1,000 nanometers. High etch selectivity allows the field plate 122 to be formed simultaneously with the plurality of contacts 120 while providing a vertical offset between the bottommost surface of the field plate 122 and the bottom surface of the plurality of contacts 120. The vertical offset provides a distance d between the bottommost surface of the field plate 122 and the semiconductor substrate 102. V Good control of (i.e., good control of the breakdown voltage of the high voltage transistor device 3400).

[0165] Fig.35 Cross-sectional views of some additional embodiments of a high voltage transistor device 3500 having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact are shown.

[0166] The high voltage transistor device 3500 includes a field plate etch stop structure 3404 disposed above the first ILD layer 3402. In some embodiments, the field plate etch stop structure 3404 may have sidewalls oriented at a non-zero angle relative to a line perpendicular to the upper surface of the first ILD layer 3402. For example, in some embodiments, the non-zero angle may be in a range between 0° and approximately 30°.

[0167] The second ILD layer 3406 is disposed over the field plate etch stop structure 3404 and the first ILD layer 3402. In some embodiments, the first ILD layer 3402 includes sidewalls 3502s of the protrusion 3502 defined below the field plate etch stop structure 3404. In such embodiments, the second ILD layer 3406 laterally contacts the first ILD layer 3402 along the sidewalls 3502s.

[0168] Fig.36 Cross-sectional views of some additional embodiments of a high voltage transistor device 3600 having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact are shown.

[0169] The high voltage transistor device 3600 includes a metal gate structure 3602 disposed above the semiconductor substrate 102 between the source region 104 and the drain region 106. The metal gate structure 3602 includes a metal gate electrode 3604 separated from the substrate by a gate dielectric 3606. In some embodiments, the metal gate electrode 3604 may include aluminum, ruthenium, palladium, hafnium, zirconium, titanium, etc. In some embodiments, the gate dielectric 3606 includes a high-k dielectric, such as hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide, zirconium oxide, etc.

[0170] A contact etch stop layer (CESL) 406 is disposed over the semiconductor substrate 102. The CESL 406 has an uppermost surface 406u laterally adjacent to the metal gate structure 3602. The first ILD layer 3402 is disposed over the CESL 406. In some embodiments, the metal gate structure 3602, the CESL 406, and the first ILD layer 3402 have an uppermost surface that is substantially flat (e.g., a plane within the tolerance of a chemical mechanical planarization process). The second ILD layer 3406 is disposed over the first ILD layer 3402. The second ILD layer 3406 contacts the upper surfaces of the metal gate structure 3602, the CESL 406, and the first ILD layer 3402.

[0171] The field plate etch stop structure 3404 is disposed above the uppermost surface of the first ILD layer 3402 at a position laterally between the metal gate structure 3602 and the drain region 106. The field plate etch stop structure 3404 has a bottom surface disposed along a horizontal plane extending along the metal gate structure 3602, the CESL 406, and the uppermost surface of the first ILD layer 3402. In some embodiments (not shown), the first ILD layer 3402 may be recessed between the outermost sidewalls of the field plate etch stop structure 3404 and the CESL 406. The field plate 122 is above the field plate etch stop structure 3404. The field plate 122 extends from the top of the second ILD layer 3406 to the field plate etch stop structure 3404 such that the bottommost surface of the field plate 122 is above the top of the metal gate structure 3602.

[0172] Fig.37 Cross-sectional views of some additional embodiments of a high voltage transistor device 3700 having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact are shown.

[0173] The high voltage transistor device 3700 includes a metal gate structure 3602 disposed over a semiconductor substrate 102 between a source region 104 and a drain region 106. A CESL 406 is disposed over the semiconductor substrate 102 and has an uppermost surface 406u laterally adjacent to the metal gate structure 3602. A first ILD layer 3402 is disposed over the CESL 406. A second ILD layer 3406 is disposed over the first ILD layer 3402. The second ILD layer 3406 contacts the metal gate structure 3602, the CESL 406, and an uppermost surface of the first ILD layer 3402.

[0174] The first ILD layer 3402 has sidewalls 3402s defining a cavity 3702 within the first ILD layer 3402 between the metal gate structure 3602 and the drain region 106. In some embodiments, the sidewalls 3402s extend from the uppermost surface of the first ILD layer 3402 to the CESL 406 such that the bottom of the cavity 3702 is defined by the CESL 406.

[0175] In some embodiments, a dielectric material 3704 is disposed within the cavity 3702, and a field plate etch stop structure 3404 is disposed within the cavity 3702 above the dielectric material 3704. In some embodiments, the dielectric material 3704 may include an oxide (e.g., silicon oxide), a nitride, and the like. In some other embodiments, where the field plate etch stop structure 3404 is a dielectric, the dielectric material 3704 may be omitted (e.g., such that the field plate etch stop structure 3404 contacts the CESL 406). A second ILD layer 3406 is disposed above the first ILD layer 3402, and the field plate 122 is above the field plate etch stop structure 3404. The field plate 122 is laterally surrounded by the second ILD layer 3406. The field plate 122 extends from the top of the second ILD layer 3406 to the field plate etch stop structure 3404.

[0176] In some embodiments, the field plate etch stop structure 3404 extends from the top of the dielectric material 3704 to the top of the first ILD layer 3402. In such embodiments, the bottom of the field plate 122 is separated by a distance d defined by the dielectric material 3704, the field plate etch stop structure 3404, and the CESL 406. V Separated from the semiconductor substrate 102. In some embodiments, the distance d V Substantially equal to the thickness of the first ILD layer 3402 .

[0177] exist Fig.38 In other embodiments shown in cross-sectional view 3800, the field plate etch stop structure 3404 has a non-zero distance d r The uppermost surface of the field plate 122 is recessed below the uppermost surface of the first ILD layer 3402. Recessing the field plate etch stop structure 3404 below the uppermost surface of the first ILD layer 3402 allows a distance d between the bottommost surface of the field plate 122 and the semiconductor substrate 102. V Reduced to be lower than the thickness of the first ILD layer 3402 .

[0178] Fig.39 Cross-sectional views of some additional embodiments of a high voltage transistor device 3900 having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact are shown.

[0179] The high voltage transistor device 3900 includes an RPO 2002 disposed laterally between a metal gate structure 3602 and a CESL 406 and vertically between a semiconductor substrate 102 and the CESL 406. A first ILD layer 3402 is disposed over the CESL 406, and a second ILD layer 3406 is disposed over the first ILD layer 3402. The second ILD layer 3406 contacts the metal gate structure 3602, the CESL 406, and an uppermost surface of the first ILD layer 3402.

[0180] The sidewalls of the first ILD layer 3402 and the second ILD layer 3406 define a cavity 3902 that extends vertically from the top of the second ILD layer 3406 to the CESL 406 and laterally between the metal gate structure 3602 and the drain region 106. A dielectric material 3704 is disposed within the cavity 3902, and a field plate etch stop structure 3404 is disposed within the cavity 3902 above the dielectric material 3704. In some embodiments, the field plate etch stop structure 3404 extends from the top of the dielectric material 3704 to the top of the second ILD layer 3406. In other embodiments (not shown), the field plate etch stop structure 3404 may have an uppermost surface that is recessed below the top of the second ILD layer 3406.

[0181] The third ILD layer 3408 is disposed above the second ILD layer 3406. The field plate 122 extends through the third ILD layer 3408 to the field plate etch stop structure 3404. The bottommost surface of the field plate 122 is at a non-zero distance d v The first ILD layer 3402 and the second ILD layer 3406 are used to define the cavity 3902 to allow a larger range of non-zero distances d v .

[0182] Figures 40 to 50 Cross-sectional views 4000 to 5000 are shown illustrating some embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate, the field plate including a bottom surface vertically offset from a bottom surface of a conductive contact. Figures 40 to 50 4000 to 5000, but it should be understood that Figures 40 to 50 The structures depicted in the drawings are not limited to the methods and can in fact stand alone independently of the methods.

[0183] like Fig.40As shown in the cross-sectional view 4000 of FIG. 4001 , the semiconductor substrate 102 is selectively implanted to form a plurality of implant regions (e.g., well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form a body region 2106, a drift region 2104, a source region 104, and a drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implant regions (e.g., Figures 1 to 10 ). In some embodiments, multiple implant regions may be formed by selectively masking semiconductor substrate 102 (e.g., using a photoresist mask) and then introducing a high energy dopant (e.g., a p-type dopant species such as boron or an n-type dopant such as phosphorus) into exposed areas of semiconductor substrate 102.

[0184] A gate structure 116 having a gate dielectric layer 110 and a gate electrode material 108 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by depositing a gate dielectric layer over the semiconductor substrate 102 and by depositing a gate electrode material over the gate dielectric layer. The gate dielectric layer and the gate electrode material may then be patterned (e.g., etched according to a photoresist mask and / or a hard mask) to define the gate structure 116.

[0185] like Fig.41 As shown in the cross-sectional view 4100 of FIG. 1 , a photoresist protective oxide (RPO) layer 4102 is formed over the gate structure 116. The RPO 4102 is configured to block the formation of silicide on the bottom layer. In some embodiments, the RPO layer 4102 may be deposited by a vapor deposition technique (e.g., CVD). In some embodiments, the RPO layer 4102 may include silicon dioxide (SiO2), silicon nitride, and the like.

[0186] like Fig.42 As shown in the cross-sectional view 4200, the RPO layer ( Fig.41 The RPO layer 4102 is selectively patterned to define the RPO 2002. In some embodiments, the RPO layer is selectively patterned so that the RPO 2002 extends from a first outermost sidewall directly above the gate structure 116 to a second outermost sidewall laterally between the gate structure 116 and the drain region 106. In some embodiments, the RPO layer can be selectively patterned by forming a masking layer 2702 over the RPO layer and then exposing the RPO layer to an etchant in areas not covered by the masking layer 2702.

[0187] like Fig.43As shown in the cross-sectional view 4300 of FIG. 43, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the RPO 2002. In some embodiments, the CESL 406 may be formed by a vapor deposition process. The CESL 406 may include a nitride layer (e.g., Si3N4), a carbide layer (SiC), and the like.

[0188] like Fig.44 As shown in the cross-sectional view 4400 of FIG. 4 , a first interlayer dielectric (ILD) layer 3402 is formed over the CESL 406. In some embodiments, the first ILD layer 3402 may include an oxide (e.g., SiO2), an ultra-low-k dielectric material, a low-k dielectric material (e.g., SiCO), etc. In some embodiments, the first ILD layer 3402 may be formed by a vapor deposition process.

[0189] like Fig.45 As shown in the cross-sectional view 4500 of FIG. 45, a field plate etch stop layer 4502 is formed above the first ILD layer 3402. In various embodiments, the field plate etch stop structure 4502 may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y )、amorphous silicon (a-Si), hafnium oxide (HfO x )、ZrO x ), metal oxide, etc. In various embodiments, the field plate etch stop layer 4502 may be formed to have a thickness ranging from about 1 nanometer to about 150 nanometers.

[0190] like Fig.46 As shown in the cross-sectional view 4600, the field plate etch stop layer ( Fig.45 The field plate etch stop layer 4502 of the embodiment of the present invention is patterned to define a field plate etch stop structure 3404 above the first ILD layer 3402. In some embodiments, the field plate etch stop layer can be selectively patterned by forming a masking layer 4604 over the field plate etch stop layer and then exposing the field plate etch stop layer to an etchant 4602 in the areas not covered by the masking layer 4604. In some embodiments, the etchant 4602 can include ions for ion bombardment etching. In other embodiments, the etchant 4602 can include a plasma etchant (e.g., with a fluorine chemistry, a chlorine chemistry, etc.).

[0191] like Fig.47As shown in the cross-sectional view 4700 of FIG. 47A , the second ILD layer 3406 is formed over the first ILD layer 3402 and the field plate etch stop structure 3404. In some embodiments, the second ILD layer 3406 may include an oxide (e.g., SiO2), an ultra-low-k dielectric material, a low-k dielectric material (e.g., SiCO), etc. In some embodiments, the second ILD layer 3406 may be formed by a vapor deposition process. In some embodiments, the second ILD layer 3406 is formed in direct contact with the first ILD layer 3402.

[0192] like Fig.48 4800, an etching process is performed to simultaneously define a plurality of contact openings 1606 and field plate openings 1608. The plurality of contact openings 1606 are defined by the sidewalls of the first ILD layer 3402 and the second ILD layer 3406. The resulting field plate openings 1608 are defined by the second ILD layer 3406 and the upper surface of the field plate etch stop structure 3404. The etching process uses an etchant that is highly selective between the field plate etch stop structure 3404 and the first ILD layer 3402 and the second ILD layer 3406 (e.g., the etchant etches the first ILD layer 3402 and the second ILD layer 3406 faster than the field plate etch stop structure 3404), so that the contact openings 1606 and the field plate openings 1608 have an etch depth offset of a non-zero distance.

[0193] Since the thickness of a deposition process is generally easier to control than the depth of an etching process, the distance between the bottom of the field plate opening 1608 and the semiconductor substrate 102 can be well controlled (as it is defined by the thickness of the deposition process used to form the CESL 406, the first ILD layer 3402, and the field plate etch stop structure 3404), thereby obtaining a field plate with well-defined electrical properties (e.g., well-defined breakdown voltage). In some embodiments, the distance between the bottom of the field plate opening 1608 and the semiconductor substrate 102 can be in a range between about 400 angstroms and about 700 angstroms.

[0194] like Fig.49As shown in the cross-sectional view 4900 of , the contact openings 1606 and the field plate openings 1608 are filled with one or more conductive materials to define the plurality of contacts 120 and the field plates 122. In some embodiments, the one or more conductive materials may be deposited by means of a deposition technique (e.g., CVD, PVD, PE-CVD, sputtering, etc.) and / or a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess one or more conductive materials and form a planar surface along line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), cobalt (Co), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN), etc. In some embodiments, before depositing the one or more conductive materials, a diffusion barrier layer and / or a liner layer may be deposited into the contact openings 1606 and the field plate openings 1608.

[0195] like Fig.50 As shown in the cross-sectional view 5000 of FIG. 5001 , the third ILD layer 3408 is formed over the second ILD layer 3406, and the first back-end-of-line (BEOL) metal line layer 128 is formed in the third ILD layer 3408. In various embodiments, the third ILD layer 3408 may be formed by depositing a third ILD material over the second ILD layer 3406. The third ILD layer 3408 is then etched to form a trench extending in the third LD layer 3408. The trench is filled with a conductive material, and a planarization process (e.g., CMP) is performed to remove excess conductive material from over the second ILD layer 3406.

[0196] Figure 51 to Figure 65 Cross-sectional views 5100 to 6500 are shown illustrating some additional embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate, the field plate including a bottom surface vertically offset from a bottom surface of a conductive contact. Figure 51 to Figure 65 5100 to 6500 are shown, but it should be understood that Figure 51 to Figure 65 The structures depicted in the drawings are not limited to the methods and can in fact stand alone independently of the methods.

[0197] like Fig.51 As shown in the cross-sectional view 5100 of FIG. 51 , the semiconductor substrate 102 is selectively implanted to form a plurality of implant regions (e.g., well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form a body region 2106, a drift region 2104, a source region 104, and a drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implant regions (e.g., Figures 1 to 10 any of those implant regions shown in FIG.

[0198] The sacrificial gate structure 5102 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The sacrificial gate structure 5102 includes a sacrificial gate electrode 5104. In some embodiments, the sacrificial gate electrode 5104 may include polysilicon. In some embodiments, the sacrificial gate structure 5102 may also include a gate dielectric 3606 separating the sacrificial gate electrode 5104 from the semiconductor substrate 102. In some embodiments, the gate dielectric 3606 may include a high-k dielectric material.

[0199] like Fig.52 As shown in the cross-sectional view 5200 of FIG. 5200 , a photoresist protective oxide (RPO) layer 4102 is formed over the sacrificial gate structure 5102. In some embodiments, the RPO layer 4102 may be deposited by a vapor deposition technique (e.g., CVD, PVD, etc.). In some embodiments, the RPO layer 4102 may include silicon dioxide (SiO2), silicon nitride, etc.

[0200] like Fig.53 As shown in the cross-sectional view 5300, the RPO layer ( Fig.52 The RPO layer 4102 is selectively patterned to define the RPO 2002. In some embodiments, the RPO layer is selectively patterned so that the RPO 2002 extends from a first outermost sidewall directly above the sacrificial gate structure 5102 to a second outermost sidewall laterally between the sacrificial gate structure 5102 and the drain region 106. In some embodiments, the RPO layer may be selectively patterned by forming a masking layer 2702 over the RPO layer and then exposing the RPO layer to an etchant in areas not covered by the masking layer 2702.

[0201] like Fig.54 As shown in the cross-sectional view 5400 of FIG. 5 , a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the RPO 2002. In some embodiments, the CESL 406 may be formed by a vapor deposition process. The CESL 406 may include a nitride layer (e.g., Si3N4), a carbide layer (SiC), and the like.

[0202] like Fig.55 As shown in cross-sectional view 5500 of , a first interlayer dielectric (ILD) layer 3402 is formed over the CESL 406 .

[0203] like Fig.56As shown in the cross-sectional view 5600 of FIG. 5102 , a first planarization process is performed along line 5602. The first planarization process removes portions of the first ILD layer 3402, CESL 406, and RPO 2002 over the sacrificial gate structure 5102. By removing portions of the first ILD layer 3402, CESL 406, and RPO 2002 over the sacrificial gate structure 5102, the top of the sacrificial gate electrode 5104 is exposed.

[0204] like Fig.57 As shown in cross-sectional view 5700 of , the sacrificial gate structure 5102 is removed to form a replacement gate cavity 5702 between the sidewalls of the CESL 406. In some embodiments, the sacrificial gate structure 5102 may be removed using an etchant that is selected relative to the sacrificial gate structure 5102.

[0205] like Fig.58 5800, a metal gate electrode 3604 is formed within the replacement gate cavity 5702 to define the metal gate structure 3602. In some embodiments, the metal gate electrode 3604 may be formed by depositing a conductive material (e.g., aluminum, tantalum, nickel, molybdenum, etc.) within the replacement gate cavity 5702 using a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.). In some embodiments (not shown), one or more gate dielectrics may be formed in the replacement gate cavity 5702 prior to the deposition of the conductive material. A second planarization process (e.g., a CMP process) is performed (along line 5806) after the conductive material is deposited within the replacement gate cavity 5702. The second planarization process removes the conductive material from above the first ILD layer 3402 to define the metal gate electrode 3604.

[0206] like Fig.59 As shown in the cross-sectional view 5900 of , an etching process is performed to define a cavity 3702 within the first ILD layer 3402, between the metal gate structure 3602 and the drain region 106. The cavity 3702 is defined by the sidewalls of the first ILD layer 3402 and the upper surface of the CESL 406. In some embodiments, the cavity 3702 may be defined such that a masking layer (not shown) is formed over the first ILD layer 3402 and then the first ILD layer 3402 is exposed to an etchant in areas not covered by the masking layer.

[0207] like Fig.60As shown in cross-sectional view 6000 of FIG. 3 , dielectric material 3704 is formed within cavity 3702. In some embodiments, dielectric material 3704 may include an oxide (e.g., silicon oxide), a nitride, etc. In some embodiments, dielectric material 3704 may be formed by a deposition process (e.g., CVD, PE-CVD, PVD, ALD, etc.), followed by removal of the dielectric material from outside cavity 3702 by a chemical mechanical planarization (CMP) process and / or an etching process.

[0208] like Fig.61 As shown in the cross-sectional view 6100 of FIG. 61, the field plate etch stop structure 3404 is formed in the cavity 3702 above the dielectric material 3704. In various embodiments, the field plate etch stop structure 3404 may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y )、amorphous silicon (a-Si), hafnium oxide (HfO x )、ZrO x ), metal oxide, etc. In various embodiments, the field plate etch stop structure 3404 may be formed to have a thickness in a range between about 1 nanometer and about 150 nanometers. In some embodiments, the field plate etch stop structure 3404 may be formed by depositing a field plate etch stop material (e.g., silicon nitride, amorphous silicon, metal oxide, etc.), followed by removing the dielectric material and / or the field plate etch stop material from outside the cavity 3702 by a chemical mechanical planarization (CMP) process and / or an etching process.

[0209] like Fig.62 As shown in the cross-sectional view 6200 , the second ILD layer 3406 is formed over the first ILD layer 3402 and the field plate etch stop structure 3404 .

[0210] like Fig.63 As shown in the cross-sectional view 6300 of FIG. 63, an etching process is performed to simultaneously define a plurality of contact openings 1606 and field plate openings 1608. In some embodiments, the etching process exposes the upper surface of the second ILD layer 3406 to the etchant 3002 in the area not covered by the masking layer 3003 to define a plurality of contact openings 1606 and field plate openings 1608. The plurality of contact openings 1606 are defined by the sidewalls of the first ILD layer 3402 and the second ILD layer 3406. The field plate openings 1608 are defined by the sidewalls of the second ILD layer 3406 and the upper surface of the field plate etch stop structure 3404. The contact openings 1606 and the field plate openings 1608 have an etch depth offset of a non-zero distance. In some embodiments, the non-zero depth may be in the range of about 400 angstroms to about 700 angstroms.

[0211] like Fig.64As shown in the cross-sectional view 6400 of FIG. 31 , the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials. In some embodiments, the one or more conductive materials may be deposited by means of a vapor deposition technique (e.g., CVD, PVD, PE-CVD, sputtering, etc.) and / or a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess one or more conductive materials and form a planar surface along line 3102.

[0212] like Fig.65 As shown in the cross-sectional view 6500 of , the third ILD layer 3408 is formed over the second ILD layer 3406 , and the first back-end of line (BEOL) metal line layer 128 is formed within the third ILD layer 3408 .

[0213] Figure 66 to Figure 76 Cross-sectional views 6600 to 7600 are shown illustrating some additional embodiments of a method of forming a high voltage transistor device having a field plate etch stop structure defining a field plate, the field plate including a bottom surface vertically offset from a bottom surface of a conductive contact. Figure 66 to Figure 76 6600 to 7600 are shown, but it should be understood that Figure 66 to Figure 76 The structures depicted in the drawings are not limited to the methods and can in fact stand alone independently of the methods.

[0214] like Fig.66 As shown in the cross-sectional view 6600 of FIG. 66, the semiconductor substrate 102 is selectively implanted to form a plurality of implant regions (e.g., well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 can be selectively implanted to form a body region 2106, a drift region 2104, a source region 104, and a drain region 106. In other embodiments, the semiconductor substrate 102 can be selectively implanted to form different implant regions (e.g., Figures 1 to 10 any of those implant regions shown in FIG.

[0215] The sacrificial gate structure 5102 is formed over the semiconductor substrate 102 between the source region 104 and the drain region 106. The sacrificial gate structure 5102 includes a sacrificial gate electrode 5104. In some embodiments, the sacrificial gate electrode 5104 may include polysilicon. In some embodiments, the sacrificial gate structure 5102 may also include a gate dielectric 3606 separating the sacrificial gate electrode 5104 from the semiconductor substrate 102. In some embodiments, the gate dielectric 3606 may include a high-k dielectric material.

[0216] like Fig.67As shown in the cross-sectional view 6700 of FIG. 67 , a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the sacrificial gate structure 5102. In some embodiments, the CESL 406 may be formed by a vapor deposition process. The CESL 406 may include a nitride layer (e.g., Si3N4), a carbide layer (SiC), and the like.

[0217] like Fig.68 As shown in cross-sectional view 6800 of , a first interlayer dielectric (ILD) layer 3402 is formed over the CESL 406 .

[0218] like Fig.69 As shown in cross-sectional view 6900 of FIG. 5 , a first planarization process is performed along line 5602. The first planarization process removes portions of the first ILD layer 3402 and the CESL 406 from above the sacrificial gate structure 5102. By removing portions of the first ILD layer 3402 and the CESL 406 from above the sacrificial gate structure 5102, a top portion of the sacrificial gate electrode 5104 is exposed.

[0219] like Fig.70 As shown in cross-sectional view 7000 of FIG. 5 , the sacrificial gate structure 5102 is removed to form a replacement gate cavity 5702 between the sidewalls of the CESL 406. In some embodiments, the sacrificial gate structure 5102 may be removed by using an etchant selected relative to the sacrificial gate structure 5102. A metal gate electrode 3604 is then formed within the replacement gate cavity 5702 to define the metal gate structure 3602. In some embodiments, the metal gate electrode 3604 may be formed by depositing a conductive material within the replacement gate cavity 5702. In some embodiments, one or more gate dielectrics may be formed in the replacement gate cavity 5702 prior to the deposition of the conductive material. A second planarization process (e.g., a CMP process) is performed (along line 5806) after the conductive material is deposited within the replacement gate cavity 5702. The second planarization process (along line 5806) removes the conductive material from above the first ILD layer 3402 to define the metal gate electrode 3604.

[0220] like Fig.71 As shown in the cross-sectional view 7100 of , an etching process is performed to define a cavity 3702 within the first ILD layer 3402, between the metal gate structure 3602 and the drain region 106. The cavity 3702 is defined by the sidewalls of the first ILD layer 3402 and the upper surface of the CESL 406. In some embodiments, the cavity 3702 may be defined such that a masking layer (not shown) is formed over the first ILD layer 3402 and then the first ILD layer 3402 is exposed to an etchant in areas not covered by the masking layer.

[0221] like Fig.72As shown in the cross-sectional view 7200 of FIG. 7201 , a dielectric material 3704 is formed within the cavity 3702. In some embodiments, the dielectric material 3704 may include an oxide (e.g., silicon oxide), a nitride, etc. A field plate etch stop structure 3404 is then formed within the cavity 3702, above the dielectric material 3704. In various embodiments, the field plate etch stop structure 4502 may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y )、amorphous silicon (a-Si), hafnium oxide (HfO x )、ZrO x ), metal oxide, etc. In some embodiments, the field plate etch stop layer 4502 may be formed by depositing a field plate etch stop material (e.g., CVD, PE-CVD, PVD, ALD, etc.), followed by a chemical mechanical planarization process and / or an etching process to remove the dielectric material and / or the field plate etch stop material from outside the cavity 3702.

[0222] like Fig.73 As shown in the cross-sectional view 7300 , the second ILD layer 3406 is formed over the first ILD layer 3402 and the field plate etch stop structure 3404 .

[0223] like Fig.74 As shown in the cross-sectional view 7400 of FIG. 74, an etching process is performed to simultaneously define a plurality of contact openings 1606 and field plate openings 1608. The plurality of contact openings 1606 are defined by the sidewalls of the first ILD layer 3402 and the second ILD layer 3406. The field plate openings 1608 are defined by the upper surface of the second ILD layer 3406 and the field plate etch stop structure 3404. The contact openings 1606 and the field plate openings 1608 have an etch depth offset of a non-zero distance. In some embodiments, the non-zero depth may be in a range of about 400 angstroms to about 700 angstroms.

[0224] like Fig.75 As shown in the cross-sectional view 7500 of FIG. 75, the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials. In some embodiments, the one or more conductive materials may be deposited by means of a vapor deposition technique (e.g., CVD, PVD, PE-CVD, sputtering, etc.) and / or a plating process (e.g., electroplating or electroless plating process). A planarization process (e.g., chemical mechanical planarization) may then be performed to remove excess one or more conductive materials from above the second ILD layer 3406.

[0225] like Fig.76 As shown in the cross-sectional view 7600 of , the third ILD layer 3408 is formed over the second ILD layer 3406 , and the first back-end of line (BEOL) metal line layer 128 is formed within the third ILD layer 3408 .

[0226] Fig.77 A flow chart illustrating some embodiments of a method 7700 of forming a high voltage transistor device having a field plate etch stop structure defining a field plate, the field plate comprising a bottom surface vertically offset from a bottom surface of a conductive contact.

[0227] At act 7702, a gate structure is formed over a substrate. Fig.40 , Fig.51 as well as Fig.66 Cross-sectional view 4000 , cross-sectional view 5100 , and cross-sectional view 6600 are shown corresponding to various embodiments of action 7702 .

[0228] At act 7704, source and drain regions are formed within the substrate, on opposite sides of the gate structure. In some additional embodiments, one or more additional doped regions (eg, body regions, drift regions, etc.) may also be formed within the substrate. Fig.40 , Fig.51 as well as Fig.66 Cross-sectional view 4000 , cross-sectional view 5100 , and cross-sectional view 6600 are shown corresponding to various embodiments of action 7704 .

[0229] At action 7706, a photoresist protective oxide (RPO) can be formed over the gate structure and laterally between the gate structure and the drain region. Figure 41 to Figure 42 as well as Figure 52 to Figure 53 Cross-sectional views 4100 - 4200 and 5200 - 5300 corresponding to various embodiments of act 7706 are shown.

[0230] At act 7708, a contact etch stop layer (CESL) is formed over the gate structure and the substrate. Fig.43 , Fig.54 as well as Fig.67 Cross-sectional view 4300 , cross-sectional view 5400 , and cross-sectional view 6700 are shown corresponding to various embodiments of action 7708 .

[0231] At act 7710, a first inter-layer dielectric (ILD) layer is formed over the CESL. Fig.44 , Fig.54 as well as Fig.68 Cross-sectional view 4400 , cross-sectional view 5400 , and cross-sectional view 6800 corresponding to various embodiments of action 7710 are shown.

[0232] At act 7712, a field plate etch stop structure is formed after the first ILD layer is formed. Figure 45 to Figure 46 , Figure 59 to Figure 61 as well as Figure 71 to Figure 72Cross-sectional views 4500 - 4600 , 5900 - 6100 , and 7100 - 7200 corresponding to various embodiments of action 7712 are shown.

[0233] At activity 7714, a second ILD layer is formed over the first ILD layer and the field plate etch stop structure. Fig.47 , Fig.62 as well as Fig.73 Cross-sectional view 4700 , cross-sectional view 6200 , and cross-sectional view 7300 are shown corresponding to various embodiments of action 7714 .

[0234] At act 7716, the first ILD layer and the second ILD layer are selectively etched to simultaneously define a plurality of contact openings extending through the first ILD layer and the second ILD layer and a field plate opening extending through the second ILD layer to the field plate etch stop structure. Fig.48 , Fig.63 as well as Fig.74 Cross-sectional view 4800 , cross-sectional view 6300 , and cross-sectional view 7400 are shown corresponding to various embodiments of action 7716 .

[0235] At activity 7718, the plurality of contact openings and the field plate openings are filled with one or more conductive materials. Fig.49 , Fig.64 as well as Fig.75 Cross-sectional view 4900 , cross-sectional view 6400 , and cross-sectional view 7500 are shown corresponding to various embodiments of action 7718 .

[0236] At act 7720, a conductive interconnect is formed in a third ILD layer above the second ILD layer. Fig.50 , Fig.65 as well as Fig.76 Cross-sectional view 5000 , cross-sectional view 6500 , and cross-sectional view 7600 are shown corresponding to various embodiments of action 7720 .

[0237] Accordingly, the present disclosure is directed to a high voltage transistor device having a field plate etch stop structure defining a field plate including a bottom surface vertically offset from a bottom surface of a conductive contact.

[0238] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: a gate structure disposed above a substrate, between a source region and a drain region; a first interlayer dielectric (ILD) layer disposed above the substrate and the gate structure; a second ILD layer disposed above the first ILD layer; a field plate etch stop structure between the first ILD layer and the second ILD layer; a field plate extending from the uppermost surface of the second ILD layer to the field plate etch stop structure; and a plurality of conductive contacts extending from the uppermost surface of the second ILD layer to the source region and the drain region. In some embodiments, the integrated chip further includes a dielectric layer extending laterally from directly above the gate structure to between the gate structure and the drain region; and a contact etch stop layer disposed above the substrate, the dielectric layer, and the gate structure. In some embodiments, the bottommost surface of the field plate is arranged along a horizontal plane parallel to the upper surface of the substrate and extending through the sidewalls of the plurality of conductive contacts. In some embodiments, the field plate etch stop structure has a bottommost surface above the topmost surface of the first ILD layer. In some embodiments, the first ILD layer has sidewalls defining a cavity laterally between the gate structure and the drain region, and the field plate etch stop structure is arranged in the cavity between the sidewalls of the first ILD layer. In some embodiments, the integrated chip further includes a dielectric material disposed in the cavity between the field plate etch stop structure and the substrate. In some embodiments, the integrated chip further includes a contact etch stop layer disposed above the substrate and the gate structure, and the upper surface of the contact etch stop layer defines the bottom of the cavity. In some embodiments, the field plate etch stop structure includes amorphous silicon. In some embodiments, the field plate etch stop structure includes silicon nitride, silicon oxynitride, or metal oxide. In some embodiments, the field plate etch stop structure includes a relatively outermost sidewall laterally between the gate structure and the drain region. In some embodiments, the integrated chip further includes an etch stop layer disposed above the second ILD layer, the bottommost surface of the second ILD layer contacts the first ILD layer, and the topmost surface of the second ILD layer contacts the etch stop layer.

[0239] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: a gate structure disposed above a substrate between a source region and a drain region; a dielectric structure disposed above the substrate and the gate structure; a field plate etch stop structure disposed in the dielectric structure; a plurality of conductive contacts disposed in the dielectric structure; and a field plate disposed on the field plate etch stop structure, the field plate having a bottommost surface arranged along a first horizontal plane parallel to the upper surface of the substrate and intersecting with the sidewalls of the plurality of conductive contacts between the top surface and the bottom surface of the plurality of conductive contacts. In some embodiments, the field plate etch stop structure has a bottommost surface arranged along a second horizontal plane parallel to the first horizontal plane and intersecting with the sidewalls of the plurality of conductive contacts between the top surface and the bottom surface of the plurality of conductive contacts. In some embodiments, the dielectric structure includes a plurality of stacked ILD layers; and the field plate and the plurality of conductive contacts are laterally surrounded by a first ILD layer of the plurality of stacked ILD layers and vertically extend to the top of the first ILD layer. In some embodiments, the dielectric structure includes a first ILD layer and a second ILD layer above the first ILD layer; the conductive contact extends from the bottom of the first ILD layer to the top of the second ILD layer; and the field plate etch stop structure is above a portion of the first ILD layer and below a lower surface of the second ILD layer. In some embodiments, the dielectric structure includes a first ILD layer and a second ILD layer above the first ILD layer; and the field plate etch stop structure contacts the uppermost surface of the first ILD layer.

[0240] In yet other embodiments, the present disclosure relates to a method for forming an integrated chip. The method includes: forming a gate structure between a source region and a drain region above a substrate; forming a contact etch stop layer above the substrate; forming a first ILD layer above the contact etch stop layer; forming a field plate etch stop structure between the gate structure and the drain region after forming the first ILD layer; forming a second ILD layer above the field plate etch stop structure; and simultaneously forming a plurality of contacts extending through the first ILD layer and the second ILD layer and a field plate extending through the second ILD layer to the field plate etch stop structure. In some embodiments, the method further includes forming a field plate etch stop layer above the first ILD layer; and patterning the field plate etch stop layer to define the field plate etch stop structure as having an outermost sidewall between the gate structure and the drain region. In some embodiments, the method further includes selectively patterning the first ILD layer to define a cavity between the gate structure and the drain region; and forming a field plate etch stop structure in the cavity. In some embodiments, the method further includes forming a dielectric material in the cavity; and forming a field plate etch stop structure above the dielectric material.

[0241] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, comprising: A gate structure is disposed above the substrate and between the source region and the drain region; A first interlayer dielectric layer is disposed above the substrate and laterally surrounds the gate structure; a second interlayer dielectric layer disposed above the first interlayer dielectric layer and above the gate structure, wherein the gate structure is located between the substrate and the second interlayer dielectric layer; a field plate etch stop structure having opposing outermost sidewalls laterally between the gate structure and the drain region; a field plate extending from the uppermost surface of the second interlayer dielectric layer to the field plate etch stop structure; as well as A plurality of conductive contacts extend from the uppermost surface of the second interlayer dielectric layer to the source region and the drain region.

2. The integrated chip according to claim 1, further comprising: a dielectric layer extending continuously from along the sidewall of the gate structure to between the gate structure and the drain region; as well as A contact etch stop layer is disposed above the substrate and the dielectric layer, wherein the field plate etch stop structure contacts an upper surface of the contact etch stop layer. 3 . The integrated chip of claim 1 , wherein a bottommost surface of the field plate is arranged along a horizontal plane parallel to an upper surface of the substrate and extending through sidewalls of the plurality of conductive contacts. 4 . The integrated chip according to claim 1 , wherein the first interlayer dielectric layer has sidewalls defining a cavity laterally between the gate structure and the drain region, and the field plate etch stop structure is arranged in the cavity between the sidewalls of the first interlayer dielectric layer.

5. The integrated chip according to claim 4, further comprising: A dielectric material is disposed in the cavity and between the field plate etch stop structure and the substrate.

6. The integrated chip according to claim 4, further comprising: A contact etch stop layer is disposed above the substrate, wherein an upper surface of the contact etch stop layer defines a bottom of the cavity. 7 . The integrated chip of claim 1 , wherein the field plate etch stop structure comprises amorphous silicon. 8 . The integrated chip according to claim 1 , wherein the field plate etch stop structure comprises silicon nitride, silicon oxynitride, or metal oxide. 9 . The integrated chip according to claim 1 , wherein the first interlayer dielectric layer or the second interlayer dielectric layer is directly between the field plate etch structure and a conductive contact of a plurality of conductive contacts.

10. An integrated chip, comprising: A gate structure is disposed above the substrate and between the source region and the drain region; A contact etch stop layer disposed above the substrate and between the gate structure and the drain region; A dielectric structure disposed above the substrate and the gate structure; a field plate etch stop structure disposed within the dielectric structure, wherein the contact etch stop layer extends continuously beyond opposite outermost sidewalls of the field plate etch stop structure; a plurality of conductive contacts disposed within the dielectric structure; as well as A field plate is disposed on the field plate etch stop structure, wherein the field plate has a bottommost surface arranged along a first horizontal plane parallel to the upper surface of the substrate and intersecting sidewalls of the plurality of conductive contacts between top and bottom surfaces of the plurality of conductive contacts.

11. The integrated chip according to claim 10, wherein the field plate etch stop structure has a bottommost surface, which is arranged along a second horizontal plane parallel to the first horizontal plane and intersecting the sidewall of the gate structure between the top surface and the bottom surface of the gate structure.

12. The integrated chip according to claim 10, wherein the dielectric structure comprises a plurality of stacked interlayer dielectric layers; and The field plate and the plurality of conductive contacts are laterally surrounded by a first interlayer dielectric layer among the plurality of stacked interlayer dielectric layers and vertically extend to a top of the first interlayer dielectric layer.

13. The integrated chip according to claim 10, wherein the dielectric structure comprises a first interlayer dielectric layer and a second interlayer dielectric layer above the first interlayer dielectric layer; wherein the conductive contact extends from a bottom of the first interlayer dielectric layer to a top of the second interlayer dielectric layer; and The field plate etch stop structure is above a portion of the first interlayer dielectric layer and below a lower surface of the second interlayer dielectric layer.

14. An integrated chip, comprising: A gate structure is disposed above the substrate and between the source region and the drain region; A first interlayer dielectric layer is disposed above the substrate and laterally surrounds the gate structure; A second interlayer dielectric layer disposed above the first interlayer dielectric layer; a plurality of conductive contacts extending from an upper surface of the second interlayer dielectric layer to the source region and the drain; A field plate etch stop structure is vertically arranged above the substrate and laterally located and directly located between the sidewalls of the first interlayer dielectric layer, or laterally located and directly located between the sidewalls of the second interlayer dielectric layer; as well as The field plate is disposed on the field plate etching stop structure and is laterally located between the side walls of the second interlayer dielectric layer.

15. The integrated chip according to claim 14, further comprising: A dielectric material having a vertical extension section and a lateral extension section, wherein the vertical extension section is arranged along the side wall of the gate structure, and the lateral extension section protrudes outward from the side wall of the vertical extension section toward the drain region, wherein the upper surface of the dielectric material is arranged along a horizontal plane parallel to the upper surface of the substrate and extends through the side wall of the gate structure. 16 . The integrated chip according to claim 14 , wherein the field plate extends continuously from an upper surface of the field plate etch stop structure to above a top of the field plate etch stop structure.

17. The integrated chip according to claim 14, further comprising a contact etch stop layer disposed above the substrate and between the gate structure and the drain region, wherein the contact etch stop layer continuously extends beyond the relatively outermost sidewalls of the field plate etch stop structure. 18 . The integrated chip according to claim 14 , wherein a maximum height of the field plate etch stop structure is smaller than a maximum height of the gate structure.

19. The integrated chip of claim 14, wherein the field plate etch stop structure has an upper surface above a top of the gate structure.

20. The integrated chip of claim 14, wherein the field plate etch stop structure comprises silicon.

21. A method for forming an integrated chip, comprising: forming a gate structure over the substrate between the source region and the drain region; forming a contact etch stop layer over the substrate; forming a first interlayer dielectric layer over the contact etch stop layer; forming a field plate etch stop structure between the gate structure and the drain region after forming the first interlayer dielectric layer; forming a second interlayer dielectric layer over the field plate etch stop structure; as well as Simultaneously forming a plurality of contacts extending through the first interlayer dielectric layer and the second interlayer dielectric layer and a field plate extending through the second interlayer dielectric layer to the field plate etch stop structure, The method further comprises: forming a field plate etch stop layer over the first interlayer dielectric layer; patterning the field plate etch stop layer to define the field plate etch stop structure to have an outermost sidewall between the gate structure and the drain region; selectively patterning the first interlayer dielectric layer to define a cavity between the gate structure and the drain region; and The field plate etch stop structure is formed in the cavity.

22. The method for forming an integrated chip according to claim 21, further comprising: forming a dielectric material within the cavity; as well as The field plate etch stop structure is formed over the dielectric material.

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