High Precision Dual Mode Free-Excited Oscillator

Abstract

A high-precision dual-mode self-excited oscillator. A self-excited oscillator (FRO) includes a reference current generator, a current converter, and a first oscillator core and a second oscillator core. The reference current generator generates a first current. The current converter generates a second current based on the first current. The first oscillator core generates a clock signal of a first frequency based on a first value of the second current. The second oscillator core generates a clock signal of a second frequency based on a second value of the second current. The second frequency may be lower than the first frequency, and the second value of the second current is lower than the first value of the second current.

Description

Technical Field

[0001] Exemplary embodiments disclosed herein generally relate to generating timing signals. Background Art

[0002] Clock signals are used to control a variety of circuits. However, clock signals are not always generated in an efficient manner. For example, many circuits generate clock signals at unnecessarily high frequencies during certain operating modes. In an attempt to improve power management, the system clock can be switched to a low-frequency mode when system activity is reduced, such as during low-power mode or sleep mode. However, implementing this approach requires the use of additional trimming or biasing circuits, especially for higher precision applications implemented in the low-frequency mode. The use of trimming and biasing circuits increases the cost and complexity of the chip. These circuits also consume a large amount of chip space and memory bits. Summary of the invention

[0003] A brief summary of multiple exemplary embodiments is given below. Some simplifications and omissions may occur in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, rather than to limit the scope of the present invention. A detailed description of the exemplary embodiments sufficient to allow a person of ordinary skill in the art to make and use the inventive concept will be given in the following section.

[0004] According to one or more embodiments, an oscillator includes: a reference current generator configured to generate a first current; a converter configured to generate a second current based on the first current; a first oscillator core configured to generate a clock signal at a first frequency; and a second oscillator core configured to generate a clock signal at a second frequency lower than the first frequency. The first oscillator core generates a clock signal at a first frequency based on a first value of the second current. The second oscillator core generates a clock signal at a second frequency based on a second value of the second current. The second value is lower than the first value.

[0005] The reference current generator may include a first current mirror having a scalable mirror ratio. The first current mirror may include a selector configured to couple to a first transistor in the first current mirror to achieve a first mirror ratio and to couple to a second transistor in the first current mirror to achieve a second mirror ratio, the second transistor having at least one parameter different from the first transistor. Adjusting the ratio of the first current mirror may generate a corresponding change in a second current output by the converter.

[0006] The first current mirror may output a first value of the first current for a first mirror ratio and a second value of the first current for a second mirror ratio, and the converter may generate a first value of the second current based on the first mirror ratio and a second value of the second current based on the second mirror ratio. The converter may include: a second current mirror configured to receive the first current; and a trimming circuit coupled to the second current mirror and configured to trim an output current of the second current mirror based on a first trimming code. The second current mirror may include a first branch and a second branch, the first branch including a first transistor, the second branch including a plurality of second transistors, wherein the plurality of second transistors mirror a current flowing through the first branch, and the trimming circuit may be coupled to the plurality of second transistors to output a second current.

[0007] The first oscillator core may include a plurality of first inverters, the second oscillator core may include a plurality of second inverters, and a size of one or more transistors in the plurality of second inverters may be smaller than a size of one or more transistors in the plurality of first inverters. The size may correspond to at least one of a transistor width and a transistor length.

[0008] The second oscillator core may include gate and drain dummy devices to match the self-capacitive loading of the plurality of second inverters in the second oscillator core to the capacitive loading of the plurality of first inverters in the first oscillator core. The second oscillator core may scale the output frequency of the second oscillator core from the frequency of the first oscillator core by scaling the width-to-length ratio of the pull-up and pull-down devices in the plurality of second inverters of the second oscillator core.

[0009] The oscillator may include a first ripple counter (or delay unit) and a second ripple counter (or delay unit), wherein the first ripple counter (or delay unit) and the second ripple counter (or delay unit) are coupled to the first oscillator core and the second oscillator core, wherein the ripple counters are configured to control the outputs of the first oscillator core and the second oscillator core based on one or more predetermined delays, wherein the one or more predetermined delays control the conversion of the clock signal at the second frequency to the clock signal at the first frequency or the conversion of the clock signal at the first frequency to the clock signal at the second frequency at a predetermined rate.

[0010] According to one or more embodiments, an oscillator includes: a first current mirror configured to generate a first current; a second current mirror configured to generate a second current; and a selector configured to select a mirror ratio of the first current mirror, wherein the first current mirror is configured to generate a first value of the first current when the selector selects the first mirror ratio, and to generate a second value of the first current when the selector selects the second mirror ratio, and wherein the second current mirror is used to generate a first value of the second current based on the first value of the first current and to generate a second value of the second current based on the second value of the first current. The first value of the second current can control the generation of a clock signal at a first frequency, and the second value of the second current can control the generation of a clock signal at a second frequency.

[0011] The selector may couple the first transistor in the first current mirror based on a first value of the control signal, and may couple the second transistor in the first current mirror based on a second value of the control signal.The first and second transistors may be different sizes.

[0012] The second current mirror may include a first transistor, a plurality of second transistors coupled to the first transistor, and a switch circuit coupled to the plurality of second transistors and configured to adjust the second current based on a trimming code. The switch circuit may include a plurality of switches, the trimming code may include a plurality of bit values, and each of the plurality of bit values ​​may control a corresponding one of the switches.

[0013] According to one or more embodiments, an oscillator includes: a first current mirror configured to generate a first current; and a converter configured to convert the first current into a second current; and an oscillator stage configured to generate a clock signal based on the second current, wherein the oscillator stage generates a clock signal at a first frequency based on a first mirror ratio of the first current mirror and generates a clock signal at a second frequency based on a second mirror ratio of the first current mirror. The first current mirror may be set to the first mirror ratio based on a first value of a control signal, and the first current mirror may be set to the second mirror ratio based on a second value of the control signal. The converter may include a second current mirror to generate a second current based on the first current and a trimming code. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other objects and features of the present invention will become more apparent from the following detailed description and the appended claims considered in conjunction with the accompanying drawings. Although several exemplary embodiments are shown and described, the same reference numerals represent the same components in each of the drawings, wherein:

[0015] Figure 1 An embodiment of a self-excited oscillator is shown;

[0016] Figure 2shows an example of a timing diagram for a self-excited oscillator;

[0017] Figure 3A An embodiment of an oscillator core for a free-running oscillator is shown, Figure 3B An embodiment of an inverter for an oscillator core is shown; and

[0018] Figure 4 An embodiment of an inverter that may be included in an oscillator core is shown. DETAILED DESCRIPTION

[0019] It should be understood that the drawings are only schematic and are not drawn to scale. It should also be understood that the same reference numerals are used in each of the drawings to represent the same or similar components.

[0020] The specification and the accompanying drawings illustrate the principles of various exemplary embodiments. Therefore, it should be understood that those skilled in the art will be able to design various arrangements that embody the principles of the present invention and are included within the scope thereof, although not explicitly described or shown herein. In addition, all examples described herein are mainly intended to be clearly used for teaching purposes to help readers understand the principles of the present invention and the concepts contributed by (one or more) inventors to promote the art, and should be interpreted as not limited to such specific examples and conditions of narration. In addition, as used herein, the term "or" refers to non-exclusive or (i.e., and / or), unless otherwise specified (e.g., "or another" or "in an alternative"). Moreover, the various exemplary embodiments described herein are not necessarily mutually exclusive, because some exemplary embodiments can be combined with one or more other exemplary embodiments to form new exemplary embodiments. Narratives such as "first", "second", "third" and the like do not mean to limit the order of the elements discussed, but are used to distinguish one element from the next element, and are generally interchangeable. Values ​​such as maximum or minimum values ​​can be predetermined and set to different values ​​based on application.

[0021] Figure 1 Embodiments of a self-excited oscillator (FRO) are shown that operates in multiple modes for generating a clock signal. For example, the mode may be determined by the application or device for which the clock signal is generated. The application or device may be any type of circuit, device, system, or software that is driven by or otherwise operates based on a clock signal or timing signal. Examples include redrivers (e.g., Type-C USB redrivers), USB PD controllers, authentication controllers, and the like.

[0022] The plurality of modes may include a first mode and a second mode. The first mode may correspond to a normal / active mode of the device or application, and the second mode may correspond to a mode different from the first mode, for example, the second mode may have a different (e.g., lower) frequency requirement than the first mode. In one embodiment, the second mode may correspond to another low power mode or a normal / active mode of the device or application.

[0023] Reference Figure 1 , the self-excited oscillator includes a reference current generator 10, a current converter 20, an oscillator stage 30, a ripple counter or delay unit group 40, and an output buffer stage 50. With these features, the self-excited oscillator generates clock signals of different frequencies in the first mode and the second mode. Figure 1 In one embodiment, the oscillator generates two clock frequencies in different modes (and may therefore be described as a dual-mode FRO, but in another embodiment the FRO may generate more than two clock frequencies in different modes)

[0024] The reference current generator 10 includes an amplifier 11, a first transistor 12, a second transistor 13, and a first current mirror 14. The amplifier 11 compares a reference voltage with a feedback signal having a voltage set by a resistor R. The feedback forces the feedback signal to have a voltage equal to the reference voltage. Therefore, the current through the first transistor 12 corresponds to the reference voltage across R. Ultimately, the current through the second transistor is a scaled version of the current through the first transistor, depending on the size difference of the first and second transistors, which are typically the same size for matching currents between the two.

[0025] The first current mirror 14 generates a scalable reference current for the current converter 20. The reference current can be generated based on a control signal, for example, the control signal can determine whether the host application or device will operate in a low power mode or in another (e.g., normal or high) power mode. In one embodiment, the control signal for scaling the first current mirror is a low power enable signal (fro_lp_enable). This signal controls the state of a selector (e.g., a switch) 15 that couples the transistors in the left branch of the first current mirror to the transistors in the right branch of the first current mirror. In one embodiment, the left branch of the first current mirror 14 can include two transistors M1 and M2 and the right branch of the first current mirror 14 can include one transistor M3. The control signal (fro_lp_enable) is used as a selection signal for the switch 15. When the control signal has a first value, the switch 15 is closed to connect M1 and M2 in parallel. Therefore, the first current mirror 14 is formed between all transistors M1 / M2 and transistor M3. When the control signal has a second value, the switch 15 is opened to disconnect the transistor M2. Thus, the first current mirror 14 is formed by the transistors M1 and M3. For example, the first and second values ​​of the switch 15 may be determined based on whether the switch 15 is formed by an NMOS or a PMOS transistor.

[0026] Transistors M1 and M2 have different sizes to scale the reference current generated by the first current mirror. Figure 1 In the example shown, transistor M1 has a size smaller than transistor M2 by a predetermined ratio. Therefore, the first current mirror 14 will output different reference currents to the current converter 20 based on the predetermined ratio. For example, in Figure 1 In the embodiment of FIG. 1 , when transistor M1 is connected in the first current mirror (e.g., switch 15 is open), the size ratio between transistor M1 and transistor M3 is 1:1. For example, when the first mode is enabled, such as when fro_lp_en is logic 0, such a ratio may exist. When this occurs, the reference current I REFERENCE has a relatively high value, which in turn generates a high current into the oscillator stage 30 (eg, a high speed oscillator core) based on the applied trim code. In another embodiment, the mirror ratio may be different.

[0027] When transistor M2 is connected in the first current mirror (e.g., switch 15 is closed), the size ratio of the sum of transistors M1 and M2 to transistor M3 is 10:1. For example, this ratio may exist when the second (low power) mode is enabled, such as when fro_lp_en is a logic 1. When this occurs, the reference current I REFERENCEhas a relatively low value, which in turn generates a low current into the oscillator stage 30 (eg, the low speed oscillator core) based on the applied trimming code.The trimming codes for the high and low power modes may be the same or different.

[0028] The current converter 20 includes a second current mirror 21 and a switch circuit 22. The second current mirror 21 includes a left branch and a right branch. The left branch includes a transistor 23, and the right branch includes a plurality of transistors 241 to 24 N , where N ≥ 2. Transistors 23 and 241 to 24 N It can be a PMOS transistor coupled to a voltage source Vdd. The current generated in the left branch is mirrored into the right branch of the second current mirror, but the amplitude of the current output from the right branch is adjusted to generate a bias current I that will help set the output clock signal to the desired frequency CCO .

[0029] Transistors 241 to 24 in the right branch N By means of a corresponding number of switches 251 to 25 N The state of the switches is controlled based on a digital trimming code, which determines the magnitude of the current to be input into the oscillation stage 30. The digital trimming code includes switches 251 to 252 corresponding in number to the state of the switches 251 to 253. N Each bit of the digital trimming code controls the on / off state of a corresponding one of the switches, a bit with logic 0 can put the corresponding switch in the off state, and a bit with logic 1 can put the corresponding switch in the on state.

[0030] In operation, the current generated in the left branch (I REFERENCE ) is mirrored into the right branch of the second current mirror 21, but the amplitude of the current is adjusted based on the trimming code. In turn, the current converter 20 converts the digital value of the current indicated by the trimming code into an analog bias current I input to the oscillator stage 30. CCO For example, when the second (low power) mode is enabled by the signal fro_lp_en at logic 1, transistor M2 is connected in the first current mirror and a relatively low bias current I CCO Flows in the left branch of the second current mirror. This low current is mirrored into the right branch of the digital-to-analog converter 20 and then adjusted by the digital trimming code. CCO The amplitude corresponds to the value of t Up to 25 N The sum of the currents of the corresponding switches in the switch 25 t Up to 25 N The resulting output is a bias current I having a desired amplitude that controls the frequency of the clock signal to be output from the oscillator stage 30.CCO .

[0031] Conversely, when the first mode is enabled by the signal fro_lp_en being at logic 0, the transistor M2 is disconnected in the first current mirror and the relatively high bias current I CCO Flows in the left branch of the second current mirror 21. This high current is mirrored to the right branch of the current converter 20 and adjusted by the trimming code to output a bias current I with a desired amplitude. CCo , for example, the current I CCo The amplitude is based on the switch 25 t Up to 25 N The sum of the currents of the corresponding switches in the switch 25 t Up to 25 N The bit selected to be in the on state is determined by the trim code. CCO The amplitude of determines the frequency of the clock signal output from the oscillator stage 30.

[0032] The oscillation stage 30 includes at least two oscillator cores: a first oscillator core 31 and a second oscillator core 32. The first oscillator core 31 generates a clock signal having a frequency within a first predetermined range. The second oscillator core 32 generates a clock signal having a frequency within a second predetermined range. The first predetermined range may be greater than the second predetermined range. In this case, the first oscillator core 31 may be described as generating a high frequency clock signal, while the second oscillator core 32 may be described as generating a low frequency clock signal. In one embodiment, the low frequency of the clock signal may be a predetermined portion of the high frequency of the clock signal. In one example, the high frequency may be 48 MHz and the low frequency may be 4.8 MHz, but different frequencies and / or different predetermined portions may be used in another embodiment.

[0033] The oscillator core used to generate the output clock signal can be selected by a control signal, which can be, for example, the same control signal as the control signal used to determine the ratio of the first current mirror, such as a low power enable signal frolp_en. In one embodiment, the first oscillator core 31 can be selected using the inversion of the low power enable signal, and the second oscillator core 32 can be selected using the low power enable signal. The amplitude of the current output from the digital-to-analog converter 20 determines the frequency of the output clock signal (within a frequency range applicable in the first frequency range and the second frequency range). In one embodiment, the (one or more) delays applied by the ripple counter or delay unit delay the availability of the core output and avoid false clock signals during startup of the core selected by the mode control signal.

[0034] In one embodiment, the ripple counter group 40 may include a first ripple counter 41 and a second ripple counter 42. The first counter 41 controls the delay of the clock signal output from the first oscillator core 31, and the second counter 42 controls the delay of the clock signal output from the second oscillator core 32. The delays applied by the first counter and the second counter may be the same or different. Once enabled / selected, the delay(s) applied by the counters may allow either core to output a clock signal with a predetermined delay, for example, to prevent the generation of a false clock signal during a mode transition.

[0035] The output buffer stage 50 includes a first buffer 51 and a second buffer 52. The first buffer 51 outputs a clock signal from the first oscillator core 31 based on the output of the first counter 41. The second buffer 52 outputs a clock signal from the second oscillator core 32 based on the output of the second counter 42. For example, a multiplexer may be coupled to the corresponding buffers in the buffer 51 and the buffer 52 to allow the outputs of the first counter 41 and the second counter 42 to control the timing of the buffer outputs. Figure 1 In an embodiment, the number of oscillator cores, counter filters and buffers is the same, i.e., two. In another embodiment, the number of oscillator cores, counter filters and buffers may be different numbers, or the number of oscillator cores, counter filters and / or buffers may be different from each other.

[0036] Figure 2 shows that it can be used to control, for example, Figure 1 An embodiment of a timing diagram for generating a clock signal output by a self-excited oscillator in FIG. Figure 2 As shown, at time t1, one or more enable signals are generated. The enable signals may include, for example, a signal (fro_core_en) for enabling the first oscillator core 31 or the second oscillator core 32, a signal (fro_output_en) for enabling the output buffer 51 and the output buffer 52, and a signal (fro_en_tempsens) for enabling the temperature sensor 60, which is used for additional temperature compensation of the self-excited oscillator.

[0037] At time t2, after applying the enable signal(s), the clock signal (Clk_out) begins to be output from one of the oscillator cores 31 and 32. A delay time (Δt) may exist between the time the enable signal is applied and the time the initial clock signal is generated, e.g., Δt=t2-t1. The oscillator core that generates the initial clock signal (e.g., before low power mode) may be at, for example, a predetermined startup frequency. In one embodiment, the initial clock signal may be output from the first oscillator core 31 at a higher frequency (e.g., 48 MHz) after Δt=15 μs.

[0038] At time t3, a low power enable signal (fro_lp_en) is generated for input to the first current mirror of the reference current generator 10 and to the multi-core oscillator stage 30. Therefore, transistor M2 is connected in the first current mirror. REFERENCE Input to current converter 20. This low current (mirrored in the right branch of converter 20) is adjusted by the digital trimming code to form the bias current I CCO , the bias current I CCO is input into the second oscillator core 32 selected by the low power enable signal. Therefore, the frequency of the clock signal is converted to a low frequency. The ripple counter 42 can force the output of the clock signal to be 0 during the delay duration (not shown in the figure).

[0039] At time t4, the frequency of the output clock signal has decreased and stabilized to the second frequency (eg, 4.8 MHz) of the second oscillator core 32. This may take a certain period of time, such as 20 s. For operation in the low power mode, this frequency may be maintained for a period of time.

[0040] At time t5, the low power enable signal (fro_lp_en) transitions to a low value, thereby indicating a transition to another operating mode, such as a higher power mode or a normal mode. The low value of the enable signal fro_lp_en connects the transistor M1 in the first current mirror and selects the first oscillator core 31 in the stage 30. Connecting the transistor M1 in the first current mirror 14 causes the reference current I REFERENCE Increases. At this time, a new trimming code may be received to adjust the bias current output from the D / A current converter 20. Therefore, the frequency of the output clock signal begins to increase. The ripple counter 41 may force the output of the clock signal to be 0 during the delay duration (not shown in the figure).

[0041] At time t6, the frequency of the output clock signal has reached the frequency of the first oscillator core, which may take a certain period of time, such as 10 qs. Figure 2 The timing diagram in applies to the case of startup. However, a similar set of transitions and adjusted clock frequencies may be implemented at other times after startup, for example, any time a mode change occurs. Enable signals, trim codes, and other control signals may be provided by, for example, Figure 1 The controller 70 shown generates . The operation of the controller may be determined, for example, based on instructions or a control program stored in a memory. The trimming codes, timing information, and other data may be stored in the same or different memory for access by the controller 70 .

[0042] Figure 3AAn embodiment of an oscillator core 300 is shown, which may correspond in structure to Figure 1 The first oscillator core 31 and the second oscillator core 32 of the self-excited oscillator.

[0043] Reference Figure 3A The oscillator core 300 includes a first stage 310 and a second stage 320. The first stage 310 includes a plurality of inverters 3111 to 311 N An N-stage ring oscillator is formed, where N>3. In one embodiment, N can be an odd number to generate an input bias current I CCO The second stage 320 includes a first output driver 321 coupled to a second output driver 322, each of which may be implemented by an inverter. The first output driver 321 outputs a first clock signal CLK1, and the second output driver 322 outputs a second clock signal CLK2. The first clock signal CLK1 may be an inverted version of the second clock signal CLK2. In one embodiment, the output drivers 321 and 322 may be coupled to respective level converters to change the signal level from V CCO brought to FRO supply level.

[0044] In operation, the output of the Nth inverter of the ring oscillator is fed back to the input of the ring oscillator. Further, for example, when N=3 and the output of inverter 3113 is logic 0, the first pass through the ring oscillator causes inverter 3111 to output logic 1, inverter 3112 to output logic 0, and inverter 3113 to output logic 1. The logic 1 value of inverter 3113 is inverted by the first output driver 321 to generate a first clock signal CLK1 having a logic low (0) value. The output of driver 321 is inverted by the second output driver 322 to generate a second clock signal CLK2 having a logic high (1) value, which corresponds to the rising edge of the clock signal pulse.

[0045] During the second pass through the ring oscillator, inverter 3111 outputs a logic 0, inverter 3112 outputs a logic 1, and inverter 3113 outputs a logic 0. The logic 0 value of inverter 3113 is inverted by first output driver 321 to generate a first clock signal CLK1 having a logic high (1) value. The output of driver 321 is inverted by second output driver 322 to generate a second clock signal CLK2 having a logic low (0) value, which corresponds to the falling edge of the clock signal pulse.

[0046] As this process continues, the corresponding Figure 2The frequency and duration of the clock pulses are based on the sum of the delays of the inverters in the first and second stages used to generate the clock pulses, wherein the clock signals of the first clock signal CLK1 and the second clock signal CLK2 are shifted relative to each other (e.g., 180°).

[0047] Figure 3B Shows Figure 3A An example of a structure of each inverter in the ring oscillator core 31 that generates a high frequency clock signal when implemented in the first oscillator core 31. In this example, each inverter includes a first transistor coupled in series to a second transistor. The first transistor and the second transistor can be of different types. For example, the first transistor can be a PMOS transistor Mp, and the second transistor can be an NMOS transistor Mn. The gates of the first transistor and the second transistor are coupled to the output of the previous inverter in the ring oscillator.

[0048] When using Figure 3A When the first oscillator core 31 is implemented by using the oscillator core in FIG. 1 , the bias current I outputted from the current converter 20 is CCO When the oscillator core is used to implement the second oscillator core 32, the bias current I output from the current converter 20 CCO The first bias current and the second bias current cause the corresponding oscillator cores in the oscillator cores to generate clock signals with different frequencies. In one embodiment, the different clock signal frequencies output from oscillator core 31 and oscillator core 32 can also be generated based on the size difference of the device used to implement the core (for example, transistors and / or other logic used to implement inverters, drivers, level shifters, etc.).

[0049] The oscillator core 31 and the oscillator core 32 can be based on the bias current bias current I CCO One way to generate their corresponding clock signal frequencies can be explained as follows. Figure 3A As shown, the bias current bias current I CCO is provided to the inverters of each stage 310 and stage 320. It takes some time (e.g., about half of the oscillator period) for the output of each inverter to charge to V in the ring before an output can be generated. CCO .

[0050] If we ignore the current to the output buffer and assume that each inverter in the ring has the same capacitive load C, then equation (1) applies:

[0051]

[0052] Where f is the oscillator frequency (the frequency of the clock signal output from the oscillator core 31 or the frequency of the clock signal output from the oscillator core 32), and N is the number of stages in the ring, corresponding to 3 for the ring oscillator in FIG3. Given equation (1), the oscillator frequency can be derived as described in equation (2):

[0053]

[0054] Where V th is the threshold of the inverter transistor Mp and β is a device parameter of Mp (eg, size, oxide thickness, etc.). The device parameter β is proportional to the width-to-length ratio (W / L) of the transistor Mp.

[0055] The high accuracy of the high frequency mode of FRO (where the clock signal is output from the oscillator core 31) can be generated by the following design considerations. First, the frequency of the high frequency oscillator core 31 is adjusted to reduce, minimize or eliminate the effects caused by process variations. Second, Figure 1 The self-excited oscillator in is designed to be insensitive to power supply variations. Finally, the temperature characteristics of the bias resistors, oscillator core, reference voltage, and / or other components that are sensitive to temperature fluctuations are adjusted to reduce or minimize the temperature variation of the self-excited oscillator. For example, additional trimming branches can be added in the D / A converter to change the core bias current based on the reading of the temperature sensor in an effort to maintain the oscillator frequency at different temperatures.

[0056] Figure 4 Another embodiment of an inverter 400 is shown, which may be used to implement one or more inverters in a ring oscillator of a second oscillator core 32, such as an oscillator core that generates a clock signal having a low frequency.

[0057] Reference Figure 4 , the oscillator 400 includes a first stage 410, a second stage 420 and a third stage 430. The first stage 410 includes a PMOS transistor Mp1 and an NMOS transistor Mn1, which are coupled in series at a power supply voltage V CCO and a reference potential such as ground. The gates of transistors Mp1 and Mn1 receive an input signal corresponding to the output of the previous stage in the ring oscillator. In order to scale the clock signal frequency to a lower value, transistors Mp1 and Mn1 may have a width that is a predetermined fraction (e.g., 1 / 10) of the width of the corresponding transistors Mp and Mn used for the inverters in the first (high frequency) oscillator core 31.

[0058] The second stage 420 includes a PMOS transistor Mp1 and an NMOS transistor Mn1, which are coupled in series at a power supply voltage V CCO The source and drain of each transistor Mp1 and Mn1 are coupled together to form a MOSFET capacitor.

[0059] The third stage 430 includes a series connection at a power supply voltage V CCO The gate and drain of each transistor Mp2 and Mn2 are coupled together to form a diode-connected transistor.

[0060] Transistors Mp1, Mp2, Mn1, and Mn2 act as virtual devices that together emulate the gate and drain capacitance effects of transistors Mp and Mn in the first (high frequency) oscillator core 31. In one embodiment, transistors Mp1 and Mp2 have the same width and length, and are close to (e.g., within 10%) the size of transistor Mp in oscillator core 31. Similarly, transistors Mn1 and Mn2 have the same width and length, and are close to (e.g., within 10%) the size of transistor Mn in oscillator core 31.

[0061] In operation, when the self-excited oscillator operates in the low frequency mode, the bias current I output from the digital-to-analog converter 20 is CCO The clock frequency of the high frequency mode is reduced to a predetermined fraction (eg, 1 / 10) of the clock frequency output from the oscillator core 32, for example.

[0062] In one embodiment, for different applications, the bias current I CCO The scaling can be done at different scales. For example, the scaling can be achieved by changing the mirror ratio of the first current mirror in the reference current generator 10, the mirror ratio of the second current mirror in the converter 20, or both. Scaling the mirror ratio can generate a corresponding scaling of the process behavior and temperature behavior of the self-excited oscillator. According to equation (2), when β is scaled down (e.g., to 1 / 10) and C is determined by, for example Figure 4 When the virtual device in is maintained at a constant value, the low frequency mode of the self-excited oscillator will have a proportionally reduced frequency, for example, 1 / 10 of the frequency of the clock signal in the high frequency mode. Figure 1 In an exemplary embodiment of the present invention, the first current mirror has a mirror ratio of 10:1 or 1:1, depending on which of the transistors M1 or M2 is connected. The mirror ratio can be changed (or scaled) to implement a bias current I input to the oscillator core. CCO Therefore, the output clock frequency can be changed by changing the mirror ratio.

[0063] In one embodiment, the size of transistors in one or more stages of inverter 400 may be adjusted to predetermined values ​​to improve accuracy. For example, to determine the size of transistors Mp1, Mn1, Mp2, and Mn2, a simulation may be performed in which the sizes of these transistors are initially given the same values ​​as those of the transistors Mp1, Mn1, Mp2, and Mn2. Figure 3BThe size (e.g., width, length, or both) of transistors Mp1, Mn1, Mp2, and Mn2 can then be gradually reduced until the desired frequency is generated with minimal size variation compared to Mp and Mn, which minimizes virtual devices and Figure 3B The differences in voltage and temperature coefficients of capacitance between the devices.

[0064] In addition to these adjustments, the process and temperature effects of the free-running oscillator can be scaled in the same proportion as the bias and beta scaling. This can generate a low-frequency clock signal with high accuracy. The process and temperature effects may not be exactly proportional, but a limited frequency variation degradation of, for example, 1-2% may be acceptable. For example, a 3% accuracy FRO at 48MHz implemented as proposed can achieve 5% accuracy at a low clock frequency of 4.8MHz, which is time-trimmed once at a high clock frequency of 48MHz. In this case, the power consumption can be reduced from 107uA at 48MHz to 18uA at 4.8MHz.

[0065] According to one or more embodiments, the self-excited oscillator generates a high-precision clock signal in both the high-frequency mode and the low-frequency mode. The high-frequency mode may be, for example, a normal operating mode of a host device or system. The bias current I CCO To achieve high accuracy in high frequency mode.

[0066] The low frequency mode can be any of a variety of power saving modes. For example, the low frequency mode can be a mode designed to save power when clock or system activity is reduced or minimized. In one embodiment, the low frequency mode can share the same trimming codes and bias circuits used in the high frequency mode. This can be present, for example, in processes where memory bits are expensive (e.g., Qubic4 processes). This method can also save test time in production, which avoids having to implement additional production test time as in the case of other circuits and methods that have been proposed.

[0067] These or other embodiments may be implemented to achieve high frequency accuracy with acceptable degradation. Additionally, the low frequency mode may not require additional trimming and thus may save the use of memory bits for trimming code. New methods for reducing bias current and devices in the oscillator core(s) may also be used to maintain accuracy in the low frequency mode. The transition between low power mode and high power mode may be controlled to meet various protocol based system timing requirements.

[0068] The controllers, selectors, generators, converters, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented in logic, which may include hardware, software, or both, for example. When implemented at least partially in hardware, the controllers, selectors, generators, converters, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits, including but not limited to an application specific integrated circuit, a field programmable gate array, a combination of logic gates, a system on a chip, a microprocessor, or another type of processing or control circuit.

[0069] When implemented at least in part in software, controllers, selectors, generators, converters, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing a code or instruction executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be one of those described herein or in addition to the elements described herein. Because the algorithms forming the basis of these methods (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of these method embodiments may transform a computer, processor, controller, or other signal processing device into a special-purpose processor for performing the method described herein.

[0070] Any benefits, advantages, solutions to problems described, and any elements that may make various benefits, advantages, or solutions present or more significant are not to be construed as critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

[0071] Although various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects of the present invention, it will be appreciated that the present invention is applicable to other exemplary embodiments and that its details can be modified in various obvious aspects. It will be apparent to those skilled in the art that changes and modifications may be made within the spirit and scope of the present invention. Therefore, the foregoing disclosure, description and drawings are for illustrative purposes only and do not limit the present invention in any way, which is limited only by the claims.

Claims

1. An oscillator, characterized in that: include: a reference current generator configured to generate a first current; a converter configured to generate a second current based on the first current; a first oscillator core configured to generate a clock signal of a first frequency; as well as a second oscillator core configured to generate a clock signal at a second frequency, the second frequency being lower than the first frequency, wherein the first oscillator core is configured to generate the clock signal at the first frequency based on a first value of the second current, and the second oscillator core is configured to generate the clock signal at the second frequency based on a second value of the second current, the second value being lower than the first value; a ripple counter or a set of delay cells coupled to the first oscillator core and the second oscillator core, wherein the ripple counter is configured to control the outputs of the first oscillator core and the second oscillator core based on one or more predetermined delays that control the availability of core outputs after a particular core is selected or enabled during a core transition.

2. The oscillator according to claim 1, characterized in that The reference current generator includes a first current mirror having a scalable mirror ratio.

3. The oscillator according to claim 2, characterized in that: The first current mirror includes a selector, and The selector is configured to couple a first transistor in the first current mirror to achieve a first mirroring ratio and to couple a second transistor in the first current mirror to achieve a second mirroring ratio, the second transistor having at least one parameter different from the first transistor.

4. The oscillator according to claim 2, characterized in that Adjusting the ratio of the first current mirror produces a corresponding change in the second current output from the converter.

5. The oscillator according to claim 4, characterized in that: The first current mirror is configured to output a first value of the first current for a first mirror ratio and to output a second value of the first current for a second mirror ratio, and The converter is configured to generate the first value of the second current based on the first mirror ratio and to generate the second value of the second current based on the second mirror ratio.

6. The oscillator according to claim 2, characterized in that The converter comprises: a second current mirror configured to receive the first current, and A trimming circuit is coupled to the second current mirror and is configured to trim an output current of the second current mirror based on a first trimming code.

7. The oscillator according to claim 6, characterized in that The second current mirror includes a first branch and a second branch, the first branch includes a first transistor and the second branch includes a plurality of second transistors, the plurality of second transistors mirror the current flowing through the first branch, and wherein the trimming circuit is coupled to the plurality of second transistors to output the second current.

8. The oscillator according to claim 1, characterized in that: The first oscillator core includes a plurality of first inverters, The second oscillator core includes a plurality of second inverters, and A width-to-length ratio of one or more transistors in the plurality of second inverters is smaller than a size of one or more transistors in the plurality of first inverters.

9. An oscillator, characterized in that: include: a first current mirror configured to generate a first current; a second current mirror configured to generate a second current; as well as a selector configured to select a mirror ratio of the first current mirror, wherein the first current mirror is configured to generate a first value of the first current when the selector selects a first mirroring ratio and to generate a second value of the first current when the selector selects a second mirroring ratio, and wherein the second current mirror is configured to generate a first value of the second current based on the first value of the first current and to generate a second value of the second current based on the second value of the first current; a ripple counter or a set of delay cells coupled to a first oscillator core and a second oscillator core, wherein the ripple counter is configured to control outputs of the first oscillator core and the second oscillator core based on one or more predetermined delays that control availability of core outputs after a particular core is selected or enabled during a core transition; The first oscillator core is configured to generate a clock signal of a first frequency; The second oscillator core is configured to generate a clock signal of a second frequency.

10. An oscillator, characterized in that: include: a first current mirror configured to generate a first current; as well as a converter configured to convert the first current into a second current; as well as an oscillator stage configured to generate a clock signal based on the second current, wherein the oscillator stage is configured to generate the clock signal at a first frequency based on a first mirror ratio of the first current mirror and is configured to generate the clock signal at a second frequency based on a second mirror ratio of the first current mirror; a ripple counter or a set of delay cells coupled to a first oscillator core and a second oscillator core, wherein the ripple counter is configured to control outputs of the first oscillator core and the second oscillator core based on one or more predetermined delays that control availability of core outputs after a particular core is selected or enabled during a core transition; The first oscillator core is configured to generate a clock signal of a first frequency; The second oscillator core is configured to generate a clock signal of a second frequency.

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