Quantum bit control electronic circuit

Abstract

A device for generating a qubit control signal comprises: a first signal envelope generator circuit comprising a first plurality of signal sources, wherein an output of each of the first plurality of signal sources is combined to provide a first cumulative output; and a first mixer circuit coupled to the first signal envelope generator circuit, wherein the first cumulative output is coupled to a first input of the first mixer circuit, and an output of the first mixer circuit comprises a first qubit control signal.

Description

Technical Field

[0001] The present disclosure relates to qubit control electronic circuits. Background Art

[0002] A classical computer has a memory composed of bits, each of which can represent either 0 or 1. A quantum computer maintains a sequence of quantum bits (called qubits), each of which can represent 0, 1, or any quantum superposition of 0 and 1. A quantum computer operates by setting the qubits in an initial state and controlling the qubits (e.g., according to a sequence of quantum logic gates). A computation can include collapsing a system of qubits into an eigenstate, in which each qubit represents either 0 or 1. Measurements can be made during or at the end of a computation. For example, in a quantum error correction algorithm, measurements are made every cycle to detect errors. Furthermore, measurements are typically performed on a subset of qubits rather than on the entire array. Summary of the invention

[0003] The qubit control electronic circuit of the present disclosure may be embodied in an integrated circuit (IC) including CMOS integrated circuit elements. The IC may be operated in a cryogenic environment such as an intermediate cooling stage (e.g., between about 3-4K) of a cryogenic container between room temperature and the operating temperature of a superconducting qubit. The qubit control electronic circuit that may be embodied in the IC generates qubit control signals, such as qubit XY control signals, using an envelope generator circuit electrically coupled to a mixer circuit. The signal envelope generator circuit generates a signal envelope and includes a plurality of programmable individual signal sources (e.g., current sources). In certain embodiments, the envelope generator circuit cumulatively sums the outputs from the plurality of individual signal sources and provides the summed output to a first mixer circuit of a vector modulator circuit. The first mixer circuit may include, for example, a double-balanced mixer circuit for up-converting the summed output of the envelope generator circuit. The first mixer circuit mixes the summed output from the signal envelope generator circuit with a local oscillator signal to provide a qubit control signal. In some implementations, the qubit control electronics include a second envelope generator circuit coupled to a second mixer circuit of the vector modulator circuit, wherein the second envelope generator circuit is constructed in the same manner as the first envelope generator circuit. The output of the second mixer circuit can be combined with the output of the first mixer circuit to provide a qubit control signal.

[0004] The qubit control electronic circuits disclosed herein can have various advantages. For example, in some embodiments, the qubit control electronic circuits disclosed herein can be used to reduce the wiring requirements of a quantum computing system. The qubit control electronic circuits can also reduce the power consumption of a quantum computing system. The qubit control electronic circuits disclosed herein can be used while consuming the order of 1 mW / qubit or less without adversely affecting the error rate, making cryogenic cooling of the qubit control electronic circuits feasible. By enabling the qubit control electronic circuits to operate at cryogenic temperatures, power consumption can be further reduced by allowing the use of lossless superconducting interconnects rather than room temperature interconnects to transmit data between the qubit control electronic circuits and the devices on which the qubits are formed.

[0005] In general, in certain aspects, the disclosed subject matter may be embodied in a device for generating a qubit control signal, wherein the device comprises: a first signal envelope generator circuit comprising a first plurality of signal sources, wherein an output of each of the first plurality of signal sources is combined to provide a first cumulative output; and a first mixer circuit coupled to the first signal envelope generator circuit, wherein the first cumulative output is coupled to a first input of the first mixer circuit, and an output of the first mixer circuit comprises a first qubit control signal.

[0006] Embodiments of the device may include one or more of the following features. For example, in some embodiments, the first plurality of signal sources include a plurality of current sources. The plurality of current sources may include programmable current sources. The output of each current source may be attached to a common node.

[0007] In some implementations, the first signal envelope generator circuit includes a variable capacitor coupled to the first accumulation output.

[0008] In some implementations, the first signal envelope generator circuit includes a delay circuit coupled to the first plurality of signal sources. The delay circuit may include a plurality of flip-flops configured to cause sequential activation and deactivation of the first plurality of signal sources.

[0009] In some implementations, the first mixer circuit includes a double balanced mixer circuit.The double balanced mixer circuit may include a plurality of MOSFETs.

[0010] In some implementations, the first mixer circuit is configured to mix the first accumulated output with a local oscillator signal received at a second input of the first mixer circuit.

[0011] In some implementations, the device includes a memory.The device may include a multiplexer array coupled to the memory and the first signal envelope generator circuit.

[0012] In some embodiments, the device further comprises: a second signal envelope generator circuit comprising a second plurality of signal sources, wherein the output of each of the second plurality of signal sources is combined to provide a second cumulative output; and a second mixer circuit, wherein the second cumulative output is coupled to a first input of the second mixer circuit, the output of the second mixer circuit comprises a second qubit control signal, and the first qubit control signal is combined with the second qubit control signal to provide a qubit XY control signal. The first mixer circuit can be configured to mix the first cumulative output with a first local oscillator signal received at a second input of the first mixer circuit, and the second mixer circuit can be configured to mix the second cumulative output with a second local oscillator signal received at a second input of the second mixer circuit. The first local oscillator signal can be out of phase with the second local oscillator signal. For example, the first local oscillator signal can be out of phase with the second local oscillator signal by any one of 90°, 180°, or 270°.

[0013] In some embodiments, the device is an integrated circuit chip.

[0014] In general, in another aspect, the subject matter of the present disclosure may be embodied in a quantum computing system, the quantum computing system comprising: a cooling device capable of providing a plurality of cooling stages, wherein each cooling stage is maintained at a different temperature; a qubit chip comprising a qubit, wherein the qubit chip is arranged in the cooling device and maintained at a first cooling stage, wherein the temperature of the first cooling stage is between 0 K and 100 mK; and a control circuit for generating a qubit XY control signal, the control circuit being arranged in the cooling device and maintained at a second cooling stage, wherein the temperature of the second cooling stage is higher than the temperature of the first cooling stage and lower than room temperature, and wherein the control circuit is coupled to the qubit chip. The control circuit for generating the qubit XY control may include any of the qubit control signal generating devices described above.

[0015] In general, in another aspect, the disclosed subject matter can be embodied in a method for generating a qubit control signal, the method comprising: sequentially activating a first plurality of signal sources; combining outputs of the sequentially activated first plurality of signal sources to provide a first combined output; passing the first combined output to a first mixer circuit; and mixing the first combined output with a local oscillator signal in the first mixer circuit to provide a first qubit control signal.

[0016] Implementations of the method may include one or more of the following features. For example, in some implementations, the first plurality of signal sources includes a first plurality of current sources. The first plurality of current sources may be programmable current sources.

[0017] In some embodiments, the method includes sequentially deactivating the first plurality of signal sources. The first combined output may include a combined output of the sequentially deactivated first plurality of signal sources.

[0018] In some implementations, the method further includes smoothing the first combined output before passing the first combined output to the first mixer circuit.

[0019] In some embodiments, the method further comprises: sequentially activating a second plurality of signal sources; combining the outputs of the sequentially activated second plurality of signal sources to provide a second combined output; passing the second combined output to a second mixer circuit; mixing the second combined output with a second local oscillator signal in the second mixer circuit to provide a second qubit control signal; and combining the first qubit control signal with the second qubit control signal to provide a qubit XY control signal. The first local oscillator signal can be out of phase with the second local oscillator signal.

[0020] In some embodiments, the method is performed in an environment having a temperature greater than 1 mK and less than 40K.

[0021] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A is a schematic diagram illustrating an example of a single qubit quantum computing system.

[0023] Figure 1B It is an anharmonic energy diagram.

[0024] Figure 2 is a schematic diagram showing an example of a qubit control circuit.

[0025] Figure 3 is a graph illustrating an exemplary signal envelope generation process.

[0026] Figure 4 is a schematic diagram showing an example of a qubit control circuit.

[0027] Figure 5 is a schematic diagram showing an example of a qubit control circuit implemented in an integrated circuit.

[0028] Figure 6 is a schematic diagram showing a detailed configuration of an exemplary signal envelope generator circuit.

[0029] Figure 7 is a schematic diagram showing a detailed configuration of an exemplary vector modulator circuit.

[0030] Figure 8 is a block diagram of an exemplary test setup for a qubit control circuit.

[0031] Fig. 9 is a graph showing example waveforms obtained by testing a qubit control circuit.

[0032] Fig.10 is a graph showing state probabilities obtained by performing a pair of Rabi experiments using qubit controlled electronic circuits.

[0033] Fig.11 are graphs illustrating pulse trains generated by qubit control electronics, example qubit trajectories, and comparisons of ideal qubit trajectories with measured qubit trajectories.

[0034] Fig.12 is a block diagram illustrating an exemplary process for generating qubit XY control signals. DETAILED DESCRIPTION

[0035] Quantum computing requires coherent processing of quantum information stored in the quantum bits (qubits) of a quantum computer. Superconducting quantum computing is a promising implementation of solid-state quantum computing technology, in which the quantum information processing system is partially formed by superconducting materials. In order to operate a quantum information processing system using solid-state quantum computing technology (such as superconducting qubits), the system is maintained at extremely low temperatures, for example, at tens of mK. The extreme cooling of the system keeps the superconducting materials below their critical temperature and helps to avoid unnecessary state transitions. In order to maintain such a low temperature, the quantum information processing system can be operated in a cryogenic container such as a dilution refrigerator. In some embodiments, the control signal is generated in a higher temperature environment and transmitted to the quantum information processing system using a shielded impedance-controlled GHz-capable transmission line (such as a coaxial cable). The cryogenic container can be dropped from room temperature (e.g., about 300K) to the operating temperature of the qubit of one or more intermediate cooling stages. For example, the cryogenic container can employ a first stage maintained in a first temperature range T1 that is one or two orders of magnitude cooler than room temperature (e.g., about 30-40K or about 3-4K) and warmer than the operating temperature of the qubit (e.g., about 10 mK or less, or about 100 mK or less).

[0036] Even at extremely low qubit operating temperatures, qubits can still suffer from decoherence and gate errors. Therefore, large-scale quantum error correction algorithms can be deployed to compensate for gate errors and qubit decoherence. Error-correcting quantum processors use redundancy to synthesize protected logical qubits from clusters of error-prone qubits. Although the required redundancy depends on the error rate of the component qubits, in some embodiments, it is expected that at least 1,000 physical qubits may be required to implement a single error-correcting logical qubit. Current implementations of superconducting quantum systems use, for example, at least two room-temperature coaxial cables per qubit to provide qubit control signals. In addition, in order to solve complex problems using quantum computers, it is expected that more than 1,000 or more error-correcting logical qubits may be required. Using current systems, this scale may require millions of independent cables. In addition, such a system would require a lot of power consumption to generate control signals for the qubits that drive the quantum processor.

[0037] The present disclosure relates to qubit control electronics that can be used to reduce the wiring requirements of a quantum computing system and can also reduce the power consumption of a quantum computing system. The qubit control electronics of the present disclosure can be used while consuming the order of 1 mW / qubit or less without adversely affecting the error rate, making cryogenic cooling of the qubit control electronics feasible. By enabling the qubit control electronics to operate at cryogenic temperatures, power consumption can be further reduced because lossless superconducting interconnects can be used instead of room temperature interconnects to transmit data between the qubit control electronics and the devices that form the qubits. In addition, on-chip waveform memory provides a method for greatly reducing the amount of data transfer required to generate band-limited XY control signals.

[0038] The qubit control electronics of the present disclosure may be embodied in an integrated circuit (IC) including, for example, CMOS integrated circuit elements on a plate (in some embodiments, a monolithic) or chip of a semiconductor material such as silicon. The IC may operate in a cryogenic environment such as an intermediate cooling stage (e.g., about 3-4K) of a cryogenic container between room temperature and the operating temperature of a superconducting qubit. The qubit control electronics, which may be embodied in the IC, generates a qubit control signal using a first signal envelope generator circuit electrically coupled to a first mixer circuit. The signal envelope generator circuit generates a signal envelope and includes a plurality of programmable individual signal sources (e.g., current sources). In certain embodiments, the envelope generator circuit cumulatively sums the outputs from the plurality of individual signal sources and provides the summed output to the first mixer circuit. The first circuit mixer circuit may include, for example, a double-balanced mixer circuit element for up-converting the summed output of the envelope generator circuit. The first mixer circuit mixes the summed output from the first signal envelope generator circuit with a local oscillator signal to provide a qubit control signal. In some embodiments, the qubit control electronics circuit includes a second signal envelope generator circuit coupled to a second mixer circuit, wherein the second signal envelope generator circuit is constructed in the same manner as the first envelope generator circuit. The first mixer circuit and the second mixer circuit can form part of a vector modulator circuit. The output of the first mixer circuit can be combined with the output of the second mixer circuit to provide a qubit control signal, such as a qubit XY control signal.

[0039] Before describing further details of the qubit control electronics, a brief review of the standard quantum computing system consisting of qubits, quantum control elements, and quantum measurements is given.

[0040] An ideal qubit is a two-level system whose state can be represented as a superposition of its eigenstates: |ψ〉=cos(θ / 2)|0〉+exp{jφ}sin(θ / 2)|1〉. Therefore, the state of a qubit has a unique interpretation as a point on the surface of a Bloch sphere. In a typical quantum algorithm, a sequence of, for example, single-qubit and / or two-qubit gates is applied to a collection of qubits, and then the states of a subset of these qubits are measured. Single-qubit gates involve well-defined rotations on the surface of the Bloch sphere, while two-qubit gates are conditional rotations on the Bloch sphere.

[0041] Figure 1Ais a schematic diagram showing a single qubit quantum computing system. The quantum computing system includes a qubit chip 100 coupled to a qubit control electronic circuit 10. The qubit chip 100 includes one or more qubits 102 (such as superconducting qubits) and can be operated at extremely low temperatures using a cryogenic container (e.g., about 10mK or lower, such as 1mK, depending on the minimum possible temperature that the cryogenic container can reach). For the purposes of this disclosure, the qubits operated by the qubit control electronic circuit are assumed to be frequency-tunable transmon qubits with fast gating times (e.g., <15ns), low single qubit and double qubit error rates (e.g., <0.1% and <0.6%), medium coherence times (e.g., ~0.1ms), and monolithic implementations. However, the qubit control electronic circuits described herein are not limited to working with transmon qubits, but can also be used with other qubit configurations, such as fluxmon qubits or gmon qubits. Each qubit 102 of qubit chip 100 may be coupled to a Z drive qubit circuit element 106 (e.g., a resonator), an XY drive qubit circuit element 110 (e.g., a capacitor), and a qubit readout resonator 112. Qubits 102 and associated circuit elements formed on qubit chip 100 may be formed of patterned superconductor material on a dielectric substrate (e.g., aluminum on silicon or sapphire substrate).

[0042] The qubit chip 100 is coupled to qubit control electronics 10 that operates at room temperature (e.g., about 300K). The data lines connecting the qubit control electronics 10 to the qubit chip 100 can be subjected to one or more cryogenic intermediate stages of a cryogenic container. For example, the qubit Z control line 12, the qubit XY control line 14, and the qubit readout line 16 can be subjected to an intermediate stage of a cryogenic container that is cooled to below room temperature but above the qubit operating temperature (e.g., around 3-4K). In some embodiments, the control lines can also include attenuators (e.g., attenuators 18, 20) or amplifiers (e.g., amplifier 22). The data lines can be coupled to ports (e.g., ports 104, 108, and 116) of the qubit chip 100.

[0043] like Figure 1A As shown, qubit 102 is a nonlinear resonator that includes a capacitor in parallel with a pair of Josephson junctions (illustrated as X) that form a squid in a loop, the effective inductance of the squid being tunable by driving it through the loop with an external magnetic flux (e.g., provided by qubit Z control wire 12). The nonlinearity associated with the (multiple) Josephson junctions results in an anharmonic energy diagram 150, as shown in FIG. Figure 1BAs shown, discrete energy levels (152, 154, 156, 158) are formed. The interval between the energy levels can be expressed as ΔE = hf mn , where h is Planck's constant, f mn is the frequency difference between energy levels m and n. 01 and f 12 -f 01 Typical values ​​for are 6 GHz and 250 MHz, respectively. It is therefore possible to use microwave (XY) drive to specifically address the |0> to |1> transition, thereby approximating the desired two-level qubit.

[0044] Microwave gating operations on a qubit, such as qubit 102, can be performed by generating an XY control signal at qubit control electronics 10, and then applying the XY control signal to XY port 108 of qubit 102 when the qubit is operating at its resonant frequency, resulting in a deterministic rotation of the qubit state about an axis in the XY plane of the Bloch sphere, where the rotation axis and rotation angle are determined by the carrier phase and integrated envelope amplitude of the microwave signal, respectively. The finite coherence time of the qubit makes it desirable to minimize the duration of the applied pulse, but a pulse that is short in time contains a broad spectrum. Therefore, there is a tradeoff between pulse duration and the population of |2> states, because energy in the pulse sidebands can couple to f 12 transition. Therefore, the XY pulses used to drive the qubit are typically shaped to minimize leakage to the |2> state, with Gaussian and raised cosine envelopes being the most popular. With reference to XY port 108, exemplary pulse duration and envelope amplitude are 10-30ns and 10-100μV, respectively. The state of the qubit 102 can be sensed by projection measurement, in which the reflection coefficient of the readout resonator 112 is measured, resulting in the qubit being measured in cos 2 The probability of (θ / 2) collapses to the |0> state, with sin 2 Depending on which state the qubit collapses to, the measured reflection coefficient will take on one of two different values.

[0045] Standard control circuits operating at room temperature use high-speed (~1 GSPS or higher) and high-resolution (~14-bit) digital-to-analog converter (DAC) waveform generators to generate each qubit XY control signal. Such high-speed waveform generators consume a lot of power.

[0046] Rather than using high power, high speed, and very high resolution digital-to-analog converters, at least a portion of the qubit control electronics 10 can be replaced with control electronics that are capable of generating a wide range of qubit control signals (e.g., qubit XY control signals), use lower bit resolution, require lower data rates, and consume less power. In addition, the integrated circuit can operate at cryogenic temperatures (e.g., at or below 30-40K, such as 3-4K). Thus, the coaxial cables that typically couple the control electronics to the qubit chip can be replaced with superconductor connectors that are lossless when the transition temperature of the superconductor is above the cryogenic temperature of operation, further reducing the power consumption of the quantum computing system.

[0047] Figure 2 is a schematic diagram showing an example of a simplified qubit control circuit 200 for generating a qubit control signal, such as a qubit XY control signal. Qubit control circuit 200 may be used in place of Figure 1A At least a portion of the qubit control electronic circuit 10 shown. In some embodiments, qubit control circuit 200 can be implemented as an IC, which includes a set of electronic circuits integrated as part of a piece of semiconductor material. In some embodiments, qubit control circuit 200 operates at cryogenic temperatures (e.g., at 30-40K or below, such as 3-4K) instead of operating at room temperature as qubit control electronic circuit 10 shown in FIG. 1.

[0048] The qubit control circuit 200 includes a signal envelope generator circuit 202 coupled to a mixer circuit 210. Figure 2 As shown in the example of , the signal envelope generator circuit 202 may include a current mode envelope generator. The current mode envelope generator includes a plurality of different current sources 204. Although Figure 2 Eleven current sources 204 are shown in the figure (where dotted lines represent current sources that are not depicted), but at least two current sources may be used. The current sources 204 may be programmable so that each current source 204 may be controlled to output a defined current level. In some embodiments, the waveform of each current source 204 is stored in a memory of the qubit control circuit 200. Multiple current sources 204 are coupled in parallel so that the output of each of the current sources 204 is attached to a common output or node 208. When one or more of the current sources 204 are activated, the total current output measured at the node 208 is provided as i(t). A switch 206 is provided in series with each current source 204. The switch 206 of each source may be opened or closed to allow the output of the current source to be added to or removed from the total current output i(t). Although Figure 2In the embodiment, the switch 206 is shown as being used to control whether the output of the current source is combined with the total current output, but other control mechanisms may be used instead. Figure 2 In the embodiment of the present invention, multiple programmable current sources are shown, but other signal sources may be used instead. For example, multiple programmable voltage sources may be used instead of current sources. Other circuit elements of the qubit control circuit 200 may be modified accordingly for use with programmable voltage sources. For example, the voltage sources may be combined in series.

[0049] In some implementations, the output of the signal envelope circuit is smoothed prior to coupling to the mixer circuit 210. For example, smoothing may be accomplished by using a variable capacitor 216 placed between the positive and negative outputs of the signal envelope generator circuit 202. The voltage across the capacitor 216 is provided as v env (t). The graph 201 above the qubit control circuit 200 shows the envelope signal v env An example of (t).

[0050] The smoothed output of the signal envelope circuit is coupled to a mixer circuit 210. In some implementations, the mixer circuit 210 mixes the output from the signal envelope generator circuit with a local oscillator signal 212. The local oscillator signal 212 is at the carrier frequency. Figure 2 As shown, mixer circuit 210 includes a current mode double balanced mixer circuit. The double balanced mixer circuit provides up-conversion of the signal received from signal envelope generator circuit 202. In this example, the double balanced mixer is constructed using a CMOS integrated circuit 214 such as a MOSFET. Figure 2 The mixer design shown is only an example and is not intended to limit the use of other mixer circuit designs. The output of the mixer circuit 210 is coupled to the transformer 218 and is provided as an output signal v out (t) is provided to the load 220.

[0051] The signal envelope generator circuit 202 can be used to generate a variety of different waveforms, including but not limited to symmetrical waveforms, such as Gaussian and raised cosine waveforms commonly used in quantum computing. Figure 3 In the example signal envelope generation process shown, each of the current sources 204 is activated sequentially so that once all current sources 204 are activated, the total current output i(t) steadily increases to a maximum value. For example, a first current source having an output current value I1(t) is activated at a first time t1, and a second current source having an output current value I2(t) is activated at a second time t2 later than t1, but while the first current source is still activated, so that the total current output i(t) is the sum of I1(t) and I2(t). Current activation continues in this manner until a second current source having an output current value IN The last current source at time t N are activated so that the total current output i(t) is the sum of all activated current sources. In this simplified example, once all current sources are activated, they can be deactivated in the reverse order in which they were turned on. The total current output appears as Figure 3 As explained herein, the output from the signal envelope generator circuit 202 can be smoothed. Smoothing can be achieved, for example, using a variable capacitor such as capacitor 216, but other smoothing techniques can be used instead. In some embodiments, the timing at which the current source 204 is activated and turned off is based on the number of clock cycles that have passed. For example, in some cases, the shortest activation time of the current source 204 can be one clock cycle.

[0052] although Figure 2 The qubit control circuit 200 shown includes one signal envelope generator circuit 202 coupled to a mixer circuit 210, but in general, the qubit control circuit 200 may also include an identical second signal envelope generator circuit coupled to a second mixer circuit. For example, the first mixer circuit and the second mixer circuit may be part of a vector modulator circuit. The output of each mixer circuit may then be combined to provide a phase rotated signal. As described above, the rotation axis and rotation angle of the qubit state in the Bloch sphere are determined by the carrier phase and the integrated envelope amplitude of the microwave signal, respectively. Figure 4 A simplified schematic diagram of a qubit control circuit illustrating this arrangement is shown. Qubit control circuit 400 can be used to replace Figure 1A At least a portion of qubit control electronic circuit 10 is shown. As with qubit control circuit 200, qubit control circuit 400 may be implemented as an IC and operated at cryogenic temperatures (eg, at 3-4K).

[0053] The qubit control circuit 400 includes a first signal envelope generator circuit 402 and a second signal envelope generator circuit 404. Each of the first signal envelope generator circuit 402 and the second signal envelope generator circuit 404 can be constructed in the same manner as described herein for the signal envelope generator circuit 202. For example, each of the first signal envelope generator circuit 402 and the second signal envelope generator circuit 404 can include a plurality of individually programmable current sources that are attached to a common output or node to provide a cumulative current output. In addition, each of the first signal envelope generator circuit 402 and the second signal envelope generator circuit 404 can include a corresponding smoothing circuit coupled to a respective common node to smooth the stepped appearance of the signal output. The first signal envelope generator circuit 402 provides a first output, such as DAC_Iv out(t), and the second signal envelope generator circuit 404 provides a second output, such as DAC_Q v out (t).

[0054] The qubit control circuit 400 also includes a first mixer circuit 414 and a second mixer circuit 416. In some embodiments, the first mixer circuit 414 and the second mixer circuit 416 are part of a vector modulator circuit that includes two mixer circuits and a combiner circuit, wherein the first mixer and the second mixer are driven by a sine wave and a cosine wave, respectively. Each of the first mixer circuit 414 and the second mixer circuit 416 can be constructed as described herein for the mixer circuit 210. The first mixer circuit 414 receives the first output DAC_Iv from the first signal envelope generator circuit 402. out (t) as input, and the second mixer circuit 416 receives DAC_Qv from the second signal envelope generator circuit 404 out (t) as input. In addition, each of the first mixer circuit 414 and the second mixer circuit 416 receives a corresponding local oscillator signal. For example, the first mixer circuit 414 receives a local oscillator signal from the first local oscillator 406, and the second mixer circuit 416 receives a local oscillator signal from the second local oscillator 408. In some embodiments, the first local oscillator 406 and the second local oscillator 408 include arbitrary waveform generators operating at room temperature and are not part of the qubit control circuit 400. For example, the first local oscillator 406 and the second local oscillator 408 can be part of the qubit control electronic circuit 10 shown in Figure 1. In other embodiments, the first local oscillator 406 and the second local oscillator 408 are formed as part of the qubit control circuit 400. In some embodiments, the first local oscillator 406 and the second local oscillator 408 provide a periodic waveform, such as a sine or cosine waveform. In some embodiments, the first local oscillator 406 provides an output signal that is out of phase with the output signal provided by the second local oscillator 408. For example, the output signal from the first local oscillator 406 can be 90°, 180°, or 270° out of phase with the output signal provided by the second local oscillator 408. For example, the output signal from the first local oscillator 406 can be a sine wave, while the output signal from the second local oscillator 408 can be a cosine wave. In some embodiments, the oscillator signals are amplified before being passed to the mixer. For example, the qubit control circuit 400 includes a first amplifier 410 that amplifies the signal from the first local oscillator 406, and includes a second amplifier 412 that amplifies the signal from the second local oscillator 408.

[0055] The first mixer circuit 414 combines the first oscillator output with the first output DAC_I v from the first signal envelope generator circuit 402. out (t) Mixing, and the second mixer circuit 416 mixes the second oscillator output with the second output DAC_Q v from the second signal envelope generator circuit 404 out (t) Mixing. The outputs of each of the first mixer circuit 414 and the second mixer circuit 416 are then summed at the adder circuit 418 to provide the qubit XY drive signal in the form of an RF output.

[0056] Figure 5 is a schematic diagram showing an example of a qubit control circuit (such as qubit control circuit 400) implemented in an integrated circuit IC 500. IC 500 may be manufactured using CMOS manufacturing technology. Figure 5 As shown in the example of , IC 500 includes a serial-to-parallel interface (SPI) circuit 502 and a configuration / waveform memory 504. The configuration / waveform memory 504 may include, for example, a trigger-based memory or a random access memory. During operation of IC 500, waveform data is loaded into the SPI circuit 502 and then transferred to parallel registers in the configuration / waveform memory 504. The configuration / waveform memory 504 allows storage of multiple different waveforms, including individual weights for each programmable signal source of the signal envelope generator, and weights for one or more independent reference signals (e.g., current or voltage). The weight represents the amplitude of the current required to generate the waveform. For example, the weight 506 of the first current source in Figure 5, I1A, I1B . . . , I1N in the configuration / waveform memory 504. In some embodiments, the configuration / waveform memory 504 stores 4, 8, 12, 16, 20, 24, 28, or 32 different waveforms for each programmable signal source, although other numbers of waveforms may be stored. The waveforms may have different bit depths. For example, the waveform may be programmed to have 4-bit resolution, 6-bit resolution, 8-bit resolution, or 10-bit resolution, although other resolutions are possible. The waveform data is provided to the DIN pin of the IC 500. In some embodiments, data may be transferred to the SPI circuit 502 at each cycle of the clock signal provided to SCLK. When a load signal is received at the data load pin LD, data may be transferred from the SPI circuit 502 to the parallel registers in the configuration / waveform memory 504. The SPI circuit 502 itself updates relatively slowly. For example, the SPI circuit 502 may be updated based on a clock cycle having a frequency of several kHz. Both the clock signal of SCLK and the data load signal may be provided by the room temperature control electronic circuit. Alternatively, in some embodiments, the clock and load signals may be generated on the IC 500 itself. In some embodiments, there may be an on-chip sequencer to define a series of waveform select signals corresponding to a series of waveforms.

[0057] IC 500 also includes a multiplexer array 508 that includes a plurality of multiplexers 510. In this example, each multiplexer 510 is a 16:1 multiplexer, but other multiplexer configurations including, but not limited to, 4:1, 8:1, or 12:1 may also be used. The waveform from configuration / waveform memory 504 is loaded into the multiplexer 510 of the multiplexer. Thus, for example, in Figure 5 500, one of which is selected based on a waveform select signal received at the WFM input to IC 500. In this example, the waveform select signal is a 4-bit signal that allows up to 16 different waveforms to be selected from each multiplexer 510. The waveform select signal can be generated using room temperature control electronics or on IC 500 itself. In some embodiments, the waveform select signal can be generated using an on-chip sequencer.

[0058] The output waveform from each multiplexer 510 is coupled to a corresponding programmable signal source. Half of the multiplexer (mux) output is provided to the programmable signal source in the first signal envelope generator 512, and the other half of the multiplexer output is provided to the programmable signal source in the second signal envelope generator 514. Therefore, if each signal envelope generator includes 11 programmable signal sources (e.g., 11 programmable current sources), a total of 22 multiplexers 510 are provided, half of which are coupled to the corresponding programmable signal source in the first signal envelope generator 512, and the other half are coupled to the corresponding programmable signal source in the second signal envelope generator 514.

[0059] Figure 6 A more detailed schematic diagram of one of the first signal envelope generator 512 and the second signal envelope generator 514 is provided in FIG. Each of the first signal envelope generator 512 and the second signal envelope generator 514 receives a clock signal from a clock pin CLK and a trigger signal from a trigger pin TRIG. The trigger signal and the clock signal are used to cycle through the activation of the programmable signal source, as referred to herein. Figure 6 The trigger signal and clock signal may be provided by a room temperature arbitrary waveform generator, or may be generated by a source on the IC 500. The outputs of the first signal envelope generator 512 and the second signal envelope generator 514 are passed to the vector modulator 516. A more detailed schematic diagram of the vector modulator 516 is shown in Figure 7 . The vector modulator 516 includes a first mixer 522 and a second mixer 524, each of which receives a corresponding signal from one of the first signal envelope generator 512 and the second signal envelope generator 514. The first mixer 522 also receives a first local oscillator signal provided at the oscillator pin LO_I, and the second mixer 524 receives a second local oscillator signal provided at the oscillator pin LO_Q. Amplifiers 518 and 520 may be provided to amplify the received oscillator signals. The vector modulator 516 also includes a summing circuit 526 for summing the outputs of the first mixer 522 and the second mixer 524. The output of the adder circuit 526 is provided to the RF output pin RF_OUT.

[0060] refer to Figure 6 , the signal envelope generator circuit 600 includes a plurality of independent 8-bit digital-to-analog converters (DACs) 606. Figure 6In the particular example shown, 11 DACs 606 are provided, but other numbers of DACs may also be used. For example, the signal envelope generator circuit 600 may include, but is not limited to, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, or 15 DACs. In addition, the DACs may be configured to have different bit resolutions. For example, the DACs 606 may include, but are not limited to, 4-bit, 6-bit, 10-bit, or 12-bit DACs. Although the DACs are shown as current mode, voltage mode DACs may also be used. The output of each DAC 606 is coupled to a common node 601 so that the total current output of the signal envelope generator circuit 600 corresponds to the sum of the currents provided by each DAC 606. The total current may be converted into a voltage signal by providing a load 618 (e.g., a resistor) attached to the common node. In some embodiments, the combined output signal may be smoothed by providing a capacitor (such as a variable capacitor 616) in parallel with the load 618.

[0061] Each DAC 606 receives weights for generating a waveform from a corresponding multiplexer 604. In this example, the weights are provided with 8-bit resolution, allowing the DAC 606 to generate 256 different current values. The current weights are passed to the multiplexer 604 from the waveform memory 602, which covers Figure 5 SPI interface circuit 502 and configuration / waveform memory 504 are shown. Waveform memory 602 can also store weights for reference DAC 608. Reference DAC 608 generates a reference current I that is input to each of DAC 606. N Current I P is the reference current I N 604 because the current is mirrored. Similar to DAC 606, DAC 608 receives current weights from corresponding multiplexers 604 coupled to waveform memory 602. The bit resolution of the waveform provided to the multiplexer coupled to the reference DAC 608 can be the same or different than the bit resolution provided to the other multiplexers. A Select Signal (SEL) received at the IC is attached to each multiplexer 604, allowing selection of one of the different waveform weights input to each multiplexer 604.

[0062] The delay circuit 610 is coupled to the DAC 606 and allows the DACs to be activated sequentially. In this example, the delay circuit 610 is configured to cause the DACs to produce a symmetrical envelope. Specifically, the exemplary delay circuit 610 includes a latch RS flip-flop 611, a plurality of D-type flip-flops 612, and logic gates (e.g., AND gates, OR gates, NOT gates, etc.), which are configured to sequentially activate each DAC 606 and, after all DACs 606 are activated, sequentially deactivate each DAC 606 in an order opposite to the order in which all DACs 606 are activated. For example, when a trigger signal is received at TRIG, each of the DACs 606 is sequentially activated at each clock cycle of the clock signal provided at CLK until all DACs 606 are activated. The activation of the DAC 606 causes the DAC 606 to output a current at an amplitude specified by the weight received at the DAC 606 from the multiplexer coupled thereto. After all DACs 606 are activated, the latch RS flip-flop 611 is updated so that each DAC 606 is sequentially deactivated. This deactivation causes the DAC 606 to stop outputting current. The width of the combined current pulse generated by the DAC 606 is a function of the number of DACs used in this configuration. For example, in this example, there are 11 different DACs 606, so that the width of the entire combined current pulse generated by the sequential activation and deactivation is 22 clock cycles, and the shortest width of a single current pulse provided by a single DAC is 1 clock cycle. Figure 6 The configuration shown is an example of a delay circuit using flip-flops and logic gates, but other delay circuit configurations using flip-flops and / or logic gates are also possible. Although the delay circuit 610 is configured to provide sequential activation and deactivation of the DAC, other DAC activation and deactivation sequences may be used instead. In addition, in some embodiments, the activation and / or deactivation sequence may be stored in a memory rather than determined based on a clock signal. For example, IC500 may include a series of different waveforms pre-stored in a memory on the chip. The signal envelope generator circuit 600 may also include a shift register coupled to a select line to dial a sequence of waveforms into the DAC 606. Depending on the selected selection sequence, different waveforms may be combined in different sequences.

[0063] In some embodiments, it is provided that the combined current signal from the DAC 606 can reverse its polarity before being passed to the mixer circuit. In order to cover all four quadrants of any carrier phase, the amplitude of each signal from each signal envelope generator circuit should include a positive waveform and a negative waveform. In this example, polarity reversal is achieved using a polarity switch circuit including MOSFET 620. The source (or drain) of the first pair of MOSFETs 620 is coupled to a common input receiving the combined current output from the DAC 606, while the source (or drain) of the other pair of MOSFETs is coupled to a common ground terminal. The gate of one MOSFET 620 in the first pair is controlled by a first control signal (POL+), and the gate of the other MOSFET 620 in the first pair is controlled by the compensation of the first control signal (POL-). The same configuration is applied to the second pair of MOSFETs 620. Therefore, the polarity switch provides a positive envelope wave (ENV+) and a negative envelope wave (ENV-). Other circuit designs may also be used to achieve polarity reversal. In some embodiments, differential current may instead be used to provide positive and negative waves, eliminating the use of polarity switching circuitry entirely.

[0064] Figure 7 is a diagram showing an exemplary vector modulator circuit (e.g., such as Figure 5 516 in FIG. 1 ). A schematic diagram of a more detailed configuration of FIG. 1 . The positive and negative waveforms (also referred to as baseband currents) provided by each signal envelope generator circuit are up-converted using a pair of double-balanced passive mixers: a first mixer 708a and a second mixer 708b, whose differential outputs are transformer coupled using transformers 710a, 710b and combined in the current domain into a single-ended signal RF_OUT. A variable capacitor 712 allows the center frequency of the transformer to be tuned. In some embodiments, an additional DAC may be used to provide a continuous current to the baseband input of each mixer to allow for the elimination of LO leakage.

[0065] The local oscillator port (LO_I or LO_Q) of each mixer is driven by an amplifier chain that trades off power consumption and frequency coverage. Each local oscillator signal is converted from single-ended to differential by a corresponding transformer-based balun (balun 704a and balun 704b), followed by a fully differential gain amplifier (amplifier 706a and amplifier 706b) for the purpose of improving common-mode rejection. The differential signal is then amplified using a first mixer 708a, a second mixer 708b comprising a series of digital gates (e.g., NOT gates and NOR gates) so that the mixer LO port is driven rail-to-rail. The NOR gate configuration that receives the enable signal ENB prevents more than one signal from being high at the same time. To accommodate the octave bandwidth of operation, a tuning capacitor 702 can be incorporated on the local oscillator signal input side of each transformer.

[0066] Figure 8 1 shows a block diagram of an exemplary test setup 800 in which IC 500 is used to replace at least a portion of the qubit control electronic circuit 10 of FIG. Figure 8 As shown, IC 500 is located at an intermediate cooling stage 804 of a dilution refrigerator / cryogenic container. For example, IC 500 can be located at a 3K intermediate cooling stage. Alternatively, IC 500 can be located at other intermediate cooling stages of a dilution refrigerator / cryogenic container. Certain control signals and waveforms provided to IC 500 can be generated at a room temperature stage 802. For example, in some embodiments, data of an SPI interface, a select (SEL) control signal, a trigger (TRIG) control signal, a clock (CLK) signal, and a local oscillator (LO) signal are generated from a control electronic circuit 808 at a room temperature stage 802. The control electronic circuit 808 can include a plurality of different arbitrary waveform generators for generating one or more signals. The control electronic circuit 808 can also generate a Z drive control signal and a readout control signal for driving a qubit readout operation. As explained herein, in some embodiments, one or more of the signals provided to IC 500 can be generated on IC 500 instead. IC 500 is coupled to qubit chip 812, which is located in the primary cooling stage 806 of the dilution refrigerator / cryogenic vessel. Each output of IC 500 may be coupled to a different corresponding qubit XY drive line on qubit chip 812. In some embodiments, various attenuators and filters may be provided on the output lines of IC 500 to remove noise and match the power requirements of the qubits.

[0067] In some embodiments, the LO signal is also split to drive an auxiliary path, which, after passing through the amplitude and phase control unit, is weakly coupled to the XY signal path after the 3dB attenuator at the output of IC 500, allowing signal leakage to be eliminated. A second use of this auxiliary path is to permit the use of a room temperature arbitrary waveform generator to drive the qubit XY lines. In some embodiments, a second directional coupler is used to monitor the RF signal (PULSEMON) that propagates down to the qubit chip.

[0068] Fig. 9 is shown by having Figure 5 The IC 500 is shown as a test IC with the same configuration as the Figure 6-Figure 7 Graphs of example waveforms obtained with the signal envelope generator circuit configuration and the vector modulator circuit configuration shown. Waveform 900 corresponds to a trigger signal provided to IC 500 that initiates activation of a DAC (e.g., DAC 606). Waveform 900 has a frequency period of approximately 18ns. Waveform 902 corresponds to an RF output obtained from the IC with a carrier frequency of 5.6GHz. For this measurement, the IC was initialized to output a series of sixteen different waveforms, and the control lines were driven to step through all sixteen states. The chip was found to be selectable for LO frequencies and clock frequencies over the range of 4–8GHz and 0.5-3GHz, respectively. At a frequency of 5.5GHz, the minimum power required to drive the LO port was less than -10dBm, referenced to the input of the quadrature mixer. Referring to the output of the signal generator, the minimum power required to drive the clock port was found to be less than -20dBm.

[0069] After completing the room temperature measurement, use Figure 8 The test apparatus 800 shown has a cooling system. The qubit used in the quantum chip is a frequency-tunable transmon qubit. After determining the qubit frequency tuning curve and nominal readout parameters using a standard bringup routine, the qubit is tuned to 5.6 GHz, and the nominal values ​​for the room temperature attenuators and phase shifters are determined so that the |1> state occupancy is minimized in the absence of intentional XY drive. Next, a pair of Rabi experiments are performed using a CMOS integrated circuit. For these experiments ( Fig.10 ), corresponding to a 1 GHz clock, when the qubit is initialized and then driven by one or two pulses of varying amplitude but fixed duration of 22 ns, the state probabilities are measured as a function of the pulse amplitude. These measurements are performed using a single orthogonal set of weights to produce a nominally raised cosine envelope, while the other set of envelope weights is zero. By sweeping the DAC reference current (I N ) to change the amplitude. In a total of 11 different I PThe scan was repeated at 5000 values. 5000 measurements were made at each point to calculate the state probabilities. Although the state probabilities are nominally plotted against the envelope amplitudes predicted based on the digital settings, it was found that the state probabilities produced by I N The DAC is nonlinear and non-monotonic at cryogenic temperatures. Therefore, a calibration was performed in which the chip was triggered at 5MHz and a spectrum analyzer was used to measure the integrated power in a 190MHz band centered around 5.6GHz at the output of the monitor port to estimate the relative pulse amplitude. Fig.10 The results in show the expected behavior, with the maximum values ​​of the |0> and |1> state probabilities being consistent with expectations, with the measured readout error rates being 2.4% and 6.8% for the |0> and |1> states, respectively.

[0070] Power consumption was also measured for each configuration of the Rabi scan, where the chip was configured to output pulses continuously. The maximum power consumption was then conservatively estimated as that required to produce a continuous stream of π-pulses. Using this procedure, an upper limit on the DC power consumption was estimated to be 1.8 mW based on a room temperature 1.05 V supply (the voltage supplied at the reference plane of the IC was estimated to be about 950 mV due to IR drops along resistive cryogenic wiring).

[0071] The feasibility of using the fast switching and phase control features of ICs to perform coherent control of the qubit state is evaluated through a three-pulse based experiment. The protocol consists of (1) initializing the qubit to the |0> state, (2) applying an X-pulse to generate a θ A degrees rotation, (3) applying a carrier phase φ B The π-pulse is generated around an angle φ with the x-axis in the XY plane. B (4) Apply a second X-pulse to produce a θ rotation of the vector of A degrees of rotation, and (5) reading out the qubit state (see Fig.11 ). This sequence is φ B In (0, 2π) and the pulse amplitude A A The two-dimensional scan is performed on the A Before performing this measurement, the optimal configuration parameters required to generate π-pulses were determined to be φ according to the digital settings. B The results are presented together with baseline measurements using standard qubit control electronics. Fig.11 The RMS error between the two is 9.5% and can be improved by further calibration of the CMOS pulse generator. Fig.11 A performance comparison of the proposed cryogenic control IC with a standard room temperature control system is provided in .

[0072] Fig.12 1 is a block diagram illustrating an exemplary process 1200 for generating a qubit XY control signal. Process 1200 may be performed using a qubit control circuit described herein (such as IC 500). In a first step 1202, a first plurality of signal sources are sequentially activated. The signal sources may include current sources or voltage sources as described herein. The outputs of each signal source are combined (1204) to provide a first combined output. The first combined output is passed (1206) to a first mixer circuit, such as any mixer circuit described herein (e.g., mixer circuit 210). The mixer circuit mixes the first combined output with a local oscillator signal (1208) to provide a first qubit control signal. As explained herein, the signal source may include a programmable current source. Process 1200 may also include sequentially deactivating the first plurality of signal sources. The first combined output may also include the combined output of the sequentially deactivated first plurality of signal sources. Process 1200 may also include smoothing the first combined output before passing the first combined output to the first mixer. Process 1200 may also include: sequentially activating a second plurality of signal sources; combining the outputs of the sequentially activated second plurality of signal sources to provide a second combined output; passing the second combined output to a second mixer circuit; mixing the second combined output with a second local oscillator signal in the second mixer circuit to provide a second qubit control signal; and combining the first qubit control signal with the second qubit control signal to provide a qubit XY control signal. The qubit XY control signal may then be coupled to a qubit on a qubit chip (e.g., qubit chip 100 or qubit chip 812). The first local oscillator signal may be out of phase with the second local oscillator signal. For example, the first local oscillator signal may be a sine wave and the second local oscillator signal may be a cosine wave. Process 1200 may be performed at a temperature above 10 mK (e.g., above 100 mK) and below 40 K.

[0073] The discussion of exemplary control circuits presented herein relates to implementing a single qubit gate using an integrated circuit. However, the control circuits can also be used to implement multiple qubit gates.

[0074] The embodiments of quantum themes and quantum operations described in this specification may be implemented in suitable quantum circuits, or more generally in quantum computing systems (also referred to as quantum information processing systems), including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. The terms "quantum computing system" and "quantum information processing system" may include, but are not limited to, quantum computers, quantum cryptographic systems, topological quantum computers, or quantum simulators.

[0075] The terms quantum information and quantum data refer to information or data carried, held, or stored by a quantum system, where the smallest non-trivial system is a qubit, e.g., a system that defines a unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., having two or more levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting qubits. In some embodiments, the computational basis states are identified as the ground state and the first excited state, however it should be understood that other arrangements where computational states are identified as higher-order excited states are possible. It should be understood that quantum memories are devices capable of storing quantum data for long periods of time with high fidelity and efficiency, such as light-matter interfaces, where light is used for transmission and matter is used to store and preserve quantum features of quantum data such as superposition or quantum coherence,

[0076] Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, quantum circuit elements are configured to perform operations on data in a non-deterministic manner using quantum mechanical phenomena such as superposition and entanglement. Certain quantum circuit elements such as qubits can be configured to simultaneously represent information in more than one state and operate on the information. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs).

[0077] In contrast, classical circuit elements typically process data in a deterministic manner. Classical circuit elements can be configured to collectively execute the instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form. In some embodiments, classical circuit elements can be used to send data to or receive data from quantum circuit elements via electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuits, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQ that do not use bias resistors.

[0078] The manufacture of quantum circuit elements and classical circuit elements described herein may require the deposition of one or more materials, such as superconductors, dielectrics and / or metals. Depending on the selected materials, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering) or epitaxial techniques and other deposition processes. The process for manufacturing circuit elements described herein may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching techniques, dry etching techniques, or stripping processes. The materials forming the circuit elements described herein can use known lithography techniques (e.g., photolithography or electron beam lithography).

[0079] In the operation process of the quantum computing system using superconducting quantum circuit elements and / or superconducting classical circuit elements (such as, the circuit elements described herein), the superconducting circuit elements are cooled in a cryogenic container to a temperature that allows the superconductor material to exhibit superconducting properties. Superconductor (or superconducting) materials can be understood as materials that exhibit superconducting properties at or below the superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature of about 1.2 Kelvin), indium (superconducting critical temperature of about 3.4 Kelvin), NbTi (superconducting critical temperature of about 10 Kelvin) and niobium (superconducting critical temperature of about 9.3 Kelvin). Therefore, superconducting structures such as superconducting traces and superconducting ground planes are formed by materials that exhibit superconducting properties at or below the superconducting critical temperature.

[0080] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in this specification in the context of independent embodiments may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented independently in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0081] Similarly, although operations are described in a particular order in the drawings, this should not be understood as requiring that the operations be performed in the particular order shown or sequentially, or that all of the operations shown be performed, in order to obtain the desired results. For example, the actions listed in the claims can be performed in a different order and still obtain the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various components in the above implementations should not be understood as requiring such separation in all embodiments.

[0082] Several embodiments of the present invention have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of the present invention. Therefore, other embodiments are within the scope of the following claims.

Claims

1. A device for generating a quantum bit control signal, wherein: The device is operable at cryogenic temperatures, the device comprising: a first signal envelope generator circuit comprising a first plurality of signal sources, wherein an output of each of the first plurality of signal sources is combined to provide a first cumulative output; a first mixer circuit coupled to the first signal envelope generator circuit for up-conversion of a first accumulated output, wherein the first accumulated output is coupled to a first input of the first mixer circuit, an output of the first mixer circuit comprises a first qubit control signal, and the first mixer circuit is configured to mix the first accumulated output with a first local oscillator signal received at a second input of the first mixer circuit; a second signal envelope generator circuit comprising a second plurality of signal sources, wherein an output of each of the second plurality of signal sources is combined to provide a second cumulative output; and a second mixer circuit coupled to the second signal envelope generator for up-conversion of the second accumulated output, wherein the second accumulated output is coupled to a first input of the second mixer circuit, an output of the second mixer circuit comprises a second qubit control signal, and the second mixer circuit is configured to mix the second accumulated output with a second local oscillator signal received at a second input of the second mixer circuit, and the first qubit control signal is combined with the second qubit control signal to provide the qubit XY control signal, wherein the first local oscillator signal is out of phase with the second local oscillator signal.

2. The device according to claim 1, wherein The first plurality of signal sources includes a plurality of current sources.

3. The device according to claim 2, wherein The plurality of current sources include programmable current sources.

4. The device according to claim 2, wherein The output of each signal source is attached to a common node.

5. The device according to claim 1, wherein The first signal envelope generator circuit includes a variable capacitor coupled to the first accumulation output.

6. The device according to claim 1, wherein The first signal envelope generator circuit includes a delay circuit coupled to the first plurality of signal sources.

7. The device according to claim 6, wherein The delay circuit includes a plurality of flip-flops configured to cause sequential activation and deactivation of the first plurality of signal sources.

8. The device according to claim 1, wherein The first mixer circuit comprises a double balanced mixer circuit.

9. The device according to claim 8, wherein The double-balanced mixer circuit includes a plurality of MOSFETs.

10. The device of claim 1, further comprising a memory.

11. The device of claim 10, further comprising a multiplexer array coupled to the memory and the first signal envelope generator circuit.

12. The device according to claim 1, wherein The first local oscillator signal is any one of 90°, 180° or 270° out of phase with the second local oscillator signal.

13. The device according to claim 1, wherein The device is an integrated circuit.

14. A quantum computing system comprising: a cooling device capable of providing multiple cooling stages, wherein each cooling stage is maintained at a different temperature; a qubit chip comprising qubits, wherein the qubit chip is arranged in the cooling device and maintained at a first cooling stage, wherein the temperature of the first cooling stage is between 0 K and 100 mK; as well as A control circuit for generating qubit XY control signals, the control circuit being arranged in the cooling device and maintained at a second cooling stage, wherein the temperature of the second cooling stage is higher than the temperature of the first cooling stage and lower than room temperature, and wherein the control circuit is coupled to the qubit chip, wherein the control circuit for generating the qubit XY control signals comprises the device of any one of claims 1-13.

15. A method for generating a qubit control signal, wherein: Control signals are generated at cryogenic temperatures and include: sequentially activating a first plurality of signal sources; combining outputs of a first plurality of sequentially activated signal sources to provide a first combined output; passing the first combined output to a first mixer circuit; mixing the first combined output with a first local oscillator signal in the first mixer circuit by upconverting the first combined output to provide a first qubit control signal; sequentially activating a second plurality of signal sources; combining outputs of a second plurality of sequentially activated signal sources to provide a second combined output; passing the second combined output to a second mixer circuit; mixing the second combined output with a second local oscillator signal in a second mixer circuit to provide a second qubit control signal by upconverting the second combined output; and The first qubit control signal is combined with the second qubit control signal to provide a qubit XY control signal, wherein the first local oscillator signal is out of phase with the second local oscillator signal.

16. The method according to claim 15, wherein: The first plurality of signal sources includes a first plurality of current sources.

17. The method according to claim 16, wherein: The first plurality of current sources are programmable current sources.

18. The method of claim 15, comprising sequentially deactivating the first plurality of signal sources.

19. The method according to claim 18, wherein: The first combined output comprises a combined output of a first plurality of signal sources that are sequentially deactivated.

20. The method of claim 15, further comprising smoothing the first combined output prior to passing the first combined output to the first mixer circuit.

21. The method of claim 15, comprising performing the method at a temperature above 10 mK and below 40 K.

Images