Semiconductor device

Abstract

Balancing heat dissipation and durability. The semiconductor device (1) includes: an insulating circuit board (2) having an insulating board (20), a first metal layer (21) formed on the upper surface of the insulating board, and a second metal layer (22) formed on the lower surface of the insulating board; a heat sink (10) on which the insulating circuit board is disposed on the upper surface; a semiconductor element (3) disposed on the upper surface of the first metal layer by means of a bonding material; and a housing (11) surrounding the insulating circuit board and the semiconductor element. The first metal layer has circuit layers (23, 24, 25) electrically connected to the semiconductor element and an annular layer (26) formed with a gap from the circuit layers and surrounding the periphery of the circuit layers. The second metal layer is disposed at a position opposite to the annular layer. The housing portion is fixed to the annular layer by means of an adhesive (B).

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Semiconductor devices have a substrate on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes) are mounted, and are used in inverter devices and the like. These semiconductor devices are constructed by placing these semiconductor elements on a metal foil formed on the surface of an insulating substrate. The semiconductor elements are secured to the metal foil using a bonding material such as solder.

[0003] In the past, there was a proposal for an IGBT module in which an insulating substrate is arranged on the upper surface of a copper base serving as a heat sink, and a semiconductor element is arranged on the upper surface of the insulating substrate by means of solder and joined. However, the requirements for miniaturization, high heat resistance, and long life of the package are increasing. For example, as a countermeasure for miniaturization, high density of device mounting is considered, but the heat density also increases, so it is required to further improve the heat dissipation. In addition, in order to improve the heat dissipation, it is effective to thin or reduce the thermal resistance part. As an example, a so-called copper-free base structure in which the copper base serving as a heat sink is removed has been put into practical use (for example, refer to patent documents 1 and 2).

[0004] In the insulating substrates described in Patent Documents 1 and 2, a metal pattern is formed on the upper surface of the substrate (ceramic substrate) and a metal film is formed on the lower surface of the substrate. In addition, in Patent Documents 1 and 2, a housing covering the insulating substrate and semiconductor elements is directly bonded to the periphery of the substrate.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-216349

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2017-228811 Summary of the Invention

[0009] Problems to be Solved by the Invention

[0010] However, in Patent Documents 1 and 2, in order to ensure the bonding area of the outer shell, it is necessary to move the metal pattern on the substrate toward the center side of the substrate. As a result, it is assumed that the volume difference between the metal pattern on the upper surface side and the metal film on the lower surface side becomes larger. In this case, since the amount of deformation with respect to thermal changes differs between the upper surface side and the lower surface side of the substrate, shear stress is generated, and problems such as deterioration of durability may occur.

[0011] The present invention has been made in view of this point, and an object thereof is to provide a semiconductor device capable of achieving both heat dissipation and durability.

[0012] Solutions for Solving the Problems

[0013] A semiconductor device according to one aspect of the present invention is characterized in that the semiconductor device includes: an insulating circuit substrate having an insulating board, a first metal layer formed on the upper surface of the insulating board, and a second metal layer formed on the lower surface of the insulating board; a semiconductor element disposed on the upper surface of the first metal layer by means of a bonding material; and a housing portion surrounding the insulating circuit substrate and the semiconductor element. The first metal layer has a circuit layer electrically connected to the semiconductor element and a ring-shaped layer formed so as to surround the circuit layer with a gap therebetween. The second metal layer has a first recess recessed toward the insulating board at a portion opposite to the ring-shaped layer, and the housing portion is fixed to the ring-shaped layer by means of an adhesive.

[0014] A semiconductor device according to another aspect of the present invention is characterized in that the semiconductor device includes: an insulating circuit substrate having an insulating board, a first metal layer formed on the upper surface of the insulating board, and a second metal layer formed on the lower surface of the insulating board; a semiconductor element disposed on the upper surface of the first metal layer by means of a bonding material; and a housing portion surrounding the insulating circuit substrate and the semiconductor element. The first metal layer has a circuit layer electrically connected to the semiconductor element and a ring-shaped layer formed so as to surround the circuit layer with a gap therebetween. The ring-shaped layer has a second recess recessed toward the insulating board, and the housing portion is fixed to the ring-shaped layer by means of an adhesive.

[0015] Effects of the Invention

[0016] According to the present invention, both heat dissipation and durability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a plan view showing an example of the semiconductor device according to the present embodiment.

[0018] Figure 2is disposed on the radiator, Figure 1 The cross-sectional schematic view of the semiconductor device shown.

[0019] Figure 3 is from Figure 1 The figure of the semiconductor device shown with the housing removed.

[0020] Figure 4 is the partial enlarged view of the semiconductor device according to the present embodiment.

[0021] Figure 5 is the schematic diagram showing the change of the semiconductor manufacturing device according to the modified example.

[0022] Figure 6 is the schematic diagram showing the change of the semiconductor manufacturing device according to the modified example. Detailed implementation mode

[0023] Hereinafter, the semiconductor device to which the present invention can be applied will be described. Figure 1 is the plan view showing an example of the semiconductor device according to the present embodiment. Figure 2 is disposed on the radiator, Figure 1 The cross-sectional schematic view of the semiconductor device shown. Figure 3 is from Figure 1 The figure of the semiconductor device shown with the housing removed. In addition, the semiconductor device shown below is only an example and is not limited thereto, and can be appropriately changed.

[0024] The semiconductor device 1 is applied to a power conversion device such as a power module, for example. As Figures 1 to 3 shown, the semiconductor device 1 is constituted by disposing the semiconductor element 3 on the upper surface of the insulating circuit board 2. The semiconductor device 1 can be used by disposing the insulating circuit board 2 on the upper surface of the radiator 10. The radiator 10 has a square shape in plan view and is formed of a metal such as copper. For example, a plating treatment is applied to the surface of the radiator 10. A thermally conductive mixture can be interposed between the insulating circuit board 2 and the radiator 10. In the present specification, the plan view means the case of observing the semiconductor device 1 from the direction perpendicular to the insulating circuit board 2.

[0025] The insulating circuit board 2 is constituted by laminating a metal layer and an insulating layer, and the insulating circuit board 2 is formed into a square shape in plan view slightly smaller than the upper surface of the radiator 10. Specifically, the insulating circuit board 2 has: an insulating board 20 including an upper surface (one side surface) and a lower surface (the other side surface) opposite to the upper surface; a first metal layer 21 formed on the upper surface of the insulating board 20; and a second metal layer 22 (refer to Figure 2 , Figure 3), which is formed on the lower surface of the insulating board 20. The thicknesses of the insulating board 20, the first metal layer 21, and the second metal layer 22 may be the same or different from each other.

[0026] The insulating board 20 is formed of an insulator such as ceramics, and the first metal layer 21 and the second metal layer 22 are formed of copper foil, for example. The first metal layer 21 has a plurality of metal patterns. Specifically, the first metal layer 21 has a first circuit layer 23, a second circuit layer 24, a third circuit layer 25, and an annular layer 26 formed around these circuit layers as a circuit layer electrically connected to the semiconductor element 3.

[0027] The first circuit layer 23 has a rectangular shape in plan view, and two are arranged side by side in the width direction at the center of the insulating board 20. The second circuit layer 24 has a longitudinally long shape in plan view extending in the width direction on the side of the first circuit layer 23. Two second circuit layers 24 are arranged so as to sandwich the two first circuit layers 23 in the length direction. The third circuit layer 25 has a longitudinally long shape in plan view extending in the length direction on the side of the first circuit layer 23. Two third circuit layers 25 are arranged so as to sandwich the two first circuit layers 23 in the width direction. These circuit layers are arranged with a slight gap between each other.

[0028] The annular layer 26 has a plane, and is formed in a quadrangular annular shape in plan view so as to surround the periphery of these circuit layers with a gap relative to each of the above circuit layers. The outer edge portion of the annular layer 26 is located slightly inside the outer edge portion of the insulating board 20. As will be described in detail later, the annular layer 26 does not function as a circuit pattern, and a plurality of shallow recesses (Japanese: dimple) 29 are formed on the upper surface of the annular layer 26 (refer to Figure 4 ). The annular layer 26 may be insulated from the first circuit layer 23, the second circuit layer 24, and the third circuit layer 25 in the first metal layer 21. The annular layer 26 may also be insulated from the second metal layer 22. In addition, as will be described in detail later, a gap G having an annular shape in plan view is formed between the annular layer 26 and each circuit layer (circuit layers 23, 24, 25).

[0029] The second metal layer 22 has a plane and has a quadrangular shape in plan view covering substantially the entire lower surface of the insulating board 20. Specifically, the outer edge portion of the second metal layer 22 is located slightly inside the outer edge portion of the insulating board 20 and slightly outside the outer edge portion of the annular layer 26. That is, in plan view, the entire annular layer 26 overlaps with the second metal layer 22. As will be described in detail later, a plurality of shallow recesses 28 are formed at a portion of the lower surface of the second metal layer 22 facing the annular layer 26 (refer to Figure 4 ).

[0030] As described above, since a predetermined gap is formed between the first metal layer 21 and the plurality of circuit layers (the first circuit layer 23, the second circuit layer 24, and the third circuit layer 25) and the annular layer 26, the area of the first metal layer 21 is smaller than that of the second metal layer 22 when viewed from above. If the thickness of the first metal layer 21 is the same as the thickness of the second metal layer 22, the volume of the second metal layer 22 becomes larger than the volume of the first metal layer 21.

[0031] The insulating circuit board 2 configured in this way can be, for example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazing) board. In addition, the insulating board 20 can be formed of ceramic materials such as alumina (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4).

[0032] A semiconductor element 3 is disposed on the upper surface of the first circuit layer 23 of the insulating circuit board 2. The semiconductor element 3 is formed, for example, of a semiconductor substrate such as silicon (Si) or silicon carbide (SiC) into a square shape when viewed from above. For one first circuit layer 23, two semiconductor elements 3 are arranged and disposed along the length direction of the first circuit layer 23. The semiconductor elements 3 are respectively disposed on the first circuit layer 23 by a bonding material S such as solder. Thereby, the semiconductor element 3 is electrically connected to the first circuit layer 23.

[0033] In addition, as the semiconductor element 3, switching elements such as IGBT (Insulated Gate Bipolar Transistor) and power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and diodes such as FWD (Free Wheeling Diode) can be used. In addition, as the semiconductor element 3, an RC (Reverse Conducting) - IGBT obtained by integrating an IGBT and an FWD, an RB (Reverse Blocking) - IGBT having sufficient withstand voltage with respect to reverse bias, etc. can also be used.

[0034] The two semiconductor elements 3 are electrically connected by a wiring member W1. One semiconductor element 3 is electrically connected to the second circuit layer 24 via a wiring member W2. The second circuit layer 24 is electrically connected to an external terminal 27 described later via a wiring member W3. The other semiconductor element 3 is electrically connected to the third circuit layer 25 via a wiring member W4. The third circuit layer 25 is electrically connected to the other external terminal 27 via a wiring member W5.

[0035] In addition, each of the above-described wiring members uses a wire. The material of the wire can be any one of gold, copper, aluminum, gold alloy, copper alloy, and aluminum alloy, or a combination thereof. In addition, members other than the wire can also be used as the wiring member. For example, a strip can be used as the wiring member.

[0036] The insulating circuit board 2 and the semiconductor element 3 are covered by a housing 11, which is a housing portion surrounding the insulating circuit board 2 and the semiconductor element 3. The housing 11 is composed of an annular wall portion 12 surrounding the outer peripheral side of the insulating circuit board 2 and a lid portion 13 covering the upper side of the insulating circuit board 2 and the semiconductor element 3. The housing 11 is formed of, for example, a synthetic resin.

[0037] The annular wall portion 12 is formed in a quadrangular annular shape in plan view corresponding to the insulating plate 20 and the annular layer 26, and stands up in the thickness direction (vertical direction) of the insulating circuit board 2. External terminals 27 are buried in each side of the specified quadrangular annular shape of the annular wall portion 12. The external terminal 27 is formed in an L shape in cross section, one end protruding from the inner wall surface of the annular wall portion 12, and the other end protruding from the upper surface of the annular wall portion 12. One end of the external terminal 27 faces the annular layer 26 above the insulating circuit board 2.

[0038] A quadrangular annular step portion 14 capable of accommodating the outer edge portion of the insulating circuit board 2 is formed at the lower end of the annular wall portion 12. As will be described in detail later, the step portion 14 is composed of a lower surface portion 15 and a side surface portion 16 and is formed in an L shape in cross section. The annular wall portion 12 is arranged to fill (coat) an adhesive B in the step portion 14 and accommodate the outer edge portion of the insulating circuit board 2 in the step portion 14. By curing the adhesive B, the annular wall portion 12 is bonded to the insulating circuit board 2. That is, the annular wall portion 12 is fixed to the annular layer 26 by means of the adhesive B.

[0039] In addition, as shown in the above semiconductor device, in order to improve heat dissipation, for a so-called copperless base structure in which the copper base as a heat sink is removed, thinning of the insulating plate as a thermal resistance portion has been achieved. However, since it is a copperless base, it is necessary to directly dispose the housing as the housing portion on the outer peripheral edge of the insulating circuit board. Therefore, it is necessary to make the circuit pattern formed on the upper surface of the insulating plate close to the center and ensure an area for bonding the housing on the outer periphery of the circuit pattern.

[0040] In this case, there may be a difference in volume between the metal layer (circuit pattern) formed on the upper surface of the insulating board and the metal layer formed on the lower surface of the insulating board. Generally, an insulating circuit board is a laminate of metals and ceramics with different coefficients of linear expansion. Therefore, there is a tendency that the greater the volume difference between the metal layer on the upper surface side and the metal layer on the lower surface side of the insulating board, the greater the amount of substrate deformation with respect to thermal changes. As a result, a large shear stress is generated in the insulating circuit board, and the durability deteriorates. That is, it can be said that there is a trade-off relationship between the heat dissipation and durability of the semiconductor device.

[0041] Therefore, the inventor of the present application came up with the present invention in order to balance the heat dissipation and durability of the semiconductor device. Specifically, in the present embodiment, the following structure is adopted: a ring-shaped layer 26 unrelated to the circuit pattern is formed in the outer peripheral region of the insulating circuit board 2 for arranging the housing 11, and the housing 11 (ring-shaped wall portion 12) is arranged on the ring-shaped layer 26.

[0042] According to this structure, since there is a ring-shaped layer 26 that is electrically unrelated to each circuit layer (the first circuit layer 23, the second circuit layer 24, and the third circuit layer 25), the volume of the first metal layer 21 on the upper surface side of the insulating board 20 can be made close to the volume of the second metal layer 22 on the lower surface side. That is, the volume difference between the metal layers can be reduced on the upper surface side and the lower surface side of the insulating board 20. Therefore, even in the structure of the copper-free base with improved heat dissipation, the shear stress generated due to thermal deformation can be reduced, and the heat dissipation and durability can be balanced.

[0043] Next, refer to Figure 4 to describe the detailed structure of the semiconductor device according to the present embodiment. Figure 4 is a partially enlarged view of the semiconductor device according to the present embodiment. Specifically, Figure 4 A is Figure 2 a partially enlarged view near the ring-shaped layer of Figure 4 B is Figure 3 a partially enlarged view near the ring-shaped layer of

[0044] As described above, in the upper surface of the insulating board 20, a ring-shaped layer 26 is formed so as to surround the peripheries of the plurality of circuit layers (the first circuit layer 23, the second circuit layer 24, and the third circuit layer 25) with a prescribed gap left in the outer periphery. In addition, as Figure 4 shown in A and Figure 4 B, a plurality of shallow recesses 28 are formed in the portion of the second metal layer 22 opposite to the ring-shaped layer 26, and the plurality of shallow recesses 28 are first recesses that are recessed toward the insulating board 20. The plurality of shallow recesses 28 are arranged directly below the ring-shaped layer 26 and overlap the plane of the ring-shaped layer 26 in a top view. More specifically, as Figure 4As shown in FIG. B, a plurality of shallow recesses 28 are arranged to form a discontinuous double quadrilateral ring shape at a predetermined interval. In addition, each shallow recess 28 is formed to a depth reaching the lower surface of the insulating board 20.

[0045] In addition, as described above, in a plan view, an annular gap G is provided between the annular layer 26 and the circuit layers 23, 24, and 25. Preferably, no shallow recess 28 is arranged in the portion of the second metal layer 22 facing the annular gap G. That is, preferably, no shallow recess 28 is arranged in the portion of the second metal layer 22 directly below the gap G. In this way, the gap G and the shallow recess 28 are arranged so as not to overlap each other in a plan view, so that a decrease in the rigidity of the insulating board 20 near the gap G can be suppressed. As a result, the generation of cracks in the insulating board 20 near the gap G can be reduced.

[0046] On the other hand, a plurality of shallow recesses 29 are formed in the annular layer 26, and the plurality of shallow recesses 29 are second concave portions recessed toward the insulating board 20. The plurality of shallow recesses 29 overlap the plane of the second metal layer 22 in a plan view. In addition, each shallow recess 29 is formed to a depth reaching the upper surface of the insulating board 20. As Figure 4 shown in FIG. B, the shallow recess 28 and the shallow recess 29 are arranged at positions that do not overlap each other in a plan view. In addition, the number of shallow recesses 28 is larger than the number of shallow recesses 29. Moreover, the shallow recess 28 is formed larger than the shallow recess 29.

[0047] In addition, as described above, an annular wall portion 12 is bonded to the outer edge portion of the insulating circuit board 2 by an adhesive B. Specifically, the outer peripheral edge portion of the insulating circuit board 2 enters the stepped portion 14 of the annular wall portion 12. The stepped portion 14 has a lower surface portion 15 facing the upper surface of the annular layer 26 and a side surface portion 16 extending downward from the outer peripheral end of the lower surface portion 15. The inner peripheral side end of the lower surface portion 15 is located at a position closer to the inside (center side) of the annular layer 26 than the shallow recess 29. As Figure 4 shown in FIG.A, the lower end of the side surface portion 16 extends to a position below the lower surface of the insulating board 20 and in the middle of the thickness of the second metal layer 22. The adhesive B enters between the lower surface portion 15 and the annular layer 26 and between the side surface portion 16 and the insulating board 20. That is, the adhesive B enters the bottom of the shallow recess 29.

[0048] In this way, in the present embodiment, since a plurality of shallow recesses 28 are formed in the second metal layer 22, the volume of the second metal layer 22 can be made close to the volume of the first metal layer 21. That is, the volume difference between the first metal layer 21 and the second metal layer 22 can be reduced. Therefore, the shear stress generated by thermal deformation can be further reduced, and the durability can be improved.

[0049] In addition, since a plurality of shallow recesses 29 are formed in the annular layer 26, the surface area of the annular layer 26 can be increased, and the adhesive B also enters the shallow recesses 29, thereby improving the adhesiveness of the annular wall portion 12.

[0050] In addition, since the shallow recess 28 and the shallow recess 29 are arranged so as not to overlap each other, the rigidity of the insulating circuit board 2 is not affected, and the durability of the insulating circuit board 2 can be ensured.

[0051] As described above, according to the present embodiment, since the annular layer 26 unrelated to the circuit pattern is arranged on the upper surface of the insulating board 20, the heat dissipation and durability of the insulating circuit board 2 can be taken into account.

[0052] In addition, in the above embodiment, a structure in which two semiconductor elements 3 are arranged for one first circuit layer 23 is provided, but the structure is not limited thereto. The number of semiconductor elements 3 can be one or three or more.

[0053] In addition, in the above embodiment, a structure in which the semiconductor element 3 is formed in a square shape in plan view is provided, but the structure is not limited thereto. The semiconductor element can also be formed in a polygon shape other than a rectangle.

[0054] In addition, in the above embodiment, a structure in which the shallow recess 28 is formed as the first recess and the shallow recess 29 is formed as the second recess is provided, but the structure is not limited thereto. For example, continuous or discontinuous grooves can be formed instead of the shallow recesses. In addition, shallow recesses and grooves can be combined. For example, the first recess can be a shallow recess and the second recess can be a groove, or vice versa. In addition, the number, size, and depth of the shallow recesses 28 and 29 can be appropriately changed in consideration of the required heat dissipation and adhesiveness.

[0055] In addition, in the above embodiment, a case where the thickness of each circuit layer is the same as the thickness of the annular layer 26 is described, but the structure is not limited thereto. For example, the thickness of the annular layer 26 can be made larger than the thickness of each circuit layer. According to this structure, the volume of the first metal layer 21 can be made closer to the volume of the second metal layer 22, and the durability can be further improved.

[0056] In addition, in the above embodiment, a case where the thickness of the first metal layer 21 is the same as the thickness of the second metal layer 22 and the volume of the second metal layer 22 is larger than the volume of the first metal layer is described, but the structure is not limited thereto. The thickness of the second metal layer 22 can be made smaller than the thickness of the first metal layer 21 within a range where the heat dissipation of the second metal layer 22 can be ensured, and the size relationship of the volumes can be the same or reversed.

[0057] In the above-described embodiment, a structure in which shallow recesses are formed in both the second metal layer 22 and the annular layer 26 has been described, but the structure is not limited thereto. It may also be Figure 5 such a structure. Figure 5 It is a schematic diagram showing changes in the semiconductor device according to the modified example. Specifically, Figure 5 A is an example in which shallow recesses 28 are formed only in the second metal layer 22, Figure 5 B is an example in which shallow recesses 29 are formed only in the annular layer 26. In either case, the above-described effects can be obtained. Especially in Figure 5 B, the depth of the shallow recess 29 does not reach the upper surface of the insulating plate 20. In this case, the adhesiveness is improved by the shallow recess 29, and the volume of the first metal layer 21 can be made close to the volume of the second metal layer 22, ensuring the durability of the insulating circuit board 2.

[0058] In the above-described embodiment, the semiconductor device 1 in which a plurality of shallow recesses 28 are provided in the region of the second metal layer 22 that overlaps the annular layer 26 in plan view has been described. The arrangement of the shallow recesses 28 is not limited to this embodiment. It may also be Figure 6 such a structure. Figure 6 It is a schematic diagram showing changes in the semiconductor device according to the modified example. Specifically, Figure 6 A is a partial enlarged view of the semiconductor device in cross section, Figure 6 B is a partial enlarged view of the semiconductor device in plan view. Similar to the above-described embodiment, in Figure 6 A and Figure 6 B shown in the modified example, an annular gap G that is annular in plan view and is defined by the annular layer 26, the circuit layers 23, 24, 25, and the insulating plate 20 is provided between the annular layer 26 and the circuit layers 23, 24, 25. The shallow recesses 28 are provided in the region of the second metal layer 22 that overlaps the annular layer 26 and in the region of the second metal layer 22 that overlaps the circuit layers 23, 24, 25 in plan view. In addition, the shallow recesses 28 are not arranged in the portion of the second metal layer 22 that faces the annular gap G. By arranging the shallow recesses 28 in this way, the volume of the second metal layer 22 can be further reduced to be close to the volume of the first metal layer 21. As a result, the volume difference between the first metal layer 21 and the second metal layer 22 can be reduced.

[0059] In addition, the present embodiment and the modified example have been described, but as other embodiments, the above-described embodiment and the modified example may be combined as a whole or partially.

[0060] In addition, the present embodiment is not limited to the above-described embodiments and modifications, and various changes, substitutions, and modifications can be made without departing from the gist of the technical idea. Moreover, if the technical idea can be implemented in other ways due to technological advancements or other derived technologies, such methods can also be used for implementation. Therefore, the claims cover all embodiments that can be included within the scope of the technical idea.

[0061] The following summarizes the characteristic points in the above embodiments.

[0062] The semiconductor device described in the above embodiment is characterized in that the semiconductor device includes: an insulating circuit board having an insulating plate, a first metal layer formed on the upper surface of the insulating plate, and a second metal layer formed on the lower surface of the insulating plate; a semiconductor element disposed on the upper surface of the first metal layer by means of a bonding material; and a housing portion surrounding the insulating circuit board and the semiconductor element. The first metal layer has a circuit layer electrically connected to the semiconductor element and a ring-shaped layer formed to surround the circuit layer with a gap therebetween. The second metal layer has a first recess recessed toward the insulating plate at a position opposite to the ring-shaped layer, and the housing portion is fixed to the ring-shaped layer by means of an adhesive.

[0063] In addition, in the semiconductor device according to the above embodiment, it is characterized in that the ring-shaped layer has a plane, and in a top view, the ring-shaped layer and the second metal layer at least partially overlap, and the first recess and the plane of the ring-shaped layer overlap.

[0064] In addition, in the semiconductor device according to the above embodiment, it is characterized in that the ring-shaped layer has a second recess recessed toward the insulating plate.

[0065] The semiconductor device according to the above embodiment is characterized in that the semiconductor device includes: an insulating circuit board having an insulating plate, a first metal layer formed on the upper surface of the insulating plate, and a second metal layer formed on the lower surface of the insulating plate; a semiconductor element disposed on the upper surface of the first metal layer by means of a bonding material; and a housing portion surrounding the insulating circuit board and the semiconductor element. The first metal layer has a circuit layer electrically connected to the semiconductor element and a ring-shaped layer formed to surround the circuit layer with a gap therebetween. The ring-shaped layer has a second recess recessed toward the insulating plate, and the housing portion is fixed to the ring-shaped layer by means of an adhesive.

[0066] Further, in the semiconductor device according to the above-described embodiment, the second metal layer has a plane, and in a plan view, the annular layer and the second metal layer at least partially overlap, and the second concave portion and the plane of the second metal layer overlap.

[0067] Further, in the semiconductor device according to the above-described embodiment, the second metal layer has a first concave portion recessed toward the insulating plate at a portion facing the annular layer.

[0068] Further, in the semiconductor device according to the above-described embodiment, the volume of the second metal layer is larger than the volume of the first metal layer.

[0069] Further, in the semiconductor device according to the above-described embodiment, the first concave portion and the second concave portion are provided at positions that do not overlap each other in a plan view.

[0070] Further, in the semiconductor device according to the above-described embodiment, the first concave portion and / or the second concave portion are formed by a plurality of shallow recesses and / or grooves.

[0071] Further, in the semiconductor device according to the above-described embodiment, the first concave portion and the second concave portion are formed by a plurality of shallow recesses, and the number of the first concave portions is larger than the number of the second concave portions.

[0072] Further, in the semiconductor device according to the above-described embodiment, the thickness of the annular layer is larger than the thickness of the circuit layer.

[0073] Industrial Applicability

[0074] As described above, the present invention has an effect of achieving both heat dissipation and durability, and is particularly useful in terms of a semiconductor device and a method for manufacturing a semiconductor device.

[0075] This application is based on Japanese Patent Application No. 2018-230623 filed on Dec. 10, 2018. The entire content thereof is incorporated herein by reference.

Claims

1. A semiconductor device, characterized in that, the semiconductor device includes: an insulating circuit board having an insulating plate, a first metal layer formed on the upper surface of the insulating plate, and a second metal layer formed on the lower surface of the insulating plate; a semiconductor element disposed on the upper surface of the first metal layer by means of a bonding material; and a housing portion surrounding the insulating circuit board and the periphery of the semiconductor element, the first metal layer has a circuit layer electrically connected to the semiconductor element and a ring-shaped layer that forms a gap with respect to the circuit layer and is formed to surround the periphery of the circuit layer, the second metal layer has a first concave portion recessed toward the insulating plate at a portion opposite to the ring-shaped layer, the housing portion is fixed to the ring-shaped layer by means of an adhesive, the volume of the second metal layer is close to the volume of the first metal layer, when viewed from above, the gap and the first concave portion do not overlap with each other, the ring-shaped layer has a second concave portion recessed toward the insulating plate, the first concave portion and the second concave portion are provided at positions that do not overlap with each other when viewed from above.

2. The semiconductor device according to claim 1, characterized in that, the ring-shaped layer has a plane, when viewed from above, the ring-shaped layer and the second metal layer at least partially overlap, and the first concave portion and the plane of the ring-shaped layer overlap.

3. The semiconductor device according to claim 1, characterized in that, the volume of the second metal layer is greater than the volume of the first metal layer.

4. The semiconductor device according to claim 3, characterized in that, the first concave portion and / or the second concave portion is formed by a plurality of shallow recesses and / or grooves.

5. The semiconductor device according to claim 3, characterized in that, the first concave portion and the second concave portion are formed by a plurality of shallow recesses, the number of the first concave portions is more than the number of the second concave portions.

6. The semiconductor device according to claim 1 or 2, characterized in that, the thickness of the ring-shaped layer is greater than the thickness of the circuit layer.

7. The semiconductor device according to claim 1, characterized in that, the outer edge portion of the ring-shaped layer is located at a position closer to the inside than the outer edge portion of the insulating plate.

8. A semiconductor device, characterized in that, the semiconductor device includes: an insulating circuit board having an insulating plate, a first metal layer formed on the upper surface of the insulating plate, and a second metal layer formed on the lower surface of the insulating plate; a semiconductor element disposed on the upper surface of the first metal layer by means of a bonding material; and a housing portion surrounding the insulating circuit board and the periphery of the semiconductor element, the first metal layer has a circuit layer electrically connected to the semiconductor element and a ring-shaped layer that forms a gap with respect to the circuit layer and is formed to surround the periphery of the circuit layer, the ring-shaped layer has a second concave portion recessed toward the insulating plate, the housing portion is fixed to the ring-shaped layer by means of an adhesive, the volume of the second metal layer is close to the volume of the first metal layer, the second concave portion is formed to a depth reaching the upper surface of the insulating plate, the ring-shaped layer is electrically independent of the circuit layer, The second metal layer has a first recess that is recessed toward the insulating plate at a portion opposite to the annular layer. The first recess and the second recess are provided at positions that do not overlap each other in a top view.

9. The semiconductor device according to claim 8, wherein the second metal layer has a plane, in a top view, the annular layer and the second metal layer at least partially overlap, and the second recess and the plane of the second metal layer overlap.

10. The semiconductor device according to claim 8, wherein the volume of the second metal layer is larger than the volume of the first metal layer.

11. The semiconductor device according to claim 10, wherein the first recess and / or the second recess are formed by a plurality of shallow recesses and / or grooves.

12. The semiconductor device according to claim 10, wherein the first recess and the second recess are formed by a plurality of shallow recesses, and the number of the first recesses is larger than the number of the second recesses.

13. The semiconductor device according to claim 8 or 9, wherein the thickness of the annular layer is larger than the thickness of the circuit layer.

14. The semiconductor device according to claim 8, wherein the outer edge portion of the annular layer is located at a position closer to the inside than the outer edge portion of the insulating plate.

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