Robust current sensing during reverse current load conditions

Abstract

Various embodiments of the present application are directed to robust current sensing during reverse current load conditions. A current sensing circuit includes: a load transistor having a current path coupled between a power terminal and a corresponding load terminal; a sense transistor having a current path coupled between a power terminal and a corresponding sense terminal, each sense transistor being coupled to a corresponding load transistor; an N-channel transistor having a current path coupled between a corresponding sense transistor and a corresponding sense terminal; an amplifier for selectively equalizing a voltage across one of the load transistors and a voltage across one of the sense transistors; and a bypass circuit coupled to a body terminal of the N-channel transistor.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for robust current sensing during reverse current load conditions. Background Art

[0002] Over the past two decades, there has been a trend to replace electromechanical relays with integrated circuit smart power switches, for example in the automotive industry and for automotive body power applications. Smart power switches are typically installed in body control modules, which are interfaces between very noisy power supply networks and sensitive loads that need to be protected under all conditions. Smart power switches must operate under harsh temperature and voltage conditions. Furthermore, smart power switches must also operate under certain load conditions that could seriously jeopardize the normal operation of the body control module. Summary of the invention

[0003] According to one embodiment, a current sensing circuit includes: a plurality of load transistors having a current path coupled between a power terminal and a plurality of load terminals; a plurality of sense transistors having a current path coupled between a power terminal and a sense terminal, each sense transistor being coupled to a corresponding load transistor; a plurality of N-channel transistors having a current path coupled between a corresponding sense transistor and a corresponding sense terminal; an amplifier for selectively equalizing a voltage across one of the load transistors and a voltage across one of the sense transistors; and a plurality of bypass circuits coupled to body terminals of the plurality of N-channel transistors.

[0004] According to another embodiment, a current sensing circuit includes: a plurality of load transistors having a current path coupled between a power terminal and a plurality of load terminals; a plurality of sense transistors having a current path coupled between a power terminal and a sense terminal, each sense transistor being coupled to a corresponding load transistor; a plurality of N-channel transistors having a current path coupled between a corresponding sense transistor and a corresponding sense terminal; an amplifier for selectively equalizing a voltage across a load transistor of the load transistors and a voltage across a sense transistor of the sense transistors; and a plurality of bypass circuits coupled to body terminals of the plurality of N-channel transistors.

[0005] In another embodiment, a current sensing method includes: providing a load current in a first current path; sensing the load current to provide a sensing current in a second current path; passing the sensing current through an N-channel transistor in the second current path; and bypassing a parasitic current flowing out of a body terminal of the N-channel transistor so that the parasitic current is not added to the sensing current in the second current path. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a schematic diagram of a current sensing circuit with reverse current protection for a multi-channel power switch according to one embodiment;

[0008] Figure 2 is a cross-sectional view of a lateral multi-collector parasitic PNP device associated with an exemplary current sensing circuit;

[0009] Figure 3A and Figure 3B According to one embodiment, Figure 1 A schematic diagram of a bias circuit in a power switch;

[0010] Figure 4A and Figure 4B According to another embodiment, Figure 1 A schematic diagram of a bias circuit in a power switch;

[0011] Figure 5 According to an embodiment Figure 1 Detailed schematic diagram of the power switch;

[0012] Figure 6 According to another embodiment Figure 1 Detailed schematic diagram of the power switch;

[0013] Figure 7 is a graph of the sense current before and after a reverse current condition using a prior art sensing circuit;

[0014] Figure 8 is a graph of a sense current before and after a reverse current condition using a sense circuit according to an embodiment; and

[0015] Fig. 9 is a block diagram of a body control module in an automotive application including a sensing circuit according to an embodiment.

[0016] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0017] Embodiment systems and methods address one of the key load conditions of an intelligent power integrated switch, namely, operation during a reverse current condition and how the reverse current condition affects an important function of the integrated circuit switch, namely, accurate load current sensing. For example, when one or more of the channels of a multi-channel integrated switch are disconnected but still in a reverse current condition, the embodiment systems and methods minimize possible errors seen by the system during the load current diagnostic phase of the multi-channel integrated switch. By implementing a current bypass circuit coupled to a reverse current sensitive N-channel transistor in the sense current path of the integrated switch, crosstalk between the channels of the integrated switch is overcome. In one embodiment, the current bypass circuit includes separating the bulk terminal of the N-channel transistor from the source terminal of the N-channel transistor and coupling the bulk terminal to a local ground connection. In another embodiment, the current bypass circuit includes a buffer amplifier coupled between the bulk terminal of the N-channel transistor and the source terminal of the N-channel transistor.

[0018] Reverse current conditions often occur for body control modules driving capacitive loads. For example, a capacitive load may be turned off and shortly thereafter the car battery voltage may experience a negative surge of at least several hundred millivolts.

[0019] Figure 1 is a schematic diagram of a sensing circuit with reverse current protection according to one embodiment, the sensing circuit including a multi-channel intelligent power high-side switch device 100. In one embodiment, the high-side switch device 100 may include an integrated circuit including a plurality of integrated circuit terminals or pins: VS for receiving a power supply voltage, OUT0 for driving a load on a first channel, OUT1 for driving a load on a second channel, and IS for sensing a current on a selected channel. In one embodiment, the high-side switch device may include a plurality of channels, such as four channels or eight channels or more, and have the ability to selectively sense the current flowing through each channel.

[0020] The circuit 100 includes a load transistor M LOAD0 , the load transistor M LOAD0 A current path is coupled between the power terminal VS and the load terminal OUT0. The load terminal OUT0 is coupled to an external load labeled LOAD. The load may be a resistive load. The sensing transistor M SENSE The transistor M108 is coupled to a power terminal VS and a sense terminal IS. The sense terminal IS may be coupled to an external sense resistor R1, which in turn is coupled to an external filter including a resistor R2 and a capacitor C1. The filter output node 108 may be coupled to a processing circuit device such as a microprocessor. LOAD0 and M SENSEThe control terminals or gates of Figure 1 In the embodiment, both the load transistor and the sense transistor are N-channel transistors. LOAD0 The area of ​​the sensing transistor M SENSE The area of ​​the load transistor M is K times that of the load transistor M, so that the sense current is only a fraction of the load current, where K is usually an integer. LOAD0 and the sensing transistor M SENSE The gate drive amplifier 102 may be used to provide an input signal to cause the load transistor M to be closely matched and scaled on an integrated circuit, or the sense transistor may be one or more cells of a larger load transistor comprising a plurality of transistor cells. LOAD0 and the sensing transistor M SENSE The P-channel transistor P1 has a coupled sense transistor M SENSE Amplifier 106 is used to balance the current path between load transistor M LOAD0 The drain-source voltage and the cross-sense transistor M SENSE This is accomplished by coupling the positive input of amplifier 106 to the load transistor M LOAD0 The source of the amplifier 106 couples the negative input of the sensing transistor M SENSE This is achieved by coupling the output to the source of the P-channel transistor P1. Figure 1 Additional load transistors M for individual channels are also included LOAD1 , the channel is closed and current is not sensed, but may experience reverse current conditions. Figure 1 Only one single channel is shown, but those skilled in the art will appreciate that many such single channels may be used. LOAD1 is coupled between the power supply terminal VS and the load terminal OUT1. The load terminal OUT1 is also coupled to a load designated as LOAD, which may also include a capacitive component including a capacitor C2. LOAD1 A separate gate drive amplifier 104 is provided. The sensing circuitry for the additional switching channels is not provided in Figure 1 and will be discussed below, particularly with respect to Figure 5 and Figure 6 The circuit schematic diagram shown in FIG. 1 is described in more detail.

[0021] The sensing circuit arrangement for the first sensing channel includes a P-channel transistor P2 for responding to a multiplexed signal (not shown) applied at the gate of the transistor P2. Figure 1 , and described in further detail below), the sensing current I SENSEThe sensing circuit device for the first sensing channel also includes a reverse current sensitive N-channel transistor N1 for responding to a reverse current signal applied to the gate of the transistor N1 (not in the Figure 1 and described in further detail below) and a reverse current condition is detected, the sense current I SENSE Add parasitic current I PAR Decoupling. The decoupling action of transistor N1 prevents parasitic current from flowing through the IS terminal so that the sense current measurement at node 108 remains accurate even during a reverse current condition on one of the channels that is not currently being sensed.

[0022] According to an embodiment, the body node or bulk node of the N-channel transistor N1 is separated from the source terminal. Parasitic currents that may be generated within the integrated circuit substrate of the circuit 100 may be bypassed and advantageously directed through the bias circuit 112 and thus not flow through the sense pin IS.

[0023] In one embodiment, transistors P2, N1, and bias circuit 112 are specific to each channel in circuit 100. For example, if there are four switching channels in circuit 100, there will also be four channel-specific sensing paths, each of which includes a copy of transistor P2, transistor N1, and bias circuit 112. In one embodiment, amplifier 106, transistor P1, sense terminal IS, and external resistors R1, R2, and capacitor C1 are common to all sensing channels. In one embodiment, only one channel is selected at a time for current sensing. For example, current sensing can be performed during diagnostic testing during an initial operating mode, or current sensing can be performed periodically as needed.

[0024] In the reverse current operation mode, one channel can be turned off and in a reverse current condition (e.g. at terminal OUT1), while the microcontroller reads the sensed current data of the normally operating channel (e.g. at terminal OUT0). Note that the normally flowing load current I LOAD Flowing through the load transistor M LOAD0 , and the reverse current I INVERSE In the opposite direction, the current flows through the load transistor M LOAD1 During the reverse current condition, when the OUT1 channel is in the off state, it can be observed that if the OUT1 voltage is high enough, the lateral multi-collector PNP parasitic device (Q PAR )'s emitter-to-base voltage (VEB ON ) will be activated and will draw current from the output terminal (OUT1). If a reverse current condition occurs at one of the channels, Q PAR Activation of the device. PARThe emitter is M LOAD1 The body of the device is defined (voltage > VS), and Q PAR The base is built directly into the n-substrate (voltage = VS). During reverse current operation in the off state, the emitter-to-base voltage VEB will be reached ON If the necessary VEB is reached ON , the reverse current (I INVERSE ) will be delivered proportionally to Q PAR Collector (I PAR ), depending on their corresponding voltage levels. Since current sensing is selectively performed on each channel at the common pin IS, one channel is in reverse current while the other channels are selected for diagnosis, so Q PAR The device will primarily inject current into the shared sense line, thus affecting the current read by the microcontroller on the normally operating channel. Note that the current flowing into the IS terminal includes the expected I SENSE current, but also includes the undesired I PAR If it were not for the current bypass function provided by the bias circuit 112, I PAR The current will affect the accuracy of the sensed current data.

[0025] Figure 1 Also shown is a P+ guard structure 110 formed in the substrate of the integrated circuit 100 for absorbing parasitic current generated during a reverse current condition. Figure 2 The P+ guard structure 110 is described in further detail. Figure 1 The P+ protection structure 110 is shown schematically as being coupled to the parasitic transistor Q PAR Between the collector of and the supply voltage terminal VS. Although P+ guard structure 110 can be advantageously coupled to ground, regulations regarding the maximum amount of ground current sometimes prevent this implementation.

[0026] Figure 2 yes Figure 1 Q is shown schematically in PARA cross-sectional view 200 of a lateral multi-collector parasitic PNP device is provided to further understand the nature of parasitic currents flowing in a multi-channel current sensing circuit 100 and to provide a solution for preventing these parasitic currents from flowing to the sensing circuit device portion (IS line or terminal) of the current sensing circuit. In one embodiment, the high voltage (DMOS) and low voltage (LVNMOS) portions of the multi-channel sensing circuit 100 are integrated into the semiconductor substrate 114. The cross-sectional view 200 includes a trench gate DMOS device 204, which can represent one of the aforementioned load transistors, and the trench gate DMOS device 204 has multiple P+ regions coupled to the output pin 202. In Figure 2 Also shown is a cross-sectional view of a P+ guard ring or P+ guard structure 110. The P+ guard ring 110 is located in the vicinity of the DMOS transistor 204 and can be an actual annular region surrounding the DMOS portion of the integrated circuit or the LVNMOS portion of the integrated circuit. Alternatively, the P+ structure can be one or more other regions in the shape of a rectangle, a strip, or a non-closed ring. Also shown is a low voltage LVNMOS transistor 210 (e.g., transistor N1) in the low voltage LVNMOS transistor associated with the current sensing circuit device, which has multiple P+ regions coupled to the IS line 208. Therefore, the parasitic Q PAR The transistor includes a flow of parasitic current between the emitter (one of the P+ regions of the DMOS transistor 204) and one of the collectors that is not coupled to the guard ring 110 (one of the P+ regions of the LVNMOS transistor 210). PAR The base of is formed in the N-type substrate 114 (body) of the integrated circuit. Figure 5 and Figure 6 As shown in the figure, the parasitic transistor Q PAR In practice there may be multiple parasitic collector paths to other P+ regions.

[0027] To avoid parasitic current injection into the IS line, the body of the N1 low voltage NMOS device is separated from its source (IS line). Figure 3A , Figure 3B , Figure 4A and Figure 4B An embodiment bias circuit for bypassing current flowing out of the body node of transistor N1 is discussed.

[0028] Figure 3AAn embodiment for biasing the body node of transistor N1 to a voltage lower than the VS supply voltage is illustrated. The transistor symbol of transistor N1 is labeled to identify the drain (D), gate (G), source (S), and body (B) node or bulk (B) node. Therefore, parasitic current flowing from the body node will flow into the bias voltage source and be bypassed from flowing through the source terminal and not flowing into the IS sense terminal. GND is shown UL The bias voltage (local ground voltage) of the UL The local ground voltage may be provided using any of a number of bias circuits 112A, such as a voltage regulator, a charge pump, a voltage divider, or a dedicated supply voltage.

[0029] Figure 3B One specific example of bias circuit 112A is illustrated, which is a voltage regulator that may be of conventional design including a voltage reference, an operational amplifier, an N-channel drive transistor, and a current source.

[0030] Figure 4A One embodiment is illustrated for biasing the body node of transistor N1 to a voltage substantially the same as the source voltage of transistor N1. Thus, parasitic current flowing from the body node will flow into the bias voltage source and be bypassed from flowing through the source of transistor N1 and into the IS sense terminal. The input of buffer amplifier 112B is coupled to the source node of transistor N1, and the output of buffer amplifier 112B is coupled to the body node of transistor N1. Many designs of buffer amplifier 112B may be used, as long as a relatively high input impedance and a relatively low output impedance are presented.

[0031] Figure 4B A specific example of a buffer amplifier bias circuit 112B is shown, which includes N-channel transistors MN0, MN1, P-channel transistor MP0, and bias currents Ib1 and Ib2. The input of the buffer amplifier 112B is node N1. S , and the output of buffer amplifier 112B is node N1 B The positive power supply node of the buffer amplifier 112B is coupled to the VS voltage, and the negative power supply node of the buffer amplifier 112B is coupled to the local ground voltage GND UL .

[0032] Figure 4B One advantage of the buffer amplifier 112B depicted in FIG. 1 replicating the source voltage of the N1 device at its body node is that there is no VGB violation (VGB voltage is too large) under any operating condition. Figure 4BThe SB buffer circuit 112B shown in FIG. 1 embeds two common drain stages (transistor MN0 and current source Ib1, and transistor MP0 and current source Ib2) that reduce the source voltage of N1 once (reducing VGS MN0 ), and then increase once (increase VGS MP0 ) so that ideally the bulk voltage of N1 is substantially the same as the source of N1. The gate of transistor MN0 (N1 S An input terminal) is coupled to the gate of the transistor MN1.

[0033] The positive power supply terminal of the buffer amplifier 112B is coupled to the intermediate power supply voltage VS, and the negative power supply terminal of the buffer amplifier is coupled to the local ground voltage GND. UL (GND UL Typically -3V set by voltage regulator 112A, e.g. Figure 3B ).

[0034] Therefore, the parasitic reverse current I INVERSE Will be injected into N1 B output terminal and flows through the MP0 device to the local ground GND UL The higher the injected current, the higher the VGS MP0 becomes higher, and therefore, N1 B The output node will move up accordingly. Under abnormal operating conditions, current can be forced to flow out of N1 B In this case, transistor MN1 advantageously switches N1 B The voltage is clamped below N1 S A VGS at which VGB N1 In normal operation, when no parasitic currents interfere with N1 B The body of the N1 device will be buffered to be several hundred mV lower than the source of the N1 device at the OUTPUT node. Therefore, the BS (body-to-source) diode of transistor N1 is reverse biased and there is sufficient voltage head-room for the body in case a reverse current condition occurs.

[0035] exist Figure 5 The detailed switching circuit diagram is further illustrated in Figure 3A and Figure 3B The bias circuit shown in Figure 6 The detailed switching circuit diagram is further illustrated in Figure 4A and Figure 4B The bias circuit shown in .

[0036] Figure 5is a schematic diagram of a multi-channel current sensing circuit 500 with reverse current protection. Figure 5 No more repetition or description in the reference Figure 1 Certain reference numerals are used to describe the components.

[0037] The sensing circuit 500 includes a plurality of channels. Figure 5 Two of these channels (Channel 0 and Channel 1) are shown in FIG. 5. The channel-specific portion of circuit 500 includes the aforementioned load transistors and sense transistors, as well as multiplexing circuitry for transistors N1 and P2. The multiplexing circuitry includes switches S1, S2, S3, and S4. Switches S1 and S2 are used to switch between VS and GND depending on whether a particular channel is being sensed. UL Similarly, in one embodiment, switches S3 and S4 are used to switch between the charge pump voltage VCP (VS+3V) and GND depending on whether a reverse current condition is detected. UL The gate of transistor N1 is selectively energized between the voltages (VS-3V). The logic signal for controlling switches S1, S2, S3 and S4 is provided by logic circuit 506, which is I INV The logical combination of the reverse current signal and the MUX multiplexing signal. INV The signal is in turn generated by comparator 504. The positive input of comparator 504 is coupled to a corresponding output pin, such as OUT0 or OUT1, and the negative input of comparator 504 is coupled to the VS supply voltage. If the voltage at the output pin is greater than the VS supply voltage, an I is generated at the output of comparator 504. INV signal, the I INV The signal is combined with the MUX signal in the logic circuit device 506. The channel-specific multiplexing circuit device also includes high voltage switches S5 and S6 that are also coupled to the logic circuit 506. Switch S5 selectively couples the negative input of the operational amplifier 106 to the corresponding sense transistor in the selected channel. Switch S6 selectively couples the positive input of the operational amplifier 106 to the corresponding load transistor in the selected channel. The channel-specific multiplexing circuit device also includes diodes D1 and D2 to prevent the voltage across the selected sense transistor and the voltage across the selected load transistor and the voltage across the input of the amplifier 106 from deviating by more or less than one diode drop.

[0038] Depend on Figure 5 The common circuitry shared by each of the channels in the circuit 500 shown in includes a voltage regulator 112A, an operational amplifier 106, an IS sense terminal, a sense resistor R1, an external filtering circuitry including a resistor R2 and a capacitor C1, and a P+ guard ring 110.

[0039] Note that Figure 5 In the embodiment, the body node of each N1 transistor in each channel is biased by the output of the voltage regulator 112A, which provides the local ground voltage GND. UL Therefore, during a reverse current condition, for example, the parasitic current I associated with the body node of transistor N1 PAR Flows into the voltage regulator and not into the IS terminal, thereby ensuring that the sense current measurement remains accurate during reverse current conditions. In one embodiment, each transistor N1 comprises a MVNMOS (Medium Voltage N-Channel MOS) device that can advantageously withstand higher VGB (gate-to-bulk voltage).

[0040] Figure 6 The switching circuit 600 includes Figure 5 The same channel-specific multiplexing circuitry, the same common circuitry, and the same load transistors and the same sense transistors are shown in the switching circuit 500 shown in FIG. Therefore, for the sake of clarity, the description of these components and features will not be referred to again. Figure 6 Described again, and some reference numerals are omitted.

[0041] However, it is important to note that Figure 6 In the embodiment, the body node of each N1 transistor in each channel is biased by the output of a corresponding buffer amplifier 112B, the input of which is coupled to the source node of transistor N1. The negative supply voltage of buffer amplifier 112B is provided by the output of voltage regulator 112A, the output of which is the local ground voltage GND. UL (VS-3V). Therefore, during a reverse current condition, for example, the parasitic current I associated with the body node of transistor N1 PAR Flows into the output of buffer amplifier 112B and into voltage regulator 112A and does not flow into the IS terminal, thereby ensuring that the sense current measurement remains accurate during reverse current conditions.

[0042] Figure 7 The values ​​of sense current 700 in a prior art sense circuit that does not include the bypass features and circuits described herein are shown. Note that during normal operating conditions 702, the sense current has a value between 20 μA and 25 μA. During reverse operating conditions 704, the sense current increases to a value of approximately 25 μA. The additional sense current represents an error current caused by at least a portion of the parasitic current, which in turn is caused by the reverse operating condition and enters the sense circuitry.

[0043] Figure 8The values ​​of sense current 800 in an embodiment sensing circuit including the bypass features and circuits described herein are shown. Note that during normal operating conditions 802, the sense current has a value between 20 μA and 25 μA. During reverse operating conditions 804, the sense current does not change and maintains a value between 20 μA and 25 μA. The same sense current during the two operating conditions indicates that parasitic currents caused by the reverse operating condition are bypassed and prevented from entering the sensing circuit device. Therefore, even if one or more of the additional unselected channels may be in a reverse current condition, an accurate representation of the sensed channel current can be achieved.

[0044] Fig. 9 A representative body control module 900 including a multi-channel switch 900 including the accurate current sensing features described herein is illustrated. An automotive battery 902 provides a supply voltage VS to both a microprocessor 904 and a multi-channel switch 906. In one embodiment, the battery 902 may be external to the body control module. The microprocessor 904 communicates with the multi-channel switch 906 via a digital bus 908. The multi-channel switch 906 may be a high voltage integrated circuit that includes a plurality of channels 910 coupled to various electrical automotive systems 912. Some of these automotive systems may be capacitive in nature, causing a reverse current condition on one or more of the plurality of channels 910.

[0045] In summary, embodiment circuits and methods are described herein for ensuring that an integrated multi-channel switching circuit including a multi-channel sensing function can provide accurate current sensing functionality even when one of the channels of the switching circuit is subjected to a reverse current condition that generates internal parasitic currents within the integrated circuit.

[0046] Example embodiments of the invention are summarized here. Other embodiments are also apparent from the entire specification and claims submitted herein.

[0047] Example 1. A current sensing circuit comprising: a load transistor having a control terminal and a current path coupled between a power terminal and a load terminal; a sensing transistor having a current path coupled between the power terminal and the sensing terminal, and a control terminal coupled to the control terminal of the load transistor; a P-channel transistor having a control terminal and a current path coupled between the sensing transistor and the sensing terminal; an N-channel transistor having a current path coupled between the sensing transistor and the sensing terminal, and a control terminal for receiving a control voltage; an amplifier for balancing a voltage across the load transistor and a voltage across the sensing transistor, the amplifier having an output coupled to the control terminal of the P-channel transistor; and a bypass circuit coupled to a body terminal of the N-channel transistor.

[0048] Example 2. The current sensing circuit of Example 1, wherein the bypass circuit includes a local ground connection.

[0049] Example 3. A current sensing circuit according to any of the preceding examples, wherein the bypass circuit includes a voltage regulator.

[0050] Example 4. The current sensing circuit of any of the preceding examples, wherein the bypass circuit comprises a buffer amplifier coupled between a body terminal of the N-channel transistor and a source terminal of the N-channel transistor.

[0051] Example 5. The current sensing circuit of any of the preceding examples, wherein the bypass circuit comprises a buffer coupled between the power terminal and a local ground connection.

[0052] Example 6. A current sensing circuit according to any of the preceding examples, wherein the buffer amplifier comprises: a first N-channel transistor connected in series with a first current source coupled between the power terminal and the local ground connection; a P-channel transistor connected in series with a second current source coupled between the power terminal and the local ground connection; and a second N-channel transistor coupled to the first N-channel transistor and the P-channel transistor.

[0053] Example 7. A current sensing circuit according to any of the preceding examples, wherein the gate of the first N-channel transistor constitutes an input to the buffer amplifier and the source of the second N-channel transistor constitutes an output of the buffer amplifier.

[0054] Example 8. The current sensing circuit of any of the preceding examples, wherein a body terminal of the first N-channel transistor and a body terminal of the second N-channel transistor are coupled to the local ground connection.

[0055] Example 9. A current sensing circuit according to any of the preceding examples, wherein a body terminal of the N-channel transistor is coupled to a source terminal of the N-channel transistor.

[0056] Example 10. The current sensing circuit according to any of the preceding examples further includes an integrated substrate including a P-type guard structure proximate to the sensing transistor and the load transistor.

[0057] Example 11. The current sensing circuit of any of the preceding examples, further comprising an additional P-channel transistor having a current path coupled between the sensing transistor and the sensing terminal.

[0058] Example 12. A current sensing circuit comprising: a plurality of load transistors having a current path coupled between a power terminal and a plurality of load terminals; a plurality of sense transistors having a current path coupled between the power terminal and the sense terminal, each sense transistor being coupled to a corresponding load transistor; a plurality of N-channel transistors having a current path coupled between a corresponding sense transistor and a corresponding sense terminal; an amplifier for selectively balancing a voltage across a load transistor in the load transistors and a voltage across a sense transistor in the sense transistors; and a plurality of bypass circuits coupled to body terminals of the plurality of N-channel transistors.

[0059] Example 13. The current sensing circuit of Example 12, wherein each bypass circuit of the plurality of bypass circuits includes a local ground connection.

[0060] Example 14. The current sensing circuit of any of the preceding examples, wherein each of the plurality of bypass circuits comprises a voltage regulator.

[0061] Example 15. A current sensing circuit according to any of the preceding examples, wherein each of the bypass circuits includes a buffer amplifier coupled between a body terminal of a corresponding N-channel transistor and a source terminal of the corresponding N-channel transistor.

[0062] Example 16. The current sensing circuit of any of the preceding examples, wherein each of the bypass circuits is further coupled to a local ground connection.

[0063] Example 17. A current sensing method, the method comprising: providing a load current in a first current path; sensing the load current to provide a sensing current in a second current path; passing the sensing current through an N-channel transistor in the second current path; and bypassing a parasitic current flowing out of a body terminal of the N-channel transistor so that the parasitic current is not added to the sensing current in the second current path.

[0064] Example 18. The current sensing method of Example 17, wherein bypassing the parasitic current comprises shunting the parasitic current to a local ground connection.

[0065] Example 19. A current sensing method according to any of the preceding examples, wherein bypassing the parasitic current includes shunting the parasitic current to a voltage regulator.

[0066] Example 20. A current sensing method according to any of the preceding examples, wherein bypassing the parasitic current includes shunting the parasitic current to an output of a buffer amplifier coupled between a body terminal of the N-channel transistor and a source terminal of the N-channel transistor.

[0067] Example 21. A current sensing method according to any of the preceding examples, wherein the buffer amplifier is also coupled to a local ground connection.

[0068] Specific transistor types and polarities are described herein, but may be changed in embodiments. For example, although transistor N1 is described as an N-channel transistor, a circuit embodiment may replace transistor N1 with a P-channel transistor. Similarly, specific sensing current values ​​are also described herein, but these current sensing current values ​​may be adjusted upward or downward to suit a specific application. The area ratio K between the sensing transistor and the load transistor may also be changed as desired. Other current mirror type circuits may be used to connect the sensing transistor to the load transistor. The power supply voltage will vary over a voltage range to match the corresponding transistor technology used in the embodiment circuit. Other similar changes of this kind may be made to adapt to a specific implementation while still benefiting from the current sensing concept of the embodiments described herein.

[0069] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A current sensing circuit, comprising: a load transistor having a control terminal and a current path coupled between the power terminal and the load terminal; a sense transistor having a current path coupled between the power terminal and a sense terminal, and a control terminal coupled to a control terminal of the load transistor; a P-channel transistor having a control terminal and a current path coupled between the sense transistor and the sense terminal; an N-channel transistor having a current path coupled between the sense transistor and the sense terminal, and a control terminal for receiving a control voltage; an amplifier for equalizing a voltage across the load transistor and a voltage across the sense transistor, the amplifier having an output coupled to a control terminal of the P-channel transistor; as well as A bypass circuit is directly connected to a body terminal of the N-channel transistor, wherein the body terminal of the N-channel transistor is separated from a source terminal of the N-channel transistor. 2 . The current sensing circuit of claim 1 , wherein the bypass circuit comprises a local ground connection. 3 . The current sensing circuit of claim 1 , wherein the bypass circuit comprises a voltage regulator. 4 . The current sensing circuit of claim 1 , wherein the bypass circuit comprises a buffer amplifier coupled between the body terminal of the N-channel transistor and the source terminal of the N-channel transistor. 5 . The current sensing circuit of claim 1 , wherein the bypass circuit comprises a buffer coupled between the power terminal and a local ground connection.

6. The current sensing circuit of claim 4 , wherein the buffer amplifier comprises: a first N-channel transistor in series with a first current source coupled between the power terminal and a local ground connection; a P-channel transistor in series with a second current source coupled between the power terminal and the local ground connection; as well as A second N-channel transistor is coupled to the first N-channel transistor and the P-channel transistor. 7 . The current sensing circuit of claim 6 , wherein a gate terminal of the first N-channel transistor constitutes an input of the buffer amplifier and a source terminal of the second N-channel transistor constitutes an output of the buffer amplifier. 8 . The current sensing circuit of claim 6 , wherein a body terminal of the first N-channel transistor and a body terminal of the second N-channel transistor are coupled to a local ground connection. 9 . The current sensing circuit of claim 1 , wherein the body terminal of the N-channel transistor is coupled to the source terminal of the N-channel transistor through the bypass circuit. 10 . The current sensing circuit of claim 1 , further comprising an integrated substrate comprising a P-type guard structure proximate to the sensing transistor and the load transistor. 11 . The current sensing circuit of claim 1 , further comprising an additional P-channel transistor having a current path coupled between the sense transistor and the sense terminal.

12. A current sensing circuit, comprising: a plurality of load transistors having a current path coupled between the power terminal and the plurality of load terminals; a plurality of sense transistors having a current path coupled between the power terminal and a sense terminal, each sense transistor coupled to a respective load transistor; a plurality of N-channel transistors having current paths coupled between respective sense transistors and respective sense terminals; an amplifier for selectively equalizing a voltage across one of the load transistors and a voltage across one of the sense transistors; as well as A plurality of bypass circuits are directly connected to body terminals of the plurality of N-channel transistors, wherein the body terminals of the plurality of N-channel transistors are separated from source terminals of the plurality of N-channel transistors. 13 . The current sensing circuit of claim 12 , wherein each of the plurality of bypass circuits comprises a local ground connection. 14 . The current sensing circuit of claim 12 , wherein each of the plurality of bypass circuits comprises a voltage regulator. 15 . The current sensing circuit of claim 12 , wherein each of the bypass circuits comprises a buffer amplifier coupled between the body terminal of a corresponding N-channel transistor and the source terminal of the corresponding N-channel transistor.

16. The current sensing circuit of claim 12, wherein each of the bypass circuits is further coupled to a local ground connection.

17. A current sensing method, the method comprising: providing a load current in a first current path; sensing the load current to provide a sense current in a second current path; passing the sense current through an N-channel transistor in the second current path; as well as A parasitic current flowing out of a body terminal of the N-channel transistor is bypassed so that the parasitic current is not added to the sense current in the second current path, wherein the parasitic current is bypassed by a bypass circuit directly coupled to the body terminal of the N-channel transistor, and wherein the body terminal of the N-channel transistor is separated from a source terminal of the N-channel transistor. 18 . The current sensing method of claim 17 , wherein bypassing the parasitic current comprises shunting the parasitic current to a local ground connection of the bypass circuit.

19. The current sensing method of claim 17, wherein bypassing the parasitic current comprises shunting the parasitic current to a voltage regulator of the bypass circuit.

20. The current sensing method of claim 17, wherein bypassing the parasitic current comprises shunting the parasitic current to an output of a buffer amplifier of the bypass circuit, wherein the buffer amplifier is coupled between the source terminals of the N-channel transistor.

21. The current sensing method of claim 20, wherein the buffer amplifier is further coupled to a local ground connection.

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