Semiconductor device manufacturing method and metal lamination method

Abstract

The embodiment provides a method for manufacturing a semiconductor device and a method for stacking metals that can shorten the time required to form a gold layer using electroless plating. The semiconductor device of the embodiment includes a semiconductor portion, an electrode selectively disposed on the semiconductor portion and electrically connected to the semiconductor portion, and a plurality of metal layers disposed on the electrode. In the method for manufacturing the semiconductor device, a first metal layer is selectively formed on the electrode; a palladium layer is formed to cover the first metal layer; a second metal layer is formed to cover the palladium layer; the second metal layer is replaced with a gold layer, and a gold layer is directly formed on the palladium layer.

Description

[0001] This application claims the priority of Japanese Patent Application No. 2019-131287 (filing date: July 16, 2019) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] The embodiments relate to a method for manufacturing a semiconductor device and a method for laminating metals. Background Art

[0003] In the manufacturing process of semiconductor devices, when forming a thick metal layer such as a pad, an electroless plating method is used. For example, sometimes a gold layer is formed on a thin palladium layer using electroless plating. However, if the palladium layer is thick, the precipitation rate of the gold layer slows down. Therefore, in order to obtain a gold layer of a specified thickness, the electroless plating time becomes longer, which reduces the manufacturing efficiency. Summary of the invention

[0004] An object of the present invention is to provide a method for manufacturing a semiconductor device and a method for laminating a metal, which are capable of shortening the time required to form a gold layer using electroless plating.

[0005] The semiconductor device of the related technical solution comprises a semiconductor part, an electrode selectively provided on the semiconductor part and electrically connected to the semiconductor part, and a multi-layer metal layer provided on the electrode. In the manufacturing method of the semiconductor device, a first metal layer is selectively formed on the electrode; a palladium layer is formed on the first metal layer; a second metal layer is formed on the palladium layer; the second metal layer is replaced by a gold layer, and the gold layer is directly formed on the palladium layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

[0007] Figure 2 It is a schematic cross-sectional view showing an electrode structure of a semiconductor device according to an embodiment.

[0008] Figure 3 (a)~ Figure 3 (c) is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.

[0009] Figure 4 (a) Figure 4 (b) is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a comparative example.

[0010] Figure 5 (a) Figure 5 (b) is a schematic cross-sectional view showing the structure of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0011] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The same reference numerals are assigned to the same parts in the drawings, and the detailed description thereof is appropriately omitted, and the different parts will be described. In addition, the accompanying drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. In addition, even when representing the same part, the mutual dimensions or ratios may be represented differently through the accompanying drawings.

[0012] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, the Z direction is sometimes set as the upper direction and the opposite direction is set as the lower direction for description.

[0013] Figure 1 FIG. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment of the present invention. Figure 1 In the example shown, the semiconductor device 1 is mounted on a mounting substrate 10 .

[0014] like Figure 1 As shown, the mounting substrate 10 includes a mounting pad 11 and wiring 13. The mounting pad 11 is provided on the surface of the mounting substrate 10. The semiconductor device 1 is mounted on the mounting pad 11 via a connection member 15. The semiconductor device 1 is electrically connected to the wiring 13 via a connection conductor 20, for example.

[0015] The semiconductor device 1 includes a semiconductor portion 30, an electrode 31, an electrode 33, an insulating layer 34, a metal layer 35, a metal layer 37, and a metal layer 38. The semiconductor device 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor). The electrode 31 is, for example, a collector electrode, and the electrode 33 is, for example, an emitter electrode. The semiconductor portion 30 is, for example, silicon.

[0016] The electrode 31 is provided on the back surface of the semiconductor unit 30. The electrode 31 is connected to the mounting pad 11 via the connection member 15. The mounting pad 11 is, for example, a metal plate containing copper or a copper alloy. The connection member 15 is, for example, a solder.

[0017] The electrode 33 is provided on the surface of the semiconductor portion 30. The insulating layer 34 is provided so as to cover the outer edge of the electrode 33. The insulating layer 34 is, for example, an insulating resin such as polyimide. The electrode 33 has a surface exposed in a region surrounded by the insulating layer 34. The metal layer 35 is selectively provided on the surface of the electrode 33. The metal layer 37 is provided in a region surrounded by the insulating layer 34 so as to cover the metal layer 35. The metal layer 38 is provided in a region surrounded by the insulating layer 34 so as to cover the metal layer 37.

[0018] The connection conductor 20 is bonded to the metal layer 38 via the connection member 23. The connection conductor 20 is, for example, a plate-shaped connector containing copper or a copper alloy. The connection member 23 is, for example, a solder. Furthermore, the connection conductor 20 is bonded to the wiring 13 via the connection member 25. The connection member 25 is, for example, a solder.

[0019] The semiconductor device 1 is not limited to the above-mentioned example. For example, the semiconductor device 1 may be a MOSFET or a diode. In addition, in mounting the semiconductor device 1, a lead frame or the like may be used instead of the mounting substrate 10.

[0020] Figure 2 It is a schematic cross-sectional view showing an electrode structure of a semiconductor device 1 according to an embodiment. Figure 2 Indicates being Figure 1 The area enclosed by the dotted line.

[0021] The semiconductor device 1 includes, for example, a metal layer 35, a metal layer 37, and a metal layer 38 stacked on an electrode 33. The electrode 33 is, for example, an aluminum electrode. Alternatively, the electrode 33 may be a metal layer containing copper. The metal layer 35 is, for example, a nickel layer. The metal layer 37 is, for example, a palladium layer. The metal layer 38 is, for example, a gold (Au) layer.

[0022] The metal layer 37 functions as a barrier layer, for example, to prevent the nickel contained in the metal layer 35 from diffusing into the metal layer 38. This can prevent the metal layer 38 from being deteriorated. That is, when the metal layer 37 is not provided, the nickel in the metal layer 35 diffuses into the metal layer 38, and the metal layer 38 becomes, for example, a gold layer containing nickel. For example, the connection strength between the metal layer 38 and the connection member 23 (see Figure 1 ) is sometimes decreased compared to the metal layer 38 not containing nickel.

[0023] Figure 3 (a)~ Figure 3 (c) is a schematic cross-sectional view showing a manufacturing process of the semiconductor device 1 according to the embodiment. Figure 3 (a)~ Figure 3 (c) is a schematic diagram showing a process of forming metal layers 35 , 37 , and 38 on the electrode 33 .

[0024] like Figure 3 As shown in (a), metal layers 35, 37 and 39 are sequentially formed on an electrode 33 as a base layer. The electrode 33 contains, for example, aluminum or an aluminum alloy on its surface.

[0025] The metal layer 35 contains nickel as a main component, for example. The metal layer 35 is formed by, for example, electroless plating. The metal layer 35 is not limited to this example, and any metal layer may be used as long as a predetermined adhesion strength with respect to the electrode 33 is obtained.

[0026] Metal layer 37 contains palladium (Pd) as a main component, for example. Metal layer 37 is formed to have a thickness of, for example, greater than 0.3 micrometers in order to effectively function as a barrier layer. Metal layer 37 is formed to cover metal layer 35 by, for example, electroless plating.

[0027] Metal layer 39 contains nickel as a main component, for example. Metal layer 39 is formed by, for example, electroless plating so as to cover metal layer 37. Metal layer 39 has a layer thickness of, for example, several tens of nanometers.

[0028] exist Figure 3 In the process shown in (b), the metal layers 35, 37, and 39 stacked on the electrode 33 are immersed in a gold plating solution for electroless plating. As a result, the nickel atoms in the metal layer 39 are replaced by gold atoms in the gold plating solution, and the nickel atoms are dissolved into the gold plating solution. Subsequently, gold atoms are precipitated on the metal layer 39. This reaction continues, for example, until all the nickel atoms contained in the metal layer 39 are replaced by gold atoms.

[0029] like Figure 3 As shown in (c), the metal layer 39 is replaced by the metal layer 38. The metal layer 38 contains gold as a main component. As a result, the metal layer 38 is formed directly on the metal layer 37. That is, the metal layer 39 is not sandwiched between the metal layer 37 and the metal layer 38. As a result, during the heat treatment after the metal layer 38 is formed, nickel will not diffuse into the metal layer 38, and it is possible to avoid, for example, a decrease in the adhesion strength between the connecting member 23 and the metal layer 38 (see Figure 1 ). In addition, if the entire surface of the metal layer 37 is covered with a gold layer, gold is directly precipitated on the gold layer. For example, a metal layer 38 thicker than the metal layer 39 in the stacking direction (Z direction) of the metal layers 35, 37, and 39 may be formed.

[0030] In addition, the metal layer 39 is not limited to a metal layer mainly composed of nickel. For example, any metal layer mainly composed of an element that can be precipitated on the palladium layer under the condition of electroless plating and can replace gold atoms will do. In addition, as long as the element contained in the metal layer 39 is an element that does not deteriorate the metal layer 38, the metal layer 39 may remain between the metal layer 37 and the metal layer 38.

[0031] Figure 4 (a) and Figure 4 (b) is a schematic cross-sectional view showing a manufacturing process of the semiconductor device 1 according to the comparative example. Figure 4 (a) is a schematic diagram showing a process of depositing gold atoms on a palladium layer formed on a nickel layer. Figure 4 (b) is a schematic cross-sectional view showing an electrode structure of a semiconductor device 1 according to a comparative example.

[0032] For example, in the electroless plating method, it is difficult to precipitate gold atoms that react with palladium. That is, palladium atoms are not precipitated into the plating solution, and gold atoms cannot be precipitated by the reaction between the plating solution and palladium. However, if the thickness of the palladium layer is thin, for example, about 0.1 micrometer, gold atoms can be precipitated onto the palladium layer.

[0033] like Figure 4 As shown in (a), there are atomic-level pinholes in the palladium layer. The gold plating solution reaches the nickel layer through the pinholes, dissolving nickel atoms. As a result, gold atoms are precipitated on the palladium layer.

[0034] On the other hand, if the thickness of the palladium layer is increased to be greater than 0.3 micrometers, the density of pinholes in the palladium layer decreases rapidly, so that the precipitation rate of gold atoms through the pinholes slows down, and it takes a long time to form the gold plating layer.

[0035] In addition, if Figure 4 As shown in (b), when the metal layer 35 and the metal layer 37 are immersed in the plating solution, for example, the plating solution sometimes intrudes from the gap between the insulating layer 34 and the metal layer 37 and replaces the nickel of the metal layer 35. Therefore, if the plating time is long, undesirable voids VS may be formed due to the dissolution of nickel atoms from the metal layer 35. If such voids VS are formed, the adhesion strength between the electrode 33 and the metal layer 35 is reduced. In addition, due to the intrusion of impurities and the like through the voids VS, the reliability of the semiconductor device 1 may also be reduced.

[0036] In contrast, in the method for manufacturing the semiconductor device 1 according to the embodiment, the plating time for forming the metal layer 38 can be shortened by sandwiching the metal layer 39. Thus, the manufacturing efficiency of the semiconductor device 1 can be improved. Furthermore, the intrusion of the plating solution through the gap between the insulating layer 34 and the metal layer 37 can be suppressed, and the formation of the void VS can be avoided. Thus, the reliability of the semiconductor device 1 can be improved.

[0037] Figure 5 (a) and Figure 5 (b) is a schematic cross-sectional view showing the structure of the semiconductor devices 2 and 3 according to the embodiment. Figure 5 (a) is a schematic diagram showing a cross-sectional structure of an IGBT having a trench gate structure. Figure 5 (b) is a schematic diagram showing the cross-sectional structure of a diode.

[0038] Figure 5 The semiconductor device 2 shown in (a) further includes a gate electrode 40. The gate electrode 40 is located inside a gate trench GT provided on the surface side of the semiconductor portion 30. The gate electrode 40 is electrically insulated from the semiconductor portion 30 by a gate insulating film 43 covering the inner surface of the gate trench GT. In addition, the gate electrode 40 is electrically insulated from the electrode 33 by an interlayer insulating film 45.

[0039] The semiconductor portion 30 includes, for example, an n-type base layer 30 a , a p-type base layer 30 b , an n-type emitter layer 30 c , a p-type contact layer 30 d , and a p-type collector layer 30 e .

[0040] The p-type base layer 30 b is located between the n-type base layer 30 a and the electrode 33 , and is provided between the gate electrodes 40 adjacent to each other.

[0041] The n-type emitter layer 30c and the p-type contact layer 30d are selectively provided between the p-type base layer 30b and the electrode 33. The electrode 33 is in contact with the n-type emitter layer 30c and the p-type contact layer 30d, and is electrically connected thereto.

[0042] The n-type emitter layer 30c contains n-type impurities at a higher concentration than the n-type base layer 30a. The p-type contact layer 30d contains p-type impurities at a higher concentration than the p-type base layer 30b. The electrode 33 is electrically connected to the p-type base layer 30b via the p-type contact layer 30d.

[0043] The p-type collector layer 30e is located between the n-type base layer 30a and the electrode 31. The electrode 31 is in contact with the p-type collector layer 30e and is electrically connected thereto.

[0044] exist Figure 5 In the semiconductor device 3 shown in (b), the semiconductor portion 30 includes an I layer 30f, an anode layer 30g, and a cathode layer 30h. The I layer 30f is, for example, an n-type semiconductor layer containing a low concentration of n-type impurities.

[0045] The anode layer 30g is located between the I layer 30f and the electrode 33, and is selectively provided on the surface side of the semiconductor portion 30. The anode layer 30g is, for example, a p-type semiconductor layer containing p-type impurities. The electrode 33 is in contact with the anode layer 30g and is electrically connected.

[0046] The cathode layer 30h is located between the I layer 30f and the electrode 31. The cathode layer 30h contains n-type impurities at a higher concentration than the n-type impurity concentration of the I layer 30f. The electrode 31 is electrically connected to the cathode layer 30h.

[0047] The semiconductor device 3 further includes an insulating layer 36. The insulating layer 36 is located between the semiconductor portion 30 and the insulating layer 34. For example, a silicon oxide film is used for the insulating layer 36, and the insulating layer 36 functions as a so-called passivation film.

[0048] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A method for manufacturing a semiconductor device, The semiconductor device comprises a semiconductor portion, an electrode provided on the semiconductor portion and electrically connected to the semiconductor portion, and a plurality of metal layers provided on the electrode. In the method for manufacturing a semiconductor device, forming a first metal layer on the electrode; forming a palladium layer covering the first metal layer; forming a second metal layer containing nickel covering the palladium layer; The second metal layer is replaced with a gold layer, and the gold layer is formed directly on the palladium layer.

2. The method for manufacturing a semiconductor device according to claim 1, The first metal layer contains nickel.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, The gold layer is formed by electroless plating.

4. The method for manufacturing a semiconductor device according to claim 3, The first metal layer, the palladium layer, and the second metal layer are formed by electroless plating.

5. A metal lamination method, forming a metal layer containing nickel on the base layer; forming an intermediate layer containing palladium in a manner covering the metal layer; forming a replacement layer containing nickel in such a manner as to cover the intermediate layer; The nickel in the replacement layer is replaced with gold by electroless plating, thereby forming a gold layer directly on the intermediate layer.

6. The metal lamination method according to claim 5, The metal layer, the intermediate layer, and the replacement layer are formed by electroless plating.

7. The metal lamination method according to claim 5 or 6, The gold layer in contact with the intermediate layer is formed by replacing the replacement layer.

8. The metal lamination method according to claim 7, The thickness of the gold layer in the stacking direction of the metal layer, the intermediate layer, and the replacement layer is formed to be thicker than the thickness of the replacement layer in the stacking direction before being replaced by the gold layer.

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