Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate; forming a stop layer on the surface of the substrate; forming a dielectric layer on the surface of the stop layer; forming a first opening in the dielectric layer, the first opening exposing the surface of the stop layer; modifying the stop layer at the bottom of the first opening to form a modified layer; and removing the modified layer to form a second opening, the second opening exposing the substrate surface. The resulting semiconductor structure has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Integrated circuit manufacturing is a planar fabrication process that combines multiple processes, including photolithography, etching, deposition, and ion implantation, to form a large number of complex devices of various types on a single substrate and interconnect them to achieve complete electronic functionality. Deviations in any process step can cause circuit performance parameters to deviate from designed values. Currently, with the continuous proportional reduction in device feature sizes and increasing integration density of very large-scale integrated circuits, higher requirements are placed on the control of each process step and the accuracy of the process results.

[0003] Therefore, the existing integrated circuit manufacturing process needs to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a stop layer on the surface of the substrate; forming a dielectric layer on the surface of the stop layer; forming a first opening in the dielectric layer, the first opening exposing the surface of the stop layer; modifying the stop layer at the bottom of the first opening to form a modified layer; removing the modified layer to form a second opening, the second opening exposing the surface of the substrate.

[0006] Optionally, the process of modifying the stop layer exposed by the first opening is a plasma treatment process.

[0007] Optionally, the material of the stop layer includes aluminum nitride, aluminum oxide or silicon nitride; the material of the modified layer includes aluminum or silicon oxide.

[0008] Optionally, the gas used in the plasma treatment process includes: a mixed gas of hydrogen and argon, wherein the volume ratio of the hydrogen is greater than 20%; or, the gas used in the plasma treatment process is oxygen.

[0009] Optionally, the process of removing the modified layer includes a wet etching process; the solution used in the wet etching process includes: NH2OH solution or HF solution.

[0010] Optionally, the substrate includes a base and an isolation layer located on the base, the isolation layer has an interconnection structure therein, and the isolation layer exposes a portion of the surface of the interconnection structure.

[0011] Optionally, the second opening exposes the surface of the interconnection structure.

[0012] Optionally, the material of the interconnect structure includes metal, and the metal includes a combination of one or more of copper, tungsten, cobalt and ruthenium.

[0013] Optionally, the dielectric layer includes: a first dielectric layer located on the stop layer and a second dielectric layer located on the first dielectric layer; and the first opening is located in the second dielectric layer and the first dielectric layer.

[0014] Optionally, the material of the first dielectric layer includes silicon oxide, silicon nitride or silicon; the material of the second dielectric layer includes silicon oxide, silicon nitride or silicon.

[0015] Optionally, the method for forming a first opening in the first dielectric layer and the second dielectric layer includes: forming a patterned mask layer on the surface of the second dielectric layer, the patterned mask layer exposing a portion of the surface of the second dielectric layer; etching the second dielectric layer and the first dielectric layer using the patterned mask layer as a mask until the surface of the stop layer is exposed to form the first opening.

[0016] Optionally, the process of etching the second dielectric layer and the first dielectric layer includes a dry etching process.

[0017] Optionally, the method further includes: forming a conductive plug in the second opening.

[0018] Optionally, the process of forming the stop layer includes a deposition process.

[0019] Optionally, the process of forming the dielectric layer includes a deposition process.

[0020] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by adopting any of the above methods.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] In the method of the technical solution of the present invention, the stop layer at the bottom of the first opening is modified to form a modified layer. The modified layer and the material of the stop layer have a large selective etching ratio. Therefore, in the process of removing the modified layer to form the second opening, the etching process causes less damage to the stop layer on the side wall of the second opening, thereby avoiding the situation where the conductive plug formed subsequently in the second opening is prone to short circuit and leakage, thereby improving the performance of the semiconductor structure.

[0023] Furthermore, the material of the modified layer includes aluminum or silicon oxide, and the etching selectivity of the modified layer and the stop layer is relatively large. Therefore, in the process of removing the modified layer to form the second opening, the removal process causes less damage to the stop layer on the side wall of the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0025] Figures 4 to 10 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] As described in the background art, the existing integrated circuit manufacturing process still needs to be improved.

[0027] Figures 1 to 3 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0028] Please refer to Figure 1 , providing a substrate, the substrate including a base 100, an isolation layer 101 located on the base 100, and an interconnect structure 102 located in the isolation layer 101; forming a stop layer 103 on the substrate; and forming a dielectric layer 104 on the stop layer 103.

[0029] Please refer to Figure 2 , a first opening 105 is formed in the dielectric layer 104 , wherein the first opening 105 exposes the surface of the stop layer 103 .

[0030] Please refer to Figure 3 , the stop layer 103 at the bottom of the first opening 105 is removed to form a second opening 106 , where the second opening 106 exposes the surface of the interconnect structure 102 .

[0031] During the formation of the semiconductor structure, after the first opening 105 is formed, a wet etching process is used to remove the stop layer 103 at the bottom of the first opening 105. Due to the isotropic characteristics of the wet etching process, when the stop layer 103 at the bottom of the first opening 105 is removed to form the second opening 106, the stop layer 103 on the side wall of the second opening 106 will inevitably be laterally etched, causing the stop layer 103 on the surface of the substrate between adjacent interconnect structures 102 to be damaged or even penetrated. After a conductive plug is subsequently formed in the second opening 106 to electrically connect with the interconnect structure 102, the adjacent conductive plugs are prone to short circuits and leakage, thereby affecting the performance of the semiconductor structure.

[0032] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein a modified layer is formed by modifying the stop layer at the bottom of the first opening, and the material of the modified layer and the stop layer have a large selective etching ratio. Therefore, in the process of removing the modified layer to form the second opening, the etching process causes less damage to the stop layer on the side wall of the second opening, thereby avoiding the situation where the conductive plug subsequently formed in the second opening is prone to short circuit and leakage, thereby improving the performance of the semiconductor structure.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 4 to 10 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0035] Please refer to Figure 4 , providing a substrate.

[0036] In this embodiment, the substrate includes a base 200 and an isolation layer 201 located on the base 200 .

[0037] In other embodiments, the substrate includes a base and an isolation layer located on the base, the base having a device structure, conductive wiring, multi-layer metal layers or multi-layer conductive layers, and the device structure, conductive wiring, multi-layer metal layers or multi-layer conductive layers are located in the isolation layer.

[0038] The isolation layer 201 has an interconnection structure 202 therein, and the isolation layer 201 exposes a portion of the surface of the interconnection structure 202. In this embodiment, the interconnection structure 202 is used to electrically connect to other interconnection structures. The interconnection structure includes a conductive plug.

[0039] In other embodiments, the interconnect structure is electrically connected to the device structure, conductive wiring, multiple metal layers, or multiple conductive layers. The device structure includes a transistor, a diode, or a PN junction.

[0040] In this embodiment, the material of the interconnect structure 202 includes metal, and the metal includes one or more combinations of copper, tungsten, cobalt, and ruthenium.

[0041] The material of the interconnection structure 202 includes metal. A conductive plug is subsequently formed on the surface of the interconnection structure 202. The interconnection structure 202 is electrically connected to other devices through the conductive plug.

[0042] In other embodiments, the material of the interconnect structure includes metal silicide, including titanium silicide, zirconium silicide, tantalum silicide, or tungsten silicide.

[0043] The material of the isolation layer 201 includes silicon oxide or silicon nitride. In this embodiment, the material of the isolation layer 201 includes silicon oxide.

[0044] The material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0045] Please refer to Figure 5 , forming a stop layer 203 on the surface of the substrate.

[0046] The stop layer 203 is used as an etching stop layer when an opening is subsequently formed in a dielectric layer formed on the substrate surface, so as to prevent the opening from directly exposing the surface of the interconnect structure 202 and thereby damaging the interconnect structure 202 .

[0047] The stop layer 203 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0048] In this embodiment, the stop layer 203 is formed by a chemical vapor deposition process, which can efficiently form a stop layer 203 with a dense structure.

[0049] The material of the stop layer 203 includes aluminum nitride, aluminum oxide, or silicon nitride. In this embodiment, the material of the stop layer 203 includes aluminum nitride.

[0050] Aluminum nitride is selected as a stop layer for subsequently etching the first dielectric layer and the second dielectric layer to form a first opening. The aluminum nitride has a different etching selectivity ratio from the first dielectric layer, so it can be used as a stop layer to control the etching process of the first dielectric layer. On the other hand, the aluminum nitride is a non-conductive material, thereby insulating the interconnect structure 202 at the bottom of the first opening, preventing the interconnect structure 202 from being connected to each other through the stop layer 203, which would affect the performance of the semiconductor structure.

[0051] In this embodiment, the thickness of the stop layer 203 ranges from 1 nm to 5 nm.

[0052] If the thickness of the stop layer 203 is less than 1 nm, the stopping effect as the etching stop layer is poor; if the thickness of the stop layer 203 is greater than 5 nm, when the stop layer is subsequently modified, the penetration depth of the modified gas is limited and the stop layer cannot be completely modified.

[0053] Please refer to Figure 6 , forming a dielectric layer on the surface of the stop layer 203 .

[0054] The dielectric layer is used to provide structural support for the subsequent formation of conductive plugs in the second opening, and also serves as an insulation for the subsequent conductive plugs to avoid short circuits between the conductive plugs, thereby affecting the performance of the semiconductor structure.

[0055] In this embodiment, the dielectric layer includes a first dielectric layer 204 located on the stop layer 203 and a second dielectric layer 205 located on the first dielectric layer 204 .

[0056] A first dielectric layer 204 and a second dielectric layer 205 are formed on the stop layer 203. The materials of the first dielectric layer 204 and the second dielectric layer 205 are different. The material structure of the first dielectric layer 204 is relatively dense, so that when an opening is formed in the first dielectric layer 204, the sidewall of the opening is relatively straight, so that the pattern accuracy of the opening is higher, and the conductive plug subsequently formed in the opening has a larger contact surface with the interconnect structure 202, and has better conductivity.

[0057] The material of the first dielectric layer 204 includes silicon oxide, silicon nitride, or silicon; the material of the second dielectric layer 205 includes silicon oxide, silicon nitride, or silicon.

[0058] In this embodiment, the material of the first dielectric layer 204 is different from the material of the second dielectric layer 205 .

[0059] In this embodiment, the material of the first dielectric layer 204 includes silicon nitride; the material of the second dielectric layer 205 includes silicon oxide.

[0060] The process of forming the first dielectric layer 204 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0061] In this embodiment, the process of forming the first dielectric layer 204 includes a chemical vapor deposition process.

[0062] The process of forming the second dielectric layer 205 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0063] In this embodiment, the process of forming the second dielectric layer 205 includes a chemical vapor deposition process.

[0064] In other embodiments, the material of the first dielectric layer is the same as that of the second dielectric layer, and the material of the first dielectric layer is formed using a different process than that of the second dielectric layer.

[0065] The material of the first dielectric layer 204 and the material of the second dielectric layer 205 include silicon oxide, silicon nitride or silicon.

[0066] The process of forming the first dielectric layer 204 includes an atomic layer deposition process; the process of forming the second dielectric layer 205 includes a chemical vapor deposition process or a physical vapor deposition process.

[0067] Compared with the chemical vapor deposition process, the atomic layer deposition process can form silicon oxide or silicon nitride with a denser structure.

[0068] In other embodiments, when the material of the stop layer includes silicon nitride, the material of the first dielectric layer is the same as the material of the second dielectric layer, and the material of the first dielectric layer and the material of the second dielectric layer include silicon.

[0069] The stop layer of the silicon nitride material is modified to form silicon oxide. The silicon oxide has a larger selective etching ratio to silicon nitride, and the silicon oxide has a larger etching selectivity to silicon. Therefore, in the process of removing the modified layer, the damage to the stop layer and the dielectric layer can be relatively small.

[0070] Please refer to Figure 7 , a first opening 207 is formed in the dielectric layer, wherein the first opening 207 exposes the surface of the stop layer 203 .

[0071] The method for forming a first opening 207 in the first dielectric layer 204 and the second dielectric layer 205 includes: forming a patterned mask layer 206 on the surface of the second dielectric layer 205, the patterned mask layer 206 exposing a portion of the surface of the second dielectric layer 205; etching the second dielectric layer 205 and the first dielectric layer 204 using the patterned mask layer 206 as a mask until the surface of the stop layer 203 is exposed, thereby forming the first opening 207.

[0072] In this embodiment, the process of etching the second dielectric layer 205 and the first dielectric layer 204 includes a dry etching process; in other embodiments, the process of etching the second dielectric layer 205 and the first dielectric layer 204 includes a wet etching process.

[0073] In this embodiment, the material of the patterned mask layer 206 includes photoresist; in other embodiments, the material of the patterned mask layer 206 includes a hard mask layer.

[0074] After forming the first opening 207 , the patterned mask layer 206 is removed.

[0075] In this embodiment, the process of removing the patterned mask layer 206 includes an ashing process.

[0076] Please refer to Figure 8The stop layer 203 at the bottom of the first opening 207 is modified to form a modified layer 208. The modified layer 208 has a large etching selectivity to the stop layer 203. When the modified layer 208 is subsequently removed to expose the surface of the interconnect structure 202, damage to the stop layer 203 on the sidewalls of the modified layer 208 is minimized, thereby preventing over-etching of the stop layer 203 and short-circuiting of the subsequently formed conductive plug.

[0077] In this embodiment, the material of the modified layer 208 includes aluminum; in other embodiments, the material of the modified layer 208 includes silicon oxide.

[0078] In this embodiment, the process of modifying the stop layer 203 exposed by the first opening 207 is a plasma treatment process.

[0079] In this embodiment, the material of the stop layer 203 includes aluminum nitride, the gas used in the plasma treatment process is a mixture of hydrogen and an inert gas, the inert gas includes argon or helium, and the volume ratio of the hydrogen is greater than 20%.

[0080] The hydrogen is a reaction gas, and the hydrogen can chemically react with the aluminum nitride to generate metallic aluminum and ammonia. The ammonia can be discharged along with the reaction gas, thereby modifying the aluminum nitride in contact with the plasma into aluminum. The aluminum and aluminum nitride have a large etching selectivity, so when the aluminum is subsequently removed to form a second opening, the aluminum removal process causes less damage to the stop layer 203 on the side wall of the second opening, thereby avoiding short circuits and leakage after a conductive plug is subsequently formed in the second opening, thereby improving the performance of the semiconductor structure.

[0081] The inert gas is easily ionized to release electrons, thereby providing electrons for the reaction; at the same time, the inert gas can maintain the gas pressure of the reaction chamber stable and prevent chemical reactions from occurring.

[0082] In other embodiments, when the stop layer material is silicon nitride, the plasma treatment gas is oxygen. The oxygen reacts with the silicon nitride to produce a modified silicon oxide layer and nitrogen dioxide gas, which can be exhausted along with the reaction gas. The modified silicon oxide layer has a large etching selectivity ratio with the silicon nitride stop layer.

[0083] Please refer to Figure 9 , removing the modified layer 208 to form a second opening 209 , wherein the second opening 209 exposes the substrate surface.

[0084] In this embodiment, the second opening 209 exposes the surface of the interconnection structure 202 . The second opening 209 is used to subsequently form a conductive plug in the second opening 209 to electrically connect to the interconnection structure 202 .

[0085] In this embodiment, the process of removing the modified layer 208 includes a wet etching process.

[0086] The parameters of the wet etching process include: the solution is NH2OH solution, and the solution temperature range is 0°C to 40°C.

[0087] The NH2OH solution has a relatively high selective etching effect on the aluminum and the aluminum nitride in the temperature range of 0°C to 40°C, and can cause less damage to the stop layer 203 on the side wall of the second opening 209 during the removal of the modified layer 208. At the same time, the NH2OH solution has a high etching selectivity for the interconnect structure 202, so it can cause less damage to the interconnect structure 202 while completely removing the modified layer 208, thereby improving the performance of the semiconductor structure.

[0088] If the temperature of the NH2OH solution is greater than 40°C, the reaction temperature is high, and the aluminum nitride is easily hydrolyzed to form aluminum hydroxide under this temperature condition, thereby reacting with the NH2OH solution. As a result, during the process of removing the modified layer 208, the stop layer 203 on the side wall of the second opening 209 is damaged, and the purpose of the technical solution of the present invention cannot be achieved.

[0089] In another embodiment, the material of the stop layer includes silicon nitride, the material of the modified layer includes silicon oxide, the material of the first dielectric layer and the second dielectric layer includes silicon, and the solution of the wet etching process includes HF solution.

[0090] The HF solution has a relatively large selective etching effect on the silicon oxide and silicon nitride. Therefore, in the process of removing the modified layer, the stop layer on the side wall of the second opening is less damaged, and the dielectric layer is also less damaged.

[0091] Please refer to Figure 10 After forming the second opening 209 , a conductive plug 210 is formed in the second opening 209 .

[0092] The method for forming the conductive plug 210 includes: forming a conductive plug material layer (not shown) in the second opening 209 and on the surface of the second dielectric layer 205 ; and planarizing the conductive plug material layer until the surface of the second dielectric layer 205 is exposed to form the conductive plug 210 .

[0093] The conductive plug 210 is made of a metal, which may be one or more of copper, tungsten, aluminum, titanium, titanium nitride, and tantalum. In this embodiment, the conductive plug 210 is made of titanium or titanium nitride.

[0094] In this embodiment, the process of forming the material layer of the conductive plug 210 includes a deposition process. In other embodiments, the process of forming the material layer of the conductive plug includes an electroplating process.

[0095] In this embodiment, the process of planarizing the material layer of the conductive plug 210 includes a chemical mechanical polishing process.

[0096] In this embodiment, the conductive plug 210 is electrically connected to the interconnect structure 202 .

[0097] Thus, the conductive plug 210 formed has a larger contact area with the interconnection structure 202, and has a better conductive effect. At the same time, short circuits are reduced, and the performance of the semiconductor structure is improved.

[0098] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method.

[0099] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a stop layer on the surface of the substrate; forming a dielectric layer on the surface of the stop layer; forming a first opening in the dielectric layer, wherein the first opening exposes a surface of the stop layer; performing a modification treatment on the stop layer at the bottom of the first opening to form a modified layer, wherein the modified layer is formed by a chemical reaction of the stop layer; The modified layer is removed by a wet etching process to form a second opening, wherein the second opening exposes the substrate surface, the modified layer has a larger etching selectivity to the stop layer, and the modified layer has a larger etching selectivity to the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process of modifying the stop layer exposed by the first opening is a plasma treatment process.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the stop layer includes aluminum nitride, aluminum oxide or silicon nitride; the material of the modified layer includes aluminum or silicon oxide.

4. The method for forming a semiconductor structure according to claim 3, wherein: The gas used in the plasma treatment process includes: a mixed gas of hydrogen and argon, wherein the volume ratio of the hydrogen is greater than 20%; or, the gas used in the plasma treatment process is oxygen.

5. The method for forming a semiconductor structure according to claim 3, wherein: The process of removing the modified layer includes a wet etching process; the solution used in the wet etching process includes: NH2OH solution or HF solution.

6. The method for forming a semiconductor structure according to claim 1, wherein: The substrate comprises a base and an isolation layer located on the base, wherein the isolation layer has an interconnection structure therein, and the isolation layer exposes a portion of the surface of the interconnection structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The second opening exposes the surface of the interconnection structure.

8. The method for forming a semiconductor structure according to claim 6, wherein: The material of the interconnect structure includes metal, and the metal includes one or more combinations of copper, tungsten, cobalt and ruthenium.

9. The method for forming a semiconductor structure according to claim 1, wherein: The dielectric layer includes: a first dielectric layer located on the stop layer and a second dielectric layer located on the first dielectric layer; the first opening is located in the second dielectric layer and the first dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the first dielectric layer includes silicon oxide, silicon nitride or silicon; the material of the second dielectric layer includes silicon oxide, silicon nitride or silicon.

11. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming a first opening in the first dielectric layer and the second dielectric layer includes: forming a patterned mask layer on the surface of the second dielectric layer, the patterned mask layer exposing a portion of the surface of the second dielectric layer; etching the second dielectric layer and the first dielectric layer using the patterned mask layer as a mask until the surface of the stop layer is exposed to form the first opening.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of etching the second dielectric layer and the first dielectric layer includes a dry etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A conductive plug is formed in the second opening.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the stop layer includes a deposition process.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the dielectric layer includes a deposition process.

16. A semiconductor structure formed by the method according to any one of claims 1 to 15.

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