Microelectronic devices including manganese-containing conductive structures, and related electronic systems and methods

Abstract

This application relates to microelectronic devices including a manganese-containing conductive structure, as well as related electronic systems and methods. A microelectronic device includes: a first conductive material including copper; a conductive plug including tungsten, the conductive plug being in electrical communication with the first conductive material; and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application Serial No. 16 / 515,265, filed on July 18, 2019, for "MICROELECTRONIC DEVICES COMPRISING MANGANESE-CONTAINING CONDUCTIVE STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS". Technical Field

[0003] The embodiments disclosed herein relate to microelectronic devices, related electronic systems, and related methods that include manganese-containing conductive structures. More specifically, embodiments of the present disclosure relate to microelectronic devices, related electronic systems, and related methods that include conductive structures that contain manganese positioned at least proximate to an interface between a first conductive material and a second conductive material. Background Art

[0004] Microelectronic device designers generally desire to increase the level of integration or density of features within a given semiconductor device architecture by reducing the critical dimensions of individual features and by reducing the separation distance or pitch between adjacent features. Additionally, microelectronic device designers generally seek to design architectures that are not only compact but also provide performance advantages and simplified designs.

[0005] One example of a microelectronic device is a memory device. Memory devices are typically provided in the form of an integrated circuit within a computer or other electronic device. There are many types of memory, including but not limited to random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistive random access memory. Non-limiting examples of resistive random access memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

[0006] A memory device may include an active surface that includes interacting components such as transistors, capacitors, electrodes, diodes, other access devices, or other elements. During the manufacture of the memory device, electrical connections may be formed between the active surface of the memory device and other portions thereof to form electrical connections to circuitry positioned remote from the active surface.

[0007] For example, a typical memory cell of a memory device includes an access device (e.g., a transistor) and a memory storage structure (e.g., a capacitor) electrically coupled to the access device through a conductive contact. The access device typically includes a channel region between a pair of source / drain regions and a gate electrode configured to electrically connect the source / drain regions to each other through the channel region. One or more of the source region, the drain region, and the gate electrode may be in electrical communication with one or more voltage sources to operate the memory cell.

[0008] As the number of memory cells in a memory device increases, electrically connecting the memory cells to control logic circuitry and other components of the memory device may give rise to feature size setting and spacing complexities associated with an increase in the number and size of the wiring and interconnect structures required to facilitate the electrical connections. In addition, as the feature size of the memory device continues to shrink, it becomes increasingly difficult to form patterns of features having a desired critical dimension. As the critical dimensions of the components of the memory device shrink, it becomes increasingly difficult to form reliable electrical connections between the conductive components of the memory device. SUMMARY

[0009] Embodiments disclosed herein relate to microelectronic devices including manganese-containing conductive structures and related electronic systems and methods. For example, in some embodiments, a microelectronic device includes: a first conductive material including copper; a conductive plug including tungsten, the conductive plug being in electrical communication with the first conductive material; and manganese particles dispersed along an interface between the first conductive material and the conductive plug.

[0010] According to other embodiments of the present disclosure, an electronic system includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device. The memory device includes: a first conductive material located within a first dielectric material; a second conductive material adjacent to the first conductive material and located within a second dielectric material adjacent to the first conductive material; at least a first barrier material located between the first conductive material and the second conductive material; and manganese particles located within the first conductive material and adjacent to the first barrier material.

[0011] According to another embodiment of the present disclosure, an electronic device includes: a copper interconnect; a tungsten plug in direct contact with a portion of the copper interconnect; and manganese particles separated within the copper interconnect around the portion of the copper interconnect.

[0012] According to yet another embodiment of the present disclosure, a method of forming a microelectronic device includes: forming an opening in a first dielectric material; forming a first barrier material within the opening in the first dielectric material; forming a seed material including copper and manganese on the first barrier material; forming a first conductive material on the seed material; forming a second dielectric material on the first dielectric material and the first conductive material; forming an additional opening in the second dielectric material; forming a second barrier material within the additional opening in the second dielectric material; forming a second conductive material on the second barrier material; and separating at least some of the manganese in the seed material to a position proximate to an interface between the first conductive material and the second barrier material. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a simplified cross-sectional view of a microelectronic device in accordance with an embodiment of the present disclosure;

[0014] Figure 1B is Figure 1A a cross-sectional view of box B of Figure 1A showing an enlarged portion of the microelectronic device of

[0015] Figures 2A to 2I is a simplified cross-sectional view showing a method of forming a microelectronic device in accordance with an embodiment of the present disclosure;

[0016] Figure 3 is a block diagram of an electronic system in accordance with an embodiment of the present disclosure; and

[0017] Figure 4 is a processor-based system in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The diagrams included herein are not intended to be actual views of any particular system, microelectronic structure, or microelectronic device, but are merely idealized representations for describing the embodiments herein. Elements and features common between the drawings may retain the same numerical designations, except as follows: For ease of the following description, the reference numerals begin with the number of the drawing in which the element is introduced or most fully described.

[0019] The following description provides specific details, such as material types, material thicknesses, and processing conditions, in order to provide a comprehensive description of the embodiments described herein. However, those of ordinary skill in the art should understand that the embodiments disclosed herein may be practiced without these specific details. In fact, the embodiments may be practiced in conjunction with conventional manufacturing techniques employed in the microelectronics industry. Additionally, the description provided herein does not form a complete description of a microelectronic device or an electronic system that includes a conductive structure including manganese, or a complete description of a process flow for manufacturing such a microelectronic device or electronic system. The structures described below do not form a complete microelectronic device. Only those process operations and structures necessary to understand the embodiments described herein are described in detail below. Additional operations for forming a complete microelectronic device or electronic system that includes a conductive structure including manganese during the manufacture of a microelectronic device or an electronic system may be performed by conventional techniques.

[0020] The materials described herein may be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (e.g., sputter deposition), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials may be grown in situ. Those of ordinary skill in the art may select the technique for depositing or growing the material based on the specific material to be formed. Unless otherwise indicated by the context, the removal of the material may be accomplished by any suitable technique, including but not limited to etching, polishing planarization (e.g., chemical-mechanical planarization), or other known methods.

[0021] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are referenced to a main plane in which one or more structures and / or features of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) are formed in or on and are not necessarily defined by the earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the main plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the main plane of the substrate. The main plane of the substrate is defined by a substrate surface that has a relatively larger area compared to other surfaces of the substrate.

[0022] As used herein, the term “substantially” with respect to a given parameter, property, or condition means and includes the extent to which a given parameter, property, or condition is met with a degree of variance, such as variance within an acceptable tolerance, as would be understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be met at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0023] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter encompasses the recited value and a degree of variation relative to the recited value that a person of ordinary skill in the art would understand to be within an acceptable tolerance of the particular parameter. For example, "about" or "approximately" with respect to a numerical value can include additional numerical values that are within a range of 90.0% to 110.0% of the numerical value, such as within a range of 95.0% to 105.0% of the numerical value, within a range of 97.5% to 102.5% of the numerical value, within a range of 99.0% to 101.0% of the numerical value, within a range of 99.5% to 100.5% of the numerical value, or within a range of 99.9% to 100.1% of the numerical value.

[0024] Spatial relative terms such as "beneath", "below", "lower", "bottom", "above", "upper", "top", "front", "rear", "left", "right", etc. as used herein may be used for convenience in describing the relationship of one element or feature to another or other elements or features as shown in the figures. Unless otherwise specified, spatial relative terms are also intended to encompass different orientations in addition to the orientation depicted in the figures. For example, if the materials in the figures are inverted, an element described as being "beneath" or "below" or "under" or "at the bottom" of other elements or features will be oriented as being "above" or "at the top" of the other elements or features. Thus, the term "beneath" can encompass both upward and downward orientations, depending on the context in which the term is used, which will be apparent to a person of ordinary skill in the art. The materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatial relative descriptors used herein can be interpreted accordingly.

[0025] As used herein, "conductive material" can refer to one or more of the following: metals such as tungsten, titanium, nickel, platinum, palladium, ruthenium, aluminum, copper, molybdenum, gold, etc., metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide), metal carbides, metal oxides), conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, other materials that exhibit conductivity, or combinations thereof. The conductive material can include at least one of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental ruthenium (Ru), elemental molybdenum (Mo), elemental iridium (Ir), iridium oxide (IrO x )、elemental ruthenium (Ru), ruthenium oxide (RuO x)), the elements tungsten (W), aluminum (Al), copper (Cu), gold (Au), silver (Ag), polysilicon, their alloys, or combinations thereof. The terms "electrically conductive material" and "conductive material" are used interchangeably herein.

[0026] As used herein, "memory device" means and includes microelectronic devices that exhibit, but are not limited to, memory functions.

[0027] According to embodiments described herein, conductive interconnects that electrically connect different portions (e.g., different wiring levels) of a microelectronic device include an interconnect structure that includes a first conductive material having manganese therein. The first conductive material may include copper. The interconnect structure may be patterned within a first dielectric material. In some embodiments, the interconnect structure includes a first barrier material adjacent a sidewall of the first dielectric material and the first conductive material adjacent the first barrier material. Each of the interconnect structures is independently in electrical communication with a conductive contact. The conductive contact may be located within an opening defined in a second dielectric material adjacent the first dielectric material. The conductive contact may include a second barrier material within the opening adjacent the second dielectric material and a third barrier material adjacent the second barrier material within the opening. A second conductive material, such as tungsten, may be adjacent the third barrier material. At least a portion of the second barrier material and the third barrier material may be located between the first conductive material and the second conductive material. Manganese may be dispersed within the first conductive material, and the first conductive material may exhibit a greater atomic percentage of manganese at a location proximate the interface of the first conductive material and the second barrier material compared to other portions of the first conductive material. Having a greater atomic percentage of manganese at the interface between the first conductive material and the conductive contact may reduce or prevent voids and electrical discontinuities between the interconnect structure and the conductive contact.

[0028] Forming a conductive interconnect can include forming a first barrier material in an opening within a first dielectric material. A seed material including copper and manganese can be formed adjacent to the first barrier material within the opening. The seed material can include an atomic percentage of manganese in the range of about 0.50 atomic percent to about 1.50 atomic percent. A first conductive material including copper can be formed adjacent to the seed material within the opening to form an interconnect structure. A conductive contact including a second conductive material can be formed adjacent to the interconnect structure (e.g., over the interconnect structure) and within a second dielectric material. Forming the conductive contact can include forming a second barrier material in an opening within the second dielectric material and forming a third barrier material adjacent to the second barrier material. The second conductive material can be formed adjacent to the third barrier material within the opening. After forming the conductive contact, the microelectronic device including the conductive interconnect and the conductive contact can be exposed to annealing conditions in a hydrogen atmosphere to cause manganese from the seed material to diffuse through the first conductive material. In some embodiments, manganese from the seed material can move and separate and accumulate near an interface between the first conductive material and the second barrier material. The interface between the first conductive material and the second conductive material (e.g., the interface between the first conductive material and the second barrier material) can exhibit a greater atomic percentage of manganese compared to other portions of the first conductive material. For example, the first conductive material can exhibit a greater atomic percentage of manganese where it is closer to the second barrier material compared to other portions of the first conductive material. Having a greater atomic percentage of manganese near the interface can increase the electrical continuity between the first conductive material and the second conductive material and increase the reliability of the electrical connection of the conductive interconnect.

[0029] Figure 1A is a simplified cross-sectional view of a microelectronic device 100. The microelectronic device 100 can include a conductive interconnect including an interconnect structure 110 electrically coupled to a conductive contact 120 for electrically connecting one or more components of the microelectronic device 100 to at least one other component of the microelectronic device 100. The interconnect structure 110 can be adjacent to a substrate material 102. Although Figure 1A only one interconnect structure 110 and one conductive contact 120 are shown, the microelectronic device 100 can include multiple (e.g., a plurality of) interconnect structures 110 and conductive contacts 120.

[0030] The substrate material 102 may include a substrate or a structure with additional materials formed thereon. The substrate material 102 may be a semiconductor substrate, a substrate semiconductor layer on a support structure, a metal electrode, or a metal electrode on a semiconductor substrate with one or more layers, structures, or regions formed thereon. The substrate material 102 may be a conventional silicon substrate or other bulk substrates including semiconductor material layers. As used herein, the term "bulk substrate" not only means and includes silicon wafers, but also means and includes silicon-on-insulator ("SOI") substrates such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, epitaxial silicon layers on a substrate semiconductor base, and other semiconductor or optoelectronic materials such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate material 102 may be doped or undoped.

[0031] In addition, when "substrate" or "substrate material" is referred to in the following description, materials, regions, or junctions may have been formed in the substrate semiconductor structure or base using previous process stages. The substrate material 102 may include one or more materials associated with the manufacture of an integrated circuit system. Such materials may include, for example, one or more of refractory metals, barrier materials, diffusion materials, and insulator materials. The substrate material 102 may include, for example, a complementary metal oxide semiconductor (CMOS) structure or other semiconductor structures. Different portions of the substrate material 102 may be electrically isolated from each other by one or more dielectric materials.

[0032] The substrate material 102 may include, for example, one or more components of a memory cell. By way of non-limiting example, the substrate material 102 may include one or more semiconductor components such as one or more of the following: transistors (e.g., including a channel region between a pair of source / drain regions and a gate configured to electrically connect the source / drain regions to each other through the channel region), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), charge pumps (e.g., V CCP charge pump, V NEWWL charge pump, DVC2 charge pump), delay locked loop (DLL) circuitry (e.g., ring oscillators), drain supply voltage (V dd ) regulators, decoders (e.g., column decoders, row decoders), word line (WL) drivers, repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh / wear leveling devices, clock tree modules, and various control circuitry.

[0033] In some embodiments, the interconnect structure 110 is in electrical communication with at least one component of the substrate material 102. By way of non-limiting example, the interconnect structure 110 can be in electrical communication with at least a portion of a transistor of the substrate material 102. In other embodiments, the interconnect structure 110 is in electrical communication with at least a portion of a capacitor.

[0034] The interconnect structure 110 can be positioned within a first dielectric material 104, which may also be referred to herein as a so-called "interlayer dielectric" (ILD) material. The first dielectric material 104 can comprise an electrically insulating material. For example, the first dielectric material 104 can comprise silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si 3 N 4 )), oxynitrides (e.g., silicon oxynitride), another gate dielectric material, dielectric carbonitride materials (e.g., silicon carbonitride (SiCN)), dielectric carbon oxynitride materials (e.g., silicon carbon oxynitride (SiOCN)), or combinations thereof. In some embodiments, the first dielectric material 104 comprises silicon dioxide.

[0035] The interconnect structure 110 can comprise a first barrier material 112 adjacent to the first dielectric material 104 and a first conductive material 114 adjacent to the first barrier material 112. The first barrier material 112 can be formulated and configured to reduce or substantially prevent the diffusion of the components of the first conductive material 114 into the first dielectric material 104. The reactivity of the first barrier material 112 with the material composition of the first conductive material 114, the first dielectric material 104, or both can be relatively low.

[0036] The first barrier material 112 can comprise one or more of the following: tantalum, titanium, cobalt, ruthenium, tungsten, tantalum nitride (TaN), titanium nitride, tungsten nitride, titanium tungsten (TiW), indium oxide, titanium zirconium nitride, tantalum silicide (Ta x Si (1-x) ), tantalum carbide (Ta x C (1-x) ), tungsten silicide (W x Si (1-x) ), tantalum silicon nitride (Ta x Si y N (1-x-y) ), titanium silicon nitride (Ti x Si y N (1-x-y) ), tungsten silicon nitride (W x Si y N (1-x-y) ), or molybdenum silicon nitride (Mox Si y N (1-x-y) )。The first barrier material 112 may include a binary compound or a ternary compound. In some embodiments, the first barrier material 112 includes tantalum.

[0037] The first conductive material 114 may include a conductive material. In some embodiments, the first conductive material 114 includes copper. However, the present disclosure is not limited thereto, and the first conductive material 114 may include other materials (e.g., tungsten, polysilicon).

[0038] The first barrier material 112 may be positioned adjacent to each of the first dielectric material 104 and the first conductive material 114. In some embodiments, the first barrier material 112 is directly located between the first dielectric material 104 and the first conductive material 114 and directly contacts the first dielectric material and the first conductive material.

[0039] Continuing to refer Figure 1A , the capping material 106 may be adjacent to the first dielectric material 104 (e.g., located above the first dielectric material). The second dielectric material 108 may be adjacent to the capping material 106 (e.g., located above the capping material).

[0040] The capping material 106 may include one or more of silicon nitride, silicon carbonitride, or another nitride material. In some embodiments, the capping material 106 includes a first portion including silicon nitride adjacent to the first dielectric material 104, a second portion including silicon carbonitride adjacent to the first portion, and a third portion including silicon nitride adjacent to the second portion and the second dielectric material 108.

[0041] The second dielectric material 108 may include one or more of the materials described above with reference to the first dielectric material 104. In some embodiments, the material composition of the second dielectric material 108 is the same as the material composition of the first dielectric material 104. In some embodiments, the second dielectric material 108 includes silicon dioxide.

[0042] The conductive contact 120 may extend through a portion of the second dielectric material 108 and the capping material 106 to contact the interconnect structure 110. The conductive contact 120 may include a second barrier material 122 adjacent to the second dielectric material 108, a third barrier material 124 adjacent to the second barrier material 122, and a second conductive material 126 adjacent to the third barrier material 124. The second conductive material 126 may be in electrical communication with the first conductive material 114.

[0043] The second barrier material 122 may include materials that are formulated and configured to reduce or substantially prevent the interaction (e.g., diffusion) of components (e.g., the second conductive material 126) of the conductive contact 120 into, for example, the second dielectric material 108. The second barrier material 122 may include one or more of the following: tantalum, titanium, cobalt, ruthenium, tungsten, tantalum nitride (TaN), titanium nitride, tungsten nitride, indium oxide, titanium zirconium nitride, tantalum silicide (Ta x Si (1-x) )), tantalum carbide (Ta x C (1-x) ), tungsten silicide (W x Si (1-x) ), tantalum silicon nitride (Ta x Si y N (1-x-y) ), titanium silicon nitride (Ti x Si y N (1-x-y) ), tungsten silicon nitride (W x Si y N (1-x-y) ), or molybdenum silicon nitride (Mo x Si y N (1-x-y) ). In some embodiments, the composition of the second barrier material 122 is different from the composition of the first barrier material 112. In some embodiments, the second barrier material 122 includes titanium.

[0044] The thickness of the second barrier material 122 may be in the range of about 1 nm to about 10 nm, such as in the range of about 1 nm to about 2 nm, about 2 nm to about 4 nm, about 4 nm to about 6 nm, about 6 nm to about 8 nm, or about 8 nm to about 10 nm. In some embodiments, the thickness of the second barrier material 122 is in the range of about 2 nm to about 7 nm.

[0045] The third barrier material 124 may include a material having a composition different from that of the second barrier material 122. The third barrier material 124 may include one or more of the materials described above with reference to the first barrier material 112. In some embodiments, the third barrier material 124 includes a nitride of the second barrier material 122. In some embodiments, the third barrier material 124 includes titanium nitride.

[0046] The thickness of the third barrier material 124 may be in the range of about 1 nm to about 25 nm, such as in the range of about 1 nm to about 2 nm, about 2 nm to about 5 nm, about 5 nm to about 10 nm, about 10 nm to about 15 nm, about 15 nm to about 20 nm, or about 20 nm to about 25 nm. In some embodiments, the thickness of the third barrier material 124 is in the range of about 2 nm to about 15 nm.

[0047] The second conductive material 126 may include one or more conductive materials. In some embodiments, the material composition of the second conductive material 126 is different from the material composition of the first conductive material 114. In some embodiments, the second conductive material 126 includes tungsten.

[0048] The aspect ratio of the conductive contact 120 can be defined as the height H of the conductive contact 120 1 and the width W 1 ratio. The aspect ratio can be in the range of about 1:1 to about 30:1, such as about 1:1 to about 5:1, about 5:1 to about 10:1, about 10:1 to about 15:1, about 15:1 to about 20:1, about 20:1 to about 25:1, or about 25:1 to about 30:1. However, the present disclosure is not limited thereto, and the aspect ratio can be different from those described.

[0049] Figure 1B is Figure 1A a cross-sectional view of the frame B of, showing Figure 1A a magnified portion of the microelectronic device 100 of. Due to the aspect ratio of the conductive contact 120 and the formation method of the second barrier material 122 and the third barrier material 124, the combined thickness T of the second barrier material 122 and the third barrier material 124 1 may be non-uniform. In other words, the combined thickness T 1 may be non-uniform across the width W of the conductive contact 120 1 or along the height H of the conductive contact 120 1 is non-uniform. For example, the thickness T 1 may be non-uniform along, for example, the interface between the first conductive material 114 and the second barrier material 122 or along the interface between the cover material 106 and the second barrier material 122.

[0050] At least one of the second barrier material 122 and the third barrier material 124 may be discontinuous at least at the corner 130 of the conductive contact 120. For example, the second barrier material 122 and the third barrier material 124 may not cover the corner of the conductive contact 120. Due to the discontinuity of the second barrier material 122 and the third barrier material 124, there may be voids (e.g., air gaps) 132 at positions near the corner 130. However, the voids 132 may increase the contact resistance between the first conductive material 114 of the interconnect structure 110 and the second conductive material 126 of the conductive contact 120.

[0051] Figures 2A to 2Iis a simplified cross-sectional view showing a method of forming a microelectronic device 200 in accordance with an embodiment of the present disclosure. From the description provided below, it will be apparent to those of ordinary skill in the art that the methods described herein can be used to fabricate a variety of devices. For example, whenever it is desired to form an electrical connection, such as between different wiring levels of a microelectronic device (e.g., between components of a transistor (e.g., source region, drain region, gate electrode) and a portion of a capacitor (e.g., first electrode, second electrode)), the methods of the present disclosure can be used.

[0052] Referring Figure 2A , the microelectronic device 200 can include a first dielectric material 204 over a substrate material 202. The substrate material 202 can be substantially similar to the substrate material 102 described above (e.g., can be formed of and include the same materials). For example, the substrate material 202 can include one or more components of a microelectronic device, such as one or more of the following: transistors (e.g., including a channel region between a pair of source / drain regions and a gate configured to electrically connect the source / drain regions to each other through the channel region), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), charge pumps (e.g., V CCP charge pump, V NEWWL charge pump, DVC2 charge pump), delay locked loop (DLL) circuitry (e.g., ring oscillator), drain supply voltage (V dd ) regulator, decoder (e.g., column decoder, row decoder), word line (WL) driver, repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), test devices, array multiplexer (MUX), error checking and correction (ECC) devices, self-refresh / wear leveling devices, clock tree modules, and various control circuitry.

[0053] The first dielectric material 204 can be formed adjacent to the substrate material 202. An opening 213 (e.g., trench, such as a damascene trench) can be formed in the first dielectric material 204 to expose a portion of the substrate material 202 through the opening 213. As will be described herein, a conductive interconnect structure can be formed in the opening 213 and the conductive interconnect structure can be electrically connected to a transistor (e.g., a vertical transistor, a planar transistor), an electrode of a capacitor, an electrode material (e.g., a gate electrode), or another material within the substrate material 202. As an example, the conductive interconnect structure can be electrically connected to a source region of a transistor or a drain region of a transistor.

[0054] A first barrier material 212 may be formed adjacent to the first dielectric material 204 (e.g., on top of the first dielectric material) and within the opening 213. The first barrier material 212 may include one or more of the materials described above with reference to the first barrier material 112. In some embodiments, the first barrier material 212 includes tantalum.

[0055] In some embodiments, the first barrier material 212 may be formed substantially conformally over the surfaces of the first dielectric material 204 and the opening 213 (e.g., sidewalls, bottom surface). The first barrier material 212 may be formed by one or more of PVD, ALD, CVD, LPCVD, or PECVD. In some embodiments, the first barrier material 212 is formed by PVD (such as sputtering using a target including tantalum).

[0056] The thickness T of the first barrier material 212 2 may be in the range of about 1 nm to about 10 nm, such as about 1 nm to about 2 nm, about 2 nm to about 4 nm, about 4 nm to about 6 nm, about 6 nm to about 8 nm, or about 8 nm to about 10 nm. In some embodiments, the thickness T of the second barrier material 122 2 is in the range of about 2 nm to about 7 nm.

[0057] A seed material 216 may be formed adjacent to the first barrier material 212. The seed material 216 may include an alloy of copper and manganese. In some embodiments, the seed material 216 includes CuMn.

[0058] The seed material 216 may include copper containing one or more additive materials. The one or more additive materials may include, for example, manganese. By way of non-limiting example, the seed material 216 may include copper in which manganese is dispersed. The atomic percentage of manganese in the seed material 216 may be in the range of about 0.50 atomic percentage to about 1.50 atomic percentage, such as about 0.50 atomic percentage to about 0.60 atomic percentage, about 0.60 atomic percentage to about 0.70 atomic percentage, about 0.70 atomic percentage to about 0.80 atomic percentage, about 0.80 atomic percentage to about 1.00 atomic percentage, about 1.00 atomic percentage to about 1.25 atomic percentage, or about 1.25 atomic percentage to about 1.50 atomic percentage. In some embodiments, the atomic percentage of manganese in the seed material 126 is in the range of 0.50 atomic percentage to about 1.20 atomic percentage. In some embodiments, manganese constitutes about 0.53 atomic percentage of the seed material 216. Copper may constitute the remainder of the seed material 216. In some embodiments, about 0.53 atomic percentage of the seed material 216 is manganese and about 99.47 atomic percentage of the seed material 216 is copper.

[0059] Manganese can be dispersed substantially uniformly (e.g., substantially evenly, substantially invariantly) throughout the seed material 216. Different portions of the seed material 216 can all exhibit substantially the same amount of manganese as each other. In other embodiments, the seed material 216 exhibits a non-uniform (e.g., non-uneven, variable) manganese distribution. Different portions of the seed material 216 can exhibit different amounts of manganese as each other.

[0060] The seed material 216 can be formed by physical vapor deposition, such as sputtering using a target including the components of the seed material (e.g., copper and manganese). By way of non-limiting example, the target can include manganese in the range of about 0.50 atomic percent to about 1.50 atomic percent, with the remainder of the target including copper. However, the present disclosure is not limited thereto, and the seed material 216 can be formed by other methods, such as by one or more of ALD, CVD, LPCVD, or PECVD.

[0061] Reference Figure 2B , the first conductive material 214 can be formed within the opening 213 ( Figure 2A ) and adjacent to the seed material 216 within the opening 213 (e.g., over the seed material) to form a conductive interconnect structure 210 including the first conductive material 214, the seed material 216, and the first barrier material 212. The first conductive material 214 can comprise the same materials as described above with reference to the first conductive material 114. In some embodiments, the first conductive material 214 includes copper. In some embodiments, the formed first conductive material 214 may not contain manganese.

[0062] The first conductive material 214 can be formed, for example, by electrodeposition (e.g., electroplating). However, in other embodiments, the conductive material 214 can be formed by other methods, such as by one or more of ALD, CVD, PVD, LPCVD, or PECVD.

[0063] After forming the first conductive material 214 adjacent to the seed material 216, portions of the first barrier material 212, the seed material 216, and the first conductive material 214 can be removed to expose the first dielectric material 204. By way of non-limiting example, portions of the first barrier material 212, the seed material 216, and the first conductive material 214 can be removed by chemical-mechanical planarization (CMP) to expose the upper surface of the first dielectric material 204.

[0064] After removing portions of the first barrier material 212, the seed material 216, and the first conductive material 214, a capping material 206 can be formed over the microelectronic device 200 (e.g., adjacent to the first dielectric material 204 and the first conductive material 214).

[0065] The cap material 206 can be formulated and configured to be chemically inert relative to the conductive material 214. In some embodiments, the cap material 206 can substantially not interact (e.g., chemically react) with the first conductive material 214, the seed material 216, or the first barrier material 212.

[0066] The cap material 206 can include, for example, a first portion 205 adjacent to the first dielectric material 204 and the first conductive material 214, a second portion 207 adjacent to the first portion 205, and a third portion 209 adjacent to the second portion 207. The second portion 207 can be directly positioned between the first portion 205 and the third portion 209. In some embodiments, the second portion 207 directly contacts the first portion 205 and the third portion 209.

[0067] The first portion 205 can include a dielectric material. By way of non-limiting example, the first portion 205 can include a nitride material (e.g., silicon nitride (Si 3 N 4 )). The second portion 207 can include a carbonitride material (e.g., silicon carbonitride (SiCN)). The third portion 209 can include a nitride material (e.g., silicon nitride). In some embodiments, the first portion 205 and the third portion 209 have the same material composition, such as silicon nitride.

[0068] Reference Figure 2C , a second dielectric material 208 can be formed adjacent to the cap material 206 and the interconnect structure 210 (e.g., over the cap material and the interconnect structure). The second dielectric material 208 can include the same materials as those described above with reference to the second dielectric material 108. In some embodiments, the second dielectric material 208 includes the same material composition as the first dielectric material 204. In some embodiments, the second dielectric material 208 includes silicon dioxide.

[0069] An opening 215 can be formed in the second dielectric material 208 and the cap material 206 over the interconnect structure 210. The opening 215 can expose the first conductive material 214 of the interconnect structure 210. In some embodiments, the opening 215 does not expose the first barrier material 212 or the seed material 216.

[0070] The opening 215 can have a height H defined as 2 and a width W 2The aspect ratio of the opening can be in the range of about 1:1 to about 30:1, such as about 1:1 to about 5:1, about 5:1 to about 10:1, about 10:1 to about 15:1, about 15:1 to about 20:1, about 20:1 to about 25:1, or about 25:1 to about 30:1. However, the present disclosure is not limited thereto, and the aspect ratio can be different from those described.

[0071] Reference Figure 2D , after forming the opening 215, a second barrier material 222 can be formed over portions of the microelectronic device 200 that are both inside and outside the opening 215. The second barrier material 222 can be formed adjacent to the second dielectric material 208, the capping material 206, and the first conductive material 214.

[0072] The second barrier material 222 can include one or more of the materials described above with reference to the second barrier material 122. In some embodiments, the second barrier material 222 includes titanium.

[0073] The second barrier material 222 can be formed by one or more of ALD, CVD, PVD, LPCVD, or PECVD. In some embodiments, the second barrier material 222 is formed by PVD (such as sputtering using a target including titanium).

[0074] Figure 2E shows Figure 2D a simplified cross-sectional view of box E. In some embodiments, at least a portion of the second barrier material 222 can be formed non-conformally within the opening 215. For example, the thickness T of the second barrier material 222 3 can be substantially non-uniform across the interface between the second barrier material 222 and the first conductive material 214 (such as along the width W of the opening 215 2 ( Figure 2C ). In other words, the second barrier material 222 can exhibit a non-uniform (e.g., variable) thickness T across the interface between the second barrier material 222 and the first conductive material 214 3 . Additionally, the second barrier material 222 can exhibit a non-uniform (e.g., variable) thickness T along at least a portion of the height H of the opening 215 2 ( Figure 2C ). 3For example, the second barrier material 222 may exhibit a relatively reduced thickness at the corner 230 of the opening 215. In some such embodiments, the thickness of the second barrier material 222 may be relatively greater at a portion thereof that is positioned within the central portion of the opening 215 (e.g., away from the interface with the second dielectric material 208 and the capping material 206). Thus, at least a portion of the second barrier material 222 may be formed non-conformally within the opening 215, such as at least a portion of the second barrier material 222 that is adjacent to the first conductive material 214. In some such embodiments, the second barrier material 222 may be discontinuous at one or more locations proximate to the interface between the second barrier material 222 and the first conductive material 214.

[0075] Without being bound by any particular theory, it is believed that the thickness T of the second barrier material 222 3 varies due to the relatively high aspect ratio of the opening 215.

[0076] The thickness T of the second barrier material 222 3 may vary in the range of from about 1 nm to about 10 nm, such as from about 1 nm to about 2 nm, from about 2 nm to about 4 nm, from about 4 nm to about 6 nm, from about 6 nm to about 8 nm, or from about 8 nm to about 10 nm. In some embodiments, the thickness T of the second barrier material 222 3 is in the range of from about 2 nm to about 7 nm.

[0077] Continuing to refer to Figure 2D and Figure 2E , after the second barrier material 222 is formed in the opening 215, a third barrier material 224 may be formed within the opening 215 adjacent to the second barrier material 222.

[0078] The third barrier material 224 may comprise one or more of the materials described above with reference to the third barrier material 114. In some embodiments, the third barrier material 224 comprises a nitride of the second barrier material 222. In some embodiments, the third barrier material 224 comprises titanium nitride.

[0079] The third barrier material 224 may be formed by one or more of ALD, CVD, PVD, LPCVD, or PECVD. In some embodiments, the third barrier material 224 is formed by sputtering using a target comprising titanium nitride.

[0080] Continuing to refer to Figure 2E , the third barrier material 224 may exhibit a non-uniform (e.g., variable) thickness T corresponding to the non-uniform thickness T of the second barrier material 222 3 The thickness T of the third barrier material 224 4 . 4along the width W of the opening 215 2 ( Figure 2C ) vary at least in part. For example, the third barrier material 224 may exhibit a relatively reduced thickness T at the corner 230 of the opening 215 4 . In some such embodiments, the thickness of the third barrier material 224 may be relatively large at a portion thereof positioned within the central portion of the opening 215.

[0081] The thickness T of the third barrier material 224 4 may vary in the range of about 1 nm to about 25 nm, such as about 1 nm to about 2 nm, about 2 nm to about 5 nm, about 5 nm to about 10 nm, about 10 nm to about 15 nm, about 15 nm to about 20 nm, or about 20 nm to about 25 nm. In some embodiments, the thickness T4 of the third barrier material 224 is in the range of about 2 nm to about 15 nm.

[0082] As already referenced Figure 1B and discussed, the discontinuities of the second barrier material 122 and the third barrier material 124 may result in voids 132 near the corner 130 and may increase the resistance between the first conductive material 114 and other conductive materials intended to be in electrical communication with the first conductive material 114. However, as discussed herein, the present disclosure can prevent the formation of such voids 132.

[0083] Referring Figure 2F , after forming the third barrier material 224, a second conductive material 226 may be formed within the opening 215( Figure 2D ) to form a conductive contact 220 in electrical communication with the conductive material 214 of the interconnect structure 210.

[0084] The conductive contact 220 may also be referred to herein as a "conductive plug". The conductive contact 220 may include the second barrier material 222, the third barrier material 224, and the second conductive material 226. The second conductive material 226 may be formed by one or more of electrodeposition, ALD, CVD, PVD, LPCVD, or PECVD. In some embodiments, the second conductive material 226 is formed by electrodeposition.

[0085] The second conductive material 226 may include one or more of the conductive materials described above with reference to the second conductive material 126. In some embodiments, the second conductive material 226 includes tungsten.

[0086] After forming the second conductive material 226, the portions of the second conductive material 226, the third barrier material 224, and the second barrier material 222 that are located within the microelectronic device 200 (within the opening 215( Figure 2D)a portion above the (outer) surface to expose a portion of the second dielectric material 208. In some embodiments, the microelectronic device 200 may be exposed to a CMP process to remove portions of the second conductive material 226, the third barrier material 224, and the second barrier material 222 that are located outside the opening.

[0087] Referring Figure 2G , after performing CMP on the microelectronic device 200, the microelectronic device 200 may be exposed to annealing conditions to separate at least some of the manganese in the manganese of the seed material 216 ([ Figure 2F ) along the interface 228 between the first conductive material 214 and the second conductive material 226. The manganese of the seed material 216 may be substantially separated from the copper of the seed material 216 and may accumulate along the interface 228 between the first conductive material 214 and the second conductive material 226. In some embodiments, annealing the microelectronic device 200 may cause the manganese particles 240 of the seed material 216 to separate into the first conductive material 214. The copper of the seed material 216 may be mixed with the first conductive material 214. In some such embodiments, the copper of the seed material 216 and the copper of the first conductive material 214 may be indistinguishable.

[0088] Exposing the microelectronic device 200 to annealing conditions may include exposing the microelectronic device 200 to a temperature in the range of about 350 °C to about 500 °C, such as in the range of about 350 °C to about 375 °C, about 375 °C to about 400 °C, about 400 °C to about 425 °C, about 425 °C to about 450 °C, about 450 °C to about 475 °C, or about 475 °C to about 500 °C. In some embodiments, the microelectronic device is exposed to a temperature in the range of about 400 °C to about 480 °C. In some embodiments, the microelectronic device 200 is exposed to a temperature of about 420 °C.

[0089] The microelectronic device 200 may be exposed to the temperature for a time in the range of about 30 minutes to about 120 minutes, such as in the range of about 30 minutes to about 60 minutes, about 60 minutes to about 90 minutes, or about 90 minutes to about 120 minutes. In some embodiments, the microelectronic device 200 is exposed to annealing conditions for about 60 minutes.

[0090] Exposing the microelectronic device 200 to annealing conditions may include exposing the microelectronic device 200 to a hydrogen atmosphere. For example, the microelectronic device 200 may be exposed to annealing conditions in an environment including hydrogen (H 2 ) and at least one inert gas (such as at least one of nitrogen, argon, helium, or another gas). In some embodiments, the microelectronic device 200 is exposed to annealing conditions without an oxidant (e.g., oxygen). In some embodiments, exposing the microelectronic device 200 to annealing conditions substantially does not form MnSi xO y It is believed that since the seed material 216 is physically separated from the silicon-containing material, the manganese in the seed material 216 does not interact with silicon. In other words, since the seed material 216 is separated from silicon (e.g., the first dielectric material 204) by the first barrier material 212, the first barrier material 212 can prevent or reduce the diffusion of manganese into the first dielectric material 204.

[0091] During exposure of the microelectronic device 200 to annealing conditions, the manganese particles 240 of the seed material 216 ( Figure 2F ) can segregate into the first conductive material 214, and the seed material 216 can be dispersed within the first conductive material 214. The manganese particles 240 can segregate (or disperse) within the first conductive material 214 in the form of individual particles or aggregates of particles. In some embodiments, the first conductive material 214 may exhibit a relatively large atomic percentage of manganese particles 240 at a location near the interface 228 between the second barrier material 222 and the first conductive material 214. In some embodiments, the first conductive material 214 contains a relatively large atomic percentage of manganese at the intersection of the second barrier material 222, the first conductive material 214, and the material (e.g., the capping material 206) adjacent to the first conductive material 214 and the first dielectric material 204.

[0092] Figure 2H shows a Figure 2G simplified cross-sectional view of box H. In some embodiments, the manganese particles 240 can segregate into the first conductive material 214 around the corner 230. Such segregation of the manganese particles 240 can compensate for the discontinuities of the second barrier material 222 and the third barrier material 224 between the second conductive material 226 and the first conductive material 214 to reduce or prevent the formation of voids in the microelectronic device 200.

[0093] Thus, the manganese particles 240 can facilitate the formation of reliable conductive interconnects without discontinuities between the conductive materials of the conductive interconnects. For example, the manganese particles 240 can segregate and aggregate into portions of the first conductive material 214 where voids (e.g., void 1 32 ( Figure 1B )) may form, thereby reducing the discontinuous portions and electrical connections between the first conductive material 214 and the second conductive material 226. The atomic percentage of manganese at the corner 230 in the first conductive material 214 can be greater than the atomic percentage of manganese at other portions of the first conductive material 214. In some embodiments, the atomic percentage of manganese at the corner 230 in the first conductive material 214 can be greater than at other portions ( Figure 2G) percentage of manganese atoms. Additionally, the percentage of manganese atoms in the first conductive material 214 close to the interface 228 can be greater than the percentage of manganese atoms at other portions of the first conductive material 214. For example, the percentage of manganese atoms within the first conductive material 214 can decrease as the distance from the first dielectric material 204 increases. Additionally, the percentage of manganese atoms within the first conductive material 214 can decrease as the distance from the substrate material 202 and the conductive contact 220 increases. The percentage of manganese atoms at the central portion of the first conductive material 214 can be lower than the percentage of manganese atoms at other portions of the first conductive material 214.

[0094] The percentage of manganese atoms in the seed material 216 ( Figure 2F ) can be selected to promote substantially eliminating the voids 132 ( Figure 1B ) while providing sufficient conductivity between the interconnect structure 210 and the conductive contact 220. Thus, the percentage of manganese atoms in the seed material 216 can be selected to be greater than about 0.50 atomic percent to reduce or prevent voids in the first conductive material 214. The thickness T of the first barrier material 212 2 , the thickness T of the second barrier material 222 3 or the thickness T of the third barrier material 224 4 can be selected, one or more of which, to reduce the resistivity of the electrical connection between the interconnect structure 210 and the conductive contact 220. In some embodiments, the resistivity of the electrical connection between the conductive contact 220 and the conductive interconnect structure 210 can be counteracted by reducing one or more of the thickness T of the first barrier material 212 2 , the thickness T of the second barrier material 222 3 or the thickness T of the third barrier material 224 4 .

[0095] Referring Figure 2I , another interconnect structure 250 in electrical communication with the conductive contact 220 can be formed. For example, a third dielectric material 242 can be formed over the second dielectric material 208 and the conductive contact 220. The third dielectric material 242 can include an electrically insulating material, such as one or more of the materials described above with reference to the first dielectric material 204 or the second dielectric material 208. In some embodiments, the third dielectric material 242 includes silicon dioxide.

[0096] An opening can be formed in the third dielectric material 242 adjacent to the conductive material 226. For example, the opening can be formed to at least expose the second conductive material 226. The width of the opening (in the Figure 2I left - right direction) can be greater than the width W of the conductive contact 220 2 ( Figure 2C ).

[0097] After forming an opening in the third dielectric material 242, a third conductive material 244 can be formed in the opening, and the third conductive material is in electrical communication with the second conductive material 226. The third conductive material 244 can include a conductive material. In one embodiment, the third conductive material 244 includes aluminum.

[0098] Thus, in some embodiments, a microelectronic device includes: a first conductive material that includes copper; a conductive plug that includes tungsten, the conductive plug being in electrical communication with the first conductive material; and manganese particles dispersed along an interface between the first conductive material and the conductive plug.

[0099] Thus, in some embodiments, an electronic device includes: a copper interconnect; a tungsten plug in direct contact with a portion of the copper interconnect; and manganese particles separated within the copper interconnect around the portion of the copper interconnect.

[0100] In addition, in some embodiments, a method of forming a microelectronic device includes: forming an opening in a first dielectric material; forming a first barrier material within the opening in the first dielectric material; forming a seed material including copper and manganese on the first barrier material; forming a first conductive material on the seed material; forming a second dielectric material on the first dielectric material and the first conductive material; forming an additional opening in the second dielectric material; forming a second barrier material within the additional opening in the second dielectric material; forming a second conductive material on the second barrier material; and separating at least some of the manganese in the seed material to a location proximate an interface between the first conductive material and the second barrier material.

[0101] The electronic systems of the present disclosure can include microelectronic devices in accordance with embodiments of the present disclosure (e.g., Figure 2I the depicted microelectronic device 200). For example, Figure 3 is a block diagram of an electronic system 303 in accordance with an embodiment of the present disclosure. The electronic system 303 can include, for example, a computer or computer hardware component, a server or other networked hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or tablet computers), e - books, navigation devices, etc. The electronic system 303 includes at least one memory device 305. The memory device 305 may include, for example, embodiments of the microelectronic devices (e.g., microelectronic device 200) described previously herein, the microelectronic devices including a first conductive material (e.g., first conductive material 214), the first conductive material including manganese particles (e.g., manganese particles 240) at least adjacent to the interface between the first conductive material and a second conductive material (e.g., second conductive material 226 or second barrier material 222).

[0102] The electronic system 303 may further include at least one electronic signal processor device 307 (commonly referred to as a “microprocessor”). The electronic signal processor device 307 may optionally include embodiments of the microelectronic devices (e.g., microelectronic device 200) described previously herein. Although in Figure 3 FIGures, the memory device 305 and the electronic signal processor device 307 are depicted as two (2) separate devices, in additional embodiments, the electronic system 303 includes a single (e.g., only one) memory / processor device having the functions of the memory device 305 and the electronic signal processor device 307. In such embodiments, the memory / processor device may include one or more of the microelectronic device structures and microelectronic devices (e.g., microelectronic device 200) described previously herein.

[0103] The electronic system 303 may further include one or more input devices 309 for a user to input information into the electronic system 303, such as a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual output or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 309 and the output device 311 may include a single touch - screen device that can be used both for inputting information into the electronic system 303 and for outputting visual information to the user. The input device 309 and the output device 311 may be in electrical communication with one or more of the memory device 305 and the electronic signal processor device 307.

[0104] Figure 4Depicts an electronic system 400 (e.g., a processor-based system) according to another embodiment of the present disclosure. The electronic system 400 may include various microelectronic devices (e.g., microelectronic device 200) manufactured according to embodiments of the present disclosure. The electronic system 400 may be of any of a variety of types such as a computer, pager, cellular phone, personal digital assistant, control circuit, or other electronic device. The electronic system 400 may include one or more processors 402, such as a microprocessor, for controlling system functions and processing requests in the electronic system 400. The processor 402 and other sub-components of the processor-based system 400 may include microelectronic devices (e.g., microelectronic device 200 described previously with reference to Figure 2I the microelectronic device described).

[0105] The electronic system 400 may include a power supply 404 operably coupled to the processor 402. For example, if the electronic system 400 is a portable system, the power supply 404 may include one or more of a fuel cell unit, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. The power supply 404 may also include an AC adapter; thus, the electronic system 400 may be plugged into, for example, a wall outlet. The power supply 404 may also include a DC adapter such that the electronic system 400 may be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0106] Depending on the functions performed by the electronic system 400, various other devices may be coupled to the processor 402. For example, a user interface 406 may be coupled to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers, and styli, touchscreens, voice recognition systems, microphones, or combinations thereof. A display 408 may also be coupled to the processor 402. The display 408 may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or combinations thereof. In addition, an RF subsystem / baseband processor 410 may be coupled to the processor 402. The RF subsystem / baseband processor 410 may include an antenna coupled to an RF receiver and an RF transmitter (not shown). One or more communication ports 412 may also be coupled to the processor 402. The communication port 412 may be adapted to couple to one or more peripheral devices 414, such as a modem, printer, computer, scanner, or camera, or to a network such as a local area network, a remote local area network, an intranet, or the Internet.

[0107] The processor 402 can control the electronic system 400 by implementing software programs stored in the memory. The software programs can include, for example, an operating system, database software, graphics software, word processing software, media editing software, or media playback software. The memory is operatively coupled to the processor 402 to store various programs and facilitate the execution of various programs. For example, the processor 402 can be coupled to a system memory 416, which can include one or more of the following: spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory 416 can include volatile memory, non-volatile memory, or a combination thereof. The system memory 416 is typically large enough such that it can store dynamically loaded applications and data. In some embodiments, the system memory 416 can include microelectronic devices, such as the microelectronic devices described above (e.g., the microelectronic device 200 previously referenced Figure 2I as described).

[0108] The processor 402 can also be coupled to a non-volatile memory 418, which does not imply that the system memory 416 is necessarily volatile. The non-volatile memory 418 can include one or more of the following: STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in combination with the system memory 416. The size of the non-volatile memory 418 is typically chosen to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memory 418 can include high-capacity memory, such as disk drive memory, e.g., a hybrid drive that includes resistive memory or other types of non-volatile solid-state memory. The non-volatile memory 418 can include microelectronic devices, such as the microelectronic devices described above (e.g., the microelectronic device 200 previously referenced Figure 2I as described).

[0109] Thus, in at least some embodiments, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device. The memory device includes: a first conductive material located within a first dielectric material; a second conductive material adjacent to the first conductive material and located within a second dielectric material adjacent to the first conductive material; at least a first barrier material located between the first conductive material and the second conductive material; and manganese particles located within the first conductive material and adjacent to the first barrier material.

[0110] Additional non-limiting example embodiments of the present disclosure are described below.

[0111] Example 1: A microelectronic device includes: a first conductive material including copper; a conductive plug including tungsten, the conductive plug being in electrical communication with the first conductive material; and manganese particles dispersed along an interface between the first conductive material and the conductive plug.

[0112] Example 2: The microelectronic device according to Example 1, wherein the conductive plug further includes a barrier material between the tungsten and the first conductive material.

[0113] Example 3: The microelectronic device according to Example 2, wherein a portion of the first conductive material near a corner of the barrier material exhibits a relatively large amount of manganese compared to other portions of the first conductive material.

[0114] Example 4: The microelectronic device according to Example 2 or Example 3, wherein the barrier material is discontinuous.

[0115] Example 5: The microelectronic device according to any one of Examples 1 to 4, further including additional manganese particles dispersed throughout the first conductive material.

[0116] Example 6: The microelectronic device according to any one of Examples 1 to 5, further including an interconnect structure including aluminum, the interconnect structure being in contact with the conductive plug that electrically connects the first conductive material to the interconnect structure.

[0117] Example 7: The microelectronic device according to any one of Examples 1 to 6, wherein the first conductive material exhibits a gradient of the manganese particles, and the first conductive material has a relatively large amount of manganese near the conductive plug compared to positions away from the conductive plug.

[0118] Example 8: An electronic system, comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a first conductive material located within a first dielectric material; a second conductive material adjacent to the first conductive material and located within a second dielectric material adjacent to the first conductive material; at least a first barrier material located between the first conductive material and the second conductive material; and manganese particles located within the first conductive material and adjacent to the first barrier material.

[0119] Example 9: The electronic system according to Example 8, wherein a portion of the first conductive material adjacent to the first barrier material contains a relatively large amount of manganese compared to other portions of the first conductive material.

[0120] Example 10: The electronic system according to Example 8 or Example 9, wherein the first conductive material comprises copper.

[0121] Example 11: The electronic system according to any one of Examples 8 to 10, further comprising a capping material between the first dielectric material and the second dielectric material, with at least some of the manganese particles adjacent to the capping material.

[0122] Example 12: The electronic system according to Example 11, wherein the capping material comprises silicon carbonitride between a first silicon nitride portion and a second silicon nitride portion.

[0123] Example 13: The electronic system according to any one of Examples 8 to 12, wherein the second conductive material comprises tungsten.

[0124] Example 14: The electronic system according to any one of Examples 8 to 13, wherein the first barrier material comprises titanium.

[0125] Example 15: The electronic system according to any one of Examples 8 to 14, further comprising a second barrier material between the first barrier material and the second conductive material.

[0126] Example 16: The electronic system according to Example 15, wherein the second barrier material comprises titanium nitride.

[0127] Example 17: The electronic system according to any one of Examples 8 to 16, wherein the second conductive material comprises tungsten and the first conductive material comprises copper.

[0128] Example 18: An electronic device, comprising: a copper interconnect; a tungsten plug in direct contact with a portion of the copper interconnect; and manganese particles separated in the copper interconnect around the portion of the copper interconnect.

[0129] Example 19: The electronic device according to Example 18, wherein the tungsten plug comprises a tungsten material and a barrier material, the barrier material being interposed between the tungsten material and the copper interconnect.

[0130] Example 20: The electronic device according to Example 19, wherein the barrier material comprises a corner portion, and the manganese particles aggregate at the corner portion of the barrier material in the copper interconnect.

[0131] Example 21: The electronic device according to any one of Examples 18 to 20, further comprising additional manganese particles separated in a scattered manner in the copper interconnect.

[0132] Example 22: The electronic device according to any one of Examples 19 to 21, further comprising an aluminum interconnect in contact with the tungsten plug, wherein the aluminum interconnect and the copper interconnect are coupled to each other through the tungsten plug.

[0133] Example 23: A method of forming a microelectronic device, the method comprising: forming an opening in a first dielectric material; forming a first barrier material in the opening in the first dielectric material; forming a seed material comprising copper and manganese on the first barrier material; forming a first conductive material on the seed material; forming a second dielectric material on the first dielectric material and the first conductive material; forming an additional opening in the second dielectric material; forming a second barrier material in the additional opening in the second dielectric material; forming a second conductive material on the second barrier material; and separating at least some of the manganese in the manganese of the seed material to a position close to the interface between the first conductive material and the second barrier material.

[0134] Example 24: The method according to Example 23, wherein separating at least some of the manganese in the manganese of the seed material comprises heating the seed material to a temperature in the range of about 400 °C to about 480 °C in a hydrogen atmosphere.

[0135] Example 25: The method according to Example 23 or Example 24, wherein separating at least some of the manganese in the seed material to a position close to the interface between the first conductive material and the second barrier material includes forming a portion of the first conductive material close to the interface between the first conductive material and the second barrier material to have a relatively large amount of manganese compared to other portions of the first conductive material.

[0136] Example 26: The method according to any one of Examples 23 to 25, wherein forming the seed material including copper and manganese includes forming the seed material to include from about 0.50 atomic percent to about 1.50 atomic percent of manganese.

[0137] Example 27: The method according to any one of Examples 23 to 25, wherein forming the seed material including copper and manganese includes forming the seed material to include more than about 0.50 atomic percent of manganese.

[0138] Example 28: The method according to any one of Examples 23 to 27, further comprising selecting the first conductive material to include copper.

[0139] Example 29: The method according to any one of Examples 23 to 28, further comprising selecting the second conductive material to include tungsten.

[0140] Although certain illustrative embodiments have been described in connection with the accompanying drawings, those of ordinary skill in the art will recognize and understand that the embodiments covered by the present disclosure are not limited to those expressly shown and described herein. Instead, many additions, deletions, and modifications, including legal equivalents, may be made to the embodiments described herein without departing from the scope of the embodiments covered by the present disclosure (such as the embodiments claimed hereinafter). Additionally, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being within the scope of the present disclosure.

Claims

1. A microelectronic device, which comprises: a first conductive material; a conductive plug, the conductive plug being in electrical communication with the first conductive material, wherein the conductive plug further comprises a barrier material between the conductive plug and the first conductive material; and manganese particles, the manganese particles being dispersed along an interface between the first conductive material and the conductive plug, wherein a portion of the first conductive material adjacent to a corner of the barrier material exhibits a relatively large amount of manganese compared to other portions of the first conductive material.

2. The microelectronic device according to claim 1, wherein the barrier material is discontinuous.

3. The microelectronic device according to claim 1, which further comprises additional manganese particles dispersed throughout the first conductive material.

4. The microelectronic device according to claim 1, which further comprises an interconnect structure, the interconnect structure comprising aluminum, the interconnect structure being in contact with the conductive plug, the conductive plug electrically connecting the first conductive material to the interconnect structure.

5. The microelectronic device according to claim 1, wherein the first conductive material exhibits a gradient of the manganese particles, and the first conductive material has a relatively large amount of manganese near the conductive plug compared to positions away from the conductive plug.

6. The microelectronic device according to claim 1, wherein the first conductive material comprises copper and the conductive plug comprises tungsten.

7. An electronic system, which comprises: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a first conductive material located within a first dielectric material; a second conductive material adjacent to the first conductive material and located within a second dielectric material adjacent to the first conductive material; at least a first barrier material located between the first conductive material and the second conductive material; and manganese particles located within the first conductive material and adjacent to the at least first barrier material, wherein a portion of the first conductive material adjacent to a corner of the at least first barrier material exhibits a relatively large amount of manganese compared to other portions of the first conductive material.

8. The electronic system according to claim 7, wherein the first conductive material comprises copper.

9. The electronic system according to claim 7, which further comprises a capping material between the first dielectric material and the second dielectric material, and at least some of the manganese particles are adjacent to the capping material.

10. The electronic system according to claim 9, wherein the capping material comprises silicon carbonitride between a first silicon nitride portion and a second silicon nitride portion.

11. The electronic system according to claim 7, wherein the second conductive material comprises tungsten.

12. The electronic system according to claim 11, wherein the first barrier material comprises titanium.

13. The electronic system according to claim 7, further comprising a second barrier material located between the first barrier material and the second conductive material.

14. The electronic system according to claim 13, wherein the second barrier material comprises titanium nitride.

15. The electronic system according to claim 7, wherein the second conductive material comprises tungsten and the first conductive material comprises copper.

16. An electronic device, which comprises: a copper interconnect; a tungsten plug in direct contact with a portion of the copper interconnect; and manganese particles separated in the copper interconnect around the portion of the copper interconnect, wherein the tungsten plug comprises a tungsten material and a barrier material, the barrier material being between the tungsten material and the copper interconnect, wherein the barrier material comprises a corner portion, and the manganese particles aggregate in the copper interconnect at the corner portion of the barrier material.

17. The electronic device according to claim 16, further comprising additional manganese particles separated in the copper interconnect in a dispersed manner.

18. The electronic device according to claim 16, further comprising an aluminum interconnect in contact with the tungsten plug, the aluminum interconnect and the copper interconnect being coupled to each other through the tungsten plug.

19. A method of forming a microelectronic device, the method comprises: forming an opening in a first dielectric material; forming a first barrier material in the opening in the first dielectric material; forming a seed material comprising copper and manganese on the first barrier material; forming a first conductive material on the seed material; forming a second dielectric material on the first dielectric material and the first conductive material; forming an additional opening in the second dielectric material; forming a second barrier material in the additional opening in the second dielectric material; forming a second conductive material on the second barrier material; and separating at least some of the manganese in the seed material to a position close to the interface between the first conductive material and the second barrier material, wherein separating at least some of the manganese in the seed material to a position close to the interface between the first conductive material and the second barrier material comprises forming a portion of the first conductive material close to the corner of the second barrier material to have a relatively large amount of manganese compared to other portions of the first conductive material.

20. The method according to claim 19, wherein separating at least some of the manganese in the seed material comprises heating the seed material to a temperature in the range of 400 °C to 480 °C in a hydrogen atmosphere.

21. The method according to claim 19, wherein forming a seed material comprising copper and manganese comprises forming the seed material to comprise from 0.50 atomic percent to 1.50 atomic percent of manganese.

22. The method according to claim 19, wherein forming a seed material comprising copper and manganese comprises forming the seed material to comprise more than 0.50 atomic percent of manganese.

23. The method according to claim 19, further comprising selecting the first conductive material to include copper.

24. The method according to claim 19, further comprising selecting the second conductive material to include tungsten.

Images