Semiconductor devices and semiconductor packages

Abstract

A semiconductor device and a semiconductor package are provided. The semiconductor device includes: a semiconductor substrate having at least one semiconductor structure; an interlayer insulating layer disposed on the semiconductor substrate; at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer and including a first region and a second region, the first region having a first width on the upper surface of the interlayer insulating layer, the second region extending from the first region and having a second width on the lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region; and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width on the upper surface of the interlayer insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0086351 filed on July 17, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concepts relate to semiconductor devices and semiconductor packages. Background Art

[0004] Semiconductor devices mounted on electronic devices can be packaged in various forms. Recently, packages in which semiconductor devices are stacked in a vertical direction have been proposed to potentially improve the performance of semiconductor devices (such as integration density, accessible bandwidth, power consumption, etc.). In such a package, the semiconductor device may include bumps for input and output signals and via structures connected to these bumps. The via structure may have various forms and sizes depending on the purpose of the via structure. Summary of the invention

[0005] Some example embodiments of the inventive concepts are provided to relate to semiconductor devices and / or semiconductor packages including via structures having different shapes and / or sizes and which may have improved reliability and yield by improving a process of manufacturing the via structure.

[0006] According to an example embodiment conceived in the present invention, a semiconductor device includes: a semiconductor substrate having at least one semiconductor structure; an interlayer insulating layer, which is arranged on the semiconductor substrate; at least one first via structure, which penetrates the semiconductor substrate and the interlayer insulating layer and includes a first region and a second region, the first region has a first width on the upper surface of the interlayer insulating layer, the second region extends from the first region and has a second width on the lower surface of the semiconductor substrate, wherein the side surface of the first region and the side surface of the second region have different profiles in a region adjacent to a boundary between the first region and the second region; and at least one second via structure, which penetrates the semiconductor substrate and the interlayer insulating layer and has a third width greater than the first width on the upper surface of the interlayer insulating layer.

[0007] According to an example embodiment conceived in the present invention, a semiconductor package includes: a first semiconductor device; and a second semiconductor device stacked with the first semiconductor device, the first semiconductor device including at least one first via structure and at least one second via structure penetrating the first semiconductor device, and the at least one first via structure including a first region and a second region, the first region having a first width on an upper surface of the semiconductor device, the second region having a second width on a lower surface of the first semiconductor device, and a width of a boundary surface between the first region and the second region being less than the first width.

[0008] According to an example embodiment conceived in the present invention, a semiconductor package includes: a packaging substrate; a plurality of memory dies mounted on the packaging substrate and including memory cells configured to store data, the plurality of memory dies can be stacked in a direction perpendicular to an upper surface of the packaging substrate; a first via structure penetrating the plurality of memory dies and providing a transmission path for data signals; and a second via structure penetrating the plurality of memory dies and providing a transmission path for power signals, the difference between a maximum value and a minimum value of a width of the first via structure being smaller than a difference between a maximum value and a minimum value of a width of the second via structure, and the minimum value of the width of the first via structure being smaller than the minimum value of the width of the second via structure.

[0009] According to an example embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a plurality of semiconductor structures on a semiconductor substrate; forming an interlayer insulating layer on an upper surface of the semiconductor substrate; forming a first trench having a first width and exposing the semiconductor substrate by partially removing the interlayer insulating layer in a first position; forming a second trench having a width greater than the first width and exposing the semiconductor substrate by partially removing the interlayer insulating layer in a second position different from the first position; extending the first trench and the second trench by etching the semiconductor substrate in the first trench and the second trench; and filling the first trench and the second trench with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating an electronic device including a semiconductor device according to an example embodiment of the inventive concept;

[0012] Figure 2 is a perspective view showing a semiconductor device according to an example embodiment of the inventive concept;

[0013] Figure 3 is a diagram illustrating a semiconductor device according to an example embodiment of the inventive concept;

[0014] Figure 4 is shown along Figure 3 The line I-I' in Figure 3 A cross-sectional view of a semiconductor device shown in FIG.

[0015] Figures 5 to 10 is an enlarged view showing a partial region of a semiconductor device according to an example embodiment of the inventive concept;

[0016] Figures 11 to 19 is a diagram illustrating a process of manufacturing a semiconductor device according to an example embodiment of the inventive concept;

[0017] Fig. 20 is a diagram illustrating a semiconductor package according to an example embodiment of the inventive concept;

[0018] Fig.21 and Fig. 22 are diagrams illustrating semiconductor packages according to example embodiments of the inventive concepts; and

[0019] Fig.23 and Fig.24 are diagrams illustrating semiconductor packages according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0020] For ease of description, spatially relative terms such as "below," "vertical," "above," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "below" will then be positioned as "above," or if the device is rotated 90 degrees, an element that is "vertically stacked" will then be positioned as "horizontally stacked." In addition, when an element is referred to as being "between" two elements, the element may be the only element of the two elements, or one or more other intermediate elements may be present.

[0021] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings as follows.

[0022] Figure 1 is a block diagram illustrating an electronic apparatus including a semiconductor device according to example embodiments.

[0023] Figure 1 The electronic device 10 in the example embodiment shown in FIG. 1 may include a display 11, a sensor unit 12, a memory 13, a processor 14, and a port 15. The electronic device 10 may also include wired and wireless communication means and a power supply means. Figure 1Among the elements shown in , port 15 can allow electronic device 10 to communicate with other electronic components (like video card, sound card, memory card, USB device, etc.). Electronic device 10 may include a general desktop computer or general notebook computer, a smart phone, a tablet PC, a smart wearable device, etc.

[0024] The processor 14 may perform calculations, execute command words, manage tasks, etc. The processor 14 may be implemented as a central processing unit (CPU), a microprocessor unit (MCU), a system on a chip (SoC), an application processor (AP), etc., and may include two or more cores that perform calculations, command words, etc. The processor 14 may communicate with the display 11, the sensor unit 12, the memory 13, and other devices connected to the port 15 through the bus 16.

[0025] The memory 13 may be implemented as a storage medium that stores data required for the operation of the electronic device 10, multimedia data, etc. The memory 13 may include a volatile memory such as a random access memory (RAM) or a non-volatile memory such as a flash memory, etc. The memory 13 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD). The sensor unit 12 may include a GPS sensor, an image device, an optical sensor, a motion sensor, etc.

[0026] At least one of the elements 11 to 15 included in the electronic device 10 may include a semiconductor package in which two or more semiconductor devices are stacked in a vertical direction. For example, an image device included in the sensor unit 12 may include an image sensor, a memory, etc. stacked in a vertical direction. In another example, a memory die for storing data may be vertically stacked in the memory 13.

[0027] In a semiconductor package in which semiconductor devices are stacked in a vertical direction, at least one of the semiconductor devices may include a via structure for sending and receiving signals. For example, the via structure may be implemented as a through silicon via (TSV). In example embodiments, at least some portions of the via structure included in a single semiconductor device may be configured to have different shapes and sizes, thereby improving the integration density of the via structure.

[0028] Figure 2 is a perspective view illustrating a semiconductor device according to example embodiments.

[0029] Reference Figure 2, the semiconductor package 20 in the example embodiment may include a plurality of semiconductor devices 21 to 24 stacked in a vertical direction. For example, each of the plurality of semiconductor devices 21 to 24 may be implemented as a memory device for storing data, or may be implemented as an image sensor that generates image data in response to external light. At least some portions of the plurality of semiconductor devices 21 to 24 may perform different functions. For example, the second semiconductor device 22 to the fourth semiconductor device 24 may include a memory region having a memory cell for storing data, and the first semiconductor device 21 may include a logic circuit that controls the memory region included in the second semiconductor device 22 to the fourth semiconductor device 24.

[0030] The plurality of semiconductor devices 21 to 24 may transmit and receive data through the plurality of via structures 25 and 26. The plurality of via structures 25 and 26 may be TSVs penetrating the plurality of semiconductor devices 21 to 24, and may include first via structures 25 and second via structures 26 having different sizes. For example, the width of each of the first via structures 25 may be smaller than the width of each of the second via structures 26. The number and arrangement of the first via structures 25 and the second via structures 26 may vary in example embodiments.

[0031] Compared to the width of each of the second via structures 26, Figure 2 Each of the first via structures 25 in the example embodiment shown in FIG. 1 may have a relatively small width. The width may be defined as the length of each of the via structures taken in a direction parallel to the upper surface of each of the plurality of semiconductor devices 21 to 24. The first via structure 25 may also provide a function different from that of the second via structure 26. For example, the first via structure 25 may provide a transmission path for a data signal, and the second via structure 26 may provide a transmission path for a power signal.

[0032] The first via structure 25 and the second via structure 26 having different widths may be formed in the same process. In other words, the first via structure 25 and the second via structure 26 may be formed by forming a plurality of grooves having different widths (e.g., by applying an etching process to each of the plurality of semiconductor devices 21 to 24 and filling the grooves with a conductive material). The grooves corresponding to the first via structure 25 and the grooves corresponding to the second via structure 26 may have different widths, and therefore, there may be a difference between the etching speeds, so that the length of each of the first via structures 25 may be different from the length of each of the second via structures 26.

[0033] When forming the first via structure 25 and the second via structure 26, a grinding process may be performed on each of the semiconductor devices 21 to 24, thereby exposing the first via structure 25 and the second via structure 26. When the length of each of the first via structures 25 is different from the length of each of the second via structures 26, the first via structure 25 and the second via structure 26 may receive different stresses generated by performing the grinding process. For example, the length of each of the first via structures 25 may be longer than the length of each of the second via structures 26, and the first via structure 25 may be exposed earlier than the second via structure 26 by the grinding process. Therefore, since the grinding process is continued until the second via structure 26 is exposed, the first via structure 25 may be bent or broken.

[0034] In example embodiments, the first via structures 25 may have different widths on the upper and lower surfaces of each of the semiconductor devices 21 to 24. For example, when a grinding process is performed on the lower surface of each of the semiconductor devices 21 to 24, the width of each of the first via structures 25 on the upper surface of each of the semiconductor devices 21 to 24 may be smaller than the width of each of the first via structures 25 on the lower surface of each of the semiconductor devices 21 to 24. Therefore, the reliability of the via structures 25 and 26 may be improved by significantly reducing the length difference between the first via structure 25 and the second via structure 26 and reducing the stress applied to the via structures 25 and 26 in the grinding process.

[0035] Figure 3 is a diagram illustrating a semiconductor device according to example embodiments. Figure 4 is shown along Figure 3 The line I-I' in Figure 3 0014 is a cross-sectional view of a semiconductor device shown in FIG.

[0036] Reference Figure 3 and Figure 4 , the semiconductor device 100 in the example embodiment may include a semiconductor substrate 101, an interlayer insulating layer 105, a first via structure 110, a second via structure 120, and a plurality of semiconductor structures 130. The plurality of semiconductor structures 130 may be covered by the interlayer insulating layer 105, and the interlayer insulating layer 105 may include an insulating material such as silicon oxide.

[0037] Figure 3 It may be a diagram showing a plane of the semiconductor device 100 viewed from the upper surface of the semiconductor device 100. Figure 3, the first via structure 110 may be separated from the second via structure 120. In other words, the first via structure 110 may be located in a first region of the semiconductor device 100, and the second via structure 120 may be located in a second region of the semiconductor device 100 that is different from the first region of the semiconductor device 100. Alternatively, Figure 3 Unlike the example shown in FIG. 1 , the first via structure 110 and the second via structure 120 may be adjacent to each other in other example embodiments.

[0038] Reference Figure 4 , the first via structure 110 and the second via structure 120 may penetrate the semiconductor device 100. For example, the first via structure 110 and the second via structure 120 may be TSVs. The first via structure 110 and the second via structure 120 may extend from the upper surface of the interlayer insulating layer 105 to the lower surface of the semiconductor substrate 101. In other words, the first via structure 110 and the second via structure 120 may be exposed from the upper surface of the interlayer insulating layer 105 and from the lower surface of the semiconductor substrate 101.

[0039] Reference Figure 4 , the first via structure 110 may include a first region 111 and a second region 112. The first region 111 may be configured to extend from the upper surface of the interlayer insulating layer 105, and the second region 112 may be configured to extend from the lower surface of the semiconductor substrate 101. A boundary surface 113 may be defined between the first region 111 and the second region 112. The boundary surface may include a portion of a boundary that is a region between the first region 111 and the second region 112. The length of each of the first region 111 and the second region 112 may vary in example embodiments. For example, the first region 111 may be longer than the second region 112, or the length of the first region 111 may be the same as the length of the second region 112. As another example, the length of the second region 112 may also be longer than the length of the first region 111. The boundary surface 113 may be located in the semiconductor substrate 101 and may be closer to the upper surface of the semiconductor substrate 101 than to the lower surface of the semiconductor substrate 101.

[0040] The first region 111 may have a first width W1 on the upper surface of the interlayer insulating layer 105, and the second region 112 may have a second width W2 on the lower surface of the semiconductor substrate 101. The second width W2 may be greater than the first width W1. The width of the first region 111 may be less than the width of the second region 112, and as shown in FIG. Figure 4 As shown in FIG. 1 , the first via structure 110 may have a curved side surface on the boundary surface 113 . Therefore, the side surface of the first region 111 and the side surface of the second region 112 may have different profiles in regions adjacent to the boundary surface 113 .

[0041] The second via structure 120 may have a third width W3 on the upper surface of the interlayer insulating layer 105, and in an example embodiment, unlike the first via structure 110, the second via structure 120 may not be divided into a plurality of regions. The third width W3 may be greater than the first width W1. In other words, the width of the second via structure 120 may be greater than the width of the first region 111. The third width W3 may be greater than the second width W2, may be the same as the second width W2, or may be less than the second width W2.

[0042] The profiles of the first via structure 110 and the second via structure 120 may be similar to Figure 4 . For example, the second via structure 120 may have a third width W3 on the upper surface of the interlayer insulating layer 105, and may have a profile in which the width of the second via structure 120 decreases toward the lower surface of the semiconductor substrate 101. The first region 111 of the first via structure 110 may have a width that decreases from the upper surface of the interlayer insulating layer 105 toward the boundary surface 113. The second region 112 of the first via structure 110 may have a width that increases from the region adjacent to the boundary surface 113, and the width may decrease toward the lower surface of the semiconductor substrate 101. The first region 111 and the second region 112 of the first via structure 110 and the second via structure 120 may have a tapered shape whose width decreases in the length direction. Therefore, the minimum value of the width of the first via structure 110 and the minimum value of the width of the second via structure 120 may appear at different positions in the length direction.

[0043] Figures 5 to 10 is an enlarged view illustrating a partial region of a semiconductor device according to example embodiments.

[0044] Figures 5 to 10 1 is an enlarged view showing the first via structures 110, 110A, 110B, 110C, 110D, and 110E and the second via structure 120 included in each of the semiconductor devices 100, 100A, 100B, 100C, 100D, and 100E. Figures 5 to 10 In the example embodiment shown in FIG. 1 , each of the semiconductor devices 100, 100A, 100B, 100C, 100D, and 100E may include a semiconductor substrate 101 and an interlayer insulating layer 105 covering the semiconductor substrate 101. The first via structures 110, 110A, 110B, 110C, 110D, and 110E and the second via structure 120 may be TSVs penetrating the semiconductor substrate 101 and the interlayer insulating layer 105.

[0045] Reference Figure 5, the first via structure 110 may include a first region 111, a second region 112, and a boundary surface 113. The boundary surface 113 may be defined as an intersection space between the first region 111 and the second region 112. The first region 111 may have a first width W1, and the second region 112 may have a second width W2 greater than the first width W1. The second via structure 120 may have a third width W3, and the third width W3 may be greater than the first width W1 and the second width W2.

[0046] In the region adjacent to the boundary surface 113, the second region 112 may have a width that increases from the boundary surface 113. Alternatively, in the region adjacent to the boundary surface 113, the first region 111 may have a constant width that does not change significantly, or may have a width that decreases toward the boundary surface 113. Therefore, in the region adjacent to the boundary surface 113, the first region 111 and the second region 112 may have different profiles.

[0047] The first via structure 110 may have a first maximum width in the second region 112 and a minimum width in the first region 111. The second via structure 120 may also have a maximum width and a minimum width. The difference between the maximum width and the minimum width of the first via structure 110 may be smaller than the difference between the maximum width and the minimum width of the second via structure 120. In example embodiments, when measured from a direction perpendicular to the upper surface of the interlayer insulating layer 105, the minimum width of the second via structure 120 may be located at a different position from the minimum width of the first via structure.

[0048] Reference Figure 6 , the first via structure 110A may include a first region 111A and a second region 112A, and a boundary surface 113A may be defined between the first region 111A and the second region 112A. Figure 5 In the example embodiment shown in FIG. 1 , the first region 111A may have a first width W1, and the second region 112A may have a second width W2 greater than the first width W1. The second via structure 120 may have a third width W3 greater than the first width W1. Figure 6 In the example embodiment shown in FIG. 1 , the third width W3 may be substantially the same as the second width W2. Figure 6 In the example embodiment shown in , the first region 111A and the second region 112A may have different profiles in a region adjacent to the boundary surface 113 .

[0049] Reference Figure 7 , the first via structure 110B may include a first region 111B and a second region 112B, and a boundary surface 113B may be defined between the first region 111B and the second region 112B. Figure 7 In the example embodiment shown in FIG. 1 , the first region 111B may have a first width W1, and the second region 112B may have a second width W2 greater than the first width W1. The second via structure 120 may have a third width W3 greater than the first width W1 and less than the second width W2. Figure 7 In the example embodiment shown in FIG. 1 , the first region 111B and the second region 112B may have different profiles in a region adjacent to the boundary surface 113B.

[0050] Reference Figure 8 , the semiconductor device 100C may include a first via structure 110C and a second via structure 120. Figure 8 In the example embodiment shown in FIG. 1 , the third width W3 of the second via structure 120 may be greater than the first width W1 of the first region 111C. The first region 111C may include a region whose width decreases toward the boundary surface 113C in a region adjacent to the boundary surface 113C between the first region 111C and the second region 112C.

[0051] Therefore, if Figure 8 As shown in FIG. 1 , the recess 114C may be formed at the boundary surface 113C or in an area adjacent to the boundary surface 113C. In the area in which the recess 114C is formed, the width of the first via structure 110C may have a minimum value. As an example, when the recess 114C is formed in the boundary surface 113C, the width of the boundary surface 113C may be determined as the minimum value of the width of the first via structure 110C.

[0052] Reference Fig. 9 , the semiconductor device 100D may include a first via structure 110D and a second via structure 120. The first via structure 110D may include a first region 111D and a second region 112D, and a boundary surface 113D may be defined between the first region 111D and the second region 112D. Fig. 9 In the example embodiment shown in FIG. 1 , the side surface of the second region 112D may have a texture in a region adjacent to the boundary surface 113D. As an example, in a region adjacent to the boundary surface 113D, a plurality of embossed structures 115D may be formed on the side surface of the second region 112D. The plurality of embossed structures 115D may add additional curves (e.g., surface area) to the second region 112D.

[0053] The relief structure 115D may be located at a partial region of the second region 112D whose width may be increased from the boundary surface 113D. Alternatively, in other example embodiments, the relief structure 115D may be formed to extend across a side surface of the second region 112D. Fig. 9The example shown is a larger area.

[0054] Reference Fig.10 , the semiconductor device may include a first via structure 110E and a second via structure 120. The first via structure 110E may include a first region 111E and a second region 112E, and a boundary surface 113E may be defined between the first region 111E and the second region 112E. Fig.10 In the example embodiment shown in FIG. 1 , the first via structure 110E may include a recess 114E formed at or in a region adjacent to the boundary surface 113E. The second region 112E of the first via structure 110E may include a plurality of relief structures 115E forming a bend on a side surface of the second region 112E.

[0055] Can refer to Figure 8 and Fig. 9 The description of the recess 114E and the relief structure 115E is understood from the foregoing exemplary embodiments described. For example, the width of the first via structure 110E may have a minimum value in the region in which the recess 114E is formed. In addition, the relief structure 115E may be formed on a side surface of the second region 112E adjacent to the boundary surface 113E.

[0056] Figures 11 to 19 is a diagram illustrating a process of manufacturing a semiconductor device according to example embodiments.

[0057] Reference Fig.11 , a plurality of semiconductor structures 230 may be disposed on the semiconductor substrate 201, and an interlayer insulating layer 205 covering the semiconductor structures 230 may be disposed on one surface of the semiconductor substrate 201. In the following description, the surface on which the interlayer insulating layer 205 is disposed may be defined as the upper surface of the semiconductor substrate 201.

[0058] A first mask layer PM1 may be disposed on an upper surface of the interlayer insulating layer 205. As an example, the first mask layer PM1 may be configured as a hard mask layer and may be a photomask. A first opening OP1 may be formed in the first mask layer PM1 by selectively removing at least some portions of the first mask layer PM1. As an example, the first opening OP1 may be formed in a region where the plurality of semiconductor structures 230 are not disposed.

[0059] When forming the first opening OP1, a portion of the interlayer insulating layer 205 exposed in the first opening OP1 may be removed. Fig.11, the formation of the first opening OP1 may remove only a portion of the interlayer insulating layer 205 exposed in the first opening OP1, and therefore, the upper surface of the semiconductor substrate 201 may not be exposed. By removing a portion of the interlayer insulating layer 205 from the first opening OP1, a first trench T1 corresponding to the first opening OP1 may be formed in the interlayer insulating layer 205. When the first trench T1 is formed, the first mask layer PM1 may be removed from the interlayer insulating layer 205.

[0060] Reference Fig.12 , a second mask layer PM2 may be disposed on the upper surface of the interlayer insulating layer 205. The second mask layer PM2 may be a photomask. The second mask layer PM2 may include a first opening OP1 formed in the first trench T1 and a second opening OP2 formed separately from the first opening OP1. Similar to the first opening OP1, the second opening OP2 may be formed in a region where the plurality of semiconductor structures 230 are not disposed.

[0061] The width of each of the first openings OP1 included in the second mask layer PM2 may be smaller than the width of each of the first openings OP1 included in the first mask layer PM1. Fig.12 As shown in FIG. 1 , some portions of the first trenches T1 may be filled with the second mask layer PM2, and the width of each of the first trenches T1 may be reduced by the second mask layer PM2. In the second mask layer PM2, the width of each of the second openings OP2 may be greater than the width of each of the first openings OP1.

[0062] Reference Fig.13 , an etching process may be performed on the interlayer insulating layer 205 exposed in the first opening OP1 and the second opening OP2. By performing the etching process, the depth of each of the first trenches T1 corresponding to the first opening OP1 may be extended, and the second trenches T2 may be formed while removing the portion of the interlayer insulating layer 205 exposed in the second opening OP2.

[0063] The depth of each of the first trenches T1 may extend to a level at which the semiconductor substrate 201 may be exposed. Therefore, the interlayer insulating layer 205 may be completely removed through the first opening OP1, and the semiconductor substrate 201 may be exposed in the first trench T1. In the second opening OP2, only a portion of the interlayer insulating layer 205 may be removed, and therefore, the depth of each of the second trenches T2 may be formed to reach only a portion of the interlayer insulating layer 205. Therefore, in the second trenches T2, the semiconductor substrate 201 may not be exposed.

[0064] Reference Fig.14 , the semiconductor substrate 201 can be partially removed by additionally etching the first trench T1. Fig.14As shown in FIG. 1 , the first depth d1 of each of the first trenches T1 may be increased to a depth at which the semiconductor substrate 201 may be removed. Under certain process conditions, the semiconductor substrate 201 may have a relatively high etching selectivity relative to the interlayer insulating layer 205. Therefore, by selecting appropriate process conditions, when the semiconductor substrate 201 is removed from the first trenches T1, the interlayer insulating layer 205 exposed from the second opening OP2 may not be etched.

[0065] Fig.15 It is shown Fig.14 An enlarged view of region A is shown in FIG. Fig.15 , the width of each of the first trenches T1 may have a width that decreases toward the bottom surface. Therefore, in a region adjacent to the bottom surface of each of the first trenches T1, a cross-sectional surface of each of the first trenches T1 may appear to have a width that decreases toward the bottom surface. Fig.15 The curved shape shown in FIG.

[0066] Reference Fig.16 , the depth of each of the second trenches T2 may be extended by additionally etching the interlayer insulating layer 205 in the second opening OP2. The interlayer insulating layer 205 in the second opening OP2 may be etched until the semiconductor substrate 201 is exposed. As described in the aforementioned example embodiments, under certain process conditions, the interlayer insulating layer 205 may have a relatively high etching selectivity with respect to the semiconductor substrate 201. Therefore, when the interlayer insulating layer 205 is removed from the second opening OP2 by the etching process, the semiconductor substrate 201 exposed by the first opening OP1 and the first trench T1 may not be etched.

[0067] When the semiconductor substrate 201 is exposed in the second trench T2, the second mask layer PM2 may be removed. In addition, an etching process for removing the semiconductor substrate 201 exposed in the first trench T1 and the second trench T2 may be performed. Fig.17 In the example embodiment shown in FIG. 1 , a portion of the second mask layer PM2 may remain in a region adjacent to an upper portion of the first trench T1 , but example embodiments thereof are not limited thereto. The second mask layer PM2 may also be completely removed.

[0068] Reference Fig.17 , the semiconductor substrate 201 may be removed in the first trench T1 and the second trench T2. Therefore, the depth of each of the first trenches T1 may increase from the first depth d1 to the third depth d3, and each of the second trenches T2 may have a second depth d2. As an example, the second depth d2 and the third depth d3 may be less than the thickness of the semiconductor substrate 201. Therefore, the first trench T1 and the second trench T2 may not completely penetrate the semiconductor substrate 201.

[0069] Reference Fig.17By performing an etching process for extending the depths of the first trenches T1 and the second trenches T2, each of the first trenches T1 may be divided into an upper region having a relatively small width and a lower region having a relatively large width. Fig.15 In the aforementioned exemplary embodiments described, when executing the reference Fig.17 Before the described etching process, the point of the cross-sectional surface where the side surface of each of the first trenches T1 meets the bottom surface of the first trench T1 may have a curved shape. Therefore, when the etching process is performed, in example embodiments, a recess may be formed between the upper and lower regions of each of the first trenches T1.

[0070] A plurality of relief structures may be formed on the side surface of the lower region of each of the first trenches T1. This is because etching processes for respectively forming the upper region and the lower region of each of the first trenches T1 may be performed separately. The size of each of the relief structures formed on the side surface of the lower region and / or the number of relief structures may increase toward the upper region of each of the first trenches T1.

[0071] Reference Fig.18 , the first via structure 210 and the second via structure 220 may be formed by filling the first trench T1 and the second trench T2 with a conductive material. The first via structure 210 and the second via structure 220 may be formed of a material such as a metal, a metal compound, etc., and the shapes of the first via structure 210 and the second via structure 220 may correspond to the shapes of the first trench T1 and the second trench T2, respectively.

[0072] Reference Fig.19 , a grinding process may be applied to the semiconductor substrate 201 to expose the first via structure 210 and the second via structure 220. As an example, the grinding process may be a chemical mechanical polishing (CMP) process. The grinding process may be performed from the lower surface of the semiconductor substrate 201. The grinding process may be performed until the first via structure 210 and the second via structure 220 are completely exposed. Therefore, each of the first via structures 210 may have a height that is the same as or less than the third depth d3, and each of the second via structures 220 may have a height that is the same as or less than the second depth d2.

[0073] When the height of the first via structure 210 is different from the height of the second via structure 220, the time point at which the first via structure 210 is exposed by the grinding process performed from the lower surface of the semiconductor substrate 201 may be different from the time point at which the second via structure 220 is exposed. Additionally, a via structure having a longer height among the first via structure 210 and the second via structure 220 may be exposed earlier than other via structures. As an example, among the first via structure 210 and the second via structure 220, a via structure having a relatively larger width may be exposed earlier than other via structures.

[0074] Since the grinding process may need to be performed until all of the first via structures 210 and the second via structures 220 are exposed, the via structures exposed earlier than other via structures may be bent or broken due to the stress generated by the grinding process. By reducing the length difference between the first via structure 210 and the second via structure 220, the via structures 210 and 220 can be prevented from being bent or broken during the grinding process.

[0075] The greater the width difference between the first via structure 210 and the second via structure 220, the more the length difference between the first via structure 210 and the second via structure 220 increases. As an example, when each of the first via structures 210 has a constant width without significant change in the length direction like the width of the second via structure 220, the length difference between the first via structure 210 and the second via structure 220 increases.

[0076] In example embodiments, each of the first via structures 210 may be divided into a first region 211 and a second region 212 connected by a boundary surface 213. The first region 211 may extend from an upper surface of the interlayer insulating layer 205, and the second region 212 may extend from a lower surface of the semiconductor substrate 201. A width of the first region 211 exposed on the upper surface of the interlayer insulating layer 205 may be smaller than a width of the second region 212 exposed on the lower surface of the semiconductor substrate 201.

[0077] Among the processes for forming the first via structure 210, the etching process for removing the semiconductor substrate 201 can be divided into two processes. Figures 11 to 18 As described in the aforementioned example embodiments, the first trench T1 may be formed by etching the semiconductor substrate 201 to form the first via structure 210. The etching process for forming the first trench T1 may include a first etching process for removing a region corresponding to the first region 211 from the semiconductor substrate 201 and a second etching process for removing a region corresponding to the second region 212 from the semiconductor substrate 201.

[0078] Referring to the second etching process Fig.17 , both the region corresponding to the second region 212 and the region corresponding to the second via structure 220 can be removed from the semiconductor substrate 201. In other words, both the region corresponding to the second region 212 of each of the first via structures 210 and the region corresponding to the second via structure 220 can be removed from the semiconductor substrate 201 under the same etching conditions. Therefore, the difference between the depth d3 of each of the first trenches T1 corresponding to the first via structure 210 and the depth d2 of each of the second trenches T2 corresponding to the second via structure 220 can be significantly reduced.

[0079] Fig. 20 is a diagram illustrating a semiconductor package according to example embodiments.

[0080] Reference Fig. 20 , the semiconductor package 300 in the example embodiment may provide an image device. The semiconductor package 300 may include a first semiconductor device 310, a second semiconductor device 320, a third semiconductor device 330, and the like. The first semiconductor device 310, the second semiconductor device 320, and the third semiconductor device 330 may be stacked in a vertical direction. In an example embodiment, the first semiconductor device 310 and the second semiconductor device 320 may be stacked at a wafer level, and the third semiconductor device 330 may be attached to a lower portion of the second semiconductor device 320 at a chip level.

[0081] The first semiconductor device 310 may include a sensing area SA in which a plurality of pixels PX are arranged and a first pad area PA1 arranged around the sensing area SA. A plurality of via structures 311 may be provided in the first pad area PA1. The plurality of via structures 311 may penetrate the semiconductor substrate included in the first semiconductor device 310 and may be connected to a pad arranged in a second pad area PA2 of the second semiconductor device 320.

[0082] Each of the plurality of pixels PX included in the first semiconductor device 310 may include a photodiode receiving light and generating charges, a pixel circuit for processing the charges generated by the photodiode, etc. The pixel circuit may include a plurality of transistors for outputting voltages corresponding to the charges generated by the photodiode.

[0083] The control logic LC of the second semiconductor device 320 may provide a circuit (such as a clock driver, a readout circuit, a calculation circuit, a timing controller, an image processor, a power supply circuit, etc.) for driving the plurality of pixels PX arranged in the first semiconductor device 310. The plurality of circuits included in the control logic LC may be connected to the pixel circuit through the first pad area PA1 and the second pad area PA2. The control logic LC may obtain a reset voltage and a pixel voltage from the plurality of pixels PX, and may generate a pixel signal.

[0084] As an example, a plurality of pixels PX disposed in the first semiconductor device 310 may be electrically connected to a control logic LC disposed in the second semiconductor device 320 through a via structure 311 and a pad. The control logic LC may transmit data signals and power signals to the plurality of pixels PX, and may receive data signals and power signals from the plurality of pixels PX, and the via structure 311 may include a first via structure for transmitting a data signal and a second via structure for transmitting a power signal. As an example, the width of each of the first via structures may be smaller than the width of each of the second via structures.

[0085] In example embodiments, as described in the foregoing example embodiments, each of the first via structures may have a first region and a second region having different widths. The width of the second region may be greater than the width of the first region, and may be closer to the second semiconductor device 320 than the first region. Therefore, by significantly reducing the length difference between the first via structure and the second via structure, damage to the via structure 311 caused by a grinding process or other processes for exposing the first via structure and the second via structure may be reduced.

[0086] Fig.21 and Fig. 22 is a diagram illustrating a semiconductor package according to example embodiments.

[0087] Reference Fig.21 and Fig. 22 , the semiconductor packages 400 and 500 in example embodiments may be implemented as memory packages for storing data. Fig.21 and Fig. 22 The semiconductor packages 400 and 500 in the example embodiments shown in FIG. 4 may be implemented as a high bandwidth memory (HBM) device including a plurality of vertically stacked memory dies.

[0088] Reference Fig.21 , the semiconductor package 400 may include a plurality of vertically stacked memory dies 411 to 414 (410), a memory controller 420 controlling the memory dies 410, an interposer substrate 430, a package substrate 440, etc. If necessary, the number of vertically stacked memory dies 410 may be changed, and each of the memory dies 410 may include a microbump 415 and a via structure 416 for transmitting and receiving data signals and power signals. The memory die 410 may be mounted on the interposer substrate 430.

[0089] The memory controller 420 may control the memory die 410. For example, the memory controller 420 may store data in the memory die 410, or may read out data stored in the memory die 410. The memory controller 420 may be mounted on the interposer substrate 430, and may be connected to the internal wiring 436 of the interposer substrate 430 through the microbumps 425. Therefore, the memory controller 420 may be at the same level as the memory die 411 mounted on the interposer substrate 430.

[0090] The interposer substrate 430 may connect the memory die 410 , the memory controller 420 , and the package substrate 440 . The interposer substrate 430 may be connected to the package substrate 440 through micro bumps 435 , and may include internal wiring 436 connecting the memory die 410 , the memory controller 420 , and the package substrate 440 .

[0091] The package substrate 440 may include a bump 445, and may transmit and receive a data signal, a power signal, and the like to and from an external entity, such as the semiconductor package 400, the memory controller 420, and / or the memory die 410, through the interposer substrate 430. The size of the bump 445 disposed on the lower surface of the package substrate 440 may be larger than the size of each of the other micro bumps 415, 425, and 435 included in the semiconductor package 400.

[0092] The memory die 410 may transmit and receive data signals and power signals to and from the memory controller 420, the interposer substrate 430, or the package substrate 440 through the via structure 416. The via structure 416 may include a first via structure provided as a transmission path for the data signal and a second via structure provided as a transmission path for the power signal.

[0093] As an example, the first via structure and the second via structure may have different shapes, different sizes, and other different characteristics. Each of the first via structures may be smaller than each of the second via structures, as shown in FIG. Figures 1 to 19 In the aforementioned exemplary embodiments described above, each of the first via structures may include a first region and a second region having different widths. Therefore, by significantly reducing the length difference that occurs in the process of forming the via structure 416, the bending or breaking of the via structure 416 that occurs in the grinding process for exposing the via structure 416 can be significantly reduced.

[0094] Reference Fig. 22, the semiconductor package 500 may include a memory controller 510, a plurality of memory dies 521 to 524 (520) stacked on the memory controller 510, a package substrate 530, etc. If necessary, the number of the plurality of memory dies 520 may be changed, and each of the memory dies 520 may include a micro bump 525 and a via structure 526 for sending and receiving data and power signals.

[0095] The memory controller 510 may be directly mounted on the package substrate 530 through the bumps 515. The memory controller 510 may transmit and receive data signals and power signals to and from an external entity through the package substrate 530, and may control the operation of the memory die 520. The memory controller 510 may include a via structure 516 for ensuring electrical connection with the memory die 520 and the package substrate 530. At least some portions of the via structure 516 may penetrate the memory controller 510.

[0096] The via structures 516 and 526 arranged in the memory controller 510 and the memory die 520 may include a first via structure providing a transmission path for a data signal and a second via structure providing a transmission path for a power signal. Fig.21 In the aforementioned example embodiments described, the shape and / or size of each of the first via structures may be different from the shape and / or size of each of the second via structures. The first via structure and the second via structure may be configured to transmit different signals, for example, the first via structure may be configured to transmit a data signal, and the second via structure may be configured to transmit a power signal. As an example, the profile of the side surface of the first via structure may be different from the profile of the side surface of the second via structure. Each of the first via structures may include a first region and a second region having different widths, and the recess in which the minimum width occurs may be formed at the boundary surface between the first region and the second region or near the boundary surface between the first region and the second region. The side surface of the second region may have a curvature formed by a relief structure in a region adjacent to the boundary surface between the first region and the second region.

[0097] Fig.23 and Fig.24 is a diagram illustrating a semiconductor package according to example embodiments.

[0098] exist Fig.23 and Fig.24 In the example embodiment shown in FIG. 6 , semiconductor packages 600 and 700 may be implemented as a high bandwidth memory device. Fig.23 and Fig.24In the example embodiment shown in , the semiconductor packages 600 and 700 may include two or more channels each having an independent interface, thereby having an increased bandwidth. Fig.23 , the semiconductor package 600 may include a plurality of memory dies 621 to 624 (620), and a memory controller 610 controlling the memory dies 620 may be stacked with the memory dies 620. The number of the memory dies 620 may be changed in example embodiments.

[0099] Each of the memory dies 620 may include a plurality of memory banks 625 and may include one or more channels. Fig.23 In the example embodiment shown in FIG. 6 , each of the memory dies 620 may include two channels, and thus, the semiconductor package 600 may include eight channels CH1 to CH8 .

[0100] The memory controller 610 may store data in the memory die 620, or may read out data stored in the memory die 620 based on a control command, address information, etc. received from an external entity. The memory controller 610 may be connected to the memory die 620 through a plurality of via structures 630 and 640. The number of via structures 630 and 640 may be changed according to the number of channels CH1 to CH8 and the bandwidth of each of the channels CH1 to CH8. As an example, when the bandwidth of each of the channels CH1 to CH8 is 128 bits, the via structures 630 and 640 may be configured to transmit 1024 bits of data.

[0101] The via structures 630 and 640 may include a first via structure 630 and a second via structure 640 having different widths. The width of each of the first via structures 630 may be relatively smaller than the width of each of the second via structures 640. As an example, the first via structure 630 may be set as a transmission path for a data signal, and the second via structure 640 may be set as a transmission path for a power signal. Fig.23 In the example embodiment shown in FIG. 6 , the first via structure 630 may be disposed between the second via structures 640 , but example embodiments thereof are not limited thereto. The arrangement form of the via structures 630 and 640 may be changed.

[0102] Each of the first via structures 630 in each of the memory dies 620 may be divided into a first region and a second region in the length direction. The width of the first region may be smaller than the width of the second region. Figures 1 to 19In the aforementioned example embodiments described, when the first via structure 630 is configured to include the first region and the second region, the length difference that occurs in the process for forming the via structures 630 and 640 can be significantly reduced. Therefore, the curling and / or breaking of the via structures 630 and 640 that occurs in the grinding process for exposing the via structures 630 and 640 can be significantly reduced.

[0103] Reference Fig.24 , the semiconductor package 700 may include a plurality of memory dies 721 to 724 ( 720 ), and a memory controller 710 controlling the memory dies 720 may be stacked with the memory dies 720 . Fig.24 The operation of the semiconductor package 700 in the example embodiment shown in FIG. Fig.23 The operation of the semiconductor package 600 in the example embodiment shown in FIG. 1 is similar.

[0104] exist Fig.24 In the example embodiment shown in FIG. 1 , however, the second via structure 740 provided as a transmission path for a power signal may be separated from the first via structure 730 provided as a transmission path for a data signal. Fig.24 , the second via structure 740 may be disposed between the memory banks 725 corresponding to the channels CH1 to CH8, respectively. Figures 1 to 19 The foregoing example embodiments are described to understand the shape and size of each of the first via structure 730 and the second via structure 740 .

[0105] According to the aforementioned example embodiments, the semiconductor device may include a first via structure and a second via structure, and the first via structure may include a first region and a second region having different widths. The width of the first region of the first via structure on the first surface of the semiconductor device may be smaller than the width of the second via structure. By configuring the first via structure to include the first region and the second region, the length difference between the first via structure and the second via structure may be reduced. As a result, the stress and strain on the via structure during the grinding process may be reduced, thereby also reducing or preventing the breakage of the via structure. By preventing the breakage of the via structure, the product of the semiconductor device may have improved reliability and improved yield.

[0106] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, include: Semiconductor substrate; at least one semiconductor structure; an interlayer insulating layer, which is disposed on the semiconductor substrate and the semiconductor structure; at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, the first via structure comprising a first region and a second region, the first region having a first width on an upper surface of the interlayer insulating layer, the second region extending from the first region and having a second width on a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary surface between the first region and the second region; and at least one second via structure, which penetrates the semiconductor substrate and the interlayer insulating layer and has a third width greater than the first width on the upper surface of the interlayer insulating layer, Wherein, the boundary surface is located in the semiconductor substrate.

2. The semiconductor device according to claim 1, in, The first width is smaller than the second width.

3. The semiconductor device according to claim 1, in, At least a portion of the second region has a width that increases from the boundary surface.

4. The semiconductor device according to claim 1, in, At least a portion of the first region has a width that increases from the boundary surface.

5. The semiconductor device according to claim 1, in, A side surface of the second region has a curved shape in a region adjacent to the boundary surface.

6. The semiconductor device according to claim 5, in, A side surface of the second region has a relief structure.

7. The semiconductor device according to claim 1, in, The at least one first via structure and the at least one second via structure are configured to transmit different signals.

8. The semiconductor device according to claim 7, in, The at least one first via structure is configured to transmit a data signal, and the at least one second via structure is configured to transmit a power signal.

9. The semiconductor device according to claim 1, in, A side surface of the at least one first via structure and a side surface of the at least one second via structure have different profiles.

10. The semiconductor device according to claim 1, in, The length of the at least one first via structure is the same as the length of the at least one second via structure.

11. The semiconductor device according to claim 1, in, The third width is smaller than the second width.

12. The semiconductor device according to claim 1, in, The third width is greater than the second width.

13. A semiconductor package, include: a first semiconductor device; as well as a second semiconductor device stacked with the first semiconductor device, The first semiconductor device includes a semiconductor substrate, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer, and The at least one first via structure includes a first region and a second region, the first region has a first width on the upper surface of the interlayer insulating layer, the second region has a second width on the lower surface of the semiconductor substrate, and the width of the boundary surface between the first region and the second region is smaller than the first width, wherein the boundary surface is located in the semiconductor substrate, Wherein, a third width of the at least one second via structure is greater than the first width.

14. The semiconductor package according to claim 13, in, The first semiconductor device and the second semiconductor device are mounted on a package substrate, and the first semiconductor device includes at least one memory die configured to store data.

15. The semiconductor package according to claim 14, in, The second semiconductor device includes at least one memory die configured to store data, and The semiconductor package further includes a memory controller mounted on the package substrate at the same level as that of the second semiconductor device, and the memory controller is configured to control the first semiconductor device and the second semiconductor device.

16. The semiconductor package according to claim 14, in, The second semiconductor device includes a memory controller configured to control the first semiconductor device.

17. The semiconductor package according to claim 14, in, The at least one first via structure is located in the first region of the first semiconductor device, and the at least one first via structure is configured to transmit a data signal, and The at least one second via structure is located in a second region of the first semiconductor device, the second region of the first semiconductor device is separated from the first region of the first semiconductor device, and the at least one second via structure is configured to transmit a power signal.

18. A semiconductor package, include: Package substrate; a plurality of memory dies mounted on the package substrate, the plurality of memory dies including memory cells configured to store data, and the plurality of memory dies being stacked in a direction perpendicular to an upper surface of the package substrate; a first via structure penetrating the plurality of memory dies and configured to provide a transmission path for a data signal; as well as a second via structure penetrating the plurality of memory dies and configured to provide a transmission path for a power signal, wherein the difference between the maximum width and the minimum width of the first via structure is smaller than the difference between the maximum width and the minimum width of the second via structure, and Wherein, the minimum width of the first via structure is smaller than the minimum width of the second via structure.

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