A lock detection circuit for clock data recovery circuit

Abstract

The present invention discloses a lock detection circuit for a clock data recovery circuit, which outputs a voting result value, including: an accumulator, a delayer, a trigger and a comparator, wherein one input end of the accumulator receives the voting result value, and the other input end is connected to the output end of the delayer; the output end of the accumulator is connected to the input end of the delayer and the first input end of the trigger; the second input end of the trigger receives an external clock data recovery circuit loop sampling clock; the output end of the trigger is connected to the first input end of the comparator, and the second input end of the comparator receives the judgment threshold of the lock detection circuit. When the input of the present invention is a data signal, it can effectively judge whether the circuit is locked or unlocked.

Description

Technical Field

[0001] The invention relates to a lock detection circuit of a clock data recovery circuit. Background Art

[0002] With the development of information technology, people have higher and higher requirements for the speed of data transmission and exchange. Various interface bus specifications have emerged, from USB3, USB3.1, (USB: universal series bus is a serial bus standard for connecting computers and peripherals) to PCIE (peripheral component interconnect, peripheral interconnection standard), SATA (serial advanced technology attachment, that is, serial hardware interface standard), etc. Interface technology has also changed from the initial parallel to serial. High-speed serial circuits often use the receiver's clock recovery circuit to recover the clock from the received data (clock data recovery: CDR for short). In practical applications, there are usually two methods: the first is to use the Analog CDR (analog circuit design clock recovery) circuit method; in addition, in order to make the CDR system easy to transplant to other systems, Bang-Bang CDR (positive and negative control clock recovery circuit) is also often used.

[0003] The Bang-Bang CDR circuit structure is as follows Figure 2 , a dual-loop structure is applied. It consists of the following main modules: Bang-Bang phase detector (BBPD), voting device (Voting), proportional path and integral path (Kp and Ki), digital phase converter (DPC). The normal working mode is to let the CDR work and wait for a period of time. When the time is up, the subsequent digital circuits continue to work, otherwise the CDR is assumed to be in the capture state. To be on the safe side, this waiting working mode usually takes much longer than the time required for real locking, greatly compressing the working time of the subsequent digital circuits. Figure 2In the figure, clk: sampling clock of clock data recovery circuit; lock-threshold: judgment threshold of lock detection circuit; cdr-lock: output of lock detection circuit; PI-I: clock with phase 0 degree output by phase interpolator; PI-Q: clock with phase 90 degree output by phase interpolator; PI-IB: clock with phase 180 degree output by phase interpolator; PI-QB: clock with phase 270 degree output by phase interpolator; qdata: output of data deserialized by clocks of PI-I and PI-IB; idata: output of data deserialized by clocks of PI-Q and PI-QB; UP: value before sampling point of clock after phase detector; DN: value after sampling point of clock after phase detector; voteout: voting result of UP and DN after voting algorithm; Up-path: proportional circuit, amplifies or reduces input signal; Ui-path: integration circuit, integrates input signal; 1 / Z: delay circuit.

[0004] The traditional PLL lock detector circuit determines whether the circuit is locked or unlocked by comparing the reference (input reference) clock with the divided signal of the VCO (voltage control oscillator). If the frequency difference is within an acceptable range, it is considered locked. However, for the case where the input is data instead of clock, the traditional PLL lock detector cannot work properly because the input data signal is irregular and the sampling signal is a clock signal. Summary of the invention

[0005] The object of the present invention is to provide a lock detection circuit for a clock data recovery circuit, which can effectively determine whether the circuit is locked or unlocked when the input is a data signal.

[0006] The technical solution to achieve the above purpose is:

[0007] A lock detection circuit for a clock data recovery circuit, the clock data recovery circuit outputs a voting result value, including: an accumulator, a delay, a trigger and a comparator, wherein:

[0008] One input end of the accumulator receives the voting result value, and the other input end is connected to the output end of the delayer;

[0009] The output end of the accumulator is connected to the input end of the delay device and the first input end of the trigger;

[0010] The second input end of the trigger receives an external clock data recovery circuit loop sampling clock;

[0011] The output terminal of the trigger is connected to the first input terminal of the comparator, and the second input terminal of the comparator receives the judgment threshold of the lock detection circuit.

[0012] Preferably, the clock data recovery circuit includes a positive and negative control phase detector, a voter, a phase interpolator and a deserialization circuit;

[0013] The phase interpolator outputs clocks with phases of 0 degree, 90 degree, 180 degree and 270 degree respectively;

[0014] The 0-degree clock and the 180-degree clock are deserialized and output through the deserialization circuit, and the 90-degree clock and the 270-degree clock are deserialized and output through the deserialization circuit. After the positive and negative control phase detector, the values ​​before and after the sampling points of the clock are obtained.

[0015] The values ​​before the sampling point and the values ​​after the sampling point of the clock are passed through the voting device to obtain the voting result value.

[0016] Preferably, the accumulator adds the voting result value and the output value from the delay device and then outputs the result;

[0017] The output value of the delayer is the output value of the accumulator delayed by one clock cycle;

[0018] The trigger receives the output value of the accumulator and the loop sampling clock of the clock data recovery circuit, and outputs the accumulated value;

[0019] The comparator compares the accumulated value with the judgment threshold of the lock detection circuit and outputs a lock state signal.

[0020] The beneficial effects of the present invention are as follows: according to the characteristic of Bang-Bang CDR entering the locked state, that is, after the CDR enters the locked state, the sampling of the data edge by the clock is in a state of regular left and right jitter, so that the accumulated values ​​after voting are in a relatively stable state, by accumulating the values ​​after voting in a period of time, if it is stable and less than the set threshold, the system considers it to be locked, otherwise it is determined to be unlocked. The present invention can correctly judge the working state of the CDR and reasonably guide the subsequent circuit work. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a circuit diagram of a lock detection circuit for a clock data recovery circuit of the present invention;

[0022] Figure 2 It is a circuit diagram of a positive and negative control clock recovery circuit in the prior art;

[0023] Figure 3It is a schematic diagram of correctly judging the locking state of the locking detection circuit in the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with the accompanying drawings.

[0025] See also Figure 1 The lock detection circuit for the clock data recovery circuit of the present invention, the clock data recovery circuit outputs the voting result value, includes: an accumulator 1, a delay 2, a trigger 3 and a comparator 4.

[0026] One input of the accumulator 1 receives the voting result value, and the other input is connected to the output of the delayer 2. The output of the accumulator 1 is connected to the input of the delayer 2 and the first input of the trigger 3. The second input of the trigger 3 receives the external clock data recovery circuit loop sampling clock. The output of the trigger 3 is connected to the first input of the comparator 4, and the second input of the comparator 4 receives the judgment threshold of the lock detection circuit.

[0027] Accumulator 1 adds the voting result value and the output value from delayer 2 and outputs the result; the output value of delayer 2 is the output value of accumulator 1 delayed by one clock cycle; trigger 3 receives the output value of accumulator 1 and the sampling clock of the clock data recovery circuit loop, and outputs the accumulated value; comparator 4 compares the accumulated value with the judgment threshold of the lock detection circuit, and outputs a lock state signal.

[0028] Figure 1 In the figure, clk: the sampling clock of the clock data recovery circuit loop. voteout: the voting result value. sum: the sum of the voting result value and sum-d. sum-d: sum delayed by one clock cycle. sum-new: the accumulated value of the trigger output, that is, the output of the accumulator after being resampled by the clock. lock-threshold: the judgment threshold of the lock detection circuit. lock-state: the output of the lock detection circuit.

[0029] The clock data recovery circuit includes a positive and negative control phase detector, a voting device, a phase interpolator and a deserialization circuit; the phase interpolator outputs clocks with phases of 0, 90, 180 and 270 degrees respectively. The 0-degree clock and the 180-degree clock are deserialized and output through the deserialization circuit, and the 90-degree clock and the 270-degree clock are deserialized and output through the deserialization circuit. After passing through the positive and negative control phase detector, the values ​​before the sampling point and the values ​​after the sampling point of the clock are obtained. After passing through the voting device, the values ​​before the sampling point and the values ​​after the sampling point of the clock are obtained. The voting result value.

[0030] The present invention is based on the characteristics of Bang-Bang CDR entering the locked state: after the CDR enters the locked state, the sampling of the clock for the data edge is in a state of regular left and right jitter, so that the accumulated values ​​after voting are in a relatively stable state. Therefore, the values ​​after voting in a period of time are accumulated. If the accumulated value is stable and less than the judgment threshold of the set lock detection circuit, the system considers it locked. Otherwise, it is judged as unlocked.

[0031] When the CDR circuit starts working normally, it continuously calculates the sum of phase path (i.e. proportional path) up / down (up means that the clock lags behind the data and needs to be moved forward, and down means that the clock is ahead of the data and needs to be moved backward) within a time window to determine whether the sum is less than the threshold. This approach is based on the fact that after the CDR is locked, the integral value of the phase path should be close to 0, and the integral value of the CDR should be relatively large when it is in the locking process. The digital part is made into a state machine to control the specific locking process and loss of lock judgment. Loss of lock should not be determined once the accumulator exceeds the threshold, but it should be detected multiple times before loss of lock, otherwise it is easy to make a misjudgment. The same is true for the determination of the lock state. Generally, it is determined to be locked when the accumulator is less than the threshold in several consecutive tests. When designing, these two values ​​are set separately according to different data rates, and try to find a set of suitable values ​​that can cover different data rates. If the accumulator is saturated during the judgment process and in the window period we set, there are two ways to deal with it. One is to maintain the state and wait for the next time window to arrive, and the other is to restart the determination of the lock state.

[0032] Figure 3 This is a schematic diagram of the lock detection circuit for correctly judging the lock state.

[0033] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Those skilled in the relevant technical field may make various changes or modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions should also belong to the scope of the present invention and should be defined by the claims.

Claims

1. A lock detection circuit for a clock data recovery circuit, the clock data recovery circuit outputting a voting result value, characterized in that: include: Accumulators, delays, flip-flops, and comparators, where One input end of the accumulator receives the voting result value, and the other input end is connected to the output end of the delayer; The output end of the accumulator is connected to the input end of the delay device and the first input end of the trigger; The second input end of the trigger receives an external clock data recovery circuit loop sampling clock; The output terminal of the trigger is connected to the first input terminal of the comparator, and the second input terminal of the comparator receives the judgment threshold of the lock detection circuit.

2. The lock detection circuit for a clock data recovery circuit according to claim 1, characterized in that: The clock data recovery circuit includes a positive and negative control phase detector, a voting device, a phase interpolator and a deserialization circuit; The phase interpolator outputs clocks with phases of 0 degree, 90 degree, 180 degree and 270 degree respectively; The 0-degree clock and the 180-degree clock are deserialized and output through the deserialization circuit, and the 90-degree clock and the 270-degree clock are deserialized and output through the deserialization circuit. After the positive and negative control phase detector, the values ​​before and after the sampling points of the clock are obtained. The values ​​before the sampling point and the values ​​after the sampling point of the clock are passed through the voting device to obtain the voting result value.

3. The lock detection circuit for a clock data recovery circuit according to claim 1, characterized in that: The accumulator adds the voting result value and the output value from the delay device and outputs the result; The output value of the delayer is the output value of the accumulator delayed by one clock cycle; The trigger receives the output value of the accumulator and the loop sampling clock of the clock data recovery circuit, and outputs the accumulated value; The comparator compares the accumulated value with the judgment threshold of the lock detection circuit and outputs a lock state signal.

Images