A full-chip rapid simulation method for a negative-tone lithography process, a negative-tone photoresist model, an OPC model, and an electronic device

Abstract

The invention relates to the field of integrated circuit lithography technology, and particularly relates to a full-chip rapid simulation method for negative development lithography process, a negative development photoresist model, an OPC model and an electronic device. A full-chip rapid simulation method for negative development lithography process analyzes the deformation of photoresist based on elasticity mechanics, sets one of stress and strain as the equivalent of the deformation amount of photoresist to obtain an equivalent equation, selects a Taylor expansion formula to approximately calculate the equivalent equation to obtain an approximate value of stress or strain, adjusts the light field distribution according to the approximate value to obtain a suitable acid concentration distribution, so that the exposed pattern is closest to the target pattern, can well analyze the deformation of photoresist during the thermal shrinkage effect, improves the accuracy in the lithography calculation process, and at the same time, uses the Taylor expansion formula to fit the thermal shrinkage effect, improves the calculation speed, and therefore, solves the problem of complex calculation of the full-chip negative development lithography process.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit lithography technology, and particularly to a full-chip fast simulation method for negative development lithography process, a negative development photoresist model, an OPC model and an electronic device.

Background Art

[0002] The lithography process is the most important manufacturing process in the modern ultra-large scale integrated circuit manufacturing process, that is, an important means to transfer the design pattern of the integrated circuit on the mask to the silicon wafer through a lithography machine. As the feature size gradually shrinks, the available process window for manufacturing becomes smaller and smaller. The entire lithography process needs to be precisely controlled, and the requirement for the accuracy of computational lithography is also getting higher and higher. An accurate computational lithography model can theoretically explore ways to increase the lithography resolution and process window, and guide the optimization of process parameters.

[0003] Currently, the more advanced photoresist technologies are all negative development. The negative development technology is different from the positive development technology in the modeling process. In the positive development technology, the deformation of the photoresist mainly depends on the distribution of acid after the photoresist undergoes a light reaction, that is, the distribution of the light field. Since the imaging optical simulation process of computational lithography can be calculated more accurately based on the physical imaging model, it is easy to obtain relatively accurate results for the modeling of positive development photoresists. In the negative development photoresist, due to the thermal shrinkage effect of the photoresist during the post-baking process, the photoresist will generate additional deformation beyond the light field distribution, and this part of the deformation is very difficult to capture. At the same time, this effect is very important for the modeling of negative development photoresists. For a full chip, the size of a chip can reach up to 32mm * 26mm at most, the line width of the smallest pattern may be only 10nm, and the layout file of a lithography layer can reach hundreds of GB. Therefore, the model speed is also a very critical technical indicator. Therefore, a model that takes into account both accuracy and speed is needed to simulate the negative development photoresist.

Summary of the Invention

[0004] To overcome the defects of poor accuracy and low optimization speed in simulating the negative development photoresist in the existing lithography technology, the present invention provides a full-chip fast simulation method for negative development lithography process, a negative development photoresist model, an OPC model and an electronic device.

[0005] To solve the above technical problems, the present invention provides a full-chip rapid simulation method for a negative development lithography process, including the following steps: S1. Obtain the light field distribution of the photoresist through an optical model, set the light field distribution as E(x, y), and set the distribution of the acid concentration in the photoresist as a function of the light field distribution, that is, S(x, y) = F(E(x, y)); S2. Set the thermal shrinkage effect of the photoresist during post-baking as elastic deformation, analyze the elastic deformation of the photoresist based on elasticity mechanics, set one of the stress and strain as the equivalent of the deformation amount of the photoresist to obtain an equivalent equation, and the equivalent equation is a differential equation; and S3. Select a Taylor expansion to approximately calculate the equivalent equation to obtain an approximate value of the stress or strain, and adjust the light field distribution according to the approximate value to obtain a suitable acid concentration distribution.

[0006] Preferably, according to the continuity assumption, the elastic body remains a continuous body before and after deformation. Assume that a point in the elastic body moves from position M(x, y, z) to M'(x', y', z') during the deformation process, and this process is a continuous process. All displacements satisfy the equation:

[0007]

[0008] where u(x, y, z) = x'(x, y, z) - x, v(x, y, z) = y'(x, y, z) - y, w(x, y, z) = z'(x, y, z) - z, and u, v, and w respectively correspond to the displacements in the x, y, and z directions. The photoresist can be called an elastic body;

[0009] In the above step S2, the obtaining of the equivalent equation includes the following steps: S21. The external force is correlated with the stress through the equilibrium equation, the stress is correlated with the strain through the physical equation, and the strain is correlated with the displacement through the geometric equation; and S22. Based on the relatively thin thickness dimension of the photoresist, set the photoresist as a plane, so as to simplify the equilibrium equation, the physical equation, and the geometric equation.

[0010] Preferably, an equivalent equation regarding the correlation between strain and displacement is obtained based on the simplified geometric equation.

[0011] Preferably, the symbol definitions involved in the following formulas are all consistent with the definitions in elasticity mechanics, so they will not be defined one by one; in the above step S22, when setting the photoresist as a plane, set σ z = 0, = 0, = 0, w = 0; it can be deduced that the stress components are

[0012]

[0013] The strain components are

[0014]

[0015] The simplified equilibrium equations are as follows:

[0016]

[0017] The simplified geometric equations are as follows:

[0018]

[0019] wherein, σ x , σ y , σ z correspond to the normal stresses in the x-direction, y-direction and z-direction respectively; represents the shear stress in the y-direction on the x-plane, represents the shear stress in the x-direction on the z-plane, represents the shear stress in the y-direction on the z-plane, represents the shear stress in the x-direction on the y-plane; ε x , ε y correspond to the strain components in the x-direction and y-direction respectively.

[0020] Preferably, the equivalent equation is as follows:

[0021]

[0022] Preferably, the Taylor expansion similar to the equivalent equation is as follows,

[0023]

[0024] where: 0 < θ < 1, h and k are constants.

[0025] To solve the above technical problems, the present invention further provides an electronic device, which includes one or more processors; a storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors implement any one of the methods described above.

[0026] Compared with the prior art, by analyzing the deformation of the photoresist based on elasticity mechanics, setting one of the stress and strain as the equivalent of the deformation amount of the photoresist to obtain an equivalent equation, and using the Taylor expansion to approximately calculate the equivalent equation to obtain an approximate value of the stress or strain, adjusting the light field distribution according to the approximate value to obtain a suitable acid concentration distribution, so that the exposed pattern is closest to the target pattern, it can well analyze the deformation of the photoresist during the thermal shrinkage effect, improve the accuracy in the photolithography calculation process. At the same time, using the Taylor expansion to fit the thermal shrinkage effect improves the calculation speed. Therefore, the problem of complex calculation in the full-chip negative development photolithography process is solved.

[0027] Based on the fact that the thickness dimension of the photoresist is relatively thin, the photoresist is set as a plane, thereby simplifying the equilibrium equation, the physical equation, and the geometric equation, so that the simplified equivalent equation and the Taylor expansion have great similarity. Therefore, it is not necessary to perform differential solution on the equivalent equation, which can well improve the calculation speed and at the same time ensure the accuracy well.

[0028] The negative development photoresist model, OPC model, and electronic device provided by the present invention also have the beneficial effects as described above.

Description of the Drawings

[0029] Figure 1 is a flowchart of a full-chip fast simulation method for a negative development photolithography process provided in the first embodiment of the present invention;

[0030] Figure 2 is a schematic diagram of a differential unit body corresponding to the photoresist in the present invention;

[0031] Figure 3 is a detailed flowchart of step S2 in the full-chip fast simulation method for a negative development photolithography process provided in the first embodiment of the present invention;

[0032] Figure 4 is a schematic diagram of the initial light field distribution in the negative development photoresist model provided in the second embodiment of the present invention;

[0033] Figure 5 is a schematic diagram of the light field distribution after optimizing the initial light field distribution in the negative development photoresist model provided in the second embodiment of the present invention;

[0034] Figure 6A is a schematic diagram of a set of measurement points A used for fitting in the OPC model provided in the third embodiment of the present invention;

[0035] Figure 6B is a schematic diagram of a set of measurement points B used for fitting in the OPC model provided in the third embodiment of the present invention;

[0036] Figure 6CIt is a schematic diagram of group C measurement points used for OPC model fitting provided by the third embodiment of the present invention;

[0037] Figure 6D It is a schematic diagram of group D measurement points used for OPC model fitting provided by the third embodiment of the present invention;

[0038] Figure 6E It is a schematic diagram of group E measurement points used for OPC model fitting provided by the third embodiment of the present invention;

[0039] Figure 7 It is a columnar comparison chart of the root mean square obtained from group A - group E used for OPC model fitting provided by the third embodiment of the present invention;

[0040] Figure 8 It is a module schematic diagram of an electronic device provided in the fourth embodiment of the present invention;

[0041] Figure 9 It is a schematic structural diagram of a computer system of a server suitable for implementing the embodiments of the present invention.

Detailed implementation manners

[0042] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific implementation examples described herein are only used to explain the present invention and are not used to limit the present invention.

[0043] Please refer to Figure 1 , the first embodiment of the present invention provides a full-chip fast simulation method for negative-tone lithography process, including the following steps:

[0044] S1. Obtain the light field distribution of the photoresist through an optical model, set the light field distribution as E(x, y), and set the distribution of the acid concentration in the photoresist as a function of the light field distribution, that is, S(x, y) = F(E(x, y)).

[0045] In this step, the negative development technique is an image inversion development technique, which is the opposite of the traditional development technique. By using a special organic solvent for development, a negative image can be obtained by means of a traditional positive photoresist. The photoresist composition used in this technique contains a resin and a photoacid generator. Among them, the resin structure has acid-labile or acid-cleavable organic groups. During the post-exposure bake, in the exposed area, under the action of the acid generated by the photoacid generator upon exposure to light, the unstable groups or acid-cleavable groups in the resin break, changing from hydrophobic to hydrophilic, thereby reducing its solubility in the organic solvent. While the unexposed part still retains the property of high solubility in the organic solvent, so it can be removed by the developer made of the organic solvent during the development process. Therefore, contrary to the dissolution of the exposed part during the development of the traditional positive photoresist, in this technique, the unexposed part of the positive photoresist is dissolved during development, and the exposed part is retained.

[0046] Therefore, it can be known that the image distribution and shape after exposure are directly related to the distribution of the acid, and the distribution of the acid is directly related to the distribution of the light field. Therefore, the distribution of the acid concentration in the photoresist is set as a function of the light field distribution. During the process of fabricating the chip, adjusting the parameters of the light field distribution accordingly can adjust the quality of the corresponding exposed image.

[0047] Please refer to again Figure 1 , the full-chip rapid simulation method for the negative development lithography process further includes the following steps:

[0048] S2. Set the thermal shrinkage effect of the photoresist during the post-bake as an elastic deformation, analyze the elastic deformation of the photoresist based on elasticity mechanics, set one of the stress and strain as the equivalent of the photoresist deformation amount to obtain an equivalent equation, and the equivalent equation is a differential equation.

[0049] In this step, the photoresist is usually a resin material including polymers, which has a certain elasticity. Therefore, the photoresist can be set as an elastomeric material with a certain elasticity, so as to set the thermal shrinkage effect of the photoresist during the post-bake as an elastic deformation. Analyze the elastic deformation of the photoresist based on elasticity mechanics, and feedback and adjust the light field distribution according to the analysis results to obtain a suitable acid concentration distribution, so as to obtain an exposed image that meets the requirements.

[0050] During the specific analysis process, one of the stress and strain can be set as the equivalent of the photoresist deformation amount to obtain an equivalent equation.

[0051] Please refer to Figure 2 , during the specific analysis process, the photoresist can be divided into several differential unit bodies. According to the elasticity mechanics analysis, each differential unit body has three normal stresses σ x , σ y , σ z , and six shear stresses , , , , , , where the direction of the normal stress is determined by the normal direction, and the first subscript of the shear stress represents the acting surface and the second subscript represents the acting direction. The symbols for normal stress and shear stress are consistent with the symbol definitions in the textbook of elasticity theory. The index symbols for elasticity theory that appear below are also consistent with the definitions in the textbook of elasticity theory. Therefore, no further explanation will be given.

[0052] According to the theorem of shear stress reciprocity, we have , , .

[0053] Therefore, the shear stress will no longer distinguish which is the acting surface and which is the acting component, and the stress components

[0054]

[0055] Due to the deformation of the differential element, the differential element will produce normal strain and shear strain. Among them, the elongation and shortening of the edges of the differential element are normal strains, and the changes in the angles between the edges are shear strains. Therefore, three normal strain components, ε x , ε y , ε z , and three shear strain components, , λ yz , , can be obtained as follows:

[0056]

[0057] The strain in elasticity theory is usually called displacement. According to the continuity assumption, the differential element, that is, the elastic body, remains a continuous body before and after deformation. Assume that a point in the elastic body moves from M(x, y, z) to M'(x', y', z') during the deformation process. This process is a continuous process, and all displacements satisfy the equations:

[0058]

[0059] where u(x, y, z) = x'(x, y, z) - x, v(x, y, z) = y'(x, y, z) - y, w(x, y, z) = z'(x, y, z) - z. Among them, u, v, and w correspond to the displacements in the x, y, and z directions respectively, and the photoresist can be called an elastic body.

[0060] Please refer to Figure 3 , in the above step S2, the obtaining of the equivalent equation includes the following steps:

[0061] S21. The external force is correlated with stress through the equilibrium equation, stress is correlated with strain through the physical equation, and strain is correlated with displacement through the geometric equation; and

[0062] S22. Based on the relatively thin thickness of the photoresist, the photoresist is set as a plane, thereby simplifying the equilibrium equation, the physical equation, and the geometric equation.

[0063] In the above step S21, in elasticity mechanics, the external force can be correlated with stress through the equilibrium equation, stress can be correlated with strain through the physical equation, and strain can be correlated with displacement through the geometric equation.

[0064] Among them, the equilibrium equation is:

[0065]

[0066]

[0067] The physical equation is:

[0068]

[0069] The geometric equation is:

[0070]

[0071] In the above step S22, due to the relatively thin thickness of the photoresist, generally only about 100 nm, it can be assumed that the photoresist is a plane, which can simplify the solution process and improve the calculation speed.

[0072] When the photoresist is set as a plane, there is σ z = 0, = 0, = 0, w = 0, so the above equations will be simplified, and u, v are only functions of x, y. The stress components can be derived as:

[0073]

[0074] The strain components are:

[0075]

[0076] The equilibrium equation and the geometric equation are also simplified:

[0077] Among them, the equilibrium equation is:

[0078]

[0079] The geometric equations are as follows:

[0080]

[0081] Since what we are concerned about is the elastic deformation of the photoresist, by analyzing the elastic deformation amount, the distribution regarding the square is adjusted, thereby regulating the distribution of the acid concentration. In order to analyze the elastic deformation amount, so we choose to analyze either the stress or the strain.

[0082] The following first provides the analysis process for analyzing the strain. After the photoresist is planarized, the strain components received by a certain differential element at a certain point are: ε x and ε y , and the total strain ε is the superposition of the strains ε x and ε y in the x - direction and y - direction, specifically as follows:

[0083] According to the simplified formula, the correlation formula between the strain of the differential element and the displacement can be obtained, that is, the corresponding equivalent equation is as follows:

[0084]

[0085] In the actual application process, the displacement variable can be calculated by combining the image data after exposure with the parameters of the lithography machine.

[0086] In some other implementation manners, the equivalent equation can also be obtained by forming the correlation manner between the stress and the strain or other indexes, and no more introduction is made here.

[0087] Please refer to Figure 1 again. The full - chip fast simulation method for the negative - tone development lithography process further includes the following steps:

[0088] S3. Select the Taylor expansion formula to perform approximate calculation on the equivalent equation to obtain the approximate value of the stress or the strain, and adjust the light - field distribution according to the approximate value to obtain a suitable acid - concentration distribution.

[0089] In this step, since it is a simplified model obtained after simplifying the equation, that is, the equivalent equation, and the speed needs to be considered, so we do not consider the process of solving the differential equation, that is, avoid directly solving the equivalent equation. By observation, it is not difficult to find that there are great similarities between the equivalent equation and the Taylor expansion formula. Therefore, the Taylor expansion formula is selected to perform approximate calculation on the equivalent equation to obtain the approximate value of the stress or the strain, and the light - field distribution is adjusted according to the approximate value to obtain a suitable acid - concentration distribution.

[0090] In this embodiment, the provided Taylor expansion formula is as follows:

[0091]

[0092]

[0093] Among them, (0 < θ < 1), where h and k are constants.

[0094] The Taylor expansion formula provided in this embodiment is only an example and is not a limitation. In other embodiments, it may also be other Taylor expansions.

[0095] It should be noted that: Selecting each order sub-term of the Taylor expansion to perform fitting calculation on the shrinkage effect, since each order sub-term of the Taylor expansion is a relatively simple expression, fast calculation can be achieved. For the full-chip modeling, it has a relatively concise backpropagation expression that can be represented, which can meet our requirements for speed and ensure accuracy at the same time.

[0096] The second embodiment of the present invention provides a negative-tone development photoresist model, which is obtained based on the full-chip fast simulation method of the negative-tone development photolithography process provided in the first embodiment.

[0097] Please refer to 4 and Figure 5 , in Figure 4 initially select a mask layout area, generate a 512*512 mask image, corresponding to the M area of each grid in the figure, and then through the optical model described in step S1, obtain its light field distribution image, corresponding to Figure 4 the bright areas in, corresponding to T1 and T2 respectively. Further, based on the operations in step S2 and step S3, process the light field distribution to obtain an image after the simulated thermal shrinkage effect. During the adjustment process, it often requires multiple repeated adjustments to obtain a suitable light field distribution to obtain a qualified exposure pattern. Figure 5 corresponding to the light field distribution image when the light field distribution is adjusted to the optimal state, where the light brightness becomes T11 and T21 respectively. Through Figure 5 and Figure 4 comparison, it can be clearly seen that there is an obvious squeezing effect towards the line segment at the endpoints, and there is an obvious inward shrinkage at the corresponding places of the long line segment and the endpoints.

[0098] The third embodiment of the present invention provides an OPC model, which includes an initial OPC model and the negative-tone development photoresist model provided in the second embodiment. Generally, the initial OPC model includes a background light intensity distribution function, a light intensity gradient function, a light intensity curve function, a light base distribution function, and a photoacid distribution function, etc. After adding the negative-tone development photoresist model as described above, it can well adapt to the negative-tone photoresist process, can well simulate and calculate the thermal shrinkage effect of the negative-tone photoresist, and improve the accuracy of the photolithography process.

[0099] Please refer toFigures 6A to 6E A total of 818 gauges were provided to fit the obtained OPC model. Among them, 608 gauges under a one-dimensional mask, as described in Figure 6A -6C, were included and named Group A, Group B, and Group C respectively. Among them, Group A had a total of 428 gauges, Group B had a total of 94 gauges, and Group C had a total of 86 gauges. Also included were 210 gauges under a two-dimensional mask, as shown in Figure 6D and 6E , and named Group D and Group E respectively. Among them, Group D had a total of 17 gauges, Group E had a total of 94 gauges, and Group C had a total of 193 gauges. The root mean square of all gauges without model processing was (AI): 4.319 (RMS), after negative development model processing was (NTD): 1.289 (RMS), and after positive development model processing was (PTD): 2.025 (RMS).

[0100] The root mean square (RMS) corresponding to each group was as follows (in the following table):

[0101]

[0102] From the above data, it can be seen that the root mean square value obtained after simulation by the OPC model established based on the negative photoresist model is smaller, and the OPC model has better performance.

[0103] Please refer to Figure 7 , which corresponds to the bar chart in the above table. The obvious differences among the three can be seen more intuitively from the bar chart.

[0104] Please refer to Figure 8 , the fourth embodiment of the present invention provides an electronic device 300, which includes one or more processors 302;

[0105] A storage device 301 for storing one or more programs,

[0106] When the one or more programs are executed by the one or more processors 302, the one or more processors 302 implement any step of the full-chip fast simulation method of a negative development lithography process provided in the first embodiment.

[0107] Next, refer to Figure 9 , which shows a schematic structural diagram of a computer system 800 of a terminal device / server suitable for implementing the embodiments of the present invention. Figure 5 The terminal device / server shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0108] As Figure 9 shown, computer system 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage section 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the system 800 are also stored. The CPU 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0109] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read from it can be installed into the storage section 808 as needed.

[0110] According to an embodiment of the present disclosure, the processes described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a computer-readable medium, and the computer program includes program code for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 809, and / or installed from the removable medium 811. When the computer program is executed by a central processing unit (CPU) 801, the above-mentioned functions defined in the method of the present invention are executed. It should be noted that the computer-readable medium described in the present invention can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0111] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., by using an Internet service provider to connect through the Internet).

[0112] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks can occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0113] The above computer-readable medium carries one or more programs, which, when executed by the device, cause the device to: obtain the light field distribution of the photoresist through an optical model, set the light field distribution as E(x, y), and set the distribution of the acid concentration in the photoresist as a function of the light field distribution, i.e., S(x, y) = F(E(x, y)); set the thermal shrinkage effect of the photoresist during post-baking as elastic deformation, analyze the elastic deformation of the photoresist based on elasticity mechanics, set one of stress and strain as the equivalent of the amount of deformation of the photoresist to obtain an equivalent equation, and the equivalent equation is a differential equation; and select a Taylor expansion to approximately calculate the equivalent equation to obtain an approximate value of stress or strain, and adjust the light field distribution according to the approximate value to obtain a suitable acid concentration distribution.

[0114] Compared with the prior art, by analyzing the deformation of the photoresist based on elasticity mechanics, setting one of the stress and strain as the equivalent of the deformation amount of the photoresist to obtain an equivalent equation, and using the Taylor expansion to approximately calculate the equivalent equation to obtain an approximate value of the stress or strain, adjusting the light field distribution according to the approximate value to obtain a suitable acid concentration distribution, so that the exposed pattern is closest to the target pattern, it can well analyze the deformation of the photoresist during the thermal shrinkage effect, improve the accuracy in the photolithography calculation process. At the same time, using the Taylor expansion to fit the thermal shrinkage effect can improve the calculation speed. Therefore, the problem of complex calculation in the full-chip negative development photolithography process is solved.

[0115] Based on the relatively thin thickness dimension of the photoresist, the photoresist is set as a plane, thereby simplifying the equilibrium equation, the physical equation, and the geometric equation, making the simplified equivalent equation and the Taylor expansion have great similarity. Therefore, there is no need to perform differential solution on the equivalent equation, which can well improve the calculation speed and ensure the accuracy at the same time.

[0116] The negative development photoresist model, OPC model, and electronic device provided by the present invention also have the beneficial effects as described above.

[0117] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A full-chip rapid simulation method for negative development lithography process, characterized in that: It includes the following steps: S1. Obtain the light field distribution of the photoresist through an optical model, set the light field distribution as E(x, y), and set the distribution of the acid concentration in the photoresist as a function of the light field distribution, that is, S(x, y) = F(E(x, y)); S2. Set the thermal shrinkage effect of the photoresist during post-baking as elastic deformation, analyze the elastic deformation of the photoresist based on elasticity mechanics, set one of stress and strain as the equivalent of the deformation amount of the photoresist to obtain an equivalent equation, and the equivalent equation is a differential equation; and S3. Select a Taylor expansion to approximately calculate the equivalent equation to obtain an approximate value of stress or strain, and adjust the light field distribution according to the approximate value to obtain a suitable acid concentration distribution.

2. The full-chip rapid simulation method for a negative-tone development lithography process according to claim 1, characterized in that: According to the continuity assumption, the elastic body remains a continuous body before and after deformation. Assume that a point in the elastic body moves from position M(x, y, z) to M′(x′, y′, z′) during the deformation process, and this process is a continuous process. All displacements satisfy the equation: where u(x, y, z) = x′(x, y, z) - x, v(x, y, z) = y′(x, y, z) - y, w(x, y, z) = z'(x, y, z) - z, where u, v, and w respectively correspond to the displacements in the x, y, and z directions, and the photoresist is correspondingly called an elastic body; In the above step S2, the obtaining of the equivalent equation includes the following steps: S21. The external force is correlated with the stress through the equilibrium equation, the stress is correlated with the strain through the physical equation, and the strain is correlated with the displacement through the geometric equation; and S22. Based on the relatively thin thickness dimension of the photoresist, set the photoresist as a plane, so as to simplify the equilibrium equation, the physical equation, and the geometric equation.

3. The full-chip rapid simulation method for a negative-tone development lithography process according to claim 2, characterized in that: An equivalent equation regarding the correlation between strain and displacement is obtained based on the simplified geometric equation.

4. The full-chip rapid simulation method for the negative development lithography process according to claim 3, characterized in that: The symbol definitions involved in the following formulas are all consistent with the definitions in elasticity mechanics; In the above step S22, when the photoresist is set to a plane, set σ z = 0, = 0, = 0, w = 0; The stress components can be derived as: The strain components are: The simplified equilibrium equation is: The simplified geometric equation is: Among them, σ x , σ y , σ z correspond to the normal stresses in the x-direction, y-direction, and z-direction respectively; represents the shear stress in the y-direction on the x-plane, represents the shear stress in the x-direction on the z-plane, represents the shear stress in the y-direction on the z-plane, represents the shear stress in the x-direction on the y-plane; ε x , ε y correspond to the strain components in the x-direction and y-direction respectively.

5. The full-chip rapid simulation method for the negative development lithography process according to claim 4, characterized in that: The equivalent equation is as follows:

6. The full-chip rapid simulation method of the negative development lithography process according to claim 5, characterized in that: The Taylor expansion similar to the equivalent equation is as follows, where: 0 < θ < 1, h and k are constants.

7. A negative-tone development photoresist model, characterized in that: Obtained based on the full-chip rapid simulation method for a negative-tone development lithography process according to any one of claims 1-6.

8. An OPC model, characterized in that: Provide an initial OPC model and add the negative-tone development photoresist model according to claim 7.

9. An electronic device, characterized in that: It includes one or more processors; A storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the full-chip rapid simulation method for a negative-tone development lithography process according to any one of claims 1-6.

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