Asymmetric triode input folding operational amplifier and bandgap reference circuit

Abstract

The present invention discloses a folding operational amplifier with asymmetric triode input and a bandgap reference circuit. The problem that the reference source circuit in the prior art has a complex circuit structure and is difficult to reduce the power supply voltage is solved. The amplifier includes an input pair of tubes, a bias current source and a common source and common gate output load, the bias current source is connected to the input pair of tubes, and the input pair of tubes is folded and connected to the common source and common gate output load. The bandgap reference circuit adopts the transport amplifier. When the operational amplifier is used in the bandgap reference circuit, a voltage difference proportional to the temperature can be generated at the input end in advance. When connected to the core circuit of the bandgap reference, the voltage difference proportional to the temperature generated by the bandgap reference is superimposed, which can reduce the matching error of the output tube of the operational amplifier. At the same time, since the triode is folded, the requirement for the power supply voltage is greatly reduced, which can meet the working environment of low power supply voltage.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a folding operational amplifier with an asymmetric triode input and a bandgap reference circuit. Background Art

[0002] As the application scope of integrated circuits in mobile devices becomes wider and wider, the requirements for low power consumption in the current integrated circuit design are also getting higher and higher. Reducing power consumption requires reducing the operating current of the device on the one hand, and reducing the voltage on the other hand. At the same time, as the most commonly used chip reference source, the accuracy of the bandgap reference usually determines the accuracy of the chip. The generation of the reference source usually increases the differential voltage by superimposing two-stage transistors, thereby reducing the relative error caused by circuit matching, thereby improving the accuracy of the reference source.

[0003] Traditional high-precision bandgap reference circuits such as Figure 1 As shown, the connection relationship is as follows: the collectors of the four transistors Q1′, Q2′, Q3′ and Q4′ are grounded, wherein the transistor Q1′ is a PNP transistor, the transistor Q2′ is a PNP transistor, the transistor Q3′ is N PNP transistors connected in parallel, the transistor Q4′ is N PNP transistors connected in parallel, the bases of the transistors Q1′ and Q4′ are grounded, the base of the transistor Q2′ is connected to the emitter of the transistor Q1′ and to the drain of the PMOS tube M1′, the base of the transistor Q3′ is connected to the emitter of the transistor Q4′ and to the drain of the PMOS tube M4′. The negative end of the resistor R1′ is connected to the base of the transistor Q3′, the positive end of the resistor R1′ is connected to the positive input end of the operational amplifier and the negative end of the resistor R2′, and the positive end of the resistor R2′ is connected to the drain end of the MOS tube M3′. The sources of the MOS tubes M1′, M2′, M3′, M4′, and M5′ are all connected to the power supply VDD, and their gates are all short-circuited and connected to the output end of the operational amplifier. The reference voltage Vref is output through the positive end of the resistor R2′, and the current IPTAT proportional to the temperature is output through the drain of the MOS tube M5′.

[0004] Traditional high-precision bandgap reference circuits such as Figure 1As shown, its basic working principle is: MOS tube M1′, MOS tube M2′, MOS tube M3′, and MOS tube M4′ use the same bias, and the current flowing out of their drain ends is equal. Then, since the transistor Q3′ and the transistor Q4′ are N PNP tubes connected in parallel, the current flowing into each PNP tube of the transistor Q1′ and the transistor Q2′ will be N times that of the transistor Q3′ and the transistor Q4′. According to the current-voltage relationship of the transistor, the voltage (Vbe) between the base and emitter of the transistor Q1′ and the transistor Q2′ and the voltage difference ΔVbe between the base and emitter of the transistor Q3′ and the transistor Q4′ is a voltage quantity that is proportional to the temperature, and the voltage Vbe between the base and emitter of the transistor is a voltage quantity that is negatively correlated with the temperature. The two are added according to a suitable coefficient to obtain a voltage quantity (Vref) that does not change with temperature for reference. At the same time, the circuit can output a current (IPTAT) proportional to temperature by dividing the ΔVbe voltage proportional to temperature by a constant resistance.

[0005] This structure of bandgap reference circuit can reduce the relative error introduced by the operational amplifier due to matching by superimposing two transistors and using two ΔVbe when generating reference voltage and reference current. However, because this structure superimposes two stages of transistors, the required power supply voltage VDD must be at least greater than the voltage of the two transistors in series (about 1.4V). However, in a low power supply voltage power supply system, the power supply voltage may be required to be lower than 1.4, and the traditional bandgap reference structure is not conducive to reducing the power supply voltage. Summary of the invention

[0006] The present invention mainly solves the problem that the accuracy of the reference source is improved by superimposing two triode structures in the prior art, but the circuit structure is complex and it is difficult to reduce the power supply voltage. A folding operational amplifier with an asymmetric triode input and a bandgap reference circuit are provided.

[0007] The above technical problems of the present invention are mainly solved by the following technical solutions: a folded operational amplifier with an asymmetric triode input, comprising an input pair of tubes, a bias current source and a cascode output load, wherein the bias current source is connected to the input pair of tubes, and the input pair of tubes is folded and connected to the cascode output load. In the present invention, the bias current source provides a bias current for the input pair of tubes, and the input pair of tubes is folded and connected to the cascode output load to form a folded cascode transport amplifier. The circuit structure of the present invention is simple, the circuit area is small, the cost is low, and the precision is high. The present invention changes the circuit architecture of directly superimposing two-stage triodes in the circuit in the traditional design, and by using the triode as the input tube of the operational amplifier, a differential voltage is pre-generated at the input end of the amplifier, and this voltage is added to the voltage generated by the bandgap reference core circuit, thereby greatly reducing the power supply voltage of the circuit while ensuring the accuracy of the reference source.

[0008] As a preferred solution, the common-source and common-gate output load includes a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, and an NMOS tube M8. The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and is connected to the power supply VDD. The drain of the PMOS tube M1 is connected to the source of the PMOS tube M3. The drain of the PMOS tube M2 is connected to the drain of the PMOS tube M4. The gate of the PMOS tube M1 is connected to the gate of the PMOS tube M2 and is connected to the drain of the PMOS tube M3. The gate of the PMOS tube M3 is connected to the The gate of the PMOS tube M4 is connected and connected to the second bias voltage, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and serves as the output end of the amplifier, the gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and connected to the second bias voltage, the source of the NMOS tube M5 is connected to the drain of the NMOS tube M7, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M8, the gate of the NMOS tube M7 is connected to the gate of the NMOS tube M8 and connected to the first bias voltage, and the source of the NMOS tube M7 and the source of the NMOS tube M8 are grounded respectively. In this solution, the source of the PMOS tube M1 and the source of the PMOS tube M2 are connected and connected to the power supply voltage, the drain of the PMOS tube M1 is connected to the source of the PMOS tube M3, and the drain of the PMOS tube M2 is connected to the drain of the PMOS tube M4, forming a common source and common gate structure together. The gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and connected to the second bias voltage, the source of the NMOS tube M5 is connected to the drain of the NMOS tube M7, and the source of the NMOS tube M6 is connected to the drain of the NMOS tube M8, forming a common source and common gate structure.

[0009] As a preferred solution, the input pair of transistors includes transistor Q1 and transistor Q2, transistor Q1 includes an NPN transistor, transistor Q2 includes several parallel NPN transistors, the base of transistor Q1 serves as the positive input terminal of the operational amplifier, the base of transistor Q2 serves as the negative input terminal of the operational amplifier, the emitter of transistor Q1 and the emitter of transistor Q2 are connected and then connected to the bias current source, the collector of transistor Q1 is connected to the drain of PMOS tube M1, and the collector of transistor Q2 is connected to the drain of PMOS tube M2. In this solution, bipolar transistors are used instead of CMOS light as the input pair of transistors of the folded cascode transport amplifier, and the number of NPN transistors included in transistor Q1 and transistor Q2 is not equal. The collector of transistor Q1 is connected to the collector of transistor Q2 and is respectively connected to the cascode output load, specifically, the collector of transistor Q1 is connected to the drain of PMOS tube M1, and the collector of transistor Q2 is connected to the drain of PMOS tube M2.

[0010] As a preferred solution, the input pair of transistors includes transistor Q1 and transistor Q2, transistor Q1 includes several parallel PNP transistors, transistor Q2 includes a PNP transistor, the base of transistor Q1 serves as the positive input terminal of the operational amplifier, the base of transistor Q2 serves as the negative input terminal of the operational amplifier, the emitter of transistor Q1 and the emitter of transistor Q2 are connected and then connected to the bias current source, the collector of transistor Q1 is connected to the drain of NMOS tube M7, and the collector of transistor Q2 is connected to the drain of NMOS tube M8. This solution is another structure of the input pair of transistors. The collector of transistor Q1 is connected to the collector of transistor Q2 and is respectively connected to the common source and common gate output load, specifically, the collector of transistor Q1 is connected to the drain of NMOS tube M7, and the collector of transistor Q2 is connected to the drain of NMOS tube M8.

[0011] As a preferred solution, the bias current source includes an NMOS tube M9, the gate of the NMOS tube M9 is connected to the first bias voltage, the source of the NMOS tube M9 is grounded, and the drain of the NMOS tube M9 is connected to the connecting point of the emitter of the transistor Q1 and the emitter of the transistor Q2. In this solution, the gate of the NMOS tube M9 is biased by the first bias voltage, the drain of the NMOS tube M9 is connected to the emitters of the transistor Q1 and the transistor Q2, and the bias current is provided to the transistor Q1 and the transistor Q2.

[0012] As a preferred solution, the bias current source includes an NMOS tube M9, the gate of the NMOS tube M9 is connected to the first bias voltage, the source of the NMOS tube M9 is connected to the power supply VDD, and the drain of the NMOS tube M9 is connected to the connecting point of the emitter of the transistor Q1 and the emitter of the transistor Q2.

[0013] The invention discloses a folding operational amplifier bandgap reference circuit with asymmetric triode input, which adopts a folding operational amplifier with asymmetric triode input, including triode Q3, triode Q4, resistor R1, resistor R2, PMOS tube M10, PMOS tube M11, PMOS tube M12, PMOS tube M13, PMOS tube M14 and PMOS tube M15. The triode Q3 includes a PNP tube, the triode Q4 includes a plurality of parallel PNP tubes, the drain and gate of the triode Q3 are grounded respectively, the drain and gate of the triode Q4 are grounded respectively, the source of the triode Q4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the drain of the PMOS tube M13, the positive input end of the folding operational amplifier with asymmetric triode input is connected to the connection point of the resistor R1 and the resistor R2, the source of the triode Q3 is connected to the drain of the PMOS tube M12, the positive input end of the folding operational amplifier with asymmetric triode input is connected to the connection point of the resistor R1 and the resistor R2, the source of the triode Q3 is connected to the drain of the PMOS tube M12, the positive input end of the folding operational amplifier with asymmetric triode input is connected to the connection point of the resistor R1 and the resistor R2, the source of the triode Q3 is connected to the drain of the PMOS tube M12, the positive input end of the folding operational amplifier with asymmetric triode input is connected to the positive input end of the folding operational amplifier with asymmetric triode input is connected to the positive input end of the folding operational amplifier with asymmetric triode input The negative input terminal of the folding operational amplifier is connected to the connection point between the source of the transistor Q3 and the drain of the PMOS tube M12, the gate of the PMOS tube M12 is connected to the gate of the PMOS tube M13 and connected to the second bias voltage, the source of the PMOS tube M12 is connected to the drain of the PMOS tube M10, the source of the PMOS tube M13 is connected to the drain of the PMOS tube M11, the gate of the PMOS tube M10 is connected to the gate of the PMOS tube M11 and is connected to the power transmission end of the folding operational amplifier inputted by the asymmetric transistor, the source of the PMOS tube M14 is connected to the power supply VDD, the drain of the PMOS tube M14 is connected to the source of the PMOS tube M15, the drain of the PMOS tube M15 serves as a current reference output terminal, the gate of the PMOS tube M14 is connected to the connection point between the gate of the PMOS tube M10 and the gate of the PMOS tube M11, and the gate of the PMOS tube M15 is connected to the connection point between the gate of the PMOS tube M12 and the gate of the PMOS tube M13.

[0014] In this solution, the gate of PMOS tube M12 is connected to the gate of PMOS tube M13 and connected to the second bias voltage, the source of PMOS tube M12 is connected to the drain of PMOS tube M10, and the source of PMOS tube M13 is connected to the drain of PMOS tube M11, forming a common source and common gate current mirror to reduce the influence of channel length modulation effect. The source of PMOS tube M14 is connected to the power supply VDD, and the drain of PMOS tube M14 is connected to the source of PMOS tube M15 to form a common source and common gate current mirror. The output of the folding operational amplifier with asymmetric triode input is used as the gate bias voltage of the first-stage PMOS tube to adjust the current size of the bandgap reference bias circuit.

[0015] Therefore, the advantages of the present invention are:

[0016] 1. The circuit architecture of directly superimposing two-stage triodes in the circuit in the traditional design is changed. By using the triode as the input tube of the operational amplifier, a differential voltage is pre-generated at the input end of the amplifier. This voltage is added to the voltage generated by the bandgap reference core circuit, which greatly reduces the power supply voltage of the circuit while ensuring the accuracy of the reference source.

[0017] 2. The circuit structure is simple, the circuit area is small, the cost is low and the precision is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the structure of an existing bandgap reference circuit;

[0019] Figure 2 It is a circuit structure diagram of a folding operational amplifier with asymmetric triode input in the present invention;

[0020] Figure 3 It is another circuit connection diagram of the folding operational amplifier with asymmetric triode input in the present invention;

[0021] Figure 4 The invention is a circuit structure schematic diagram of a bandgap reference circuit of a folding operational amplifier with an asymmetric triode input.

[0022] 1- Input pair tube 2- Bias current source 3- Common source and common gate output load. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is further specifically described below through embodiments and in conjunction with the accompanying drawings.

[0024] Embodiment 1:

[0025] This embodiment is a folding operational amplifier with an asymmetric triode input, such as Figure 2 As shown, it includes an input pair of tubes 1, a bias current source 2 and a common-source and common-gate output load 3. The bias current source 2 is connected to the input pair of tubes, and the input pair of tubes is folded and connected to the common-source and common-gate output load.

[0026] The input pair of transistors includes a transistor Q1 and a transistor Q2. The transistor Q1 includes an NPN transistor, and the transistor Q2 includes a plurality of parallel NPN transistors. The base of the transistor Q1 serves as the positive input terminal of the operational amplifier, and the base of the transistor Q2 serves as the negative input terminal of the operational amplifier. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the bias current source, and the collector of the transistor Q1 and the collector of the transistor Q2 are respectively connected to the common source and common gate output load.

[0027] The common-source and common-gate output loads include PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, and NMOS tube M8. The source of PMOS tube M1 is connected to the source of PMOS tube M2 and is also connected to the power supply VDD. The drain of PMOS tube M1 is connected to the source of PMOS tube M3, and the drain of PMOS tube M2 is connected to the drain of PMOS tube M4. The collector of transistor Q1 is connected to the drain of PMOS tube M1, and the collector of transistor Q2 is connected to the drain of PMOS tube M2. The gate of the PMOS tube M1 is connected to the gate of the PMOS tube M2 and to the drain of the PMOS tube M3. The gate of the PMOS tube M3 is connected to the gate of the PMOS tube M4 and to the second bias voltage Vbn2. The drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5. The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and serves as the output end of the amplifier. The gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and to the second bias voltage Vbn2. The source of the NMOS tube M5 is connected to the drain of the NMOS tube M7. The source of the NMOS tube M6 is connected to the drain of the NMOS tube M8. The gate of the NMOS tube M7 is connected to the gate of the NMOS tube M8 and to the first bias voltage Vbn1. The source of the NMOS tube M7 and the source of the NMOS tube M8 are grounded respectively.

[0028] The bias current source 2 comprises an NMOS tube M9, a gate of the NMOS tube M9 is connected to the first bias voltage Vbn1, a source of the NMOS tube M9 is grounded, and a drain of the NMOS tube M9 is connected to the connecting point of the emitter of the transistor Q1 and the emitter of the transistor Q2.

[0029] Embodiment 2:

[0030] This embodiment is another asymmetric triode input folding operational amplifier structure, such as Figure 3 , which is different from Example 1 in the structure of the input pair of transistors and the bias current source. The input pair of transistors 1 includes transistors Q1 and Q2, wherein the transistor Q1 includes several parallel PNP transistors, and the transistor Q2 includes a PNP transistor. The base of the transistor Q1 serves as the positive input terminal of the operational amplifier, and the base of the transistor Q2 serves as the negative input terminal of the operational amplifier. The emitter of the transistor Q1 is connected to the emitter of the transistor Q2 and then connected to the bias current source. The collector of the transistor Q1 is connected to the drain of the NMOS tube M7, and the collector of the transistor Q2 is connected to the drain of the NMOS tube M8. The bias current source 2 includes an NMOS tube M9, wherein the gate of the NMOS tube M9 is connected to the first bias voltage Vbn1, the source of the NMOS tube M9 is connected to the power supply VDD, and the drain of the NMOS tube M9 is connected to the connecting point of the emitter of the transistor Q1 and the emitter of the transistor Q2. The common source and common gate output load structure is the same as that in Example 1.

[0031] Embodiment 3:

[0032] This embodiment provides a structure of a bandgap reference circuit using a folding operational amplifier with an asymmetric triode input. Figure 4 As shown, the circuit includes transistors Q3, Q4, resistors R1, R2, PMOS tubes M10, M11, M12, M13, M14, and M15. The transistor Q3 includes a PNP tube, and the transistor Q4 includes a plurality of parallel PNP tubes. The drain and gate of the transistor Q3 are grounded respectively, and the drain and gate of the transistor Q4 are grounded respectively. The source of the transistor Q4 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the drain of the PMOS tube M13. The positive input end of the folding operational amplifier with asymmetric transistor input is connected to the connection point of the resistor R1 and the resistor R2. The source of the transistor Q3 is connected to the drain of the PMOS tube M12, and the negative input end of the folding operational amplifier with asymmetric transistor input is connected to the source of the transistor Q3. The gate of the PMOS tube M12 is connected to the gate of the PMOS tube M13 and connected to the second bias voltage Vbn2, the source of the PMOS tube M12 is connected to the drain of the PMOS tube M10, the source of the PMOS tube M13 is connected to the drain of the PMOS tube M11, the gate of the PMOS tube M10 is connected to the gate of the PMOS tube M11 and is connected to the power transmission end of the folding operational amplifier with asymmetric triode input, the source of the PMOS tube M14 is connected to the power supply VDD, the drain of the PMOS tube M14 is connected to the source of the PMOS tube M15, the drain of the PMOS tube M15 is used as the current reference output end, the gate of the PMOS tube M14 is connected to the connection point between the gate of the PMOS tube M10 and the gate of the PMOS tube M11, and the gate of the PMOS tube M15 is connected to the connection point between the gate of the PMOS tube M12 and the gate of the PMOS tube M13. The structure of the folding operational amplifier with asymmetric triode input adopts the structure in embodiment 1 or 2.

[0033] The working process of this embodiment is that, under normal conditions, the currents flowing through the PMOS tube M10 and the PMOS tube M11 are equal, the currents flowing through the drain of the PMOS tube M1 and the PMOS tube M2 are equal, and thus the currents flowing through the transistors Q3 and Q4 are equal, and the currents flowing through the transistors Q1 and Q2 are equal. Since the transistor Q3 has only one PNP tube, and the transistor Q4 has N PNP tubes, the current flowing through each PNP tube in the transistor Q3 is N times the current flowing through each PNP tube in the transistor Q4, based on the relationship between the transistor voltage and the current, the voltage of the emitter of the transistor Q3 is higher than the voltage of the emitter of the transistor Q4 by ΔVbe, and the voltage is proportional to the temperature, the currents flowing through the transistors Q1 and Q2 are equal, and the base voltage of the transistor Q1 is higher than the base voltage of the transistor Q2 by ΔVbe. The two ΔVbe are superimposed on the resistor R2 to generate a voltage Vr2 that is proportional to the temperature, and a current IPTAT that is positively related to the temperature is generated through the resistor R2. This current passes through the PMOS tube M11, PMOS tube M13, PMOS tube M10 and PMOS tube M12. The current reference IPTAT that is proportional to the temperature is output by the drain of M15. The voltage superimposed on the resistor R2 generates a current proportional to the temperature that flows through the resistor R1 at the same time, generating a voltage Vr1 that is proportional to the temperature. According to the voltage-current characteristics of the transistor, the voltage Vbe between the emitter and the base of the transistor Q4 will be a voltage that is negatively correlated with the temperature. The voltage Vbe that is negatively correlated with the temperature plus the voltages Vr2 and Vr1 that are proportional to the temperature generate a reference voltage Vref that is insensitive to both temperature and power supply, which is output through the positive electrode of the resistor R1.

[0034] The present invention uses two unequal transistors as input tubes of an operational amplifier, generates a voltage difference proportional to the temperature in advance, and adds the voltage in the bandgap reference core circuit to generate a current IPTAT that is positively correlated with the temperature, thereby reducing the power supply voltage required for directly superimposing two transistors in a traditional circuit and ensuring the accuracy of the reference source.

[0035] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0036] Although this article uses more terms such as input pair transistor, bias current source, cascode output load, etc., it does not exclude the possibility of using other terms. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional restrictions is contrary to the spirit of the present invention.

Claims

1. A folding operational amplifier with an asymmetric triode input, characterized in that: The invention comprises an input pair of transistors (1), a bias current source (2) and a cascode output load (3), wherein the bias current source is connected to the input pair of transistors, and the input pair of transistors is folded and connected to the cascode output load; a bipolar transistor is used as an input pair of transistors of a folded cascode operational amplifier, wherein the input pair of transistors (1) comprises a transistor Q1 and a transistor Q2, wherein the transistor Q1 comprises an NPN transistor, and the transistor Q2 comprises a plurality of parallel NPN transistors, and the base of the transistor Q1 serves as the positive input terminal of the operational amplifier. The base of transistor Q2 serves as the negative input terminal of the operational amplifier. The emitter of transistor Q1 and the emitter of transistor Q2 are connected and then connected to a bias current source. The bias current source (2) comprises an NMOS transistor M9. The gate of NMOS transistor M9 is connected to a first bias voltage. The source of NMOS transistor M9 is grounded. The drain of NMOS transistor M9 is connected to a point where the emitter of transistor Q1 and the emitter of transistor Q2 are connected. The collector of transistor Q1 and the collector of transistor Q2 are respectively connected to a common source and common gate output load.

2. The asymmetric triode input folding operational amplifier according to claim 1, characterized in that the common source and common gate output The load (3) includes a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, and an NMOS tube M8. The source of the PMOS tube M1 is connected to the source of the PMOS tube M2 and is also connected to the power supply VDD. The drain of the PMOS tube M1 is connected to the source of the PMOS tube M3. The drain of the PMOS tube M2 is connected to the drain of the PMOS tube M4. The gate of the PMOS tube M1 is connected to the gate of the PMOS tube M2 and is also connected to the drain of the PMOS tube M3. The gate of the PMOS tube M3 is connected to the gate of the PMOS tube M4. 4 and connected to the second bias voltage, the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the drain of the PMOS tube M4 is connected to the drain of the NMOS tube M6 and serves as the output end of the amplifier, the gate of the NMOS tube M5 is connected to the gate of the NMOS tube M6 and connected to the second bias voltage, the source of the NMOS tube M5 is connected to the drain of the NMOS tube M7, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M8, the gate of the NMOS tube M7 is connected to the gate of the NMOS tube M8 and connected to the first bias voltage, and the source of the NMOS tube M7 and the source of the NMOS tube M8 are grounded respectively.

3. The folding operational amplifier with asymmetric triode input according to claim 2, characterized in that The collector of the transistor Q1 is connected to the drain of the PMOS tube M1, and the collector of the transistor Q2 is connected to the drain of the PMOS tube M2.

4. The folding operational amplifier with asymmetric triode input according to claim 2, characterized in that The input pair of transistors (1) includes a transistor Q1 and a transistor Q2. The transistor Q1 includes a plurality of parallel PNP transistors, and the transistor Q2 includes a PNP transistor. The base of the transistor Q1 serves as the positive input terminal of the operational amplifier, and the base of the transistor Q2 serves as the negative input terminal of the operational amplifier. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected and then connected to a bias current source. The collector of the transistor Q1 is connected to the drain of the NMOS tube M7, and the collector of the transistor Q2 is connected to the drain of the NMOS tube M8.

5. The asymmetric triode input folding operational amplifier according to claim 4, characterized in that The bias current source (2) comprises an NMOS tube M9, the gate of the NMOS tube M9 is connected to the first bias voltage, the source of the NMOS tube M9 is connected to the power supply VDD, and the drain of the NMOS tube M9 is connected to the connecting point of the emitter of the transistor Q1 and the emitter of the transistor Q2.

6. A folding operational amplifier bandgap reference circuit with an asymmetric triode input, using the folding operational amplifier with an asymmetric triode input according to any one of claims 1 to 5, characterized in that The invention comprises a transistor Q3, a transistor Q4, a resistor R1, a resistor R2, a PMOS tube M10, a PMOS tube M11, a PMOS tube M12, a PMOS tube M13, a PMOS tube M14 and a PMOS tube M15. The transistor Q3 comprises a PNP tube, the transistor Q4 comprises a plurality of parallel PNP tubes, the drain and the gate of the transistor Q3 are grounded respectively, the drain and the gate of the transistor Q4 are grounded respectively, the source of the transistor Q4 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the drain of the PMOS tube M13, the positive input end of the folding operational amplifier with asymmetric transistor input is connected to the connection point of the resistor R1 and the resistor R2, the source of the transistor Q3 is connected to the drain of the PMOS tube M12, and the negative input end of the folding operational amplifier with asymmetric transistor input is connected to the source of the transistor Q3 and The drain connection point of the PMOS tube M12, the gate of the PMOS tube M12 is connected to the gate of the PMOS tube M13 and is connected to the second bias voltage, the source of the PMOS tube M12 is connected to the drain of the PMOS tube M10, the source of the PMOS tube M13 is connected to the drain of the PMOS tube M11, the gate of the PMOS tube M10 is connected to the gate of the PMOS tube M11 and is connected to the power transmission end of the folded operational amplifier with an asymmetric triode input, the source of the PMOS tube M14 is connected to the power supply VDD, the drain of the PMOS tube M14 is connected to the source of the PMOS tube M15, the drain of the PMOS tube M15 is used as a current reference output end, the gate of the PMOS tube M14 is connected to the connection point of the gate of the PMOS tube M10 and the gate of the PMOS tube M11, and the gate of the PMOS tube M15 is connected to the connection point of the gate of the PMOS tube M12 and the gate of the PMOS tube M13.

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