Input stage circuit

Abstract

The invention discloses an input stage circuit. The input stage circuit is used for providing a differential current to a post-stage circuit according to a differential input signal, and comprises a first input geminate transistor, and a first cascode structure and a first tail current source which are adaptively connected with the first input geminate transistor; the first input geminate transistor, the second input geminate transistor, the second cascode structure and the second tail current source are adaptively connected with the second input geminate transistor, a first bias voltage is provided for the second cascode structure through a common node of the first input geminate transistor and the first tail current source, and a second bias voltage is provided for the second cascode structure through a common node of the second input geminate transistor. And a second bias voltage is provided for the second cascode structure through a common node of the second input geminate transistor and the second tail current source. Therefore, self-biasing can be realized, power consumption is reduced, and response speed is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an input stage circuit. Background Art

[0002] Rail-to-Rail circuit is a circuit design mainly used in analog circuits such as operational amplifiers and comparators. In the rail-to-rail input stage circuit, the limitation on the input signal range is reduced by using complementary differential input pairs (i.e., NMOS pairs and PMOS pairs), and the processing of full-range input signals (i.e., negative power rail to positive power rail) is realized, which maximizes the use of power supply voltage and improves the flexibility and dynamic range of signal processing.

[0003] In the prior art, a cascode structure is connected to the input pair of transistors to obtain higher gain, stability and linearity. However, the cascode structure requires an additional bias circuit to provide bias, and the introduction of the bias circuit increases power consumption and reduces the bias following speed.

[0004] Therefore, a new input stage circuit is needed. Summary of the invention

[0005] In view of the above problems, an object of the present invention is to provide an input stage circuit.

[0006] The present application provides an input stage circuit for providing a differential current to a subsequent stage circuit according to a differential input signal, wherein the input stage circuit includes: a first input pair of tubes, and a first cascode structure and a first tail current source adapted to be connected to the first input pair of tubes; and a second input pair of tubes, and a second cascode structure and a second tail current source adapted to be connected to the second input pair of tubes, wherein a first bias voltage is provided to the second cascode structure through a common node of the first input pair of tubes and the first tail current source, and a second bias voltage is provided to the first cascode structure through a common node of the second input pair of tubes and the second tail current source.

[0007] Optionally, the first input pair includes a first NMOS transistor and a second NMOS transistor, a common node between the second end of the first NMOS transistor and the second end of the second NMOS transistor is connected to the first tail current source, the control end of the first NMOS transistor receives one of the differential input signals, and the control end of the second NMOS transistor receives the other of the differential input signals, the first common source and common gate structure includes a third NMOS transistor and a fourth NMOS transistor, the control ends of the third NMOS transistor and the fourth NMOS transistor are connected and receive the second bias voltage, the second end of the third NMOS transistor is connected to the first end of the first NMOS transistor, the first end of the third NMOS transistor provides one of the first pair of differential currents, the second end of the fourth NMOS transistor is connected to the first end of the second NMOS transistor, and the first end of the fourth NMOS transistor provides the other of the first pair of differential currents.

[0008] Optionally, the second input pair includes a first PMOS transistor and a second PMOS transistor, a common node between the first end of the first PMOS transistor and the first end of the second PMOS transistor is connected to the second tail current source, the control end of the first PMOS transistor receives one of the differential input signals, and the control end of the second PMOS transistor receives the other of the differential input signals, the second common source and common gate structure includes a third PMOS transistor and a fourth PMOS transistor, the control ends of the third PMOS transistor and the fourth PMOS transistor are connected and receive the first bias voltage, the first end of the third PMOS transistor is connected to the second end of the first PMOS transistor, and the second end of the third PMOS transistor provides one of the second pair of differential currents, the first end of the fourth PMOS transistor is connected to the second end of the second PMOS transistor, and the second end of the fourth PMOS transistor provides the other of the second pair of differential currents.

[0009] Optionally, the subsequent circuit includes a resistor and / or a current mirror and / or a diode.

[0010] Optionally, the post-stage circuit is multiplexed as an output stage circuit of an operational amplifier.

[0011] Optionally, the output stage circuit comprises: an amplifying unit, configured to provide a differential first signal and a second signal according to the differential current; and an output unit, configured to provide an output signal at an output node according to the first signal and the second signal.

[0012] Optionally, the amplification unit includes: a third cascode structure, used to receive a first pair of differential currents provided by the first cascode structure, and provide a first signal based on the first pair of differential currents; and a fourth cascode structure, used to receive a second pair of differential currents provided by the second cascode structure, and provide a second signal based on the second pair of differential currents. The output unit includes: a push-pull common source structure capable of achieving rail-to-rail output, and an output bias module that controls the push-pull common source structure to achieve class AB operation.

[0013] Optionally, the third common-source common-gate structure includes: the third common-source common-gate structure includes: a fifth PMOS transistor and a seventh PMOS transistor connected to the control end, and a sixth PMOS transistor and an eighth PMOS transistor connected to the control end, the control end of the fifth PMOS transistor is connected to the second end of the sixth PMOS transistor, the first end is connected to the positive power rail, the second end is connected to the first end of the sixth PMOS transistor and receives one of the first pair of differential currents, the control end of the sixth PMOS transistor receives a first control voltage, the first end of the seventh PMOS transistor is connected to the positive power rail, the second end is connected to the first end of the eighth PMOS transistor and receives the other of the first pair of differential currents, and the second end of the eighth PMOS transistor provides the first signal.

[0014] Optionally, the fourth cascode structure includes: the fourth cascode structure includes: a fifth NMOS transistor and a seventh NMOS transistor connected to the control end, and a sixth NMOS transistor and an eighth NMOS transistor connected to the control end, the control end of the fifth NMOS transistor receives the second control voltage, the first end is connected to the control end of the sixth NMOS transistor, the second end is connected to the first end of the sixth NMOS transistor and receives one of the second pair of differential currents, the second end of the sixth NMOS transistor is connected to the negative power rail, the first end of the seventh NMOS transistor provides the second signal, the second end is connected to the first end of the eighth NMOS transistor and receives the other of the second pair of differential currents, and the second end of the eighth NMOS transistor is connected to the negative power rail.

[0015] Optionally, the push-pull common source structure includes a PMOS output tube and an NMOS output tube.

[0016] The output bias module includes: a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor, wherein a common node between a first end of the ninth PMOS transistor and a first end of the ninth NMOS transistor is connected to a second end of the sixth PMOS transistor, a common node between a second end of the ninth PMOS transistor and a second end of the ninth NMOS transistor is connected to a first end of the fifth NMOS transistor, a common node between a first end of the tenth PMOS transistor and a first end of the tenth NMOS transistor is connected to a second end of the eighth PMOS transistor, a common node between a second end of the tenth PMOS transistor and a second end of the tenth NMOS transistor is connected to a first end of the seventh NMOS transistor, a control end of the ninth NMOS transistor and a control end of the tenth NMOS transistor receive a third control voltage, a control end of the ninth PMOS transistor and a control end of the tenth PMOS transistor receive a fourth control voltage, and the third control voltage and the fourth control voltage are differential signals.

[0017] According to the input stage circuit provided by the present invention, the bias voltage of the first cascode structure follows the first terminal voltage of the second input pair of tubes (the first terminal voltage of the PMOS transistor), and the bias voltage of the second cascode structure follows the first terminal voltage of the first input pair of tubes (the first terminal voltage of the NMOS transistor). Self-biasing of the first cascode structure and the second cascode structure can be achieved without an additional bias circuit, which is beneficial to reducing the power consumption of the input stage circuit and can also improve the following speed of the cascode structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic circuit diagram showing an input stage circuit provided by the present invention;

[0020] Figure 2 A schematic structural diagram of an operational amplifier provided by the present invention is shown;

[0021] Figure 3 Show Figure 2 Schematic circuit diagram of the output stage circuit. DETAILED DESCRIPTION

[0022] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0023] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0024] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0025] In the present invention, the MOSFET includes a first terminal, a second terminal and a control terminal, and in the on state of the MOSFET, current flows from the first terminal to the second terminal. The first terminal, the second terminal and the control terminal of the P-type MOSFET are the source, the drain and the gate, respectively, and the first terminal, the second terminal and the control terminal of the N-type MOSFET are the drain, the source and the gate, respectively.

[0026] Figure 1 FIG. 2 shows a schematic structural diagram of an input stage circuit provided by the present invention. Figure 1 The input stage circuit 100 provided by the present invention is connected between the positive power rail and the negative power rail, and is used to provide a differential current to the subsequent stage circuit according to a differential input signal. The differential input signal includes, for example, a first input signal INN and a second input signal INP, and the differential current includes, for example, a first pair of differential currents Iout1 and Iout2 and a second pair of differential currents Iout3 and Iout4. The positive power rail receives a power supply voltage VDD, and the negative power rail receives a ground voltage GND, and the power supply voltage VDD is higher than the ground voltage GND. For example, VDD is approximately 5V, and the ground voltage is approximately 0V.

[0027] Continue to refer Figure 1 , the input stage circuit 100 comprises:

[0028] The first input pair of transistors 120, the first cascode structure 130 and the first tail current source 110 adapted to be connected to the first input pair of transistors 120, the first cascode structure 130 is connected to the subsequent circuit to provide a first pair of differential currents. Figure 1 , the first pair of differential currents includes a first output current Iout1 and a second output current Iout2.

[0029] The second input pair of transistors 150, the second cascode structure 160 and the second tail current source 140 adapted to be connected to the second input pair of transistors 150, the second cascode structure 160 is connected to the subsequent circuit to provide a second pair of differential currents. Figure 1 , the second pair of differential currents includes a third output current Iout3 and a fourth output current Iout4.

[0030] Among them, in order to achieve self-biasing of the common source and common gate structure, in the input stage circuit 100 provided by the present invention, the common node of the first tail current source 110 and the first input pair of tubes 120 provides a first bias voltage (i.e., point B voltage) to the second common source and common gate structure 160, and the common node of the second tail current source 140 and the second input pair of tubes 150 provides a second bias voltage (i.e., point A voltage) to the first common source and common gate structure 130.

[0031] It should be understood that the first current source 110, the first input pair of transistors 120, the first cascode structure 130, the second current source 140, the second input pair of transistors 150 and the second cascode structure 160 can be implemented using any related circuits in the prior art. For example, the first input pair of transistors 120 and / or the second input pair of transistors 150 may also be implemented by transistors, which is not excessively limited or described in the present invention.

[0032] As an example, in Figure 1 In the illustrated embodiment, the first tail current source 110 includes a single NMOS transistor M1 controlled by a voltage B1, wherein a first terminal of the NMOS transistor M1 provides a first current, and a second terminal is connected to a negative power rail. The second tail current source 140 includes a single PMOS transistor M2 controlled by a voltage B2, wherein a first terminal of the PMOS transistor M2 is connected to a positive power rail, and a second terminal provides a second current. The first input pair 120 and the first cascode structure 130 adapted thereto provide a first pair of differential currents according to the first current, and the second input pair 150 and the second cascode structure 160 adapted thereto provide a second pair of differential currents according to the second current.

[0033] The first input pair transistor 120 includes a first NMOS transistor NM1 and a second NMOS transistor NM2. The first cascode structure 130 includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4. The control terminal of the third NMOS transistor NM3 receives a second bias voltage, the first terminal is connected to the subsequent circuit to provide one of the first pair of differential currents (for example, the first output current Iout1), the second terminal is connected to the first terminal of the first NMOS transistor, the second terminal of the first NMOS transistor is connected to the first current source 110, and the control terminal receives the first input signal INN. The control terminal of the fourth NMOS transistor receives a second bias voltage, the first terminal is connected to the subsequent circuit to provide the other of the first pair of differential currents (for example, the second current Iout2), the second terminal is connected to the first terminal of the second NMOS transistor, the second terminal of the second NMOS transistor is connected to the first current source 110, and the control terminal receives the second input signal INP.

[0034] The second input pair transistor 150 includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The second cascode structure 160 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4. The control end of the first PMOS transistor PM1 receives the first input signal INN, the first end is connected to the second current source 140, the second end is connected to the first end of the third PMOS transistor PM3, the control end of the third PMOS transistor PM3 receives the first bias voltage, and the second end is connected to the subsequent circuit to provide one of the second pair of differential currents (for example, the third current Iout3). The control end of the second PMOS transistor PM2 receives the second input signal INP, the first end is connected to the second current source 140, the second end is connected to the first end of the fourth PMOS transistor PM4, the control end of the fourth PMOS transistor PM4 receives the first bias voltage, and the second end is connected to the subsequent circuit to provide the other of the second pair of differential currents (for example, the fourth current Iout4).

[0035] The second bias voltage is determined by the second input pair transistor 150 and can be specifically expressed by the following formula (1):

[0036] (1)

[0037] Among them, V A is the second bias voltage, INN is the first input signal, INP is the second input signal, V GSPis the gate-source voltage when the PMOS transistor is turned on. It should be understood that the PMOS transistors in the second input pair 150 are of the same type, and the PMOS transistors in the second cascode structure 160 are of the same type, so the gate-source voltages of the first PMOS transistor PM1 and the second PMOS transistor PM2 when they are turned on are the same. In other words, the gate-source voltages of the first PMOS transistor PM1 or the second PMOS transistor PM2 when they are turned on are both V GSP Similarly, when the first PMOS transistor PM1 or the second PMOS transistor PM2 is turned on, the source-drain voltage is the same and is represented by V SDP The gate-source voltage of the first NMOS transistor NM1 or the second NMOS transistor NM2 when it is turned on is the same. Indicates that the drain-source voltage is also the same and is expressed as V DSN It is indicated that no further elaboration will be given below.

[0038] In addition, the voltage at point A can also be expressed by the following formula (2):

[0039] (2)

[0040] Among them, V A is the second bias voltage, INN is the first input signal, INP is the second input signal, V DSN is the drain-source voltage when the NMOS transistor is turned on.

[0041] Based on the differential characteristic, the input stage circuit 100 can work effectively only when the first input signal INN and the second input signal INP are close to each other. The voltage at this time is recorded as Vin, that is:

[0042] Vin = INN ≈ INP (3)

[0043] Combining the above equations (1), (2) and (3), we can get:

[0044] (4)

[0045] Among them, V GSP is the gate-source voltage when the PMOS transistor is turned on, V DSN is the drain-source voltage when the NMOS transistor is turned on.

[0046] The first bias voltage is determined by the first input pair transistor 120 and can be specifically expressed by the following formula (5):

[0047] (5)

[0048] Among them, V B is the first bias voltage, INN is the first input signal, INP is the second input signal, V GSNis the gate-source voltage when the NMOS transistor is turned on.

[0049] In addition, the voltage at point B can also be expressed by the following formula (6):

[0050] (6)

[0051] Among them, V B is the first bias voltage, INN is the first input signal, INP is the second input signal, V SDP is the source-drain voltage when the PMOS transistor is turned on.

[0052] Combining the above equations (3), (5) and (6), we can obtain:

[0053] (7)

[0054] Among them, V GSN is the gate-source voltage when the NMOS transistor is turned on, V DSP is the drain-source voltage when the PMOS transistor is turned on.

[0055] Furthermore, according to the saturation region current formula, if:

[0056] (8)

[0057] The device is in the saturation region. GS When the difference is not big, the turned-on NMOS transistor and the turned-on PMOS transistor are biased in the saturation region. And even if the first input signal INN / the second input signal INP is close to the positive rail / the negative rail of the power supply, it will not affect the input stage circuit.

[0058] Furthermore, when the differential first input signal INN and the second input signal INP change rapidly (at least supporting a slew rate of 80 MV / s at a total current of 160 μA, with the pull-up speed and the pull-down speed being symmetrical), the first terminal voltages of the corresponding transistors in the first input pair 120 / the second input pair 150 will also respond rapidly and follow the changes, so the above formula still holds true.

[0059] In summary, according to the input stage circuit provided by the present invention, the bias voltage of the first cascode structure follows the first terminal voltage of the second input pair of tubes (the first terminal voltage of the PMOS transistor), and the bias voltage of the second cascode structure follows the first terminal voltage of the first input pair of tubes (the first terminal voltage of the NMOS transistor). The self-biasing of the first cascode structure and the second cascode structure can be realized without an additional bias circuit, which is conducive to reducing the power consumption of the input stage circuit and improving the following speed of the cascode structure. At the same time, the self-biased first cascode structure and the second cascode structure are more convenient to cooperate with the gain circuit in the subsequent circuit to achieve multi-stage gain.

[0060] Furthermore, in the embodiments of the present invention, there are no excessive restrictions on the subsequent circuits, for example, the subsequent circuits may include resistors and / or current mirrors and / or diodes, etc. By adjusting the circuit structure of the subsequent circuits, the rail-to-rail input stage circuit provided by the present invention can be applied to different analog circuit structures such as operational amplifiers, comparators, digital-to-analog converters, and analog-to-digital converters.

[0061] For example, taking the input stage circuit 100 as an input stage circuit of an operational amplifier, Figure 2 The schematic block diagram of the operational amplifier is shown in FIG. Figure 3 Show Figure 2 The schematic circuit diagram of the output stage circuit 200 is shown below. Figure 2 and Figure 3 The application of the input stage circuit provided by the present invention in an operational amplifier is further introduced.

[0062] refer to Figure 2 The operational amplifier 10 includes an input stage circuit 100 and an output stage circuit 200 (ie, the above-mentioned post-stage circuit) respectively connected between a positive power rail and a negative power rail, wherein the positive power rail receives a power supply voltage VDD, and the negative power rail receives a ground voltage GND.

[0063] The input stage circuit 100 receives a pair of differential input signals (i.e., the first input signal INN and the second input signal INP) and provides a differential current Iout (i.e., the first pair of differential currents and the second pair of differential currents) to the output stage circuit 200. The specific structure of the input stage circuit 100 is as described above and will not be repeated here.

[0064] The output stage circuit 200 provides an output signal Vout according to the differential current Iout. The output stage circuit 200 can be implemented by any related circuit in the prior art, for example, Figure 3 The output stage circuit 200 includes: an amplifying unit for providing a first signal and a second signal (the first signal and the second signal are differential signals) according to a differential current Iout, and an output unit for providing an output signal at an output node according to the first signal and the second signal.

[0065] Specifically, refer to Figure 3 The amplification unit includes a third cascode structure 210 for receiving a first pair of differential currents (such as the first output current Iout1 and the second output current Iout2 mentioned above) and providing a first signal S1 according to the first pair of differential currents, and a fourth cascode structure 230 for receiving a second pair of differential currents (such as the third output current Iout3 and the fourth output current Iout4 mentioned above) and providing a second signal S2 according to the second pair of differential currents. The output unit includes a push-pull common source structure 240 capable of realizing rail-to-rail output, and an output bias module 230 for controlling the push-pull common source structure to realize a class AB working mode.

[0066] For example, the third cascode structure 210 includes: a fifth PMOS transistor PM5 and a seventh PMOS transistor PM7 connected to the control end, and a sixth PMOS transistor PM6 and an eighth PMOS transistor PM8 connected to the control end. The fourth cascode structure 220 includes: a fifth NMOS transistor NM5 and a seventh NMOS transistor NM7 connected to the control end, and a sixth NMOS transistor NM6 and an eighth NMOS transistor NM8 connected to the control end. The output bias module 230 includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a ninth NMOS transistor NM9 and a tenth NMOS transistor NM10. The push-pull common source structure 240 includes a PMOS output tube PM11 and an NMOS output tube NM11.

[0067] Specifically, a common node of the first end of the ninth PMOS transistor PM9 and the first end of the ninth NMOS transistor NM9 is a first end of the output bias module 230, a common node of the first end of the tenth PMOS transistor PM10 and the first end of the tenth NMOS transistor NM10 is a second end of the output bias module 230, a common node of the second end of the ninth PMOS transistor PM9 and the second end of the ninth NMOS transistor NM9 is a third end of the output bias module 230, and a common node of the second end of the tenth PMOS transistor PM10 and the second end of the tenth NMOS transistor NM10 is a fourth end of the output bias module 230.

[0068] Among them, the control end of the ninth NMOS transistor NM9 and the control end of the tenth NMOS transistor NM10 receive the third control voltage VB3, the control end of the ninth PMOS transistor and the control end of the tenth PMOS transistor receive the fourth control voltage VB4, and the third control voltage VB3 and the fourth control voltage VB4 are differential signals.

[0069] The control end of the fifth PMOS transistor PM5 is connected to the second end of the sixth PMOS transistor PM6, the first end is connected to the positive power rail, the second end is connected to the first end of the sixth PMOS transistor PM6 and receives one of the first pair of differential currents (for example, the second output current Iout2), the control end of the sixth PMOS transistor PM6 receives the first control signal VB1, and the second end is connected to the first end of the output bias module 230. The first end of the seventh PMOS transistor PM7 is connected to the positive power rail, the second end is connected to the first end of the eighth PMOS transistor PM8 and receives the other of the first pair of differential currents (for example, the first output current Iout1), and the second end of the eighth PMOS transistor PM8 is connected to the second end of the output bias module 220 and provides the first signal S1.

[0070] The control terminal of the fifth NMOS transistor NM5 receives the second control signal VB2, the first terminal is connected to the third terminal of the output bias module 230, the second terminal is connected to the first terminal of the sixth NMOS transistor NM6 and receives one of the second pair of differential currents (for example, the fourth output current Iout4), and the second terminal of the sixth NMOS transistor NM6 is connected to the negative power rail. The first terminal of the seventh NMOS transistor NM7 is connected to the fourth terminal of the output bias module 230 and provides the second signal S2, the second terminal is connected to the first terminal of the eighth NMOS transistor NM8 and receives the other of the second pair of differential currents (for example, the third output current Iout3), and the second terminal of the eighth NMOS transistor NM8 is connected to the negative power rail.

[0071] The control end of the PMOS output tube PM11 receives the first signal S1, the first end is connected to the positive power rail, the second end is connected to the first end of the NMOS output tube NM11 and provides an output signal Vout (that is, the common node of the PMOS output tube PM11 and the NMOS output tube NM11 is the output node of the output stage circuit 200). The control end of the NMOS output tube NM11 receives the second signal S2, and the second end is connected to the negative power rail.

[0072] The operational amplifier provided according to the present application also includes the input stage circuit 100 provided by the present application, and thus also has the above-mentioned beneficial effects of the present application. At the same time, since the input stage circuit 100 includes the self-biased first cascode structure and the second cascode structure, it can be more simply coordinated with the third cascode structure and the fourth cascode structure to achieve multi-stage gain, thereby improving the linearity, stability, and total gain performance of the operational amplifier.

[0073] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to specific embodiments. Obviously, according to the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. An input stage circuit for providing a differential current to a subsequent stage circuit according to a differential input signal, wherein: The input stage circuit comprises: A first input pair of transistors, a first common-source common-gate structure and a first tail current source adapted to be connected to the first input pair of transistors; and A second input pair of transistors, a second common-source common-gate structure adapted to be connected to the second input pair of transistors, and a second tail current source, A first bias voltage is provided to the second cascode structure through a common node of the first input pair and the first tail current source, and a second bias voltage is provided to the first cascode structure through a common node of the second input pair and the second tail current source.

2. The input stage circuit according to claim 1, wherein: The first input pair includes a first NMOS transistor and a second NMOS transistor, a common node between the second end of the first NMOS transistor and the second end of the second NMOS transistor is connected to the first tail current source, a control end of the first NMOS transistor receives one of the differential input signals, and a control end of the second NMOS transistor receives the other of the differential input signals, The first common-source common-gate structure includes a third NMOS transistor and a fourth NMOS transistor, wherein the control ends of the third NMOS transistor and the fourth NMOS transistor are connected and receive the second bias voltage, the second end of the third NMOS transistor is connected to the first end of the first NMOS transistor, the first end of the third NMOS transistor provides one of the first pair of differential currents, the second end of the fourth NMOS transistor is connected to the first end of the second NMOS transistor, and the first end of the fourth NMOS transistor provides the other of the first pair of differential currents.

3. The input stage circuit according to claim 1, wherein: The second input pair includes a first PMOS transistor and a second PMOS transistor, a common node between a first end of the first PMOS transistor and a first end of the second PMOS transistor is connected to the second tail current source, a control end of the first PMOS transistor receives one of the differential input signals, and a control end of the second PMOS transistor receives the other of the differential input signals, The second common-source common-gate structure includes a third PMOS transistor and a fourth PMOS transistor, wherein the control ends of the third PMOS transistor and the fourth PMOS transistor are connected and receive the first bias voltage, the first end of the third PMOS transistor is connected to the second end of the first PMOS transistor, the second end of the third PMOS transistor provides one of the second pair of differential currents, the first end of the fourth PMOS transistor is connected to the second end of the second PMOS transistor, and the second end of the fourth PMOS transistor provides the other of the second pair of differential currents.

4. The input stage circuit according to claim 1, wherein: The subsequent circuit includes a resistor and / or a current mirror and / or a diode.

5. The input stage circuit according to claim 1, wherein: The latter stage circuit is multiplexed as the output stage circuit of the operational amplifier.

6. The input stage circuit according to claim 5, wherein: The output stage circuit comprises: an amplifying unit, configured to provide a differential first signal and a second signal according to the differential current; and An output unit is used to provide an output signal at an output node according to the first signal and the second signal.

7. The input stage circuit according to claim 6, wherein: The amplification unit comprises: a third cascode structure, configured to receive the first pair of differential currents provided by the first cascode structure, and provide a first signal according to the first pair of differential currents; and a fourth cascode structure, configured to receive a second pair of differential currents provided by the second cascode structure, and provide a second signal according to the second pair of differential currents, The output unit comprises: a push-pull common source structure capable of realizing rail-to-rail output, and an output bias module for controlling the push-pull common source structure to realize a class AB working mode.

8. The input stage circuit according to claim 7, wherein: The third cascode structure includes: a fifth PMOS transistor and a seventh PMOS transistor connected to the control end, and a sixth PMOS transistor and an eighth PMOS transistor connected to the control end, The control end of the fifth PMOS transistor is connected to the second end of the sixth PMOS transistor, the first end is connected to the positive power rail, the second end is connected to the first end of the sixth PMOS transistor and receives one of the first pair of differential currents, and the control end of the sixth PMOS transistor receives a first control voltage. The first end of the seventh PMOS transistor is connected to the positive power rail, the second end is connected to the first end of the eighth PMOS transistor and receives the other path of the first pair of differential currents, and the second end of the eighth PMOS transistor provides the first signal.

9. The input stage circuit according to claim 8, wherein: The fourth cascode structure includes: a fifth NMOS transistor and a seventh NMOS transistor connected to the control end, and a sixth NMOS transistor and an eighth NMOS transistor connected to the control end, The control terminal of the fifth NMOS transistor receives the second control voltage, the first terminal is connected to the control terminal of the sixth NMOS transistor, the second terminal is connected to the first terminal of the sixth NMOS transistor and receives one of the second pair of differential currents, and the second terminal of the sixth NMOS transistor is connected to the negative power rail. The first end of the seventh NMOS transistor provides the second signal, the second end is connected to the first end of the eighth NMOS transistor and receives the other of the second pair of differential currents, and the second end of the eighth NMOS transistor is connected to the negative power rail.

10. The input stage circuit according to claim 9, wherein: The push-pull common source structure includes a PMOS output tube and an NMOS output tube. The output bias module includes: a ninth PMOS transistor, a tenth PMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor, A common node of the first end of the ninth PMOS transistor and the first end of the ninth NMOS transistor is connected to the second end of the sixth PMOS transistor, and a common node of the second end of the ninth PMOS transistor and the second end of the ninth NMOS transistor is connected to the first end of the fifth NMOS transistor, A common node of the first end of the tenth PMOS transistor and the first end of the tenth NMOS transistor is connected to the second end of the eighth PMOS transistor, and a common node of the second end of the tenth PMOS transistor and the second end of the tenth NMOS transistor is connected to the first end of the seventh NMOS transistor, The control end of the ninth NMOS transistor and the control end of the tenth NMOS transistor receive a third control voltage, the control end of the ninth PMOS transistor and the control end of the tenth PMOS transistor receive a fourth control voltage, and the third control voltage and the fourth control voltage are differential signals.

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