On-site Online Comparison Detection Device and Detection Method for Power Quality Monitoring Terminal

Abstract

The present invention provides an on-site online comparison detection device and a detection method for a power quality monitoring terminal. The method includes connecting the power quality monitoring terminal and the detection device through Ethernet; setting the whole hour moment T to start the test, and reading and recording the real-time data of the two devices every 3 s; setting the measured value of the power quality index of the high-precision power quality measurement device at the same moment as χ s , and the corresponding measured value of the power quality monitoring terminal is χ X . Calculate the corresponding fractal dimension, and calculate the fractal dimension error between the two devices. The on-site comparison detection can stop the test after all inspection points are completed. The present invention greatly reduces the detection difficulty of the power quality monitoring terminal, improves the detection efficiency, and reduces the human and material costs at the same time. It enables the periodic detection work of the power quality online monitoring terminal to be effectively carried out, thereby ensuring the measurement accuracy of various power quality indicators and escorting the safe, stable and economic operation of the power grid.

Description

Technical Field

[0001] The present invention relates to the technical field of on-site testing of power instruments, in particular to an on-site online comparison detection device and detection method for power quality monitoring terminals. Background Art

[0002] The operation management of power quality monitoring terminals is one of the tasks of power quality technical supervision. After long-term operation in a harsh electromagnetic environment, power quality monitoring terminals will inevitably experience a decline in reliability and measurement accuracy due to component aging and failure, resulting in a large amount of invalid and abnormal data. Therefore, regular detection is required.

[0003] Currently, there are two detection methods for power quality monitoring terminals: the standard source method and the comparison method. Both methods are mainly carried out in the laboratory. They belong to off-line detection and are usually implemented based on the standard source method in the laboratory.

[0004] For the already put-into-operation power quality monitoring devices, if off-line laboratory detection is still adopted in engineering, the following problems exist:

[0005] 1) The voltage circuit of the power quality monitoring terminal is taken from the voltage transformer of the substation, and the current circuit is connected in series with the current transformer of the substation. When carrying out periodic detection on the operating power quality monitoring terminal, there is a risk of open circuit (short circuit) on the secondary side of the current (voltage) transformer.

[0006] 2) When performing periodic detection on it according to the existing technology, there are mainly the following two implementation methods: One is to remove the power quality monitoring terminal and send it to the laboratory, then control the standard source to output power quality signals with specified parameters to the power quality monitoring terminal, and finally compare the measurement results of the power quality monitoring terminal with the standard signals to determine whether the measurement accuracy of the terminal is qualified. The disadvantage of this method is that multiple work tickets need to be opened for disassembling and assembling the power quality monitoring terminal back and forth. In addition, transportation is troublesome and time-consuming, so it takes a long time to complete one inspection, and the work efficiency is very low, seriously affecting the normal operation of the monitoring terminal. The other is to carry the standard source to the site and then remove the power quality monitoring terminal for on-site off-line detection. The disadvantage of this method is that the standard source (such as the FLUKE 6100 series) is usually large in volume and not easy to carry, and the instrument is very precise and easy to damage. Sometimes, several standard sources need to be carried together to form a three-phase circuit for detection. Although some portable standard sources (such as the CMC series standard sources produced by Omicron) are convenient to use, the accuracy of the output signals is relatively low. Especially for the generation of some high-order harmonic signals, it is not ideal, so it will inevitably affect the detection results of the monitoring terminal. Any of the above methods will inevitably require a great deal of manpower and material resources.

[0007] 3) Due to the characteristics of a large number and scattered installation of power quality monitoring terminals, it is difficult to effectively carry out the periodic detection work because the feasibility of implementing the laboratory off-line detection scheme is poor.

[0008] In summary, there are many deficiencies in the existing technology. Therefore, it is necessary to improve the existing detection technology for power quality monitoring terminals. Summary of the Invention

[0009] The purpose of the present invention is to provide an on-site online comparison detection device and method for power quality monitoring terminals, which can solve the problems of high cost, low efficiency, and poor feasibility of removal for regular inspection brought by laboratory off-line detection in the existing technology.

[0010] The purpose of the present invention is achieved through the following technical solutions:

[0011] In the first aspect, the present invention provides an on-site online comparison detection device for power quality monitoring terminals, including a signal conditioning unit, an A / D sampling unit, an ARM microprocessor unit, an FPGA unit, an external storage unit, a human-computer interaction unit, a multi-protocol communication unit, a high-precision time synchronization unit, and a power management unit; the input end of the signal conditioning unit inputs a voltage signal, and the output end of the signal conditioning unit is connected to the input end of the A / D sampling unit; the output end of the A / D sampling unit is connected to the first input end of the FPGA unit, and the output end of the high-precision time synchronization unit is connected to the second input end of the FPGA unit; the FPGA unit sends the sampling data sent by the A / D sampling unit and the time data sent by the high-precision time synchronization unit to the ARM microprocessor unit; the ARM microprocessor unit conducts data interaction with the external storage unit, the human-computer interaction unit, the multi-protocol communication unit, and the high-precision time synchronization unit respectively; the power management unit is a power supply unit.

[0012] Further, the signal conditioning unit includes a current-limiting resistor Ri, a sampling resistor Rs, a first operational amplifier, a capacitor C1, and two anti-aliasing filters; the voltage signal is input to one end of the current-limiting resistor Ri, and the other end of the current-limiting resistor Ri is connected to the inverting input end of the first operational amplifier, and the non-inverting input end of the first operational amplifier is grounded; the sampling resistor Rs is connected between the inverting input end and the output end of the first operational amplifier; the capacitor C1 is connected between the output end of the first operational amplifier and the ground to play a filtering role; the output end of the first operational amplifier is connected in series with two anti-aliasing filters and then outputs a signal to the A / D sampling unit.

[0013] Further, the anti-aliasing filter includes a resistor R1, a resistor R2, a resistor R3, a capacitor C2, a capacitor C3, and a second operational amplifier. One end of the resistor R1 serves as the input end of the anti-aliasing filter. The resistor R1 and the resistor R2 are connected in series and then connected to the non-inverting input end of the second operational amplifier. The inverting input end of the second operational amplifier is connected to the ground in series with the resistor R3. The capacitor C2 is connected between the series node of the resistor R1 and the resistor R2 and the inverting input end of the second operational amplifier. The capacitor C3 is connected between the non-inverting input end of the second operational amplifier and the ground. The output end of the second operational amplifier serves as the output end of the anti-aliasing filter.

[0014] Further, the A / D sampling unit includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a capacitor C4, a capacitor C5, a capacitor C6, a diode D1, a diode D2, a dual voltage comparator chip, a voltage-controlled oscillator, and a frequency divider. One end of the resistor R4 serves as the input end of the A / D sampling unit. The other end of the resistor R4 is connected to one end of the resistor R5, one end of the capacitor C4, and the positive input end of the dual voltage comparator chip. The other end of the resistor R5 and the other end of the capacitor C4 are grounded. The anode of the diode D1 and the cathode of the diode D2 are grounded, and the cathode of the diode D1 and the anode of the diode D2 are connected to the positive input end of the dual voltage comparator chip. The resistor R6 is connected between the negative input end of the dual voltage comparator chip and the ground. The output end of the dual voltage comparator chip is connected to the input end of the voltage-controlled oscillator after passing through the resistor R7. The output end of the voltage-controlled oscillator is connected to the clock input end of the frequency divider, and after being divided by the frequency divider, it is fed back to the phase detector input end of the voltage-controlled oscillator, and after being processed by the voltage-controlled oscillator, a frequency multiplication signal is output from the output end.

[0015] Further, the high-precision time synchronization unit receives time synchronization from a satellite, enabling the on-site online comparison detection device to be time-synchronized with the power quality monitoring terminal.

[0016] Further, the external storage unit is used to store waveforms and comparison data.

[0017] Further, the human-machine interaction unit uses Bluetooth communication for data input and result display of the on-site online comparison detection device.

[0018] In a second aspect, the present invention provides a method for on-site online comparison detection of a power quality monitoring terminal, including the following steps:

[0019] Step 1: Connect the power quality monitoring terminal to be detected and the detection device through Ethernet, set the parameters of the detection device, start the network precise time synchronization of the power quality monitoring terminal and the detection device, and carry out the verification of communication protocol consistency.

[0020] Step 2: Start the test. The real-time power grid signals are synchronously sent to the power quality monitoring terminal and the detection device, and the real-time data of the power quality monitoring terminal and the detection device are read and recorded at fixed intervals.

[0021] Step 3: Let the measured value of the power quality index of the detection device at the same moment be χ s , and the corresponding measured value of the power quality monitoring terminal be χX. Calculate the corresponding fractal dimension, and calculate the fractal dimension error between the power quality monitoring terminal and the detection device to obtain the final threshold. Use the threshold to determine whether the corresponding measured value of the power quality monitoring terminal is qualified.

[0022] Step 4: Repeat Step 3 until all inspection points of the on-site comparison detection are completed, and then stop the test.

[0023] Furthermore, the said Step 3 includes:

[0024] Step 301: Use the 2-power grid division method to divide the grid for the box dimension algorithm and calculate the box dimension.

[0025] Step 302: Use the structure function method based on the FCM algorithm to calculate the slope of the scale-free interval to obtain the fractal dimension.

[0026] Step 303: Use the W-M fractal function to calculate the fractal dimension error.

[0027] Step 304: Set the final threshold according to the fractal dimension error, and use the threshold to determine whether the corresponding measured value of the power quality monitoring terminal is qualified.

[0028] The on-site online comparison detection device and method for the power quality monitoring terminal of the present invention greatly reduce the detection difficulty of the power quality monitoring terminal, improve the detection efficiency, and at the same time reduce the human and material costs. It enables the periodic detection work of the power quality online monitoring terminal to be effectively carried out, thereby ensuring the measurement accuracy of various power quality indicators, truly implementing the power quality technical supervision work, and escorting the safe, stable and economic operation of the power grid. Description of the Drawings

[0029] Figure 1 It is the circuit block diagram of the on-site online comparison detection device for the power quality monitoring terminal of the present invention;

[0030] Figure 2 It is the circuit schematic diagram of the signal conditioning unit;

[0031] Figure 3 It is the circuit schematic diagram of the A / D sampling unit;

[0032] Figure 4 It is the circuit schematic diagram of the power management unit;

[0033] Figure 5 It is a block diagram for on-site comparison and detection of power quality monitoring devices;

[0034] Figure 6 It is a schematic diagram of the data flow for on-site comparison and detection of power quality monitoring devices. Specific implementation mode

[0035] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0036] The following uses specific examples to illustrate the implementation mode of the present disclosure. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative work fall within the scope of protection of the present disclosure.

[0037] Embodiment 1

[0038] The present invention provides an on-site online comparison and detection device for a power quality monitoring terminal, which can perform on-site comparison and detection on the power quality monitoring terminal without disassembling and transporting the power quality monitoring terminal to the laboratory, and the detection can be completed on-site.

[0039] As Figure 1 shown, the on-site online comparison and detection device for the power quality monitoring terminal includes a signal conditioning unit, an A / D sampling unit, an ARM microprocessor unit, an FPGA unit, an external storage unit, a human-computer interaction unit, a multi-protocol communication unit, a high-precision time synchronization unit, and a power management unit. The input end of the signal conditioning unit inputs a voltage signal, and the output end of the signal conditioning unit is connected to the input end of the A / D sampling unit. The output end of the A / D sampling unit is connected to the first input end of the FPGA unit, and the output end of the high-precision time synchronization unit is connected to the second input end of the FPGA unit. The FPGA unit sends the sampling data sent by the A / D sampling unit and the time data sent by the high-precision time synchronization unit to the ARM microprocessor unit. The ARM microprocessor unit performs data interaction with the external storage unit, the human-computer interaction unit, the multi-protocol communication unit, and the high-precision time synchronization unit respectively. The power management unit is a power supply unit that supplies power to the signal conditioning unit, the A / D sampling unit, the ARM microprocessor unit, the FPGA unit, the external storage unit, the human-computer interaction unit, the multi-protocol communication unit, and the high-precision time synchronization unit.

[0040] The functions of each unit circuit are as follows: The signal conditioning unit filters and conditions the input voltage signal into a suitable signal and sends it to the A / D sampling unit for sampling.

[0041] After the A / D sampling unit uses zero-crossing detection and phase-locked loop circuit to achieve synchronous sampling of three-phase voltage and current signals, the sampled data is sent to the FPGA unit.

[0042] The FPGA unit controls the satellite timing of the A / D sampling unit and sends the sampled data and the time data sent by the high-precision timing unit to the ARM microprocessor. In the embodiment of the present application, the FPGA unit uses the chip DS181 of XILINX Corporation. This chip performs data interaction with the A / D sampling unit through a serial bus; this chip performs data interaction with the ARM microprocessor unit through a PCIE bus.

[0043] The ARM microprocessor unit, as the core of the entire device, processes time data, sampled data, communication data, human-computer interaction data, and storage data.

[0044] Preferably, the ARM microprocessor unit includes a human-computer interaction component, a network timing component, a data acquisition component, an accuracy calculation component, and a detection report component. The network timing component obtains the high-precision time from satellite timing in the FPGA unit and uses this time as the clock source of the entire system, setting it to the server mode. The monitoring terminal operating in the client mode requests time synchronization operation with the network timing component through the high-precision timing unit; the data acquisition component obtains the power quality monitoring index data of the monitoring terminal through the multi-protocol communication unit, and at the same time obtains the power quality monitoring index data at the same time point and monitoring point through the internal bus, and transfers the above two groups of data flows to the accuracy calculation component; the accuracy calculation component then performs fractal dimension calculation on the two groups of power quality monitoring data obtained to determine whether the accuracy of the monitoring terminal meets the requirements; the detection report component outputs the accuracy result of the on-site detection of the monitoring terminal in the form of a report; the human interaction component interacts with the above other components for data input, control startup, and result display.

[0045] The ARM microprocessor unit uses the Rockchip RK3399 chip, which has a CPU and a GPU. The CPU adopts the big.LITTLE heterogeneous core architecture, with a dual-Cortex-A72 big core + four-Cortex-A53 small core structure, which has been greatly optimized for integers, floating-point numbers, memory, etc., and has a revolutionary improvement in terms of overall performance, power consumption, and core area. The GPU uses a quad-core ARM new-generation high-end graphics processor Mali-T860, which integrates more bandwidth compression technologies, such as intelligent stacking, ASTC, local pixel storage, etc., and also supports more graphics and computing interfaces, with an overall performance improvement of 45% compared to the previous generation. The ARM microprocessor unit uses an embedded LINUX operating system.

[0046] The external storage unit is used to store waveforms, comparison data, etc. In the embodiments of this application, the external storage unit uses an SD card, and data reading, storage, deletion, etc. are performed through an SPI connection with the ARM microprocessor unit.

[0047] The human-computer interaction unit serves as the data input and result display of the detection device. The human-computer interaction unit uses Bluetooth communication and exchanges data with the ARM microprocessor unit through an APP and an application program, eliminating the device screen, facilitating development, and providing the reliability of the device operation. In the embodiments of this application, the human-computer interaction unit uses a Bluetooth module HC-05, which is connected to the serial port of the ARM microprocessor unit, allowing the ARM microprocessor unit to communicate with other devices through a Bluetooth connection. The Bluetooth module HC-05 itself can operate in master mode and slave mode and can be used for various applications. The Bluetooth module HC-05 supports the use of standard AT commands through TX and RX pins. After the Bluetooth module HC-05 is started, any Bluetooth device should be able to discover it and can connect to the device using a standard password. After the connection is established, data is transmitted through the Bluetooth module HC-05 and converted into a serial stream, which is then read by the ARM microprocessor connected to the Bluetooth module HC-05. The way of sending data from the ARM microprocessor is the opposite.

[0048] The multi-protocol communication unit is compatible with the communication protocols of devices from different manufacturers and different models and the master station, and realizes the acquisition of on-site comparison detection data. In the embodiments of this application, the multi-protocol communication unit uses the standard IEC61850 protocol and is compatible with other private protocols to meet the data communication requirements of on-site online comparison detection of power quality monitoring devices from different manufacturers and different models.

[0049] The high-precision time synchronization unit is the clock source of the entire detection device. It receives time signals from satellites to keep the device in unified time, and synchronizes the time of the power quality monitoring terminal through the network for accurate on-site comparison and detection operations. In the embodiments of this application, the high-precision time synchronization unit includes a satellite time synchronization circuit and an IEEE 1588 circuit. The satellite time synchronization circuit uses the u-blox module MAX-M8Q, which supports GPS / Galileo / GLONASS / Beidou, can simultaneously acquire and track different GNSS (Global Navigation Satellite) systems, and enables the device to obtain accurate time authorization. The satellite time synchronization circuit and the FPGA unit exchange data through a serial bus. The IEEE 1588 circuit uses the fourth-generation chip AR8031 of Qualcomm, which belongs to the single-port, 10 / 100 / 1000 Mbps Ethernet physical layer, supports IEEE 1588v2 and synchronous Ethernet timing. The IEEE 1588 circuit and the ARM microprocessor unit exchange data through a parallel bus. SNTP is a pure software function that implements the two functions of hardware IEEE 1588 and SNTP, and can meet the time synchronization request services for on-site online comparison and detection of power quality monitoring devices of different manufacturers and models.

[0050] The power management unit is the power source of the entire detection device, providing power for each unit and module to operate. The power management unit is designed with a secondary power supply scheme, using DC-DC conversion to generate the required power voltages of 5V and 3.3V. Since the voltage drop at the power input is large and the power requirement is high, if a linear power supply is used, not only will there be a large heat loss in the linear voltage regulator during operation, but its working efficiency will also be very low. Therefore, a switching power supply conversion method is adopted for each power supply. A switching power supply controls a switching transistor through a circuit to perform high-speed conduction and cut-off. It converts direct current into high-frequency alternating current and provides it to a transformer for voltage conversion, thereby generating the required set of one or more voltages. The switching power supply has low power consumption, and the average working efficiency can reach more than 90% at most. The generation of the 5V voltage uses the LM2576 of National Semiconductor Corporation. This chip belongs to a 3A current output step-down switching integrated voltage regulator, which contains a fixed-frequency oscillator and a reference voltage regulator, and has a complete protection circuit, including current limiting and thermal judgment circuits, etc. The circuit is as Figure 4 shown.

[0051] Considering that there is a large demand for 3.3V voltage in the design, such as the signal conditioning unit, A / D sampling unit, ARM microprocessor unit, FPGA unit, external storage unit, human-computer interaction unit, and high-precision time synchronization unit all require 3.3V voltage as the power supply voltage. Therefore, in the design, the ISL6443 chip of Intersil Corporation is used to generate 3.3V voltage. This chip is a high-performance three-way output controller, and each output can be as low as 0.8V. The output voltage of LM2576 is used as the input voltage of ISL6443 to generate three-way 3.3V voltage. Two pulse width modulations (PWMs) are 180° out-of-phase synchronous, reducing the effective values of input current and harmonic voltage. At the same time, there are overcurrent protection and overheat protection, avoiding damage to the DC-DC components in the case of output overload / short circuit.

[0052] Further, in a preferred embodiment of the present application, the circuit schematic diagram of the signal conditioning unit is as Figure 2 shown. It includes a current-limiting resistor Ri, a sampling resistor Rs, an operational amplifier OP07, a capacitor C1, and two anti-aliasing filters. The voltage signal on the secondary side of the voltage transformer is input to one end of the current-limiting resistor Ri after being transformed. The other end of the current-limiting resistor Ri is connected to the inverting input terminal of the operational amplifier OP07, and the non-inverting input terminal of the operational amplifier OP07 is grounded. The sampling resistor Rs is connected between the inverting input terminal and the output terminal of the operational amplifier OP07. The capacitor C1 is connected between the output terminal of the operational amplifier OP07 and the ground, playing a filtering role. The output terminal of the operational amplifier OP07 is connected in series with two anti-aliasing filters and then outputs a signal to the A / D sampling unit.

[0053] The anti-aliasing filter includes a resistor R1, a resistor R2, a resistor R3, a capacitor C2, a capacitor C3, and an operational amplifier AD706. One end of the resistor R1 is used as the input terminal of the anti-aliasing filter. The resistor R1 and the resistor R2 are connected in series and then connected to the non-inverting input terminal of the operational amplifier AD706. The inverting input terminal of the operational amplifier AD706 is connected to the ground in series with the resistor R3. The capacitor C2 is connected between the series node of the resistor R1 and the resistor R2 and the inverting input terminal of the operational amplifier AD706. The capacitor C3 is connected between the non-inverting input terminal of the operational amplifier AD706 and the ground. The output terminal of the operational amplifier AD706 is used as the output terminal of the anti-aliasing filter.

[0054] The working principle of the signal conditioning unit is as follows: in the voltage loop, a precision resistor voltage divider is used to convert the 57.74V voltage signal on the secondary side of the voltage transformer into a 0.05V voltage signal. In the current loop, a high-precision clamp-on current sensor HIOKI 9694 is used to convert the 5A current signal output on the secondary side of the PT into a 0.05V voltage signal. Then, the 0.05V voltage signals of the above voltage loop and current loop are sent to the operational amplifier OP07 chip after passing through the current-limiting resistor Ri, and a follower is established to increase the input impedance and reduce the output impedance to improve the load-carrying capacity. Both the current-limiting resistor Ri and the sampling resistor Rs are 2.5kΩ. To prevent high-frequency signals from causing spectral aliasing during A / D sampling, a two-stage anti-aliasing filter is used to filter the signal output by the operational amplifier OP07. The operational amplifier used in the anti-aliasing filter is the AD706 chip.

[0055] Further, in a preferred embodiment of the present application, the A / D sampling unit is as Figure 3 shown. It includes resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, capacitor C4, capacitor C5, capacitor C6, diode D1, diode D2, dual voltage comparator chip LM393, voltage-controlled oscillator CD4046, and frequency divider CD4040. One end of resistor R4 serves as the input end of the A / D sampling unit. The other end of resistor R4 is connected to one end of resistor R5, one end of capacitor C4, and the positive input end of the dual voltage comparator chip LM393. The other ends of resistor R5 and capacitor C4 are grounded. The anode of diode D1 and the cathode of diode D2 are grounded, and the cathode of diode D1 and the anode of diode D2 are connected to the positive input end of the dual voltage comparator chip LM393. Resistor R6 is connected between the negative input end of the dual voltage comparator chip LM393 and the ground. The output end of the dual voltage comparator chip LM393 is connected to the input end 14 of the voltage-controlled oscillator CD4046 after passing through resistor R7. The output end 4 of the voltage-controlled oscillator CD4046 is connected to the clock input end 2 of the frequency divider CD4040, and after being divided by the frequency divider, it is fed back to the phase detector input end 3 of the voltage-controlled oscillator CD4046, and a frequency-multiplied signal is output from the output end after being processed by the voltage-controlled oscillator CD4046.

[0056] The A / D sampling unit uses a high-precision 24-bit high-precision A / D sampling chip AD7768, which is much higher than the 16-bit A / D sampling accuracy of current mainstream monitoring devices. At the same time, a zero-crossing detection and phase-locked loop circuit are designed to meet the synchronous sampling of three-phase voltage and current. The zero-crossing detection circuit uses the dual voltage comparator chip LM393, and the phase-locked loop circuit uses the chip CD4046.

[0057] The power frequency signal and the locked square wave of about 50 Hz output by the frequency division circuit enter the phase detector together for phase comparison. The comparison result output by the phase detector contains a deviation voltage component, which is filtered by the loop filter to generate a control voltage and applied to the input end of the voltage-controlled oscillator; the oscillation output generated by it becomes a locked square wave after frequency division and re-enters the phase detection end to perform phase comparison with the power frequency signal. When the phase difference between the two signals deviates from the standard, the loop filter must output a deviation correction voltage to cause the voltage-controlled oscillator to generate a frequency change so that the two signals are phase-locked at the standard position. Since the voltage-controlled oscillator is in this closed-loop system, after the two signals are locked, the oscillation frequency output by its voltage-controlled oscillator must be an integer multiple of the power frequency signal frequency.

[0058] Figure 3 The input of the In is the voltage of phase A. First, it is divided by resistors R4 and R5, and the square wave output by the signal comparison of LM393 is sent to the voltage-controlled oscillator CD4046. The output of CD4046 is sent to the clock input end of the frequency divider CD4040. After frequency division, it is fed back to the phase detector input end of CD4046 to perform phase comparison with the input signal to be frequency-doubled. The obtained phase difference generates a control voltage through a low-pass filter to adjust the output oscillation frequency of the voltage-controlled oscillator. When the frequencies and phases of the two input ends of the phase detector are the same (i.e., phase-locked), the output frequency of the voltage-controlled oscillator is the frequency after frequency doubling.

[0059] The frequency tracking circuit is composed of a dedicated integrated phase-locked chip CD4046 and a frequency divider chip CD4040 to realize the phase frequency doubling of the power frequency signal, and the frequency division ratio is 1 / 4096. When the power frequency signal is exactly 50 Hz, the phase-locked frequency multiplication of this circuit is 50×4096 = 204.8 kHz, which is equivalent to having 4096 pulses within one power frequency cycle.

[0060] The present invention also provides a field on-line comparison detection method for a power quality monitoring terminal, which can perform on-site on-line comparison detection of the accuracy of the power quality monitoring terminal without disconnecting the wires and under live conditions on-site. The on-site on-line comparison detection block diagram is shown in Figure 5. Specifically, the on-site on-line comparison detection method for the power quality monitoring terminal includes the following steps:

[0061] Step 1: Connect the power quality monitoring terminal to be detected and the detection device through Ethernet, set the parameters of the detection device, start the network precise time synchronization, and carry out the verification of the communication protocol consistency.

[0062] It is necessary to temporarily disconnect the connection network cable between the power quality monitoring terminal and the power quality on-line monitoring system, and connect the power quality monitoring terminal and the measuring device according to Figure 5 Connect the power quality monitoring terminal and the measuring device.

[0063] Set parameters such as the IP address of the detection device, the transformation ratio of the instrument transformer, the data upload time interval, and the statistical record period. Start network precise time synchronization and conduct communication protocol consistency verification to ensure a high degree of consistency between the real-time power grid signals received by the detection device and the power quality monitoring terminal.

[0064] The network time synchronization component of the ARM microprocessor unit obtains the high-precision time from satellite time service within the FPGA unit and uses this time as the clock source for the entire system. It is set to server mode, and the monitoring terminal operating in client mode requests time synchronization operation from the network time synchronization component through the high-precision time synchronization unit.

[0065] Step 2: Set the whole hour moment T to start the test. The real-time power grid signal is sent to the power quality monitoring terminal and the detection device synchronously, and the real-time data of the power quality monitoring terminal and the detection device are read and recorded every fixed period.

[0066] In the embodiment of the present invention, the fixed period is set to 3s. The specific value of the fixed period should not be regarded as a limitation to the present invention.

[0067] The high-precision measurement module of the detection device receives the real-time power grid signal and sends the real-time signal to the host through the internal bus for calculation of relevant data. The host also receives the data sent by the monitoring terminal.

[0068] Step 3: Let the measured value of the power quality index of the detection device at the same moment be χ s , and the corresponding measured value of the power quality monitoring terminal be χ X . The accuracy calculation component of the ARM microprocessor unit calculates the corresponding fractal dimension and calculates the fractal dimension error between the power quality monitoring terminal and the detection device to obtain the final measurement threshold.

[0069] The commonly used algorithm in fractal dimension calculation is the box dimension algorithm. However, through the test results of the W-M fractal function, it is found that the error of the box dimension algorithm is relatively large when the fractal dimension is relatively high. The structure function method is used to calculate the fractal dimension, and the error of the structure function method is relatively large when the fractal dimension is relatively low. The present invention combines the box dimension algorithm and the structure function method to set a more accurate threshold.

[0070] The implementation method of the box dimension algorithm is simple and it is a commonly used fractal dimension calculation method. Zi Yanyang et al. proposed a method for calculating the box dimension of discrete vibration signals in 2001, which extended the box dimension algorithm to the fractal dimension calculation of one-dimensional signals.

[0071] The present invention applies the box dimension algorithm to the calculation of the fractal dimension of one-dimensional signals, and changes the grid division method of the traditional box dimension algorithm from integer grid division to power-of-two grid division. In this way, the scatter plot obtained when taking the logarithm to the base 2 shows a better distribution, and the obtained scatter plot is approximately a straight line.

[0072] The fractals randomly existing in nature do not have self-similarity at infinite scales like mathematical fractals, but only exist within a certain range, and this scale range is the scale-free interval. The scale-free interval is a relatively straight segment on the double-logarithmic curve, and the slope is approximately a constant.

[0073] The double-logarithmic curve obtained by the structure function method cannot be fitted by a straight line. Therefore, the present invention clusters the double-logarithmic curve after the first-order difference through the FCM algorithm. The final clustering result is the scale-free interval, and the fractal dimension is obtained by the least-square fitting of the scale-free interval. The box dimension algorithms with different grid divisions, the structure function algorithm based on FCM, and the W-M fractal function commonly used as a fractal dimension test function will be introduced below.

[0074] Furthermore, in an alternative embodiment of the present application, calculating the corresponding fractal dimension includes the following steps:

[0075] Step 301: Divide the grid of the box dimension algorithm by using the power-of-two grid division method, and calculate the box dimension.

[0076] Discrete signal Y is a closed set in the two-dimensional Euclidean space R2. Divide R2 with a square grid with a sufficiently small side length of 2 ε . N(2 ε ) is the grid count of the set Y. Taking the grid 2 ε as the benchmark, gradually magnify it to the 2 k grid, where k ∈ Z + , and take N(2 k ) as the grid count of the set Y in the discrete space.

[0077] During the division process, it is inevitable to encounter the situation where the length of the discrete signal cannot be evenly divided by the grid size. Discarding all the non-divisible parts will inevitably affect the calculation accuracy. Therefore, the non-divisible parts need to be processed. The processing method used in this article is to regard the non-divisible parts as a new grid for grid counting.

[0078] Box dimension calculation formula:

[0079]

[0080] That is:

[0081]

[0082] The specific calculation process is as follows

[0083]

[0084] In the formula: k = 0, 1, …, M, M < N, where N is the number of sampling points.

[0085] The grid count N(2 k ) is:

[0086] N(2 k ) = P(2 k ) / (2 k ) + 1 (4)

[0087] where N(2 k ) > 1. The meaning of the two formulas is to calculate the difference between the maximum and minimum values of each interval under grid divisions of different sizes, and then obtain the grid count N(2 k ) through the difference.

[0088] Taking i.e., k as the horizontal axis, as the vertical axis, plot a scatter plot, and use the least squares method to determine the slope of the straight line for the points in the figure:

[0089]

[0090] where k1 and k2 are the starting and ending points of the fitting interval, is the fitting slope. The box dimension D is:

[0091]

[0092] The algorithm uses a new grid division method based on the traditional box dimension algorithm, which is more convenient to calculate than the previous division method. The box dimension has a larger error when the fractal dimension is relatively high, and the structure function method has a smaller error.

[0093] Step 302: Use the structure function method based on the FCM algorithm to calculate the slope of the scale-free interval to obtain the fractal dimension.

[0094] The structure function method regards all points on the discrete signal curve as a time series with fractal characteristics. The structure function s(t) of the discrete signal y(i) is:

[0095] s(t) = <[y(x + t) - y(x)] 2 > = ct 4-2D (7)

[0096] Among them, t represents the number of intervals of data points; s(t) is a function of t; x is the abscissa on the curve; y(x) is the corresponding ordinate at coordinate x; <[y(x + t) - y(x)] 2 > represents the arithmetic mean of the squared differences; c is a constant and has no influence on the result.

[0097] For several values of t, the corresponding s(t) is calculated to obtain the scale-free interval of the double-logarithmic curve lgt - lgs(t), and the fractal dimension is obtained by calculating the slope of the scale-free interval. The scale-free interval is a relatively straight line segment on the double-logarithmic curve, and its slope is approximately constant. Therefore, a first-order difference is performed on the structure function, which is characterized by small fluctuations within the scale-free interval and large fluctuations outside the scale-free interval. According to this characteristic, the double-logarithmic curve after the first-order difference can be clustered, and the FCM algorithm is selected for clustering.

[0098] FCM is a clustering algorithm based on the objective function. It uses fuzzy theory to analyze and model data, continuously corrects the cluster centers and classification matrices until they meet the termination criteria, and obtains an uncertain description of the data category. The data category is obtained according to the membership degree, and it is an improved algorithm of K-means.

[0099] Given the fuzzy classification matrix A = [a n and the cluster centers C = [c1, c2, L, c ij of the data sample X = {x1, x2, L, x c×n}, FCM can be expressed as: c T where: c is the number of cluster centers; n is the number of samples; m is the weighting exponent; a

[0100]

[0101] and d ij and d ij are the membership degree and Euclidean distance of the jth data point to the ith cluster center, respectively.

[0102] ​The structure function after the first-order difference is divided into two categories. One category is the gross error in the data, which needs to be removed. The discrimination method for gross error is to perform least squares fitting on the clustering results respectively. The data set with a larger fitting error is the gross error. The interval range obtained from the first classification may not be accurate enough. Therefore, it is necessary to classify the remaining data again to remove some noise points in order to obtain a more accurate scale-free interval. When performing least squares fitting on the clustering results respectively, since the gross error has been removed, the fitting errors of the second clustering results will not differ much. It is inevitable to have some problems when simply using the fitting error as the discrimination criterion. Therefore, the interval with smaller scatter fluctuations and a positive fitting slope in the fitting results is selected as the finally obtained scale-free interval. The slope α of the scale-free interval, and the conversion relationship between D and the slope α is:

[0103]

[0104] Step 303: Calculate the fractal dimension error using the W-M fractal function.

[0105] The W-M fractal function is often used as a test function for the fractal dimension algorithm. The W-M fractal function evolved from the Weierstrass function, which is continuous everywhere but not differentiable. After Mandelbrot founded the theory of fractals, the Weierstrass function was combined with the fractal theory to obtain the Weierstrass-Mandelbrot fractal function, that is, the W-M fractal function. Subsequently, Majumdar and Bhushan made corrections on the basis of the W-M fractal function to make it a mathematical model more suitable for engineering surfaces, that is, the M-B function. The current W-M fractal function refers to the M-B function, and its expression is as follows.

[0106]

[0107] In the formula, Z(x) is the curve height; x is the position coordinate of the curve; G is the characteristic scale coefficient, and its value range is between [0,1]; D is the fractal dimension; λ n is the spatial frequency of the curve, λ is a constant greater than 1, usually taking λ = 1.5; nL is the ordinal number corresponding to the lowest cut-off frequency of the curve; n is the frequency index, and n does not need to take too large a value. In practical applications, it generally takes values between 10 - 100.

[0108] Substitute the data results obtained by the W-M fractal function under different fractal dimensions into the box dimension algorithm of the quadratic power grid division, and the results are shown in Table 1.

[0109] Table 1 Box dimension algorithm error

[0110]

[0111] Substitute the data results obtained from the W-M fractal function at different fractal dimensions into the structure function method, and the results are shown in Table 2.

[0112] Table 2 Errors of the structure function method

[0113]

[0114] Step 304: Set the final threshold according to the fractal dimension error, and use the threshold to judge whether the corresponding measured value of the power quality monitoring terminal is qualified.

[0115] It can be seen from Table 1 and Table 2 that the box dimension has lower errors when the fractal dimension is low and higher errors when the fractal dimension is high, while the structure function method has higher errors when the fractal dimension is low and lower errors when the fractal dimension is high. Therefore, combine the calculation results of the two algorithms to set the threshold, and adopt different algorithms in different fractal dimension intervals. The finally set threshold results are shown in Table 3.

[0116] Table 3 Fractal dimension threshold

[0117]

[0118] Set the threshold according to the algorithm characteristics, and obtain the final threshold result as a new index for measuring the two curves. The threshold result is obtained from the maximum relative error value within the interval of the specified algorithm. Since the fractal dimensions are calculated separately for the power quality monitoring terminal and the high-precision power quality measurement device, the final threshold is twice the relative error.

[0119] Step 4: Repeat Step 3 until all inspection points of the on-site comparison detection are completed, and then stop the test.

[0120] In summary, the present invention has the following beneficial effects:

[0121] The present invention realizes a simple and easy-to-use on-site online comparison detection method and device for power quality monitoring terminals based on fractal dimensions. By designing a high-precision power quality test device, its measurement accuracy and time synchronization accuracy are higher than those of conventional power quality monitoring terminals. Its communication protocol is compatible with the mainstream IEC61850 communication protocol and private protocols on the market. Innovatively invented an on-site online comparison detection method for power quality monitoring terminals based on fractal dimensions, realizing the plug-and-play of on-site comparison detection of monitoring terminals. Reduce the difficulty of on-site comparison detection of power quality online monitoring terminals, improve the work efficiency of power quality, and at the same time effectively reduce the human, material and time costs. Enable the regular detection work installed in the power quality monitoring terminal to be effectively carried out, truly implement the power quality technical supervision work, and escort the safe, stable and economic operation of the power grid.

[0122] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or capable of communicating with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0123] The above is only to illustrate the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent replacements, improvements, etc. made without creative efforts within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. On-site online comparison and detection device for power quality monitoring terminal, characterized in that, It includes a signal conditioning unit, an A / D sampling unit, an ARM microprocessor unit, an FPGA unit, an external storage unit, a human-computer interaction unit, a multi-protocol communication unit, a high-precision time synchronization unit, and a power management unit; the input end of the signal conditioning unit inputs a voltage signal, and the output end of the signal conditioning unit is connected to the input end of the A / D sampling unit; the output end of the A / D sampling unit is connected to the first input end of the FPGA unit, and the output end of the high-precision time synchronization unit is connected to the second input end of the FPGA unit; the FPGA unit sends the sampling data sent by the A / D sampling unit and the time data sent by the high-precision time synchronization unit to the ARM microprocessor unit; the ARM microprocessor unit conducts data interaction with the external storage unit, the human-computer interaction unit, the multi-protocol communication unit, and the high-precision time synchronization unit respectively; the power management unit is a power supply unit. The ARM microprocessor unit includes a human-computer interaction component, a network time synchronization component, a data acquisition component, an accuracy calculation component, and a detection report component; the network time synchronization component obtains the high-precision time from satellite time synchronization in the FPGA unit and uses this high-precision time as the clock source of the entire system and sets it to the server mode; the power quality monitoring terminal working in the client mode requests time synchronization operation with the network time synchronization component through the high-precision time synchronization unit; the data acquisition component obtains the power quality monitoring index data of the power quality monitoring terminal through the multi-protocol communication unit and simultaneously obtains the power quality monitoring index data at the same time point and monitoring point through the internal bus, and transfers the power quality monitoring index data to the accuracy calculation component; the accuracy calculation component then calculates the fractal dimension of the two sets of power quality monitoring index data obtained to judge whether the accuracy of the monitoring terminal meets the requirements; the detection report component outputs the accuracy result of the on-site online comparison detection of the power quality monitoring terminal in the form of a report. The human-computer interaction component interacts with the network time synchronization component, the data acquisition component, the accuracy calculation component, and the detection report component. When the on-site online comparison detection device of the power quality monitoring terminal is in use, the following steps are executed: Step 1: Connect the power quality monitoring terminal to be detected and the detection device through Ethernet, set the parameters of the detection device, start network precise time synchronization, and carry out the verification of communication protocol consistency. Step 2: Start the test, and synchronously send the real-time signal of the power grid to the power quality monitoring terminal and the detection device. Read and record the real-time data of the power quality monitoring terminal and the detection device every fixed period. Step 3: Let the measured value of the power quality index of the detection device at the same moment be s, and the corresponding measured value of the power quality monitoring terminal be X, calculate the corresponding fractal dimension, and calculate the fractal dimension error between the power quality monitoring terminal and the detection device to obtain the final threshold, and use the threshold to judge whether the corresponding measured value of the power quality monitoring terminal is qualified. Step 4: Repeat Step 3 until all inspection points of the on-site comparison detection are completed, and then stop the test. The said Step 3 includes: Step 301: Use the 2-power grid division method to divide the grid of the box dimension algorithm and calculate the box dimension. Step 302: Calculate the slope of the scale-free interval using the structure function method based on the FCM algorithm to obtain the fractal dimension; Step 303: Calculate the fractal dimension error using the W-M fractal function; Step 304: Set the final threshold according to the fractal dimension error, and use the threshold to determine whether the corresponding measured value of the power quality monitoring terminal is qualified.

2. The on-site online comparison and detection device for the power quality monitoring terminal according to claim 1, characterized in that The signal conditioning unit includes a current-limiting resistor Ri, a sampling resistor Rs, a first operational amplifier, a capacitor C1, and two anti-aliasing filters; the voltage signal is input to one end of the current-limiting resistor Ri, and the other end of the current-limiting resistor Ri is connected to the inverting input terminal of the first operational amplifier, and the non-inverting input terminal of the first operational amplifier is grounded; the sampling resistor Rs is connected between the inverting input terminal and the output terminal of the first operational amplifier; the capacitor C1 is connected between the output terminal of the first operational amplifier and the ground to play a filtering role; the output terminal of the first operational amplifier is connected in series with two anti-aliasing filters and then outputs a signal to the A / D sampling unit.

3. The on-site online comparison and detection device for the power quality monitoring terminal according to claim 2, characterized in that, The anti-aliasing filter includes a resistor R1, a resistor R2, a resistor R3, a capacitor C2, a capacitor C3, and a second operational amplifier; one end of the resistor R1 is used as the input terminal of the anti-aliasing filter, and after the resistor R1 is connected in series with the resistor R2, it is connected to the non-inverting input terminal of the second operational amplifier; the inverting input terminal of the second operational amplifier is connected to the ground after being connected in series with the resistor R3; the capacitor C2 is connected between the series connection node of the resistor R1 and the resistor R2 and the inverting input terminal of the second operational amplifier; the capacitor C3 is connected between the non-inverting input terminal of the second operational amplifier and the ground; the output terminal of the second operational amplifier is used as the output terminal of the anti-aliasing filter.

4. The on-site online comparison and detection device for the power quality monitoring terminal according to claim 1, characterized in that, The A / D sampling unit includes a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a capacitor C4, a capacitor C5, a capacitor C6, a diode D1, a diode D2, a dual voltage comparator chip, a voltage-controlled oscillator, and a frequency divider; one end of the resistor R4 is used as the input terminal of the A / D sampling unit; the other end of the resistor R4 is connected to one end of the resistor R5, one end of the capacitor C4, and the positive input terminal of the dual voltage comparator chip; the other end of the resistor R5 and the other end of the capacitor C4 are grounded; the anode of the diode D1 and the cathode of the diode D2 are grounded, and the cathode of the diode D1 and the anode of the diode D2 are connected to the positive input terminal of the dual voltage comparator chip; the resistor R6 is connected between the negative input terminal of the dual voltage comparator chip and the ground; the output terminal of the dual voltage comparator chip is connected to the input terminal of the voltage-controlled oscillator after passing through the resistor R7; the output terminal of the voltage-controlled oscillator is connected to the clock input terminal of the frequency divider, and after being frequency-divided by the frequency divider, it is fed back to the phase detector input terminal of the voltage-controlled oscillator, and after being processed by the voltage-controlled oscillator, a frequency-doubled signal is output from the output terminal.

5. The on-site online comparison and detection device for the power quality monitoring terminal according to claim 1, characterized in that The high-precision time synchronization unit receives time synchronization from a satellite, enabling the on-site online comparison detection device and the power quality monitoring terminal to be time-synchronized.

6. The on-site online comparison and detection device for the power quality monitoring terminal according to claim 1, characterized in that, The external storage unit is used to store waveforms and comparison data.

7. The on-site online comparison and detection device for the power quality monitoring terminal according to claim 1, characterized in that, The human-computer interaction unit uses Bluetooth communication for data input and result display of the on-site online comparison detection device.

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